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STK10C68
September 2003 2 Document Control # ML0006 rev 0.1
ABSOLUTE MAXIMUM RATINGS
a
Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS (V
CC
= 5.0V ± 10%)
Note b: I
CC
1
and I
CC
3
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: I
CC
2
is the average current required for the duration of the STORE cycle (t
STORE
).
Note d: E
≥ V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
CAPACITANCE
e
(T
A
= 25°C, f = 1.0MHz)
Note e: These parameters are guaranteed but not tested.
SYMBOL PARAMETER
COMMERCIAL
INDUSTRIAL/
MILITARY
UNITS NOTES
MIN MAX MIN MAX
I
CC
1
b
Average VCC Current 85
75
65
N/A
90
75
65
55
mA
mA
mA
mA
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
t
AVAV
= 55ns
I
CC
2
c
Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
I
CC
3
b
Average VCC Current at t
AVAV
= 200ns
5V, 25°C, Typical
10 10 mA
W ≥ (V
CC
– 0.2V)
All Others Cycling, CMOS Levels
I
SB
1
d
Average VCC Current
(Standby, Cycling TTL Input Levels)
27
23
20
N/A
28
24
21
20
mA
mA
mA
mA
t
AVAV
= 25ns, E ≥ V
IH
t
AVAV
= 35ns, E ≥ V
IH
t
AVAV
= 45ns, E ≥ V
IH
t
AVAV
= 55ns, E ≥ V
IH
I
SB
2
d
VCC Standby Current
(Standby, Stable CMOS Input Levels)
750 1500 µA
E ≥ (V
CC
– 0.2V)
All Others V
IN
≤ 0.2V or ≥ (V
CC
– 0.2V)
I
ILK
Input Leakage Current
±1 ±1 µA
V
CC
= max
V
IN
= VSS to V
CC
I
OLK
Off-State Output Leakage Current
±5 ±5 µA
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G ≥ V
IH
V
IH
Input Logic “1” Voltage 2.2 V
CC
+ .5 2.2 VCC + .5 V All Inputs
V
IL
Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs
V
OH
Note a: Output Logic “1” Voltage
2.4 2.4 V
I
OUT
= – 4mA
V
OL
Output Logic “0” Voltage 0.4 0.4 V I
OUT
= 8mA
T
A
Operating Temperature 0 70 – 40/-55 85/125 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
C
IN
Input Capacitance
8pF
∆V = 0 to 3V
C
OUT
Output Capacitance
7pF
∆V = 0 to 3V
Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK10C68
September 2003 3 Document Control # ML0006 rev 0.1
SRAM READ CYCLES #1 & #2 (V
CC
= 5.0V ± 10%)
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note g: I/O state assumes E
, G < VIL, W > V
IH
, and NE ≥ V
IH
; device is continuously selected.
Note h: Measured +
200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
SRAM READ CYCLE #2: E Controlled
f
NO.
SYMBOLS
PARAMETER
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1t
ELQV
t
ACS
Chip Enable Access Time 25 35 45 55 ns
2t
AVAV
f
t
RC
Read Cycle Time 25 35 45 55 ns
3t
AVQ V
g
t
AA
Address Access Time 25 35 45 55 ns
4t
GLQV
t
OE
Output Enable to Data Valid 10 15 20 25 ns
5t
AXQX
g
t
OH
Output Hold after Address Change 5 5 5 5 ns
6t
ELQX
t
LZ
Chip Enable to Output Active 5 5 5 5 ns
7t
EHQZ
h
t
HZ
Chip Disable to Output Inactive 10 10 12 12 ns
8t
GLQX
t
OLZ
Output Enable to Output Active 0 0 0 0 ns
9t
GHQZ
h
t
OHZ
Output Disable to Output Inactive 10 10 12 12 ns
10 t
ELICCH
e
t
PA
Chip Enable to Power Active 0 0 0 0 ns
11 t
EHICCL
d, e
t
PS
Chip Disable to Power Standby 25 35 45 55 ns
DATA VALID
5
t
AXQX
3
t
AVQ V
DQ (DATA OUT)
ADDRESS
2
t
AVAV
6
t
ELQX
STANDBY
DATA VALID
8
t
GLQX
4
t
GLQV
DQ (DATA OUT)
E
ADDRESS
2
t
AVAV
G
I
CC
ACTIVE
1
t
ELQV
10
t
ELICCH
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
STK10C68
September 2003 4 Document Control # ML0006 rev 0.1
SRAM WRITE CYCLES #1 & #2 (V
CC
= 5.0V ± 10%)
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E
or W must be ≥ VIH during address transitions. NE ≥ V
IH
.
SRAM WRITE CYCLE #1: W Controlled
j
SRAM WRITE CYCLE #2: E Controlled
j
NO.
SYMBOLS
PAR AME TE R
STK10C68-25 STK10C68-35 STK10C68-45 STK10C68-55
UNITS
#1 #2 Alt. MIN M AX MIN MAX MIN MAX MIN MAX
12 t
AVAV
t
AVAV
t
WC
Write Cycle Time 25 35 45 55 ns
13 t
WLWHtWLEH
t
WP
Write Pulse Width 20 25 30 45 ns
14 t
ELWHtELEH
t
CW
Chip Enable to End of Write 20 25 30 45 ns
15 t
DVWHtDVEH
t
DW
Data Set-up to End of Write 10 12 15 30 ns
16 t
WHDXtEHDX
t
DH
Data Hold after End of Write 0 0 0 0 ns
17 t
AVW HtAVEH
t
AW
Address Set-up to End of Write 20 25 30 45 ns
18 t
AVW L
t
AVEL
t
AS
Address Set-up to Start of Write 0 0 0 0 ns
19 t
WHAXtEHAX
t
WR
Address Hold after End of Write 0 0 0 0 ns
20 t
WLQZ
h, i
t
WZ
Write Enable to Output Disable 10 13 14 15 ns
21 t
WHQX
t
OW
Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
t
AVAV
W
16
t
WHDX
DATA IN
19
t
WHAX
13
t
WLWH
18
t
AVWL
17
t
AVW H
DATA VALID
20
t
WLQZ
15
t
DVWH
HIGH IMPEDANCE
21
t
WHQX
14
t
ELWH
DATA OUT
E
ADDRESS
12
t
AVAV
W
DATA IN
13
t
WLEH
17
t
AVE H
DATA VALID
HIGH IMPEDANCE
14
t
ELEH
18
t
AVEL
19
t
EHAX
15
t
DVEH
16
t
EHDX
STK10C68
September 2003 5 Document Control # ML0006 rev 0.1
STORE INHIBIT/POWER-UP RECALL (V
CC
= 5.0V + 10%)
Note k: t
RESTORE
starts from the time VCC rises above V
SWITCH
.
STORE INHIBIT/POWER-UP RECALL
NO.
SYMBOLS
PARAMETER
STK10C68
UNITS NOTES
Standard MIN MAX
22 t
RESTORE
Power-up RECALL Duration 550 µsk
23 t
STORE
STORE Cycle Duration 10 ms
24 V
SWITCH
Low Voltage Trigger Level 4.0 4.5 V
25 V
RESET
Low Voltage Reset Level 3.6 V
V
CC
V
SWITCH
V
RESET
POWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
22
t
RESTORE
24
25
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
NO RECALL
(V
CC
DID NOT GO
BELOW V
RESET
)
BROWN OUT
STORE INHIBIT
RECALL WHEN
V
CC
RETURNS
ABOVE V
SWITCH
STK10C68
September 2003 6 Document Control # ML0006 rev 0.1
MODE SELECTION
Note l: An automatic RECALL takes place at power up, starting when VCC exceeds 4.25V and taking t
RESTORE
.
STORE CYCLES #1 & #2 (V
CC
= 5.0V ± 10%)
Note m: Measured with W and NE both returned high, and G returned low. STORE cycles are inhibited below 4.0V.
Note n: Once t
WC
has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate
the STORE initiation cycle.
Note o: If E
is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated.
STORE CYCLE #1: W Controlled
o
STORE CYCLE #2: E Controlled
o
E W G NE MODE POWER
H X X X Not Selected Standby
L H L H Read SRAM Active
L L X H Write SRAM Active
L H L L Nonvolatile RECALL
l
Active
L L H L Nonvolatile STORE I
CC
2
L
L
L
H
L
H
L
X
No Operation Active
NO.
SYMBOLS
PARAMETER MIN MAX UNITS
#1 #2 Alt.
26 t
WLQX
m
t
ELQX
t
STORE
STORE Cycle Time 10 ms
27 t
WLNH
n
t
ELNH
t
WC
STORE Initiation Cycle Time 20 ns
28
t
GHNL
Output Disable Set-up to NE Fall 0 ns
29 t
GHEL
Output Disable Set-up to E Fall 0 ns
30 t
NLWL
t
NLEL
NE Set-up 0 ns
31 t
ELWL
Chip Enable Set-up 0 ns
32 t
WLEL
Write Enable Set-up 0 ns
HIGH IMPEDANCE
NE
G
W
E
DQ (DATA OUT)
28
t
GHNL
30
t
NLWL
27
t
WLNH
31
t
ELWL
26
t
WLQX
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
30
t
NLEL
29
t
GHEL
32
t
WLEL
27
t
ELNH
26
t
ELQX
STK10C68
September 2003 7 Document Control # ML0006 rev 0.1
RECALL CYCLES #1, #2 & #3 (V
CC
= 5.0V ± 10%)
Note p: Measured with W and NE both high, and G and E low.
Note q: Once t
NLNH
has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate
the RECALL initiation cycle.
Note r: If W
is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL.
RECALL CYCLE #1: NE Controlled
o
RECALL CYCLE #2: E Controlled
o
RECALL CYCLE #3: G Controlled
o
,
r
NO.
SYMBOLS
PARAMETER MIN MAX UNITS
#1 #2 #3
33 t
NLQX
p
t
ELQXR
t
GLQXR
RECALL Cycle Time 20 µs
34 t
NLNH
q
t
ELNHR
t
GLNH
RECALL Initiation Cycle Time 20 ns
35 t
NLEL
t
NLGL
NE Set-up 0 ns
36
t
GLNL
t
GLEL
Output Enable Set-up 0 ns
37 t
WHNL
t
WHEL
t
WHGL
Write Enable Set-up 0 ns
38 t
ELNL
t
GLEL
t
ELGL
Chip Enable Set-up 0 ns
39 t
NLQZ
NE Fall to Outputs Inactive 20 ns
40 t
RESTORE
Power-up RECALL Duration 550 µs
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
34
t
NLNH
36
t
GLNL
37
t
WHNL
38
t
ELNL
39
t
NLQZ
33
t
NLQX
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
35
t
NLEL
36
t
GLEL
37
t
WHEL
34
t
ELNHR
33
t
ELQXR
NE
G
W
E
DQ (DATA OUT)
HIGH IMPEDANCE
35
t
NLGL
33
t
GLQXR
34
t
GLNH
37
t
WHGL
38
t
ELGL
STK10C68
September 2003 8 Document Control # ML0006 rev 0.1
The STK10C68 has two modes of operation: SRAM
mode and nonvolatile mode, determined by the
state of the NE
pin. When in SRAM mode, the mem-
ory operates as a standard fast static
RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM to Nonvolatile Elements or from Nonvolatile
Elements to
SRAM.
NOISE CONSIDERATIONS
Note that the STK10C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between V
CC
and VSS, using leads and traces that are as short as
possible. As with all high-speed
CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK10C68 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A
0-12
determines which of the 8,192
data bytes will be accessed. When the
READ is initi-
ated by an address transition, the outputs will be
valid after a delay of t
AVQV
(READ cycle #1). If the
READ is initiated by E or G, the outputs will be valid
at t
ELQV
or at t
GLQV
, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the t
AVQ V
access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and NE
is high. The address inputs must be sta-
ble prior to entering the
WRITE cycle and must
remain stable until either E
or W goes high at the
end of the cycle. The data on pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W
controlled WRITE or t
DVEH
before the end of an
E
controlled WRITE.
It is recommended that G
be kept high during the
entire
WRITE cycle to avoid data bus contention on
the common I/O lines. If G
is left low, internal circuitry
will turn off the output buffers t
WLQZ
after W goes low.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and
low and G
is high. While any sequence that
achieves this state will initiate a
STORE, only W initi-
ation (
STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE that would disturb SRAM data. During a
STORE cycle, previous nonvolatile data is erased
and the
SRAM contents are then programmed into
nonvolatile elements. Once a
STORE cycle is initi-
ated, further input and output are disabled and the
DQ
0-7
pins are tri-stated until the cycle is complete.
If E
and G are low and W and NE are high at the end
of the cycle, a
READ will be performed and the out-
puts will go active, signaling the end of the
STORE.
NONVOLATILE RECALL
A RECALL cycle is performed when E, G and NE are
low and W
is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the
RECALL state. Once initiated, the RECALL
cycle will take t
NLQX
to complete, during which all
inputs are ignored. When the
RECALL completes,
any
READ or WRITE state on the input pins will take
effect.
Internally,
RECALL is a two-step procedure. First, the
SRAM data is cleared, and second, the nonvolatile
information is transferred into the
SRAM cells. The
RECALL operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
As with the
STORE cycle, a transition must occur on
any one control pin to cause a
RECALL, preventing
inadvertent multi-triggering. On power up, once V
CC
exceeds the VCC sense voltage of 4.25V, a RECALL
cycle is automatically initiated. Due to this automatic
RECALL, SRAM operation cannot commence until
t
RESTORE
after VCC exceeds approximately 4.25V.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC
< 3.0V), an internal RECALL request will be
latched. When V
CC
once again exceeds the sense
voltage of 4.25V, a
RECALL cycle will automatically
be initiated and will take t
RESTORE
to complete.
DEVICE OPERATION
STK10C68
September 2003 9 Document Control # ML0006 rev 0.1
If the STK10C68 is in a WRITE state at the end of
power-up
RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W
and system
V
CC
or between E and system VCC.
HARDWARE PROTECT
The STK10C68 offers two levels of protection to
suppress inadvertent
STORE cycles. If the control
signals (E
, G, W and NE) remain in the STORE con-
dition at the end of a
STORE cycle, a second STORE
cycle will not be started. The STORE (or RECALL)
will be initiated only after a transition on any one of
these signals to the required state. In addition to
multi-trigger protection,
STOREs are inhibited when
V
CC
is below 4.0V, protecting against inadvertent
STOREs.
LOW AVERAGE ACTIVE POWER
The STK10C68 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between I
CC
and READ cycle
time. Worst-case current consumption is shown for
both
CMOS and TTL input levels (commercial tem-
perature range, V
CC
= 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK10C68 depends on the following items:
1)
CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of
READs to WRITEs; 5) the operating
temperature; 6) the V
CC
level; and 7) I/O loading.
Figure 2: I
CC
(max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
STK10C68
September 2003 10 Document Control # ML0006 rev 0.1
ORDERING INFORMATION
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C
)
M = Military (–55 to 125°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
55 = 55ns (Military only)
Lead Finish (Plastic only)
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
P = Plastic 28-pin 300 mil DIP
S = Plastic 28-pin 350 mil SOIC
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
Blank = Comm/Ind (100 years/106cycles)
5 = Military (10 years/10
5
cycles)
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
- 5 P F 45 I
STK10C68
5962-93056 04 MX X
STK10C68
September 2003 11 Document Control # ML0006 rev 0.1
Document Revision History
Revision
Date Summary
0.0
December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device.
0.1
September 2003 Added lead-free lead finish
STK10C68
September 2003 12 Document Control # ML0006 rev 0.1
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