SIMTEK STK10C48-S45, STK10C48-S45I, STK10C48-S35I, STK10C48-S35, STK10C48-S25 Datasheet

STK10C48

2K x 8 nvSRAM

QuantumTrap™ CMOS

Nonvolatile Static RAM

FEATURES

• 20ns, 25ns, 35ns and 45ns Access Times

• STORE to EEPROM Initiated by Hardware

• RECALL to SRAM Initiated by Hardware or

Power Restore

• Automatic STORE Timing

• 10mA T ypical I

at 200ns Cycle Time

CC

• Unlimited READ, WRITE and RECALL Cycles

• 1,000,000 STORE Cycles to EEPROM

• 100-Year Data Retention over Full Industrial

Temperature Range

• Commercial and Industrial Temperatures

• 28-Pin 300 mil PDIP, 300 mil SOIC and

350 mil SOIC Packages

BLOCK DIAGRAM

EEPROM ARRAY

32 x 512

A

5

A

6

A

7

A

8

A

9

ROW DECODER

STATIC R AM

ARRAY

32 x 512

STORE

RECALL

DESCRIPTION

The Simtek STK10C48 is a fast static RAM with a non-
volatile electrically erasable
incorporated in each static memory cell. The

PROM (EEPROM) element

SRAM

can be read and written an unlimited number of times,
while independent nonvolatile data resides in

EEPROM. Data may easily be transferred from the
SRAM to the EEPROM (the STORE operation), or from

the

EEPROM to the SRAM (the RECALL operation),

using the NE

pin. Transfers from the EEPROM to the

SRAM (the RECALL operation) also take place auto-

matically on restoration of power. The STK10C48
combines the high performance and ease of use of a
fast

SRAM with nonvolatile data integrity.

The STK10C48 features industry-standard pinout for
nonvolatile

RAMs.

PIN CONFIGURATIONS

1

DQ
DQ
DQ

V

NC

NE

2
3

A

7

A

4

6

A

5

5

A

6

4

A

7

3

8

A

2

9

A

1

10

A

0

11

0

12

1

13

2

14

SS

V

28

CC

W

27
26

NC

25

A

8

A

24

9

NC

23
22

G

21

A

10

20

E

19

DQ

7

18

DQ

6

17

DQ

5

DQ
DQ

4
3

28 - 300 PDIP
28 - 300 SOIC
28 - 350 SOIC

16
15

DQ
DQ
DQ
DQ

DQ
DQ

DQ
DQ

0
1
2
3

4
5

6
7

INPUT BUFFERS

COLUMN I/O

COLUMN DEC

A

A

A0A

2

1

A

A

3

4

10

July 1999 3-1

STORE/

RECALL

CONTROL

PIN NAMES

G
NE

E
W

A0 - A

10

W Write Enable
DQ0 - DQ
E Chip Enable
G Output Enable
NE Nonvolatile Enable
V

CC

V

SS

7

Address Inputs

Data In/Out

Power (+ 5V)
Ground

STK10C48

ABSOLUTE MAXIMUM RATINGS

Volt age on Input Rel ative to VSS. . . . . . . . . . –0.6V to (VCC + 0.5V)

Volt age on DQ

Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

DC Output Current (1 output at a time, 1s duration). . . . . . . . 15m A

. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)

0-7

a

Note a: Stresses greater than those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi­tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat­ing conditions for extended periods may affect reliability.

DC CHARACTERISTICS (VCC = 5.0V ± 10%)

SYMBOL PARAMETER

c

I

CC

I

CC

I

CC

I

SB

I

SB

I

ILK

I

OLK

V
V
V
V
T

IH
IL
OH
OL

A

Average VCC Current 95

1

d

Average VCC Current during STORE 33mAAll Inputs Don’t Care, VCC = max

2

c

Average VCC Current at t

3

5V, 25°C, Typical

e

Average VCC Current

1

(Standby, Cycling TTL Input Levels)

e

VCC Standby Current

2

(Standby, Stable CMOS Input Levels )
Input Leakage Current

Off-State Output Leakage Current

Input Logic “1” Volta ge 2.2 V
Input Logic “0” Volta ge VSS – .5 0.8 VSS – .5 0. 8 V All Inputs
Output Logic “1” Voltage 2.4 2.4 V I
Output Logic “0” Voltage 0.4 0.4 V I
Operating Temperature 0 70 –40 85 °C

AVAV

= 200ns

Note b: The STK10C48-20 requires VCC = 5.0V ± 5% supply to operate at specified speed.
Note c: I
Note d: I
Note e: E

and I

CC

1

is the average current required for the duration of the STORE cycle (t

CC

2

≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.

are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.

CC

3

COMMERCIAL INDUSTRIAL
MIN MAX MIN MAX

N/A

STORE

90
75
65

N/A

26
22
19

).

85
75
65

10 10 mA

30
25
21
18

750 750 µA

±1 ±1 µA

±5 ±5 µA

+ .5 2.2 VCC + .5 V All Inputs

CC

UNITS NOTES

mA
mA
mA
mA

mA
mA
mA
mA

t

= 20ns

AVAV

t

= 25ns

AVAV

t

= 35ns

AVAV

t

= 45ns

AVAV

W

≥ (V

– 0.2V)

CC

All Others Cycling, CMOS Levels
t

= 20ns, E ≥ V

AVAV

t

= 25ns, E ≥ V

AVAV

t

= 35ns, E ≥ V

AVAV

t

= 45ns, E ≥ V

AVAV

E

≥ (VCC – 0.2V)

All Others V
V

= max

CC

V

= VSS to V

IN

V

= max

CC

V

= V

IN

SS

= –4mA

OUT

= 8mA

OUT

IH
IH
IH
IH

≤ 0.2V or ≥ (VCC – 0.2V)

IN

CC

to VCC, E or G ≥ VIH

b

AC TEST CONDITIONS

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns

Input and Output Timing Reference Levels. . . . . . . . . . . . . . . 1.5V

Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1

CAPACITANCE

SYMBOL PARAMETER MAX UNITS CONDITIONS

C
C

IN

OUT

Input Capacitance
Output Capacitance

f

(TA = 25°C, f = 1.0MHz)

8pF
7pF

∆V = 0 to 3V
∆V = 0 to 3V

Note f: These parameters are guaranteed but not tested.

July 1999 3-2

OUTPUT

5.0V

480 Ohms

30 pF

255 Ohms

INCLUDING
SCOPE AND
FIXTURE

Figure 1: AC Output Loading

STK10C48

SRAM READ CYCLES #1 & #2 (V

NO.

10 t
11 t

#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX

1t

ELQV

2t

AVAV

3t

AVQV

4t

GLQV

5t

AXQX

6t

ELQX

7t

EHQZ

8t

GLQX

9t

GHQZ
ELICCH
EHICCL

SYMBOLS

g

h

h

i

i

f

e, f

t

ACS

t

RC

t

AA

t

OE

t

OH

t

LZ

t

HZ

t

OLZ

t

OHZ

t

PA

t

PS

PARAMETER

Chip Enable Access Time 20 25 35 45 ns
Read Cycle Time 20 25 35 45 ns
Address Access Time 22 25 35 45 ns
Output Enable to Data Valid 8 10 15 20 ns
Output Hol d after Address Change 5 5 5 5 ns
Chip Enable to Output Active 5 5 5 5 ns
Chip Disable to Output Inactive 7 10 13 15 ns
Output Enable to Output Active 0 0 0 0 ns
Output Disa ble to Outpu t Inactive 7 10 13 15 ns
Chip Enable to Power Active 0 0 0 0 ns
Chip Disable to Power Standby 25 25 35 45 ns

STK10C48-20 STK10C48-25 STK10C48-35 STK10C48-45

= 5.0V ± 10%)

CC

Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
Note h: I/O state assumes E
Note i: Measured +

SRAM READ CYCLE #1: Address Controlled

, G < VIL, W > VIH , and NE ≥ VIH; device is continuously selected.

200mV from steady state output voltage.

2

t

AVAV

g, h

ADDRESS

3

t

AVQV

DATA VALID

DQ (DATA OUT)

t

AXQX

5

b

UNITS

SRAM READ CYCLE #2: E Controlled

ADDRESS

t

ELQX

t

ELICCH

6

t

GLQX

10

4

t

GLQV

8

DQ (DATA OUT)

I

CC

E

G

STANDBY

g

t

AVAV

2

t

ELQV

ACTIVE

1

t

GHQZ

DATA VALID

t

9

7

EHQZ

t

EHICCL

11

July 1999 3-3