Silicon Storage Technology Inc SST39SF020A-70-4I-UH, SST39SF020A-70-4I-PH, SST39SF020A-70-4I-NH, SST39SF020A-70-4C-WH, SST39SF020A-70-4C-UH Datasheet

©2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01 398

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

FEATURES:

• Organized as 128K x8 / 256K x8 / 512K x8

• Single 5.0V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical)
– Standby Current: 30 µA (typical)

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Fast Read Access Time:

– 45 and 70 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:

2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040

• Automatic Write Timing

– Internal V

PP

Generation

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP

PRODUCT DESCRIPTION

The SST39SF010A/020A/040 are CMOS Multi-Purpose
Flash (MPF) manufactured with SST’s proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and th ick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39SF010A/020A /040 devices write
(Program or Erase) with a 5.0V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC stan­dard pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µs ec. These devices us e Toggle
Bit or Data# Polling to indicate th e completi on of Program
operation. To protect against inad vertent write, they have
on-chip hardware and So ftware Data Prot ection s chem es.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater th an 10 0 years .

The SST39SF010A/020A/040 devices are suited for appli­cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption . They inher­ently use less energy during erase and program than alter­native flash technologies. Th e total energy consumed is a

function of the applied voltage, current, and time of applica­tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is l ess than altern ative flash technolo­gies. These devices also im prove flexibility while lowering
the cost for program, data, and configuration storage appli­cations.

The SuperFlash te ch no logy pr ovid es fi xed Erase an d P r o­gram times, independent o f the num be r of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times inc rease with accumul ated Erase/P ro­gram cycles .

To meet high density, surface mount requirements, the
SST39SF010A/020A/040 are offered in 32-pin PLCC and
32-pin TSOP packages. A 600 mil, 32-pin PDIP is also
available. See Figures 1, 2, and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation func­tions of the device. Commands ar e written to the device
using standard mi croprocessor write sequen ces. A com­mand is written by asse r ting WE# low whil e keeping CE#

SST39SF010A / 020A / 0405.0V 4Mb (x8) MPF memories

2

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latche d on
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39SF010A/020A/040 is
controlled by CE# and OE#, both have to be low for the
system to obtai n data from the outputs. CE# is used for
device sele cti on . Whe n CE# is hi gh , the ch ip is de sele ct ed
and only standby power is consumed. OE# is the output
control and is used to gate data fr om the outpu t pins. The
data bus is in high impeda nce state when either CE# or
OE# is high. Refer to the Read cycle timing diagram (Fig­ure 4) for further details.

Byte-Program Operation

The SST39SF010 A/ 0 20 A/ 0 40 are pro grammed on a b y te ­by-byte basis. Before programming, one must ensu re that
the sector, in which the byte which is bein g programmed
exists, is fully erased.The Program operation consists of
three steps. The first st ep is the three-byte-loa d sequen ce
for Software Data Protection. The secon d step is to load
byte address and byte data. During the Byte-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated afte r t he rising edge of the fourth WE# or
CE#, whichever occurs first. The Pro gram operatio n, on ce
initiated, will be completed, within 20 µs. See Figures 5 and
6 for WE# and CE# controlled Program operation timing
diagrams and Figure 15 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog­gle Bit. During the in ternal Program opera tion, the host is
free to perform additional tasks. Any commands written
during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device o n a sector-by-sector basis. The sector architecture
is based on unifor m sector size of 4 KByte. The S ector­Erase operation is initiated by executing a six-byte-com­mand load sequence for Software Data Protection with
Sector-Erase com mand (30 H) and sec tor addre ss (SA) in
the last bus cycle. The sector address is latched on the fall­ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising ed ge of the six th WE# pulse. Th e
internal Era se operation begin s after t he sixth W E# puls e.
The End-of-Erase can be determined u sing either Data#

Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector­Erase operation will be ignored.

Chip-Erase Operation

The SST39SF010A /020A/040 provide Chip-Erase opera­tion, which allows the user to erase the entire memory
array to the “1s” state. This is useful when the entire device
must be quickly erased.

The Chip-Erase operation is initiated by executing a six­byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The inter nal Erase operation beg ins with
the rising edge of th e sixt h WE # o r CE# , wh ich ever oc cu rs
first. During the internal Erase operation, the only valid read
is T oggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, an d Figu re 18 for
the flowchart. Any commands written during the Chip­Erase operation will be ignored.

Write Operation Status Detection

The SST39SF 010A/020A/0 40 provide t wo softw are means
to detect the completion of a Write (Program or Erase)
cycle, in ord er to o ptimiz e the syste m Write c ycle ti me . The
software detection in cludes two status bits: Data# Polling
(DQ

7

) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the r ising edge of WE# which ini­tiates the internal Program or Erase operation.

The actual comple tion of the nonvolatile wr ite is as ynchr o­nous with the system ; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous wi th the complet ion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con­flict with either DQ

7

or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec­tion is valid.

Data# Polling (DQ7)

When the SST39SF010A/020A/040 are in the internal Pro­gram operation, any attempt to read DQ

7

will produce the
complement of the true data. Once the Program operation
is completed, DQ

7

will produce true data. The device is
then ready for the next operation. During internal Erase
operation, any attempt to read DQ

7

will produce a ‘0’. Once

the internal Erase operation is completed, DQ

7

will produce
a ‘1’. The Data# Polling is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040

3

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

tor- or Chip-Erase, the Data# Polling is valid after the rising
edge of sixth WE# (or CE #) pu ls e. Se e F i gure 7 for Data #
Pol ling timing diag ram and Fi gure 16 f or a fl owc hart.

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any con­secutive attempts to read DQ

6

will produce alter nating 0s
and 1s, i.e., toggling between 0 and 1. W hen the internal
Program or Erase operation is com plete d, the tog gling wi ll
stop. The device is then rea dy for the next operation. Th e
Toggle Bit is valid after the rising edge of fourth WE # (or
CE#) pulse for Program operation. For Sector- or Chip­Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for T oggle Bit timing dia­gram and F igur e 16 f or a flo wcha rt.

Data Protection

The SST39SF010A/020A/040 provide both hardware and
software features to protec t n onvolatile da ta fr om i nad vert­ent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of l ess th an 5
ns will not init iate a Writ e cycle .

V

DD

Power Up/Down Detection: The Write operation is

inhibited when V

DD

is less than 2.5V.

Write Inhibit Mode:

Forcing OE# low, CE# high, or WE#
high will inhibit the W r it e operation. This prevents inadvert­ent writes during p owe r-up o r pow er- down.

Software Data Protection (SDP)

The SST39SF010A/020A/040 provide the JEDEC
approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Pro­gram operation requir es the inclusion of a s eries of three
byte sequence. The three byte-load sequence is use d to
initiate the Program operation, providing optimal protection
from inadver tent Wri te operation s, e.g., during t he system
power-up or power-down. Any Erase operation requires the
inclusion of six byte load sequenc e. The SST39SF010A/
020A/040 devices are shipped with the Software Data Pro­tection perm anently enabled. Se e Table 4 for the specific
software command codes. During SDP command
sequence, invalid commands will abo r t the device to read
mode, within T

RC

.

Product Identification

The product identification mode identifies the device as the
SST39SF040, SST39SF010A, or SST39SF020A and
manufacturer as SST . This mode may be accessed by soft­ware operations. Users may wish to use the software prod­uct identification operation to identify the part (i.e., using the
device ID) when using multi ple m anufacture rs in the s am e
socket. For details, see Table 3 for hardware operation or
T ab le 4 for software operation, Figure 11 for the software ID
entry and read timing diagram and Figure 17 for the ID
entry command sequence flowchart.

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identifica tion mode must be exited. Exi t is acco m­plished by issuing th e Exit ID comma nd sequence, whi ch
returns th e d evice to the Read operation. Pl ea se no te that
the software reset comm and is ignore d during an inte rnal
Program or Erase operation. See Table 4 for software com­mand codes, Figure 12 for timing waveform and Figure 17
for a flowchart.

TABLE 1: P

RODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH
Device ID
SST39SF010A 0001H B5H
SST39SF020A 0001H B6H
SST39SF040 0001H B7H

T1.2 398

4

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

Y-Decoder

I/O Buffers and Data Latches

398 ILL B1.2

Address Buffers & Latches

X-Decoder

DQ7 - DQ

0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

SST39SF010A

SST39SF010A

SST39SF010A

SST39SF010A

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

SST39SF020ASST39SF040

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

SST39SF020A SST39SF040

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

4 3 2 1 32 31 30

A12

A15

A16NCVDDWE#

NC

SST39SF020A SST39SF040

A12

A15

A16NCVDDWE#

A17

A12

A15

A16

A18

VDDWE#

A17

32-pin PLCC

T op Vie w

398 ILL F02.3

14 15 16 17 18 19 20

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

SST39SF020ASST39SF040

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040

5

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

FIGURE 3: P

IN ASSIGNMENTS FOR 32-PIN PDIP

A11

A9

A8
A13
A14

NC
WE#
V

DD

NC

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

389 ILL F01.1

Standard Pinout

T op Vie w

Die Up

SST39SF010A

A11

A9

A8
A13
A14
A17

WE#
V

DD

NC
A16
A15
A12

A7
A6
A5
A4

A11

A9

A8
A13
A14
A17

WE#
V

DD

A18
A16
A15
A12

A7

A6

A5

A4

SST39SF020ASST39SF040

SST39SF010A

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

SST39SF020A SST39SF040

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-pin
PDIP

T op Vie w

398 ILL F02a.2

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

SST39SF010A

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

SST39SF020A

A18
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

SST39SF040

SST39SF010A

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

DD

WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

SST39SF020A

SST39SF040

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

6

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A

MS

1

-A

0

Address Inputs To provide memory addresses.

During Sector-Erase A

MS-A12

address lines will select the sector.

DQ

7

-DQ

0

Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V

DD

Power Supply To provide 5.0V supply (±10%)

V

SS

Ground

NC No Connection Unconnected pins.

T2.1 398

1. AMS = Most significant address
A

MS

= A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

IL

V

IL

V

IH

D

OUT

A

IN

Program V

IL

V

IH

V

IL

D

IN

A

IN

Erase V

IL

V

IH

V

IL

X

1

1. X can be VIL or VIH, but no other value.

Sector address,
XXH for Chip-Erase

Standby V

IH

XXHigh Z X

Write Inhibit X V

IL

XHigh Z/ D

OUT

X

XXV

IH

High Z/ D

OUT

X
Product Identification
Software Mode V

IL

V

IL

V

IH

See Table 4

T3.3 398

Preliminary Specification

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040

7

©2001 Silicon Storage Technology, Inc. S71147-02-000 5/01 398

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command
Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA

2

Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA

X

3

30H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry

4,5

5555H AAH 2AAAH 55H 5555H 90H

Software ID Exit

6

XXH F0H

Software ID Exit

6

5555H AAH 2AAAH 55H 5555H F0H

T4.2 398

1. Address format A14-A0 (Hex), Addresses A15 - AMS can be VIL or VIH, but no other value, for the Command sequence.

2. BA = Program Byte address

3. SA

X

for Sector-Erase; uses AMS-A12 address lines

A

MS

= Most significant address

A

MS

= A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

MS-A1

=0; SST Manufac ture r’s ID= BFH, is read with A0 = 0,

SST39SF010A Device ID = B5H, is read with A

0

= 1

SST39SF020A Device ID = B6H, is read with A

0

= 1

SST39SF040 Device ID = B7H, is read with A

0

= 1

6. Both Software ID Exit operations are equivalent

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

DD

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

DD

+ 1.0V

Voltage on A

9

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circ uit Curr ent

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp V

DD

Commercial 0°C to +70°C5.0V±10%
Industrial -40°C to +85°C5.0V±10%

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

L

= 30 pF for 45 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns

See Figures 13 and 14