Silicon Storage Technology Inc SST37VF512-90-3C-WH, SST37VF010-70-3C-PH, SST37VF010-70-3C-NH, SST37VF512-90-3C-PH, SST37VF512-90-3C-NH Datasheet

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

SST37VF512 / 010 / 020 / 0402.7V-Read 512Kb / 1Mb / 2Mb / 4Mb (x8) MTP flash memories

FEATURES:

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8)

Many-Time Programmable Flash

Data Sheet

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• 2.7-3.6V Read Operation

• Superior Reliability

– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical)
– Standby Current: 2 µA (typical)

• Fast Read Access Time:

– 70 ns
– 90 ns

• Latched Address and Data

PRODUCT DESCRIPTION

The SST37VF512/010/020/040 devices are 64K x8 / 128K
x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable
(MTP), low cost flash, manufactured with SST’s proprietary ,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST37VF512/010/020/040 can
be electrically erased and programmed at least 1000 times
using an external programmer, e.g., to change the contents
of devices in inventory. The SST37VF512/010/020/040
have to be erased prior to programming. These devices
conform to JEDEC standard pinouts for byte-wide flash
memories.

• Fast Byte-Program Operation:

– Byte-Program Time: 10 µs (typical)
– Chip Program Time:

0.6 seconds (typical) for SST37VF512

1.2 seconds (typical) for SST37VF010

2.4 seconds (typical) for SST37VF020

4.8 seconds (typical) for SST37VF040

• Electrical Erase Using Programmer

– Does not require UV source
– Chip-Erase Time: 100 ms (typical)

• CMOS I/O Compatibility

• JEDEC Standard Byte-wide Flash

EEPROM Pinouts

• Packages Available

– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP

To meet surface mount and conventional through hole
requirements, the SST37VF512/010/020/040 are offered in
32-pin PLCC, TSOP, and P DIP pa ckages. See F igures 1,
2, and 3 for pinouts.

Device Operation

The SST37VF512/010/020/040 devices are nonvolatile
memory solutions that can be used instead of standard
flash devices if in-system programmability is not required. It
is functionally (Read) and pin compatible with industry
standard flash products.The device supports electrical
Erase operation via an external programmer.

Featuring high performance Byte-Program, the
SST37VF512/010/020/040 provide a typical Byte-Pro­gram time of 10 µs. Designed, manufactur ed, and tested
for a wide spectrum of applications, these devices are
offered with an endurance of at least 1000 cycles. Data
retention i s rat ed at g reat er than 100 y ears .

The SST37VF512 /010/020/ 040 are sui ted for applica tions
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.

©2001 Silicon Storage Technology, Inc.
S71151-02-000 5/01 397

1

Read

The Read operation of the SST37VF512/010/020/040 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the output s. Once
the address is s table, the addres s access time is equal t o
the delay from CE# to output (T
output after a delay of TOE from the falling edge of OE#,
assuming the CE# pin has been low and the addresses
have been stable for at least T
is high, the chip is deselected and a standby current of only
10 µA (typical) is consumed. OE# is the output control and
is used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is V
Refer to Fig ure 4 f or the ti ming di agr am.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MTP is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

). Data is available at the

CE

- TOE. When the CE# pin

CE

IH

.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

Byte-Program Operation

The SST37VF512/ 010/0 20/040 are programmed by usin g
an external programmer. The programming m ode is acti­vated by asserting 12V (±5%) on OE# pin and V

on CE#

IL

pin. The device is program me d u sing a single puls e ( W E #
pin low) of 10 µs per byte. Using the MTP programming
algorithm, the Byte-Program process continues byte-by­byte until the entire chip ha s been programmed. Refer to
Figure 10 for the flowchart and Figur e 6 for the timi ng di a­gram.

Chip-Erase Operation

The only way to change a data from a “0” to “1” is by electri-
cal erase that changes every bit in the device to “1”. The
SST37VF512/010/020/040 use an electrical Chip-Erase
operation. The entire chip can be erased in 100 ms (WE#
pin low). In order to activate erase mode, the 12V (±5%) is
applied to OE# and A
address and data pins are “don’t care”. The falling edge of
WE# will start the Chip-Erase operation. Once the chip has
been erased, all bytes must be verified for FFH. R efer to Fig­ure 9 for the f lowchart and Figure 5 for the timing diagr am.

pins while CE# is low. All other

9

Product Identification Mode

The Product Id entification mode ide ntifies the devices as
SST37VF512, SST37VF010, SST37VF020, and
SST37VF040 and manufacturer a s SST. This mode may
be accessed by the hardware method. To activate this
mode, the programming equipment must force V
(12V±5%) on address A9. Two identifier bytes may then be
sequenced from the device outputs by toggling address

. For details, see T able 3 for hardware operation.

line A

0

TABLE 1: P

Manufacturer’s ID 0000H BFH
Device ID
SST37VF512 0001H C4H
SST37VF010 0001H C5H
SST37VF020 0001H C6H
SST37VF040 0001H C2H

RODUCT IDENTIFICATION

Address Data

T1.2 397

Design Considerations

The SST37VF512/010/020/040 should have a 0.1µF
ceramic high frequency, low inductance capacitor con­nected between V
placed as close to the package terminals as possible.

and GND. This capacitor shou ld be

DD

H

FUNCTIONAL BLOCK DIAGRAM

Memory Address

CE#
OE#

A

9

WE#

Address Buffer

Control Logic

X-Decoder

OE# and A

must remain stable at VH for the entire dura-

9

tion of an Erase operati on. OE# mus t remain stable at V
for the entire duration of the Program operation.

SuperFlash

Memory

Y-Decoder

I/O Buffers

DQ7 - DQ

0

397 ILL B1.1

H

©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

A12

A15

A16

A18

VDDWE#

A17

A12

A15

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A16NCVDDWE#

A12

A15

A16NCVDDWE#

A12

A15NCNC

SST37VF512 SST37VF010 SST37VF020 SST37VF040SST37VF040 SST37VF020 SST37VF010 SST37VF512

4 3 2 1 32 31 30

5
6
7
8

32-pin PLCC

9
10

T op Vie w

11
12
13

14 15 16 17 18 19 20

VDDWE#

A17

NC

NC

29
28
27
26
25
24
23
22
21

SST37VF512 SST37VF010 SST37VF020 SST37VF040SST37VF040 SST37VF020 SST37VF010 SST37VF512

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

DQ1

DQ1

DQ1

DQ1

DQ2

DQ2

DQ2

DQ2

V

V

V

V

SS

SS

SS

DQ3

DQ3

DQ3

DQ3

DQ4

DQ4

DQ4

DQ4

DQ5

DQ5

DQ5

DQ5

DQ6

DQ6

DQ6

DQ6

397 ILL F02a.2

SS

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040

A11

A13
A14

A17
WE#
V

DD

A18

A16

A15

A12

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

A11
A9
A8

A7
A6
A5
A4

A13

A14

A17

WE#
V

DD

NC
A16
A15
A12

A9
A8

A7
A6
A5
A4

A11

A13
A14

NC
WE#
V

DD

NC

A16
A15
A12

A9
A8

A7
A6
A5
A4

A11

A13
A14

NC
WE#
V

DD

NC

NC

A15
A12

A9
A8

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Standard Pinout

T op Vie w

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

397 ILL F01.0

FIGURE 2: P

©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397

IN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

3

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

SST37VF040 SST37VF020 SST37VF010 SST37VF512

A18
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

NC

NC
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-pin

PDIP

T op Vie w

SST37VF512 SST37VF010 SST37VF020 SST37VF040

32

V

31

WE#

30

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

DD

V
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

DD

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

397 ILL F02b.1

FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

A

-A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low.
WE# Write Enable To program or erase (WE# = V
OE# Output Enable To gate the data output buffers during Read operation when low
V

DD

V

SS

NC No Connection Unconnected pins.

1. AMS = Most significant address
A

MS

Address Inputs To provide memory addresses.

0

Data Input/output To output data during Read cycles and receive input data during Program cycles.

0

The outputs are in tri-state when OE# or CE# is high.

pulse during Program or Erase)

IL

Power Supply To provide 3.0V supply (2.7-3.6V)
Ground

= A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

T2.1 397

©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040

Data Sheet

TABLE 3: OPERATION MODES SELECTION

Mode CE# WE# A

V

Read V
Output Disable V
Standby V
Chip-Erase V
Byte-Program V

IL
IL
IH
IL
IL

Program/Erase Inhibit X V

A

IH

IN

XX VIHHigh Z A

XX X High Z X
V
V

V

IL
IL
IH

H

A

IN

XXHigh Z X

XXXV

Product Identification V

1. Device ID = C4H for SST37VF512, C5H for SST37VF020, C6H for SST37VF020, and C2H for SST37VF040

2. A

= Most significant address

MS

= A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020, and A18 for SST37VF040

A

MS

Note: X = VIL or VIH (or VH in case of OE# and A9)

= 12V±5%

V

H

V

IL

V

IH

H

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

OE# DQ Address

9

IL

V

IL

V

H

V

H

or V

V

IL

D

OUT

High Z X
D

IN

High Z/ D

IH

OUT

Manufacturer’s ID (BFH)
Device ID

1

A

IN
IN

A

IN

X

2

A

- A1 = VIL, A0 = V

MS

2

A

- A1 = VIL, A0 = V

MS

IL
IH

T3.1 397

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

+ 0.5V

DD

+ 1.0V

DD

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

AC CONDITIONS OF TEST

DD

Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF

See Figures 7 and 8

©2001 Silicon Storage Technology, Inc. S71151-02-000 5/01 397

5