Silicon Storage Technology Inc SST36VF1601-70-4E-EK, SST36VF1601-70-4E-BK, SST36VF1601-70-4C-EK, SST36VF1601-70-4C-BK Datasheet

FEATURES:

16 Mbit Concurrent SuperFlash

SST36VF1601

SST36V160116Mb (x16) Concurrent SuperFlash

Data Sheet

• Organized as 1M x16

• Dual Bank Architecture for Concurrent Read/Write Operation

– 16 Mbit Bottom Sector Protection

- SST36VF1601: 12 Mbit + 4 Mbit

• Single 2.7-3.6V for Read and Write Operations

• Superior Reliability

– Endurance: 100,000 cycles (typical) – Greater than 100 years Data Retention

• Low Power Consumption:

– Active Current: 25 mA – Standby Current: 4 µA

• Hardware Sector Protection/WP# Input Pin

– Protects 4 outermost sectors (4 KWord) in the

larger bank by driving WP# low and unprotects by driving WP# high

• Hardware Reset Pin (RST#)

– Resets the internal state machine to reading

array data

• Sector-Erase Capability

– Uniform 1 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Fast Read Access Time

– 70 ns

• Latched Address and Data

• Fast Erase and Word-Program (typical):

– Sector-Erase Time: 18 ms – Block-Erase Time: 18 ms – Chip-Erase Time: 70 ms – Word-Program Time: 14 µs – Chip Rewrite Time: 8 seconds

• Automatic Write Timing

– Internal V

Generation

• End-of-Write Detection

– Toggle Bit – Data# Polling – Ready/Busy# pin

• CMOS I/O Compatibility

• Conforms to Common Flash Memory Interface (CFI)

• JEDEC Standards

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-lead TSOP (12mm x 20mm) – 48-ball TFBGA (8mm x 10mm)

PRODUCT DESCRIPTION

The SST36VF1601 is 1M x16 CMOS Concurrent Read/ Write Flash Memory manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.The SST36VF1601 writes (Program or Erase) with a 2.7-3.6V power supply. The SST36VF1601 device conforms to JEDEC standard pinouts for x16 memories.

Featuring high performance Word-Program, the SST36VF1601 device provides a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST36VF1601 device has on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the

SST36VF1601 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.

The SST36VF1601 is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST36VF1601 significantly improves performance and reliability, while lowering power consumption. The SST36VF1601 inherently uses less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST36VF1601 also improves flexibility while lowering the cost for program, data, and configuration storage applications.

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

Concurrent SuperFlash and CSF are trademarks of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST36VF1601 is offered in 48-lead TSOP and 48-ball TFBGA packages. See Figures 2 and 3 for pinouts.

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

Concurrent Read/Write Operation

Dual bank architecture of SST36VF1601 device allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank.

ONCURRENT READ/WRITE STATE

Bank 1 Bank 2

Read No Operation

Read Write

Write Read

Write No Operation

No Operation Read

No Operation Write

Note: For the purposes of this table, write means to perform Block-,

Sector-, or Chip-Erase or Word-Program operations as applicable to the appropriate bank.

Read Operation

The Read operation of the SST36VF1601 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data on the output pins.

The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 4).

Word-Program Operation

The SST36VF1601 is programmed on a word-by-word basis. Before programming, one must ensure that the sector, in which the word which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed typically within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.

Sector- (Block-) Erase Operation

The Sector- (Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST36VF1601 offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored.

Chip-Erase Operation

The SST36VF1601 provides a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the “1” state. This is useful when the device must be quickly erased.

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 22 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.

Write Operation Status Detection

The SST36VF1601 provides one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/ BY#) output pin. The software detection includes two status bits: Data# Polling (DQ Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

) and Toggle Bit (DQ6). The End-of-

) or Toggle Bit (DQ6) read may

‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling (DQ

) timing diagram and Figure 20 for a

flowchart. There is a 1 µs bus recovery time (T before valid data can be read on the data bus. New commands can be entered immediately after DQ true data.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any consecutive attempts to read DQ

will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ stop toggling. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 20 for a flowchart. There is a 1 µs bus recovery time (T

) required before

valid data can be read on the data bus. New commands can be entered immediately after DQ

no longer toggles.

Data Protection

The SST36VF1601 provides both hardware and software features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.

) required

becomes

bit will

Ready/Busy# (RY/BY#)

The SST36VF1601 includes a Ready/Busy# (RY/BY#) output signal. RY/BY# is actively pulled low while during an internal Erase or Program operation is in progress. RY/BY# is an open drain output that allows several devices to be tied in parallel to V BY# is high impedance whenever CE# is high or RST# is low. There is a 1 µs bus recovery time (T valid data can be read on the data bus. New commands can be entered immediately after RY/BY# goes high.

via an external pull up resistor. RY/

) required before

Power Up/Down Detection: The Write operation is

inhibited when V

Write Inhibit Mode:

is less than 1.5V.

Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.

Hardware Block Protection

The SST36VF1601 provides a hardware block protection which protects the outermost 4 KWord in the larger bank. The block is protected when WP# is held low. See Figure 1

Data# Polling (DQ7)

When the SST36VF1601 is in the internal Program operation, any attempt to read DQ of the true data. Once the Program operation is completed,

will produce true data. During internal Erase opera-

tion, any attempt to read DQ internal Erase operation is completed, DQ

will produce the complement

will produce a ‘0’. Once the

will produce a

for Block-Protection location.

A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed.

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least T

any in-progress operation will terminate and

RP,

return to Read mode (see Figure 16). When no internal Program/Erase operation is in progress, a minimum period of T

is required after RST# is driven high before a valid

RHR

Read can take place (see Figure 15).

The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST36VF1601 provides the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST36VF1601 is shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within T

can be VIL or VIH, but no other value during any SDP

The contents of DQ15-

RC.

command sequence.

Common Flash Memory Interface (CFI)

The SST36VF1601 also contains the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 5555H in the last byte

sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

Product Identification

The Product Identification mode identifies the device and manufacturer. For details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H 00BFH

Device ID

SST36VF1601 0001H 2761H

RODUCT IDENTIFICATION

Word Da ta

T1.1 373

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for the software command code, Figure 14 for timing waveform and Figure 21 for a flowchart.

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

Memory Address

RST#

CE#

WP#

WE#

OE#

RY/BY#

Address

Buffers

Control

Logic

(4 KWord Sector Protection)

SuperFlash Memory

12 Mbit Bank

SuperFlash Memory

4 Mbit Bank

I/O Buffers

DQ15 - DQ

373 ILL B37.5

16 Mbit Concurrent SuperFlash

Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors

SST36VF1601

Data Sheet

4 KWord Sector Protection

(4- 1 KWord Sectors)

FFFFFH

F8000H

F7FFFH

F0000H

EFFFFH

E8000H

E7FFFH

E0000H

DFFFFH

D8000H

D7FFFH

D0000H CFFFFH C8000H

C7FFFH

C0000H

BFFFFH

B8000H

B7FFFH

B0000H

AFFFFH

A8000H

A7FFFH

A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH

10000H 00FFFFH 008000H 007FFFH

001000H 000FFFH 000000H

Block 31

Block 30

Block 29

Block 28

Block 27

Block 26

Block 25

Block 24

Block 23

Block 22

Block 21

Block 20

Block 19

Block 18

Block 17

Block 16

Block 15

Block 14

Block 13

Block 12

Block 11

Block 10

Block 9

Block 8

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

Bank 2

Bank 1

373 ILL F38.2

FIGURE 1: SST36VF1601, 1 MBIT X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION

16 Mbit Concurrent SuperFlash SST36VF1601

Data Sheet

A15 A14 A13 A12 A11 A10

A9 A8

A19

WE#

RST#

WP#

RY/BY#

A18 A17

A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Standard Pinout

Top View

Die Up

FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

373 ILL F01b.3

A16 NC V

DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V

DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V

CE# A0

FIGURE 3: P

TOP VIEW (balls facing down)

SST36VF1601

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

DQ15

DQ13

DQ11

DQ9

CE#

OE#

A B C D E F G H

IN ASSIGNMENTS FOR 48-BALL TFBGA (8MM X 10MM)

DQ6

DQ4

DQ3

DQ1

373 ILL F01a.7

16 Mbit Concurrent SuperFlash

SST36VF1601

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol Name Functions

19-A0

-DQ

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers

WE# Write Enable To control the Write operations

RST# Hardware Reset To reset and return the device to Read mode

RY/BY# Ready/Busy# To output the status of a Program or Erase Operation

WP# Write Protect To protect and unprotect the bottom 4 sectors from Erase or Program operation.

NC No Connection Unconnected pins

Address Inputs To provide memory addresses. During Sector-Erase and Hardware Sector Protection,

address lines will select the sector. During Block-Erase A19-A15 address lines

19-A10

will select the block.

Data Input/output To output data during Read cycles and receive input data during Write cycles

Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high.

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read.

Power Supply To provide 2.7-3.6V power supply voltage

Ground

T2.6 373

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

Program V

Erase V

Standby V

Write Inhibit X V

XXV

Product Identification

Software Mode V

1. X can be VIL or VIH, but no other value.

2. Device ID = 2761H

X X High Z X

OUT

Sector or block address,

XXH for Chip-Erase

XHigh Z / D

High Z / D

Manufacturer’s ID (00BFH) See Table 4

Device ID

OUT

T3.6 373

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Silicon Storage Technology Inc SST36VF1601-70-4E-EK, SST36VF1601-70-4E-BK, SST36VF1601-70-4C-EK, SST36VF1601-70-4C-BK Datasheet

Specifications and Main Features

Frequently Asked Questions

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