The SST32HF2 0x /4 0 x C om boM em ory devices integrate a
128K x16 or 256K x16 CMOS fla sh memor y bank with a
64K x16 or 128K x16 CMO S SRAM memory bank in a
Multi-Chip Package (MCP), manufactured with SST’s proprietary , high performance SuperFlash technology .
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typi cally 2 seconds for the
SST32HF201/202 and 4 seconds for the SST32HF40 1/
40 2, when us ing interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the
SST32HF20x/40 x devices contain o n-chip hardware and
software data protection schemes.The SST32HF20x/40x
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF20x/40x devices consist of two independent
memory ban ks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memor y ad dress spac e. Both m emory banks sha re
common address lines, data lines, WE# and OE#. The
memory ban k selection is do ne by memory bank en able
signals. The S RAM ban k enable signa l, BES # sele cts th e
SRAM bank. The flash memory bank enable signal, BEF#
selects the flash mem ory bank. The W E# signa l has to be
used with Software Data Protection (SDP) command
sequence when controlling the Eras e an d P r ogram ope rations in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF20x/40x provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory ban k. The SRAM memo ry bank can be read or
written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automatically latch the input address and data signals and complete
the operation in ba ckground without fur ther in put stimulus
requirement. On ce the internall y controlled Erase or Program cycle in the fla sh bank has c ommenced , the SRAM
bank can be accessed for Read or Write.
The SST32HF20x/40 x devices are suited for applications
that use both flash memory and SRAM memory to store
code or data. For systems requiring low power and s mall
form factor, the SST32HF20x/40x devices significantly
improve performance and r eliability, while lowering power
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF201 / SST32HF202 / SST32HF401 / SST32HF402
Preliminary Specifications
consumption, when compared w ith multiple chip so lu tions.
The SST32HF20x/40x inherently use less energy during
erase and program than alternative flash technologies. The
total energy consumed is a function of the applied voltage,
current, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to program and has a shor ter erase time, the to tal energy consumed during any Erase or Program operation is less than
alternative flash technologies.
The SuperFlash technolog y pro vides f ixed Erase and Program times, independent of the n umbe r of Er ase/Prog r am
cycles that have occurred. Therefore the system software
or hardware does not hav e to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Device Operation
The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When
BES# is low, the SRAM Bank is activated for Read and
Write operatio n. When BEF# is l ow the flash b ank is act ivated for Read, Program or Erase operation. BES# and
BEF# cannot be at low level at the same time. If BES# and
BEF# are both asserted to low level bus contention will
result and the device may suffer permanent damage. A ll
address, data, and control lines are shared by SRAM Bank
and flash bank whi ch minimizes power consumption and
loading. The device goes into standby when both bank
enables are high.
SRAM Operation
With BES# low and BEF# high, the SST32HF201/401
operate as 64K x16 CMOS SRAM, and the SST32HF202/
402 operates as 12 8K x16 CMOS SRAM, wit h fully stat ic
operation requiring no external clocks or timing strobes.
The SST32HF201/40 1 SRAM is mapp ed into the fi rst 64
KWord address space of the device, and the
SST32HF202/402 SRAM is mapped into the first 128
KWord address space. When BES# and BEF# are high ,
both memor y ba nks a re dese le cted a nd the d evice enter s
standby mode. Read and Write cycle times are equal. The
control signals UBS# and LBS# provide access to the
upper data byte and lower data byte. See T able 3 for SRAM
read and write data byte control modes of operation.
control and is used to gate data fr om the outpu t pins. The
data bus is in high impedance state when OE# is high. See
Figure 2 for the Read cycle timing diagram.
SRAM Write
The SRAM Write operation of the SST32HF20x/40x is
controlled by WE# and BE S#, bot h have to be low for the
system to write to the SRAM. During the Word-Write operation, the addres ses and d ata are referenced to the ris ing
edge of either BES# or WE#, whi chever occurs first. The
write time is measured from the last falling edge to the first
rising edge of BES# or W E#. See F igures 3 a nd 4 for the
Write cycle timi ng diag ram s.
Flash Operation
With BEF# acti ve, the S ST3 2HF2 01/202 operate as 1 28K
x16 flash memor y and the S ST32HF401/ 402 operat es as
256K x16 flash m emory. The flash memory bank i s read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and during the
internally timed Erase and Program operations.
Flash Read
The Read operation of the SST32HF20x/40x devices is
controlled by BEF# and OE#. Both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output control and is used to gate d ata from the ou tput pins. The data
bus is in high impedance state when OE# is high. Ref er to
Figure 5 for further details.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operation s of the SST32HF20x/40x.
SDP commands are loaded to the flash memory bank
using standard microprocess or write sequences. A command is loaded by asserting WE# low while keeping BEF#
low and OE# high. The a ddress is latched on the falling
edge of WE# or BEF#, wh ichever occurs last. The dat a is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
SRAM Read
The SRAM Read operation of the SST32HF20x/40x is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data fr om the outputs.
BES# is used for SRAM bank se le ction. OE# is the ou tpu t
The flash memory bank of the SST32HF20x/40x devices is
programmed on a word-by-word basis. Before Program
operations, the memory must be erased first. The Program
Preliminary Specifications
operation consists of three steps. The first step is the three-
byte load sequence for Software Data Protection. The second step is to load word address and word data. During the
Word-Program operation, the addr esses are latched on the
falling edge of either BEF# or WE#, whichever occurs last.
The data is latched on the rising edge of either BEF# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20
µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid flash
Read operations are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform
additional tasks. Any SDP commands loaded during the
internal Program operation will be ignored.
Flash Sector/Block-Erase Operation
The Flash Sector/Block-Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF20x/40x offer both SectorErase and Block-Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block-Erase
mode is based on uniform block size of 32 KWord. The
Sector-Erase op eration is init iated by executing a six-byte
command sequence with Sector-Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A
, for SST32HF201/202, and A17-A11, for
16-A11
SST32HF401/402, are used to determine the sector
address. The Block-Erase operation is initiated by executing a six-byte command se quence with Block-E rase command (50H) and block addres s (BA) in the last bus cycle.
The address lines A
, for SST32HF401/402, are used to determine the block
A
15
, for SST32HF201/202, and A17-
16-A15
address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H
or 50H) is latched on the rising edge of the sixth WE#
pulse. The inter nal Erase operatio n begins after the sixth
WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods.
See Figures 11 and 12 for timing waveforms. Any commands issued during the Sec tor- or B l ock-Era se op eration
are ignored.
Flash Chip-Erase Operation
The SST32HF20x/40x provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entir e de vice must be
quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Eras e
operation begins with the rising edge of the sixt h WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is T oggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 9 for timing diagram,
and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST32HF20x/40x provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the syste m Write cycle time. The software detection includes two status bits: Data# Polling
) and Toggle Bit (DQ6). The End-of-Write detection
(DQ
7
mode is enabled after the r ising edge of WE#, which in itiates the internal Program or Erase operation.
The actual comple tion of the n onvolatile write is as ync hronous with the sys tem; therefore, either a Data# Polling or
Toggle Bit read may be simultaneou s with the compl etion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either D Q
or DQ6. In order to prevent spurio us
7
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Flash Data# Polling (DQ7)
When the SST32HF20x/40x flash memory banks are in
the internal Pr ogram operation, any attempt to read DQ
will produce the co mplement of the true data. Once th e
Program operation is completed, DQ
data. Note that even though DQ
immediately following the completion of an inter nal Write
operation, the remai ning data outputs may still be invalid:
valid data on the entire data bus will appear in subsequent
successive Read cycl es, after an inter val of 1 µs. During
internal Erase operation, any attempt to read DQ
duce a ‘0’. Once the internal Erase operation is completed,
will produce a ‘1’. The Da ta# Polling is valid a fter the
DQ
7
rising edge of the fourth WE# (or BEF#) pulse for Program
operation. For Sector- or Blo ck-Erase, the Da ta# Polling is
valid after the rising edge of the sixth WE# (or BEF#) pulse.
See Figure 8 for Data# Polling timing diagram and Figure
18 for a flowchart.
During the inter nal Program or Erase ope ration, any consecutive attempts to read DQ
will produce alternating ‘1’s
6
and ‘0’s, i.e., toggling between 1 and 0. Whe n the inte r nal
Program or Erase operation is com plete d, t he tog gling wi ll
stop. The flash memor y bank is then ready for the next
operation. The T oggle Bit is valid after the rising edge of the
fourth WE# (or BEF#) pulse for Program operation. For
Sector- or Bank-Er ase, t he Toggle Bit is v alid af ter the rising
edge of the sixth WE# (or BEF#) pulse. See Figur e 9 for
Toggle Bit timing diagram and Figure 18 for a flowchart.
Flash Memory Data Protection
The SST32HF20x/40x flash memory bank provides both
hardware and software features to protec t nonvolatile data
from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
Power Up/Down Detection: The Write operation is
V
DD
inhibited when V
Write Inhibi t Mode:
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
is less than 1.5V.
DD
Forcing OE# low, BEF# high, or WE #
ONCURRENT READ/WRITE STATE TABLE
C
FlashSRAM
Program/EraseRead
Program/EraseWrite
The device will ig nore a ll S DP c omma nds when an Era se
or Program operation is in progress. Note that Product
Identification comman ds use SDP; therefore, these commands will also be ignored while an Erase or Program
operation is in progress.
Product Identification
The Product Id entification mode ide ntifies the devices as
the SST32HF20x/40x and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typically used by programmers, cannot be used on this
device because of t he sh ar ed lin es be twe en fla sh and
SRAM in the multi-chip package. Therefore, application of high voltage to pin A
Users may use the software P roduct Identifica tion operation to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 3 and 4 for software operation, Figure 13 for the
software ID entry and Read timing diagram, and Figure 19
for the ID entry command sequence flowchart.
may damage this device.
9
Flash Software Data Protection (SDP)
The SST32HF20x /40x provide t he JEDEC app roved software data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadver tent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HF20x/40x devices are shipped with the software
data protection pe rmanently e nabled. See Ta ble 4 for the
specific software command codes. During SDP command
sequence, invalid SDP comma nds wil l abor t the device t o
the read mode, within Read Cycle Time (T
RC
).
Concurrent Read and Write Operations
The SST32HF20x/40x provide the unique benefi t of being
able to read from or write to S RAM, while simultaneously
erasing or programming the Flash. This allows data alteration code to be executed from SRAM, while altering the
data in Flash. The following table lists all valid states.
TABLE 1: PRODUCT IDENTIFICATION
AddressData
Manufacture r’s ID0000H00BFH
Device ID
SST32HF201/2020001H2789H
SST32HF401/4020001H2780H
T1.0 557
Product Identification Mode Exit/Reset
In order to retur n to the sta nda rd r ead mod e, the So ftwar e
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software-reset command is ignored during an
internal Pr ogram or Erase op eration. See Table 4 for software command cod es, Figur e 14 for timin g waveform and
Figure 19 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capacitor to be plac ed as close as possible between V
, e.g., less than 1 cm away from the VDD pin of the
-DQ0Data Input/outputT o output data during Read cycles and receive input data during Write cycles.
DQ
15
BES#SRAM Memory Bank EnableTo activate the SRAM memory bank when BES# is low.
BEF#Flash Memory Bank EnableTo activate the Flash memory bank when BEF# is low.
OE#Output EnableTo gate the data output buffers.
WE#Write EnableTo control the Write operations.
V
DD
V
SS
UBS#Upper Byte Control (SRAM)To enable DQ15-DQ
LBS#Lower Byte Control (SRAM)To enable DQ7-DQ
NCNo ConnectionUnconnected Pins
1. AMS = Most significant address
Address InputsTo provide flash addresses, A16-A0 for 2M and A17-A0 for 4M.
0
To pr ovide SRAM addresses, A
for 1M and A16-A0 for 2M.
15-A0
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
Power Supply2.7-3.3V power supply
Ground
8
0
T2.0 557
TABLE 3: OPERATION MODES SELECTION
ModeBES#
Not AllowedV
Flash
ReadV
ProgramV
EraseXV
SRAM
ReadV
WriteV
StandbyV
Flash Write InhibitXXV
Output DisableV
Product Identification
Software ModeV
1. Do not apply BES#=VIL and BEF#=VIL at the same time
2. X can be VIL or VIH, but no other value.
3. Device ID for: SST32HF201/202 = 2789H and SST32HF401/402 = 2780H
SST32HF201/202 Device ID = 2789H, is read with A
SST32HF401/402 Device ID = 2780H, is read with A
0
0
= 1,
= 1.
30H
50H
T4.1 557
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
SRAM20mABEF#=VIH, BES#=V
Standby VDD Current 30µAVDD=VDD Max, BEF#=BES#=V
Input Leakage Current1µAVIN=GND to VDD, VDD=VDD Max
Output Leakage Current1µAV
Input Low Voltage0.8VVDD=VDD Min
Input High Voltage0.7 V
DD
Input High Voltage (CMOS)VDD-0.3VVDD=VDD Max
Flash Output Low Voltage0.2VIOL=100 µA, VDD=VDD Min
Flash Output High VoltageVDD-0.2VIOH=-100 µA, VDD=VDD Min
Output Low Voltage0.4VIOL=1 mA, VDD=VDD Min
Output High Voltage2.2VIOH=-500 µA, VDD=VDD Min
AND V
DDF
20mA
VVDD=VDD Max
= 2.7-3.3V)
DDS
Test ConditionsMinMaxUnits
DD=VDD
Max, all DQs open
, WE#=V
IL
V
OE#=V
BEF#=VIL, BES#=V
WE#=V
IL
BEF#=VIL, BES#=V
=GND to VDD, VDD=VDD Max
OUT
IH
IH
IL
IL
OE#=V
IH,
IL
IH
IHC
T5.1 557
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
SymbolParameterMinimumUnits
T
T
1
PU-READ
PU-WRITE
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation100µs
Powe r-up to Program/Erase Operation100µs
TABLE 7: CAPACITANCE(Ta = 25°C, f=1 Mhz, other pins open)
ParameterDescriptionTest ConditionMaximum
1
C
I/O
1
C
IN
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.