Silicon Storage Technology Inc SST30VR022-70-C-WN-R, SST30VR022-70-C-WH-R, SST30VR022-70-C-UN-R, SST30VR022-70-C-UH-R, SST30VR022-500-E-WH-R Datasheet

©2001 Silicon Storage Technology, Inc.
S71135-02-000 4/01 380

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

ComboMemory is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

• ROM + SRAM ROM/RAM Combo

– SST30VR021: 256K x8 ROM + 128K x8 SRAM
– SST30VR022: 256K x8 ROM + 256K x8 SRAM
– SST30VR023: 256K x8 ROM + 32K x8 SRAM

• ROM/RAM combo on a monolithic chip

• Equivalent ComboMemory (Flash + SRAM):

SST31LF021E for code development and
pre-production

• Wide Operating Voltage Range: 2.7-3.3V

• Chip Access Time

– SST30VR022 70 ns
– SST30VR021/023 500 ns

• Low Power Dissipation:

– Sta ndby: 3 µW (Typical)
– Operating: 10 mW (Typical)

• Fully Static Operation

– No clock or refresh required

• Three state Outputs

• Packages Available

– 32-pin TSOP (8mm x14mm)

PRODUCT DESCRIPTION

The SST30VR021/022/023 are ROM/RAM com bo chips
consisting of 2 Mbi t Read Onl y Mem or y or gani zed as 256
KBytes and Static Ran dom Acce ss Memor y organized as
128, 256, and 32 KBytes.

The device is fabricated using SST’s adv a nc ed CMO S lo w
power pr ocess te chnolog y.

The SST30VR021/02 2/023 has an outpu t enable inpu t for
precise control of the data outputs. It also has two (2) sepa­rate chip enable inputs for selection of either RAM or ROM
and fo r minimi zing c urren t drai n during pow er-do wn mode .

The SST30VR021/022/023 is particularly well suited for
use in low voltage (2.7-3.3V) supplies such as pagers,
organizers and other handheld applications.

RAMCS#

OE#

ROMCS#

WE#

DQ7-DQ

0

AMS-A

0

Note: AMS = Most Significant Address

ROMCS#

RAM

ROM

WE#

OE#

OE#

380 ILL B1.1

Address Buffer

Data Buffer

RAMCS#

Control

Circuit

FUNCTIONAL BLOCK DIAGRAM

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo

2

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP

TABLE 1: P

IN DESCRIPTION

Symbol Pin Name

A

MS

1

-A

0

1. AMS = Most significant address

Address Inputs, for ROM: AMS = A17, for RAM: AMS =A16 for SST30VR021

A

17

for SST30VR022

A

14

for SST30VR023
WE# Write Enable Input
OE# Output Enable
RAMCS# RAM Enable Input
ROMCS# ROM Enable Input
DQ

7

-DQ

0

Data Input/Output

V

DD

Power Supply

V

SS

Ground

T1.2 380

A11

A9

A8
A13
A14
A17

RAMCS#

V

DD

WE#

A16
A15
A12

A7

A6

A5

A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
ROMCS#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

380 ILL F01.0

Standard Pinout

T op Vie w

Die Up

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM
ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023

3

©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Voltage on Any Pin Relative to V

SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD + 0.5V

Voltage on V

DD

Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

O

PERATING RANGE

Range Ambient Temp V

DD

Commercial 0°C to +70°C 2.7-3.3V
Extended -20°C to +85°C 2.7-3.3V

AC CONDITIONS OF TEST

Input Pulse Lev el. . . . . . . . . . . . . . . . . . . . . . . .0-V

DD

Input & Output Timing Reference Levels . . . . . . .VDD/2

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C

L

= 30 pF for 70 ns

Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C

L

= 100 pF for 500 ns

TABLE 2: RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min Max Units

V

DD

Supply Voltage 2.7 3.3 V

V

SS

Ground 0 0 V

V

IH

Input High Voltage 2.4 VDD + 0.5 V

V

IL

Input Low Voltage -0.3 0.3 V

T2.0 380

TABLE 3: DC OPERATING CHARACTERISTICS

Symbol Parameter

V

DD

= 3.0 ± 0.3V

Test ConditionsMin Max Units

I

DD1

ROM Operating Supply Current 4.0+1.1(f)

1

1. f = Frequency of operation (MHz) = 1/cycle time

mA ROMCS#=VIL, RAMCS#=VIH,

V

IN=VIH

or V

IL, II/O

=Opens

I

DD2

RAM Operating Supply Current 2.5+1(f)

1

mA ROMCS#=VIH, RAMCS#=VIL, I

I/O

=Opens

I

SB

Standby VDD Current 10 µA ROMCS#≥VDD-0.2V, RAMCS#≥VDD-0.2V

V

IN≥VDD

-0.2V or VIN ≤0.2V

I

LI

Input Leakage Current -1 1 µA VIN=VSS to V

DD

I

LO

Output Leakage Current -1 1 µA ROMCS#=RAMCS#=VIH or OE#=VIH or

WE#=V

IL

, V

I/O=VSS

to V

DD

V

OL

Output Low Voltage 0.4 V IOL = 1.0 mA

V

OH

Output High Voltage 2.2 V IOH = -0.5 mA

T3.3 380

4

Data Sheet

2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM

ROM/RAM Combo

SST30VR021 / SST30VR022 / SST30VR023

©2001 Silicon Storage Technology, Inc. S71135-02-000 4/01 380

FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 3: A TEST LOAD EXAMPLE

TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz)

Parameter Description Test Condition Maximum

C

I/O

1

I/O Pin Capacitance V

I/O

= 0V 8 pF

C

IN

1

Input Capacitance VIN = 0V 6 pF

T4.1 380

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

380 ILL F08.0

REFERENCE POINTS OUTPUTINPUT

V

IT

V

IHT

V

ILT

V

OT

AC test inputs are driven at V

IHT

(0.9 VDD) for a logic “1” and V

IL T

(0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are V

IT

(0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.

Note: V

IT

- V

INPUT

Test

V

OT

- V

OUTPUT

Test

V

IHT

- V

INPUT

HIGH Test

V

ILT

- V

INPUT

LOW Test

380 ILL F09.0

TO TESTER

TO DUT

C

L