Silicon Storage Technology Inc SST29VF040-55-4I-NH, SST29VF040-55-4C-WH, SST29VF040-55-4C-PH, SST29VF040-55-4C-NH, SST29VF020-70-4I-WH Datasheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Small-Sector Flash

SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

SST29SF/VF512 / 010 / 020 / 0405.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) Byte-Program, Small Erase Sector flash memories

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8

• Single V oltage Read and Write Operations

– 5.0V-only for SST29SF512/010/020/040
– 2.7-3.6V for SST29VF512/010/020/040

• Superior Reliability

– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Low Power Consumption:

– Ac ti ve Current: 10 mA (typical)
– Standby Current:

30 µA (typical) for SST29SF512/010/020/040

1 µA (typical) for SST29VF512/010/020/040

• Sector-Erase Capability

– Uniform 128 Byte sectors

• Fast Read Access Time:

– 55 ns
– 70 ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:

1 second (typical) for SST29SF/VF512
2 seconds (typical) for SST29SF/VF010
4 seconds (typical) for SST29SF/VF020
8 seconds (typical) for SST29SF/VF040

• Automatic Write Timing

– Internal V

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• TTL I/O Compatibility for SST29SFxxx

• CMOS I/O Compatibility for SST29VFxxx

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 32-pin PDIP

Generation

PP

Preliminary Specifications

PRODUCT DESCRIPTION

The SST29SF512/010/020/040 and SST29VF512/010/
020/040 are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS
Small-Sector Flash (SSF) manufactured with SST’s propri­etary, high performance CMOS SuperFlash technology.
The split-gate c el l d es ig n a nd thick oxide tunneling in jector
attain better reliability and manufacturability compared with
alternate approaches. The SST29SFxxx devices write
(Program or Erase) with a 4.5-5.5V power supply. The
SST29VFxxx devices write (Program or Erase) with a 2.7-

3.6V power supply . These devices conform to JEDEC stan­dard pinouts for x8 memories.

Featuring high performance Byte-Program, the
SST29SFxxx and SST29VFxxx devices provide a maxi­mum Byte-Program time of 20 µsec. To protect against
inadvertent write, they have on-chip hardware and Soft­ware Data Protection schemes. Designed, ma nufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of at least
10,000 cycles. Data ret ention is rated at greater than 100
years.

The SST29SFxxx and SST29VFxxx devices are suited for
applications that require convenient and economical updat­ing of program, configura tion, or data me mory. For all sys­tem applications, they significantly improve performance

and reliability, while lowering power consumption. They
inherently use less energy during Erase and Program than
alternative flash te chnologi es. The total ene rgy consumed
is a function of the applied voltage, current, and time of
application. Sin ce for any given voltage range, the Super­Flash technology uses less current to program and has a
short er erase time, the t otal energy consum ed duri ng any
Erase or Program opera tion is less than alter native flash
technologies. They also improve flexibility while lowering
the cost for program, data, and configuration storage appli­cations.

The SuperFlash te ch nology provides fixed Erase and P r o­gram times, independent o f th e numbe r of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times i ncrease with accumul ated Erase/P ro­gram cycles .

To meet high density, surface mount requirements, the
SST29SFxxx and SST29VFxxx devices are offered in 32­pin PLCC and 32- pin TSOP packages. A 600 mil, 32-pin
PDIP is also offered for SST29SFxxx devices. See Figures
1, 2, and 3 for pinouts.

©2001 Silicon Storage Technology, Inc.
S71160-05-000 5/01 505

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Device Operation

Commands are used to initiate the memory operation func­tions of the device. Commands are written to the device
using standard microprocess or write sequences. A com­mand is written by asse r ting WE# low whil e keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latc hed o n
the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST29SFxxx and SST29VFxxx
devices are controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is
used for device selection. W hen CE# is high, the chip is
deselected and onl y standby power is consumed . OE# is
the output control and is used to gate data from the out put
pins. The data bus is in high im pedan ce sta te when e ither
CE# or OE# is high. Refer to the Read cycle timing dia­gram for further details (Figure 4).

Byte-Program Operation

The SST29SFxxx and SST29VFxxx devices are pro­grammed on a byte-by-byte basis. The Program operation
consists of three steps. The first step is the three-byte-load
sequence for Software Data Protection. The second step is
to load byte address and byte data. Dur ing the Byte-Pr o­gram operation, the address es are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on th e rising edge of ei ther CE# or WE#,
whichever occurs first. The third step is the in ternal Pro­gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once ini tiated, will be completed , within 20 µs.
See Figure s 5 a nd 6 for WE # and CE # co nt ro ll ed P r og ram
operation timing diagrams and Figure 16 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the in tern al Program
operation, the host is fre e to perform ad ditiona l tasks. Any
commands wri tten during the inter nal Program operation
will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The SST29SFxxx and
SST29VFxxx offer Sector-Erase mode. The sector archi­tecture is based on uniform sector size of 128 Bytes. The
Sector-Erase ope ration is i nitia ted by executing a s ix-byte­command sequence with Sector-Erase command (20H)
and sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (20H) is latched on the rising

edge of the sixth W E # pu ls e. The i nte rnal Erase op eratio n
begins after the sixth WE# pulse. The End-of-Erase opera­tion can be determined using either Data# Polling or Toggle
Bit methods. See Figure 9 for timing waveforms. Any com­mands issued during the Sector-Erase operation are
ignored.

Chip-Erase Operation

The SST29SFxxx and SST29VFxxx devices provide a
Chip-Erase operation, wh ich allows the user to era se the
entire memor y array to the “1s” state. This is usefu l when
the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six­byte Software Data Protection command sequence with
Chip-Erase command (10H) wi th a ddre ss 55 5H i n th e l ast
byte sequence. The inter nal Erase operation beg ins with
the rising edge of the sixt h WE # o r CE# , which ever oc cu rs
first. During the internal Erase operation, the only valid read
is T oggle Bit or Data# Polling. See Table 4 f or the command
sequence, Figure 10 for timing diagram, an d Figu re 19 for
the flowchart. Any commands written during the Chip­Erase operation will be ignored.

Write Operation Status Detection

The SST29SFxxx and SST29VFxxx devices provide two
software means to detect the completion of a Write (Pro­gram or Erase) cycle, in order to optimize the system
write cycle time. The softw are det ection includes tw o sta­tus bits: Data# Polling (DQ
End-of-Write detection mode is enabled after the rising
edge of WE# which initiates the internal Program or
Erase operatio n.

The actual comple tion of the n onvolatile write is as ync hro­nous with the sys tem; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous wi th the complet ion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con­flict with either DQ
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec­tion is valid.

or DQ6. In order to prevent spurious

7

) and Toggle Bit (DQ6). The

7

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

2

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Data# Polling (DQ7)

When the SST29SFx xx and SST29VFxxx devices are i n
the internal Pr ogram operation, any attempt to read DQ
will produce the co mplement of the true data. Once th e
Program operation is completed, DQ

will produce true

7

data. The device is then ready for the next operation. Dur­ing intern al Erase ope ration, any atte mpt to re ad DQ

7

will
produce a ‘0’. Once the inter nal Erase operation is com-
pleted, DQ

will produce a ‘1’. The Data# Polling is valid

7

after the risin g e dge of four th WE# (or CE#) pul se for Pro­gram operation. For Sector- or Chip-Erase, the Data# Poll­ing is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 7 for Data # Polling timing diagram and
Figure 17 for a flowchart.

Toggle Bit (DQ6)

During the inter nal Program or Erase ope ration, any con­secutive attempts to read DQ

will produce alter nating 0s

6

and 1s, i.e., toggling between 0 and 1. W hen the internal
Program or Erase operation is com plete d, t he tog gling wi ll
stop. The device is then rea dy for the next operation. Th e
Toggle Bit is valid after the rising edge of fourth WE # (or
CE#) pulse for Program operation. For Sector or Chip­Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for T oggle Bit timing dia­gram an d Figur e 17 f or a flo wcha rt.

Data Protection

The SST29SFxxx and SST29VFxxx devices provide both
hardware and software features to protec t nonvolatile data
from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of le ss than 5
ns will not init iate a write cycle .

Power Up/Down Detection: The Write operation is

V

DD

inhibited when V
Write operation is in hi bi ted whe n V

is less than 2.5V f or SST29SFxxx. The

DD

is less than 1.5V. for

DD

SST29VFxxx.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the W r ite operation. This prevents inadvert­ent writes during p ow er-up o r pow er- down.

Software Data Protection (SDP)

The SST29SFxx x and SST29VFxxx provide the JE DEC
approved Software Data Protection scheme for all data
alteration operation, i.e., Program and Erase. Any Program
operation requires the inclusion of a se ries of three byte
sequence. The three byte-load sequence is used to initiate

the Program operation, p roviding optimal protection from
inadvertent write operations, e.g., during the system power­up or power -down. Any Er as e op er a t io n req u ire s th e inclu -

7

sion of six byte load sequence. These devices are shipped
with the Software Data Protection permanently enabled.
See T ab le 4 for the specific software command codes. Dur­ing SDP command sequence, invalid commands will abort
the device to read mode, within T

RC

.

Product Identification

The Product Identifi cation mode identifies the devices as
SST29SF512, SST29SF010, SST29SF020, SST29SF040
and SST29VF512, SST29VF010, SST29VF020,
SST29VF040 and manufacturer as SS T. This mode may
be accessed by software o perations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when us ing mul tiple manufactur­ers in the same socket. For details, see Table 4 f or software
operation, Figure 11 for the Software ID Entry and Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flowchart.

TABLE 1: P

Manufacturer’s ID 0000H BFH
Device ID
SST29SF512 0001H 20H
SST29VF512 0001H 21H
SST29SF010 0001H 22H
SST29VF010 0001H 23H
SST29SF020 0001H 24H
SST29VF020 0001H 25H
SST29SF040 0001H 13H
SST29VF040 0001H 14H

RODUCT IDENTIFICATION

Address Data

Product Identification Mode Exit/Reset

In order to return to the standard Read mode, the Software
Product Identific ation mode must be exited. Exit is acco m­plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the S oftware ID Exit command is ig nor e d
during an internal Program or Erase operation. See T able 4
for software command codes, Figure 12 for timing wave­form and Figure 18 for a flowchart.

T1.1 505

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

3

FUNCTIONAL BLOCK DIAGRAM

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Memory
Address

Address Buffers & Latches

CE#
OE#

WE#

X-Decoder

Control Logic

A12

A12

A12

A15

A15

A15

A16

A18

VDDWE#

A16NCVDDWE#

A16NCVDDWE#

SuperFlash

Memory

Y-Decoder

I/O Buffers and Data Latches

DQ7 - DQ

A17

A17

NC

0

505 ILL B1.1

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A12

A15NCNC

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

4 3 2 1 32 31 30

5
6
7
8

32-pin PLCC

9
10
11
12
13

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

T op Vie w

14 15 16 17 18 19 20

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

DQ1

DQ2

VDDWE#

NC

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE#

23

A10

22

CE#

21

DQ7

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

SS

V

DQ3

DQ4

DQ5

DQ6

DQ6

DQ6

DQ6

505 ILL F02a.3

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN PLCC

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

4

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

SST29SF/VF512SST29SF/VF010SST29SF/VF020SST29SF/VF040 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040SST29SF/VF512

A11

A9

A8
A13
A14
A17

WE#
V

DD

A18
A16
A15
A12

A7

A6

A5

A4

FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)

A11

A13
A14

A17
WE#
V

DD

NC
A16
A15
A12

A9
A8

A7
A6
A5
A4

A11

A13
A14

WE#
V

A16
A15
A12

NC

DD
NC

A11
A9
A8

A13

A14

NC
WE#
V

DD

NC

NC

A15

A12
A7
A6
A5
A4

1

A9

2

A8

3
4
5
6
7
8
9
10
11
12

A7

13

A6

14

A5

15

A4

16

SST29SF512SST29SF010SST29SF020SST29SF040 SST29SF010 SST29SF020 SST29SF040SST29SF512

Standard Pinout

T op Vie w

Die Up

505 ILL F01.2

OE#

32

A10

31

CE#

30

DQ7

29

DQ6

28

DQ5

27

DQ4

26

DQ3

25

V

24

DQ2

23

DQ1

22

DQ0

21

A0

20

A1

19

A2

18

A3

17

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
DQ2
DQ1
DQ0
A0
A1
A2
A3

SS

FIGURE 3: P

A18
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

NC
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

NC
A16
A15
A12

DQ0
DQ1
DQ2

V

SS

A7
A6
A5
A4
A3
A2
A1
A0

NC

NC
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

IN ASSIGNMENTS FOR 32-PIN PDIP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-pin

PDIP

T op Vie w

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

DD

WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

505 ILL F02b.4

V

DD

WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

V

DD

WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

5

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

1

-A

A

MS

-DQ

DQ

7

CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
V

DD

V

SS

NC No Connection Pin not connected internally

1. AMS = Most significant address
A

MS

Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the

0

sector.

Data Input/output To output data during Read cycles and receive input data during Write cycles.

0

Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

Power Supply To provide power supply voltage: 4.5-5.5V for SST29SF512/010/020/040

Ground

= A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

Preliminary Specifications

2.7-3.6V for SST29VF512/010/020/040

T2.3 505

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V
Program V
Erase V

Standby V
Write Inhibit X V

Product Identification
Software Mode V

1. X can be VIL or VIH, but no other value.

V

IL

V

IL

V

IL

IH

XXV

V

IL

VIHD

IL

VILD

IH

VILX

IH

OUT
IN

1

XXHigh Z X

XHigh Z/ D

IL

High Z/ D

IH

V

IL

IH

OUT
OUT

A

IN

A

IN

Sector addre ss,
XXH for Chip-Erase

X
X

See Table 4

T3.4 505

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

6

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

TABLE 4: SOFTWARE COMMAND SEQUENCE

Command
Sequence

Byte-Program 555H AAH 2AAH 55H 555H A0H BA
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Software ID Entry
Software ID Exit
Software ID Exit

1. Address format A14-A0 (Hex),

2. BA = Program Byte address

for Sector-Erase; uses AMS-A7 address lines for SST29SF/VFxxx

3. SA

X

= Most significant address

A

MS

= A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020, and A18 for SST29SF/VF040

A

MS

4. The device does not remain in Software Product ID Mode if powered down.

5. With A

6. Both Software ID Exit operations are equivalent

4,5
6
6

Address A
Addresses A
Addresses A
Addresses A

=0; SST Manufacturer’s ID= BFH, is read with A0 = 0,

MS-A1

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

2

Data

3

X

555H AAH 2AAH 55H 555H 90H

XXH F0H

555H AAH 2AAH 55H 555H F0H

can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF512.

15

- A16 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF010.

15

- A17 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020.

15

- A18 can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF040.

15

SST29SF512 Device ID = 20H, is read with A
SST29SF512 Device ID = 21H, is read with A
SST29SF010 Device ID = 22H, is read with A
SST29VF010 Device ID = 23H, is read with A
SST29SF020 Device ID = 24H, is read with A
SST29SF020 Device ID = 25H, is read with A
SST29SF040 Device ID = 13H, is read with A
SST29VF040 Device ID = 14H, is read with A

0
0
0
0
0
0
0
0

= 1
= 1
= 1
= 1
= 1
= 1
= 1
= 1

20H

T4.4 505

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

7

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040

Preliminary Specifications

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

Voltage on A

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V

9

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

1

Output Short Circ uit Curr ent

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

+ 0.5V

DD

+ 1.0V

DD

OPERATING RANGE FOR SST29S F51 2/010/020 /040

Range Ambient Temp V

Commercial 0°C to +70°C 5V±10%
Industrial -40°C to +85°C 5V±10%

DD

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . . C

Output Load . . . . . . . . . . . . . . . . . . . . . C

= 30 pF for 55 ns

L

= 100 pF for 70 ns

L

See Figures 13, 14, and 15

TABLE 5: DC OPERATING CHARACTERISTICS V

Symbol Parameter

I

DD

I

SB1

I

SB2

I

LI

I

LO

V
V
V
V
V

IL
IH
IHC
OL
OH

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min

Read 20 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Write 20 mA CE#=WE#=V
Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max
Standby VDD Current (CMOS input) 100 µA CE#=V
Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
Output Leakage Current 10 µA V
Input Low Voltage 0.8 V VDD=VDD Min
Input High Voltage 2.0 V VDD=VDD Max
Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
Output Low Voltage 0.4 V IOL=2.1 µA, VDD=VDD Min
Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

DD

OPERATING RANGE FOR SST29V F51 2/010/020 /040

Range Ambient Temp V

Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

= 5.0V±10% FOR S ST29S FXXX

Limits

Test ConditionsMin Max Units

V

DD=VDD

OUT

Max

IL

, VDD=VDD Max

IHC

=GND to VDD, VDD=VDD Max

, OE#=V

DD

IH

T5.3 505

©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505

8