Silicon Storage Technology Inc SST28VF040A-90-4I-WH, SST28VF040A-90-4I-PH, SST28VF040A-90-4I-NH, SST28VF040A-90-4I-EH, SST28VF040A-90-4C-WH Datasheet

©2001 Silicon Storage Technology, Inc.
S71077-04-000 6/01 310

1

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

4 Mbit (512K x8) SuperFlash EEPROM

SST28SF040A / SST28VF040A

FEATURES:

• Single Voltage Read and Write Operations

– 5.0V-only for SS T28SF040A
– 2.7-3.6V for SST28VF040A

• Superior Reliability

– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention

• Memory Organization: 512K x8

• Sector-Erase Capability: 256 Bytes per Sector

• Low Power Consumption

– Ac ti ve Current: 15 mA (typical) for 5.0V and

10 mA (typical) for 2.7-3.6V

– Standby Current: 5 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Byte-Program Time: 35 µs (typical)
– Sector-Erase Time: 2 ms (typical)
– Complete Memory Rewrite: 20 sec (typical)

• Fast Read Access Time

– 5.0V-only operation: 90 and 120 ns
– 2.7-3.6V operation: 150 and 200 ns

• Latched Address and Data

• Hardware and Software Data Protection

– 7-Read-Cycle-Sequence Software Data

Protection

• End-of-Write Detection

– Toggle Bit
– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– F lash EE PROM Pino uts

• Packages Available

– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm and 8mm x 20mm)
– 32-pin PDIP

PRODUCT DESCRIPTION

The SST28SF/VF040A are 512K x8 bit CMOS Sector­Erase, Byte-Program EE PROMs. The SST28SF/VF0 40A
are manufactured using SST’s proprietary, high perfor-
mance CMOS SuperFlash EEPROM Technology. The
split-gate cell design and thick oxide tunneling injector
attain better reliability and manufacturability compared with
alternative approa c hes. Th e S ST2 8S F /V F04 0A erase an d
program with a single power supply. The SST28SF/
VF040A conform to JEDEC stan da rd pi no u ts for byte wide
memories and are compatible with existing industry stan­dard flash EEPROM pinouts.

Featuring high perfor mance programming, the SST 28SF/
VF040A typically Byte-Program in 35 µs. The SST28SF/
VF040A typically Sector-Erase in 2 ms. Both Program and
Erase times can be optimized using interface features such
as Toggl e bi t or Da ta# Polling to indicat e th e c omp le ti on o f
the Write cycle. To protect agai nst an inadvertent write, the
SST28SF/VF040A have on chip hardware and Software
Data Protection schemes. Designed, manufactured, and
tested for a wide spectr um of appli cations, the SST2 8SF/
VF040A are offered with a guaranteed sector endurance of
10,000 cycles. Data retention is rated greater than 100
years.

The SST28SF/VF040A are best suited for applications that
require repro grammable nonvolatile mass storag e of pro­gram, configuration, or data memory. For all system appli-

cations, the SST28SF/VF040A significantly improve
performanc e and relia bility, while low ering pow er consu mp­tion when compared with floppy diskettes or EPROM
approaches. Flash EEPROM technology makes possible
convenient and economical updating of codes and control
programs on-line. The SST28 SF/VF040A improve flexibil­ity, while lowering the cost of program and configuration
storage application.

The functional block diagram shows the functional blocks of
the SST28SF/VF040A. Figures 1, 2, and 3 show the pin
assignments for the 32-lead PLCC, 32-lead TSOP, and 32­pin PDIP packages. Pin descriptions and operation modes
are described in T ab les 2 through 5.

Device Operation

Commands are used to initiate the memory operation func­tions of the device. Commands ar e written to the device
using standard mi croprocessor write sequen ces. A com­mand is written by asse r ting WE# low whil e keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. T he data bus is latche d on
the rising edge of WE# or CE#, whichever occurs first.
Note, during the Software Da ta Protection sequence the
addresses are latche d on the r ising edge of OE# or CE#,
whicheve r occurs first.

SST28SF040A / SST28VF040A5.0 & 2.7 4Mb (x8) Byte-Program, Small Erase Sector flash memories

2

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

Command Definitions

Table 4 contai ns a command list and a brief summar y of
the commands. The following is a detailed description of
the operations initiated by each command.

Sector-Erase Operation

The Sector-Erase operation erases all bytes within a sector
and is initiated by a setu p c om man d a nd a n execute com­mand. A sector co nta in s 25 6 B y tes. Th is s ec to r erasa bi li ty
enhances the flexibility and usefulness of th e SST28SF/
VF040A, since most applications only ne ed to change a
small number of bytes or sectors, not the entire chip.

The setup command is perfor med by writing 20H to the
device. The execute command is performed by writing D0H
to the device. The Erase operatio n begins with the risin g
edge of the WE# or CE#, whichever occurs first and termi­nates automatically by using an internal timer. The End-of­Erase can be deter min ed using eit her Data# Polling, Tog­gle Bit, or Successive Reads det ection metho ds. See Fig­ure 9 for timing waveforms.

The two-step se quence of a se tup command followed by
an execute command ensures that only memory contents
within the addresse d sector are erased a nd other sectors
are not inadvertently erased.

Sector-Erase Flowchart Description

Fast and reliable erasing of the memor y cont ents with in a
sector is accomplished by following the Sector-Erase flow­chart as shown in Figure 18. The entire procedure consists
of the execution of two commands. The Sector-Erase oper­ation will termin ate after a maximum of 4 ms. A Re set com­mand can be executed to terminate the Sector-Erase
operation; however, if the Erase operation is terminated
prior to the 4 ms time-out, the sector may not be fully
erased. A Sector-Erase command can be reissued as
many times as necessary to complete the Erase operation.
The SST28SF /VF040 A cannot be o ve r-er ased.

Chip-Erase Operation

The Chip-Erase operation is initiated by a setup command
(30H) and an execute comma nd (30H). The Chip-Erase
operation allows the en tire array of the SS T28SF/ VF040A
to be era sed i n on e op er a t ion, a s op po se d t o 20 48 Se ct o r­Erase operations. Using the Chip-Erase operation will mini­mize the time to rewrite the entire memory array. The Chip­Erase operation will terminate after a maximum of 20 ms. A
Reset command ca n be executed to termina te the Erase
operation; however, if the Chip-Erase operation is termi­nated prior to the 20 ms time-out, the chip may not be com­pletely erased. If an erase error occurs a Chip-Erase

command can be rei ssued as many times as nece ssary to
complete the Chip-Erase operation. The SST28SF/
VF040A cannot be o ve r-er ased. ( See Fig ure 8)

Byte-Progr am Op eration

The Byte-Prog ram op eratio n is init iated b y writing th e setup
command (10H). Once th e program setup is performed,
programming is executed by the next WE# pulse. See Fig­ures 5 and 6 for timing waveforms. The address bus is
latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the ris ing edge of
WE# or CE#, w hichever occurs first, and begins the Pro­gram operation. The Program operation is terminated auto­matically by an internal timer. See Figure 16 for the
programming flowchart.

The two-step seque nce of a setup command followed by
an execute command ensures that only the addressed
byte is programmed and oth er bytes are not i nadvert ently
programmed.

The Byte-Program Flowchart Description

Programming data in to the SST28SF/VF040A is accom­plished by following the Byte-Pr ogram flowchar t shown in
Figure 16. The Byte-P rogram command sets up the byte
for programming. The address bus is latched on the falling
edge of WE# or CE#, whichever occurs last. The data bus
is latched on the r ising edge of WE# or CE#, whichever
occurs first and b egi ns the Program operation. T h e end o f
program can be detected using either the Data# Polling,
Toggle bit, or Successiv e read s.

Reset Operation

The Reset command is provided as a means to safely
abort the Erase or Program command sequences. Follow­ing either setup commands (Erase or Program) with a write
of FFH will safely abort the operation. Memory contents will
not be altered. After the Reset command, the device
returns to the Read m ode. The Res et co mmand do es no t
enable Software Data Pr otection. See Figure 7 for timing
waveforms.

Read

The Read operation is initiated by setting CE#, and OE# to
logic low and setting WE # to log ic hi gh (See Table 3). See
Figure 4 for Read cycle timing waveform. The Read opera­tion from the host retrieves data from the array. The device
remains enabled for Read until an other operati on mode is
accessed. Durin g initia l po wer- up , the de vice i s in th e Read
mode and is Software Data protected. The device must be
unprotected to execute a Write command.

Data Sheet

4 Mbit SuperFlash EEPROM
SST28SF040A / SST28VF040A

3

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

The Read operation of the SST28SF/VF040A are con­trolled by OE# and CE# at logic low. When CE # is high,
the chip is deselected and only standby power will be con­sumed. OE# is the out put co ntr o l a nd i s used to gate data
from the output p ins. The data bus is in hi gh impedance
state when CE# or OE# are high.

Read-ID operation

The Read-ID operation is initiated by writing a single com­mand (90H). A read of address 0000H will output the man­ufacturer’s ID (BFH). A read of address 00 01H will output
the device ID (04H). Any other valid command will ter mi­nate this operation.

Data Protection

In order to protect th e integri ty of nonvolatile data s torage,
the SST28SF/VF040A provide both

hardware and software features to prevent inadvertent
writes to the device, for example, during system power-up
or power-down. Such provisions are described below.

Hardware Data Protection

The SST28SF/VF040A are designed with hardware fea­tures to prevent inadverte nt write s. This is done i n the fol­lowing w ays:

1. Write Cycle Inhibit Mode:

OE# low, CE#, or WE#

high will inhibit the Write operation.

2. Noise/G litch Prot ection: A WE# pulse width of less
than 5 ns will not initiate a Write cycle.

3. V

DD

Power Up/Down Detection: The Write opera-

tion is inhibited when V

DD

is less than 2.0V.

4. After power-up, the device is in the Read mode
and the device is in the Software Data Protect
state.

Software Data Protection (SDP)

The SST28SF/VF04 0A have software methods to fur ther
prevent inadvertent wri tes. In o rder to pe rform an Era se or
Program operation, a two-step command seq uence con­sisting of a set -up comma nd followed by an execute com­mand avoids inadvertent erasing and programming of the
device .

The SST28SF/VF0 40A will default to Software Data Pro­tection after power up. A sequence of seven consecutive
reads at speci fic addresses will unprotect the device Th e
address sequence is 1823H, 1820H, 1822H, 0418H,
041BH, 0419H, 041AH. The address bus is latched on the

rising edge of OE# or CE#, whichever occurs first. A similar
seven read sequence of 1823H, 1820H, 18 22H, 0418H,
041BH, 0419H, 040AH will protect the device. Also refer to
Figures 10 and 11 for the 7 read cycle sequence Software
Data Protec tion. The I/O pins c an be in any state ( i.e ., hi gh,
low , or tri-stat e).

Write Operation Status Detection

The SST28SF/VF040 A provide three me ans to detec t the
completion of a Wr ite operation, in order to optimize th e
system Write operation. The end of a Write operation
(Erase or Program ) can be detected by t hree means: 1)
monitoring the Dat a# Polling bit, 2) monitoring the Toggle
bit, or 3) by two successiv e re ad s of t he sa me dat a. Th ese
three detection mechanisms are described below.

The actual completion of the nonvolatile Write is asynchro­nous with the system ; therefore, either a Data# Polling or
Toggle Bit read may be simultan eous with the co mpletion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con­flict with the DQ used. In order to pr event spurious rejec­tion, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec­tion is valid.

Data# Polling (DQ7)

The SST28SF/VF040A feature Data# Polling to indicate
the Write ope ration status. During a Write operation, any
attempt to read the last byte loaded during the byte-load
cycle will receive the complement of the true data on DQ

7

.

Once the Write cycle is completed, DQ

7

will show true
data. The device is then re ady for the next operation. See
Figure 12 for Data# Polling timing waveforms. In order for
Data# Polling to function correctly, the byte being polled
must be erased prior to programming.

Toggle Bit (DQ6)

An alternati ve means for determining the Write operation
status is by monitoring the Toggle Bit, DQ

6

. During a Write
operation, consecutive attempts to read data from the
device will re sult in DQ

6

toggling between logic 0 (low) and
logic 1 (high). When the Wri te cycl e is comp leted, the tog­gling will stop. The device is then ready for the next opera­tion. See Figure 13 for Toggle Bit timing waveforms.

4

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

Successive Reads

An Alternative means for determining an end of a write
operation is by reading the same address for two consecu­tive data matches.

Product Identification

The Product Identification mode identifies the device as
SST28SF/VF040A and the manufacturer as SST. This
mode may be accessed by hardware and software opera­tions. The hardware operation is typically used by an exter­nal programmer to identify the correct algorithm for the

SST28SF/VF040A. Users may wish to use the software
operation to ident ify the device (i.e., using the device ID ).
For de tai l s see Tabl e 3 for the hardware operation and Fi g­ure 19 for the software operation. The ma nufacturer and
device IDs are the same for both operations.

FIGURE 1: P

IN ASSIGNMENTS FOR 32-LEAD PLCC

TABLE 1: P

RODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH
Device ID

SST28SF/VF040A 0001H 04H

T1.1 310

Y-Decoder

I/O Buffers and Data Latches

310 ILL B1.1

Address Buffer & Latches

X-Decoder

DQ7 - DQ

0

A18 - A

0

WE#

OE#

CE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7

4 3 2 1 32 31 30

A12

A15

A16

A18

VDDWE#

A17

32-lead PLCC

T op Vie w

310 ILL F02.3

14 15 16 17 18 19 20

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

Data Sheet

4 Mbit SuperFlash EEPROM
SST28SF040A / SST28VF040A

5

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP

FIGURE 3: P

IN ASSIGNMENTS FOR 32-PIN PDIP

A11

A9

A8
A13
A14
A17

WE#
V

DD

A18
A16
A15
A12

A7

A6

A5

A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V

SS

DQ2
DQ1
DQ0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

310 ILL F01.2

Standard Pinout

T op Vie w

Die Up

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-pin
PDIP

T op Vie w

310 ILL F19.0

A18
A16
A15
A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2
V

SS

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

DD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A18-A

8

Row Address Inputs To provide memory addresses. Row addresses define a sector.

A7-A

0

Column Address Inputs Selects the byte within the sector

DQ

7

-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

1

OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.

1

V

DD

Power Supply To provide: 5.0V supply (±10%) for SST28SF040A

2.7V supply (2.7-3.6V) for SST28VF040A

V

SS

Ground

T2.2 310

1. This pin is internally pull-up with a resistor.

6

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read V

IL

V

IL

V

IH

D

OUT

A

IN

Byte-Program V

IL

V

IH

V

IL

D

IN

A

IN,

See Table 4

Sector-Erase V

IL

V

IH

V

IL

D

IN

A

IN,

See Table 4

Standby V

IH

X

1

X High Z X

Write Inhibit X V

IL

X High Z/ D

OUT

X

XXV

IH

High Z/ D

OUT

X

Software Chip-Erase V

IL

V

IH

V

IL

D

IN

See Table 4
Product Identification
Hardware Mode V

IL

V

IL

V

IH

Manufacturer’s ID (BFH)
Device ID (04H)

A18-A1=VIL, A9=VH, A0=V

IL

A18-A1=VIL, A9=VH, A0=V

IH

Software Mode V

IL

V

IL

V

IH

See Table 4
SDP Enable & Disable Mode V

IL

V

IL

V

IH

See Table 4
Reset V

IL

V

IH

V

IL

See Table 4

T3.4 310

1. X can be VIL or VIH, but no other value.

TABLE 4: SOFTWARE COMMAND SUMMARY

Command Summary

Required Setup Command Cycle Execute Command Cycle

Cycle(s) Type

1

1. Type definition: W = Write, R = Read, X can be VIL or VIH, but no other value.

Addr

2,3

2. Addr (Address) definition: SA = Sector Address = A18 - A8, sector size = 256 Bytes; A7- A0 = X for this command.

3. Addr (Address) definition: PA = Program Address = A

18

- A0.

Data

4

4. Data definition: PD = Program Data, H = number in hex.

Type

1

Addr

2,3

Data4SDP

5

5. SDP = Software Data Protect mode using 7 Read Cycle Sequence.
a) Y = the operation can be executed with protection enabled
b) N = the operation cannot be executed with protection enabled

Sector-Erase 2 W X 20H W SA D0H N
Byte-Program 2 W X 10H W PA PD N
Chip-Erase

6

6. The Chip-Erase function is not supported on SST28VF040A industrial parts.

2 W X 30H W X 30H N
Reset 1 W X FFH Y
Read-ID 2 W X 90H R

7

7. Address 0000H retrieves the Manufacturer’s I D of BFH and address 0001H retrieves the Device ID of 04H.

7

Y

Software Data Protect 7 R

8

8. Refer to Figure 11 for the 7 Read Cycle sequence for Software_Data_Protect.

Software Data Unprotect 7 R

9

9. Refer to Figure 10 for the 7 Read Cycle sequence for Software_Data_Unprotect.

T4.3 310

TABLE 5: MEMORY ARRAY DETAIL

Sector Select Byte Select

A

18

- A

8

A7 - A

0

T5.0 310

Data Sheet

4 Mbit SuperFlash EEPROM
SST28SF040A / SST28VF040A

7

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause pe r manent dama ge to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater tha n those defined in the ope rational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

DD

+ 0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to V

DD

+ 1.0V

Voltage on A

9

Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circ uit Curr ent

1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST28S F040A

Range Ambient Temp V

DD

Commercial 0°C to +70°C5.0V±10%
Industrial -40°C to +85°C5.0V±10%

OPERATING RANGE FOR SST28V F040A

Range Ambient Temp V

DD

Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate andC

L

= 100 pF for SST28SF040A

C

L

= 100 pF for SST28VF040A

See Figures 14 and 15

8

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

©2001 Silicon Storage Technology, Inc. S71077-04-000 6/01 310

TABLE 6: DC OPERATING CHARACTERISTICS FOR SS T2 8SF040A

Symbol Parameter

Limits

Test ConditionsMin Max Units

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

V

DD=VDD

Max

Read 32 mA CE#=OE#=V

IL

, WE#=VIH, all I/Os open

Program and Erase 40 mA CE#=WE#=V

IL

, OE#=VIH, VDD=VDD Max

I

SB1

Standby VDD Current
(TTL input)

3mACE#=VIH, VDD=VDD Max

I

SB2

Standby VDD Current
(CMOS input)

20 µA CE#=VDD-0.3V, VDD=VDD Max

I

LI

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

I

LO

Output Leakage Current 10 µA V

OUT

=GND to VDD, VDD=VDD Max

V

IL

Input Low Voltage 0.8 V VDD=VDD Min

V

IH

Input High Voltage 2.0 V VDD=VDD Max

V

OL

Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

V

OH

Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

V

H

Supervoltage for A

9

11.6 12.4 V CE#=OE#=VIL, WE#=V

IH

I

H

Supervoltage Current for A

9

200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T6.4 310

TABLE 7: DC OPERATING CHARACTERISTICS FOR SS T2 8VF040A

Symbol Parameter

Limits

Test ConditionsMin Max Units

I

DD

Power Supply Current Address input=VIL/VIH, at f=1/TRC Min,

V

DD=VDD

Max
Read 10 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Program and Erase 25 mA CE#=WE#=V

IL

, OE#=VIH, VDD=VDD Max

I

SB2

Standby VDD Current
(CMOS input)

20 µA CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max

I

LI

Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

I

LO

Output Leakage Current 10 µA V

OUT

=GND to VDD, VDD=VDD Max

V

IL

Input Low Voltage 0.8 V VDD=VDD Min

V

IH

Input High Voltage 2.0 V VDD=VDD Max

V

OL

Output Low Voltage 0.4 V IOL=100 µA, VDD=VDD Min

V

OH

Output High Voltage 2.4 V IOH=-100 µA, VDD=VDD Min

V

H

Supervoltage for A

9

11.6 12.4 V CE#=OE#=VIL, WE#=V

IH

I

H

Supervoltage Current for A

9

200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T7.4 310