Silicon Labs Si5386 Reference Manual

Si5386 Rev. E Reference Manual
Overview
This Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the device in end applications. The official device specifications can be found in the Si5386 datasheet.
The Si5386
mable via an SPI or I2C serial interface and is easily stored in non-volatile memory (NVM) for applications which require preconfigured clocks at start-up or after reset.
Work Flow Expectations with ClockBuilder™ Pro and the Register Map
This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is im-
portant to understand that the intent is for customers to use the ClockBuilder™ Pro soft­ware to provide the initial configuration for the device. Although the register map is docu­mented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequen­cy plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.
Si5386
RELATED DOCUMENTS
• Si5386 Data Sheet
• Si5386
• Si5386A-E-EVB User Guide
• Si5386A-E-EVB Schematics, BOM and
• IBIS models
• To download evaluation board design and
• JESD204B subclass 0 and subclass 1
Device Errata
Layout
support files, see the Si534x/8x Evaluation
Kit
support
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Table of Contents

1. Functional Description............................
1.1 DSPLL.................................5
1.2 LTE Frequency Configuration .........................5
1.3 Configuration for JESD204B Subclass 1 Clock Generation ...............7
1.4 DSPLL Loop Bandwidth ...........................8
1.4.1 Fastlock ...............................8
1.4.2 Holdover Exit Bandwidth .........................9
1.5 Dividers Overview .............................9
2. Modes of Operation ............................10
2.1 Reset and Initialization ...........................11
2.1.1 Updating Registers During Device Operation ..................12
2.1.2 NVM Programming ...........................13
2.2 Free Run Mode ..............................13
2.3 Lock Acquisition Mode ...........................13
2.4 Locked Mode ..............................13
2.5 Holdover Mode ..............................14
5
3. Clock Inputs (IN0, IN1, IN2, IN3) .......................17
3.1 Input Source Selection ...........................17
3.1.1 Manual Input Selection ..........................17
3.1.2 Automatic Input Switching .........................18
3.2 Types of Inputs ..............................19
3.2.1 Hitless Input Switching with Phase Buildout ...................20
3.2.2 Ramped Input Switching .........................21
3.2.3 Glitchless Input Switching .........................21
3.2.4 Unused Inputs.............................21
3.3 Fault Monitoring .............................22
3.3.1 Input LOS (Loss-of-Signal) Detection .....................22
3.3.2 XAXB Reference Clock LOSXAXB (Loss-of-Signal) Detection ............22
3.3.3 Input OOF (Out-of-Frequency) Detection ....................24
3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin .........26
3.3.5 Device Status Monitoring .........................28
3.3.6 INTRb Interrupt Configuration .......................29
4. Output Clocks ..............................31
4.1 Output Crosspoint Switch ..........................31
4.1.1 Output R Divider Synchronization ......................32
4.2 Performance Guidelines for Outputs .......................33
4.2.1 Optimizing Output Phase Noise .......................34
4.3 Output Signal Format ............................34
4.4 Output Driver Supply Select .........................35
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4.5 Differential Outputs ............................36
4.5.1 Differential Output Terminations.......................36
4.5.2 Differential Output Amplitude Controls.....................37
4.5.3 Differential Output Common Mode Voltage Selection................37
4.5.4
4.6 LVCMOS Outputs .............................38
4.6.1 LVCMOS Output Terminations .......................39
4.6.2 LVCMOS Output Impedance and Drive Strength Selection..............40
4.6.3 LVCMOS Output Signal Swing .......................40
4.6.4 LVCMOS Output Polarity .........................41
4.7 Output Enable/Disable ...........................42
4.7.1 Output Driver State When Disabled .....................43
4.7.2 Synchronous Output Enable/Disable Feature ..................43
4.7.3 Automatic Output Disable During LOL.....................44
4.7.4 Automatic Output Disable During LOSXAXB ..................44
4.7.5 Output Driver Disable Source Summary ....................45
4.8 Output Delay Control ............................46
Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML ........38
5. Zero Delay Mode .............................47
6. Serial Interface .............................. 49
6.1 I2C Interface ...............................51
6.2 SPI Interface...............................53
7. Field Programming ............................58
8. XAXB External References .........................59
8.1 Performance of External References ......................59
9. XO and Device Circuit Layout Recommendations................. 60
9.1 Si5386 64-Pin QFN External XO Layout Recommendations ...............60
10. Power Management ...........................66
10.1 Power Management Features ........................66
10.2 Power Supply Recommendations .......................66
10.3 Power Supply Sequencing .........................67
10.4 Grounding Vias .............................67
11. Base vs. Factory Preprogrammed Devices ...................68
11.1 "Base" Devices (a.k.a. "Blank" Devices) .....................68
11.2 "Factory Preprogrammed" (Custom OPN) Devices .................68
11.3 Part Numbering Summary..........................68
12. Register Map ..............................69
12.1 Page 0 Registers.............................69
12.2 Page 1 Registers.............................83
12.3 Page 2 Registers.............................90
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12.4 Page 3 Registers.............................96
12.5 Page 4 Registers.............................98
12.6 Page 5 Registers.............................99
12.7 Page 9 Registers ............................109
12.8 Page A Registers ...........................111
12.9
Page B Registers ...........................113
12.10 Page C Registers ...........................115
13. Appendix—Custom Differential Amplitude Controls ...............116
14. Revision History.............................117
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Si5386 Rev. E Reference Manual
Functional Description

1. Functional Description

1.1 DSPLL

The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre­quency or freerun from the reference clock. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra­low-phase-noise analog VCO, and a user configurable feedback divider. Use of an external XO provides the DSPLL with a stable low­noise clock source for frequency synthesis and for maintaining frequency accuracy in the Freerun or Holdover modes. No other external components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power supplies and other uncontrolled noise sources that normally exist on printed circuit boards.
The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-vola­tile memory (NVM) or RAM. The combination of input dividers (P0-P3), frequency multiplication (M), output division (N), and output divi­sion (R0A-R9A) allows the generation of a wide range of frequencies on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

1.2 LTE Frequency Configuration

The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory. The flexible combination of dividers and a high frequency VCO allows the device to generate multiple output clock frequencies for appli­cations that require ultra-low phase-noise and spurious performance. The table below shows a partial list of possible output frequencies for LTE applications. The Si5386's DSPLL core can generate up to five unique frequencies. These frequencies are distributed to the output dividers using a configurable crosspoint mux. The output R dividers allow further division for up to 12 unique integer-related fre­quencies on the Si5386. The ClockBuilder Pro software utility provides a simple means of automatically calculating the optimum divider values (P, M, N and R) for the frequencies listed below. In addition to the LTE frequencies, the Si5386 device can simultaneously gen­erate wireline clocks like 156.25 MHz, 155.52 MHz, 125 MHz, etc. and system clocks like 100 MHz, 33 MHz, 25 MHz, etc.
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Table 1.1. Example List of Possible LTE Clock Frequencies
Si5386 Rev. E Reference Manual
Functional Description
LTE Device Clock Fout (MHz)
15.36
19.20
30.72
38.40
61.44
76.80
122.88
153.60
184.32
245.76
307.20
368.64
491.52
614.40
737.28
1
983.04
1228.80
1474.56
1638.4
1843.2
2106.51428571
2457.6
2949.12
Note:
1.
R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks.
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1.3 Configuration for JESD204B Subclass 1 Clock Generation

Si5386 Rev. E Reference Manual
Functional Description
The Si5386
can be used as a high-performance, fully-integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete
VCXO and loop filter components. The Si5386 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks (DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF clocks to drive JESD204B ADCs, DACs, FPGAs, or other logic devices. The Si5386 will clock up to six JESD204B subclass 1 targets, using six DCLK/SYSREF pairs. If SYSREF clocking is implemented in external logic, then the Si5386 can clock up to 12 JESD204B targets. Not limited to JESD204B applications, each of the 12 outputs is individually configurable as a high performance output for tradi­tional clocking applications.
For applications which require adjustable static delay between the DCLK and SYSREF signals, the Si5386 supports up to four DCLK/ SYSREF pairs, each with independently adjustable delay. An example of an adjustable delay JESD204B frequency configuration is shown in the following figure. In this case, the N0 divider determines the device clock frequencies while the N1-N4 dividers generate the divided SYSREF used as the lower frequency frame clock. Each output N divider also includes a configurable delay (Δt) for controlling deterministic latency. This example shows a configuration where all the device clocks are controlled by a single delay (Δt0) while the SYSREF clocks each have their own independent delay (Δt1 –Δt4), though other combinations are also possible. The bidirectional de­lay is programmable over ±8.6 ns in 68 ps steps. See 4.8 Output Delay Control for more information on delay control. The SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register writes.
IN_SEL[1:0]
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P
÷P
÷P
÷P
0
1
2
3
DSPLL
÷M
LPFPD
÷5
÷N
VDDO0
÷R
0A
÷R
0
÷R
5
÷R
t
0
0
÷N
1
÷N
2
÷N
3
÷N
4
6
÷R
7
÷R
8
÷R
9
÷R
9A
t
1
÷R
1
t
÷R
2
2
t
3
÷R
3
t
4
÷R
4
OUT0A OUT0Ab
OUT0 OUT0b
VDDO5
OUT5 OUT5b
VDDO6 OUT6 OUT6b
VDDO7 OUT7 OUT7b
VDDO8 OUT8 OUT8b
OUT9 OUT9b
OUT9A OUT9Ab
VDDO9
VDDO1 OUT1 OUT1b
VDDO2 OUT2 OUT2b
VDDO3 OUT3 OUT3b
VDDO4 OUT4 OUT4b
Device Clocks
4x SYSREF
Figure 1.1. Si5386 Block Diagram
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1.4 DSPLL Loop Bandwidth

Si5386 Rev. E Reference Manual
Functional Description
The DSPLL
loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. The DSPLL loop bandwidth register values are determined using ClockBuilder Pro.
Note: After manually changing bandwidth parameters, the BW_UPDATE bit must be set high to latch the new values into operation. This update bit will latch the new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.
Table 1.2. DSPLL Loop Bandwidth Registers
Register Name Hex Address
Function
[Bit Field]
BW_PLL 0x0508[7:0]-0x050D[7:0] Determines the loop BW for the DSPLL.
Parameters are generated by ClockBuilder Pro.
BW_UPDATE 0x0514[0] Writing a 1 to this register bit will latch
Loop, Fastlock, and Holdover Exit BW pa­rameter registers.

1.4.1 Fastlock

Selecting
low DSPLL loop bandwidth (e.g. 1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop band­width settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings up to 4 kHz are available for selection. Fastlock band­width should generally be set from 10x to 100x the loop bandwidth for optimal results. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or disa­bled independently by register control. If enabled, when LOL is asserted Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled.
Note: The BW_UPDATE_PLLx update bit will latch new values for Loop, Fastlock, and Holdover Exit bandwidths simultaneously.
Table 1.3. DSPLL Fastlock Bandwidth Registers
Register Name Hex Address
Function
[Bit Field]
FASTLOCK_BW_PLL 0x050E[5:0]-0x0513[5:0] Determines the Fastlock BW for the DSPLL. Parameters
are generated by ClockBuilder Pro.
FASTLOCK_AUTO_EN 0x052B[0] Auto Fastlock Enable/Disable.
0: Disable Auto Fastlock (default)
1: Enable Auto Fastlock
FASTLOCK_MAN 0x052B[1] Force Fastlock.
0: Normal Operation (default)
1: Force Fastlock
The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in 3.3.4 DSPLL
Lock) Detection and the LOLb Output Indicator Pin.
LOL
(Loss-of-
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1.4.2 Holdover Exit Bandwidth

Si5386 Rev. E Reference Manual
Functional Description
In additional
to the Loop and Fastlock bandwidths, a user-selectable bandwidth is available when exiting holdover and locking or relock­ing to an input clock when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the Loop bandwidth by default. Note that the BW_UPDATE bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.
Table 1.4. DSPLL Holdover Exit Bandwidth Registers
Register Name Hex Address
Function
[Bit Field]
HOLDEXIT_BW 0x059D[5:0]–0x05A2[5:0] Determines the Holdover Exit BW for the
DSPLL. Parameters are generated by ClockBuilder Pro.

1.5 Dividers Overview

There are
four divider classes within the Si5386. Figure 1.1 Si5386 Block Diagram on page 7 shows all of these dividers. All divider
values for the Si5386 may be either Fractional or Integer. For best phase noise performance, integer dividers are preferred..
• P0-P3: Input clock wide range dividers (0x0208–0x022F)
• 48-bit numerator, 32-bit denominator
Min. value is 1; Max. value is 224 (Fractional-P divisors must be > 5)
• Practical range limited by phase detector and VCO range
• Each divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset All will also update the P divider values
• M: DSPLL feedback divider (0x0515–0x051F)
• 56-bit numerator, 32-bit denominator
Min. value is 5, Max. value is 224 (Fractional-M divisors must be > 10)
• Practical range limited by phase detector and VCO range
• The M divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset will also update M divider values.
• The DSPLL includes an additional divide-by-5 in the feedback path. Manually calculated M divider register values must be adjus­ted accordingly.
• N: Output divider (0x0302-0x0338)
• 44-bit numerator, 32-bit denominator
Min. value is 5, Max. value is 224 (Fractional-M divisors must be > 10)
• Each N divider has an update bit that must be written to cause a newly written divider value to take effect.
• Soft Reset will also update N divider values.
• R: Final output divider (0x0247-0x026A)
• 24-bit field
Min. value is 2, Max. value is 225-2
• Only even integer divide values: 2,4,6, etc.
• R Divisor=2 x (Field +1). For example, Field=3 gives an R divisor of 8.
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Si5386 Rev. E Reference Manual
Modes of Operation

2. Modes of Operation

After initialization, the DSPLL will operate in one of the following modes: Free-run, Lock-Acquisition, Locked, or Holdover. These modes are described further in the sections below.
Power-Up
Reset and
Initialization
No valid input
clocks available
for selection
No valid
input clocks
selected
An input is
qualified and
available for
selection
Holdover
Mode
Free-run
Lock Acquisition
(Fast Lock)
Input Clock
Yes
Holdover
History
Valid?
No
Valid input clock
selected
Switch
Yes
No
Phase lock on selected
is achieved
clock
Locked
Mode
Other Valid
Clock Inputs
Available?
input
Selected input
clock
fails
Figure 2.1. Modes of Operation
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2.1 Reset and Initialization

Si5386 Rev. E Reference Manual
Modes of Operation
Once power
is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the SPI or I2C serial interface is possible once this initialization period is complete. No output clocks will be generated until the initialization is complete.
There are two types of resets available. A Hard Reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the serial interface, will be restored to their initial state. A Hard Reset is initiated using the RSTb pin or by asserting the Hard Reset bit. A Soft Reset bypasses the NVM download and is used to initiate in-system register configuration changes. The table below lists the reset and control registers.
Table 2.1. Reset Registers
Register Name Hex Address
Function
[Bit Field]
HARD_RST 0x001E[1] Writing a 1 to this register bit performs the same func-
tion as power cycling the device. All registers will be restored to their NVM values.
SOFT_RST 0x001C[0] Writing a 1 to this register bit performs a Soft Reset of
the device. Initiates register configuration changes without reloading NVM.
Power-Up
Hard Reset bit
asserted
RSTb
pin asserted
NVM download
Soft Reset bit
asserted
Initialization
Serial interface ready
Figure 2.2. Initialization from Hard Reset and Soft Reset
The Si5386 is
configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from
fully internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD and VDDA pins.
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2.1.1 Updating Registers During Device Operation

Si5386 Rev. E Reference Manual
Modes of Operation
If certain
registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefi­nitely). Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following special sequence of writes. The following are the affected registers:
Control Register(s)
P0_NUM / P0_DEN 0x0208 – 0x0211
P1_NUM / P1_DEN 0x0212 – 0x021B
P2_NUM / P2_DEN 0x021C – 0x0225
P3_NUM / P3_DEN 0x0226 – 0x022F
Px_UPDATE 0x0230
P0_FRACN_MODE / P0_FRAC_EN 0x0231
P1_FRACN_MODE/ P1_FRAC_EN 0x0232
P2_FRACN_MODE / P2_FRAC_EN 0x0233
P3_FRACN_MODE/ P3_FRAC_EN 0x0234
MXAXB_NUM / MXAXB_DEN 0x0235 – 0x023E
MXAXB_UPDATE 0x023F
PLL lockup can easily be avoided by using the following the preamble and postamble write sequence when one of these registers is modified during
device operation. ClockBuilder Pro software adds these writes to the output file by default when Exporting Register
Files.
1. To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:
Register Value
0x0B24 0xC0
0x0B25 0x00
0x0540 0x01
2. Wait 625 ms for the device state to stabilize.
3. Then modify all desired control registers.
4.
Write 0x01 to Register 0x001C (SOFT_RST) to perform a Soft Reset once modifications are complete.
5. Write the postamble by updating the following control bits using Read/Modify/Write sequences:
Register Value
0x0540 0x00
0x0B24 0xC3
0x0B25 0x02
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2.1.2 NVM Programming

Si5386 Rev. E Reference Manual
Modes of Operation
The NVM
is two-time writable by the user. Once a new configuration has been written to NVM, the old configuration is no longer acces-
sible.
While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:
• VDD and VDDA power must both be stable throughout the process.
• No additional registers may be written during the polling. This includes the page register at address 0x01. DEVICE_READY is avail­able on every register page, so no page change is needed to read it.
• Only the DEVICE_READY register (0xFE) should be read during this time.
The procedure for writing registers into NVM is as follows:
1. Write all registers as needed. Verify device operation before writing registers to NVM.
2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the contents of the NVM bank.
3. Write 0xC7 to NVM_WRITE register.
4. Poll DEVICE_READY until DEVICE_READY=0x0F.
5. Set NVM_READ_BANK 0x00E4[0]=1.
6. Poll DEVICE_READY until DEVICE_READY=0x0F.
Alternatively, Steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the de­vice to generate a POR. All of these actions will load the new NVM contents back into the device registers.
Note that the I2C_ADDR setting in register 0x000B is not saved as part of this NVM write procedure. To update this register in a non­volatile way, the "Si534x8x I2C Address Burn Tool" allows updating this value one time. This utility is included in the ClockBuilder Pro installation and can be accessed under the "Misc" folder in the installation directory.
Table 2.2. NVM Programming Registers
Register Name Hex Address
Function
[Bit Field]
ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.
NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.
NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.
DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept com-
mands when value = 0x0F.

2.2 Free Run Mode

Once power
is applied to and initialization is complete the DSPLL will automatically enter Freerun mode, generating the output frequen­cies determined by the NVM. The frequency accuracy of the generated output clocks in Freerun mode is entirely dependent on the frequency accuracy of the XAXB reference clock. Any temperature drift of this frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and lower wander while in Freerun or Hold­over modes. Since there is little jitter attenuation from the XAXB pins to the clock outputs, devices should use a low-jitter XAXB refer­ence clock to minimize output clock jitter.

2.3 Lock Acquisition Mode

The device monitors all inputs for a valid clock. If a valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the Fastlock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

2.4 Locked Mode

Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point, the XAXB reference clock frequency drift does not affect the output frequency. A loss of lock pin (LOLb) and status bit indicate when lock is achieved. See 3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin for more details on the operation of the loss of lock circuit.
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2.5 Holdover Mode

Si5386 Rev. E Reference Manual
Modes of Operation
The DSPLL
will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the out­put clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. This delay value allows recent frequency information to be ignored for Holdover in cases where the input clock source frequency changes as it is removed.
Clock Failure
and Entry into
Holdover
Historical Frequency Data Collected
time
120s
Programmable historical data window
used to
determine the final holdover value
1s,10s, 30s, 60s
Programmable delay
30ms, 60ms, 1s,10s, 30s, 60s
0s
Figure 2.3. Programmable Holdover Window
When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Hold­over, the output frequency drift is determined by the reference clock temperature drift. If a clock input becomes valid, the DSPLL will automatically exit the Holdover mode and reacquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is Glitchless and its rate is controlled by the DSPLL band­width or the Fastlock bandwidth, if Fastlock is enabled. These options are register programmable.
The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the output frequency while in holdover and the desired, new output frequency is measured. It is quite possible that the new output clock frequency will not be exactly the same as the holdover output frequency because the new input clock frequency might have changed and the holdover history circuit may have changed the holdover output frequency. The ramp logic calculates the difference in frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop BW values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramping is also used for ramped input clock switching. See 3.2.2 Ramped Input Switching for more information. See AN1057: Hitless Switching using
Si534x/8x Devices for more information on Hitless and Ramped Switching with Rev. E devices.
As shown in Figure 2.1 Modes of Operation on page 10 the Holdover and Freerun modes are closely related. The device will only enter Holdover if a valid clock has been selected long enough for the holdover history to become valid, i.e., HOLD_HIST_VALID = 1. If the clock fails before the combined HOLD_HIST_LEN + HOLD_HIST_DELAY time has been met, HOLD_HIST_VALID = 0 and the device will enter Freerun mode instead. Note that when switching between input clocks with different (non-0 ppm offset) frequencies, the hold­over history requires a time of 2 * HOLD_HIST_LEN + HOLD_HIST_DELAY to update the average frequency value. If a switch is initi­ated before this time, the average holdover frequency will be a value between the old input frequency and the new one.
Note: The Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.
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Table 2.3. Holdover Mode Control Registers
Si5386 Rev. E Reference Manual
Modes of Operation
Register Name Hex Address
Function
[Bit Field]
Holdover Status
HOLD 0x000E[5] DSPLL Holdover status indicator.
0: Normal Operation
1: In Holdover/Freerun Mode:
HOLD_HIST_VALID = 0 ≥ Freerun Mode
HOLD_HIST_VALID = 1 ≥ Holdover Mode
HOLD_FLG 0x0013[5] Holdover indicator sticky flag bit. Remains asserted after the indi-
cator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
HOLD_INTR_MSK 0x0019[5] Masks Holdover/Freerun from generating INTRb interrupt.
0: Allow Holdover/Freerun interrupt (default)
1: Mask (ignore) Holdover/Freerun for interrupt
HOLD_HIST_VALID 0x053F[1] Holdover historical frequency data valid.
0: Incomplete Holdover history, Freerun mode available
1: Valid Holdover history, Holdover mode available
Holdover Control and Settings
HOLD_HIST_LEN 0x052E[4:0] Window Length time for historical average frequency used in
Holdover mode. Window Length in seconds (s):
Window Length = (2
HOLD_HIST_LEN
- 1) x 8 / 3 x 10
HOLD_HIST_DELAY 0x052F[4:0] Delay Time to ignore data for historical average frequency in
Holdover mode. Delay Time in seconds (s):
Delay Time = 2
HOLD_HIST_DELAY
x 2 / 3 x 10
-7
FORCE_HOLD 0x0535[0] Force the device into Holdover mode. Used to hold the device
output clocks while retraining an upstream input clock.
0: Normal Operation
1: Force Holdover/Freerun Mode:
HOLD_HIST_VALID = 0 =>Freerun Mode
HOLD_HIST_VALID = 1 =>Holdover Mode
Holdover Exit Control
HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass
0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Hold­over
-7
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Si5386 Rev. E Reference Manual
Modes of Operation
Register Name Hex Address
Function
[Bit Field]
HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit
HOLDEXIT_BW_SEL1 0x052C[4] Select the exit bandwidth from Holdover when ramped exit is not
selected (HOLD_RAMP_BYP = 1).
00: Use Fastlock bandwidth on Holdover exit
01: Use Holdover Exit bandwidth on Holdover exit (default)
10, 11: Use Normal Loop bandwidth on Holdover exit
RAMP_STEP_INTERVAL 0x052C[7:5] Time Interval of the frequency ramp steps when ramping between
inputs or exiting holdover.
RAMP_STEP_SIZE 0x05A6[2:0] Size of the frequency ramp steps when ramping between inputs
or exiting holdover.
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Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)

3. Clock Inputs (IN0, IN1, IN2, IN3)

3.1 Input Source Selection

The inputs accept both standard format inputs and DC coupled CMOS clocks. Input selection from CLK_SWITCH_MODE can be man­ual (pin or register controlled) or automatic with user definable priorities. Register bit 0x052A[0] (IN_SEL_REG_CTRL) is used to select manual pin or register control, and to configure the input as shown in the table below.
Table 3.1. Input Selection Control Registers
Register Name Hex Address
CLK_SWITCH_MODE 0x0536[1:0] Selects manual or automatic switching modes. Automatic
IN_SEL_REGCTRL 0x052A[0] Manual Input Select control source.
IN_SEL 0x052A[3:1] Manual Input Select selection register.
.

3.1.1 Manual Input Selection

In manual mode, CLK_SWITCH_MODE=0x00.
Function
[Bit Field]
mode can be Revertive or Non-revertive. Selections are the following:
00: Manual (default)
01: Automatic Non-revertive
02: Automatic Revertive
03: Reserved
0: Pin controlled input clock selection (default)
1: IN_SEL register input clock selection
0: IN0 (default), 1: IN1, 2: IN2, 3: IN3/FB_IN, 4-7: Reserved
Input switching
can be done manually using the IN_SEL[1:0] device pins from the package or through register 0x052A IN_SEL[2:1]. Bit 0 of register 0x052A determines if the input selection is pin selectable or register selectable. The default is pin selectable. The following table describes the input selection on the pins. Note that when Zero Delay Mode is enabled, the FB_IN pins will become the feedback input and IN3 therefore is not available as a clock input. If there is not a valid clock signal on the selected input, the device will automati­cally enter Freerun or Holdover mode. See Chapter 5. Zero Delay Mode for further information.
Table 3.2. Manual Input Selection using IN_SEL[1:0] Pins
IN_SEL[1:0] PINS DSPLL Input Source
00 IN0
01 IN1
10 IN2
11
IN3
1
Note:
1.
IN3 not available as a DSPLL source in ZDM.
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3.1.2 Automatic Input Switching

In automatic mode CLK_SWITCH_MODE = 0x01 (Non-revertive) or 0x02 (Revertive).
Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Automatic input
switching is available in addition to the manual selection described previously in 3.1.1 Manual Input Selection. In auto­matic mode, the switching criteria is based on input clock qualification, input priority and the revertive option. The IN_SEL[0/1] pins and IN_SEL 0x052A[3:1] register bits are not used in automatic input switching. Also, only input clocks that are valid (i.e., with no active fault indicators) can be selected by the automatic clock switching. If there are no valid input clocks available, the DSPLL will enter Holdover or Freerun mode. With Revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With Non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid, an automatic switchover to the highest priority valid input will be initi­ated. Note that automatic input switching is not available in Zero Delay Mode. See section 5. Zero Delay Mode for further information.
Table 3.3. Automatic Input Switching Registers
Register Name Hex Address
Function
[Bit Field]
IN_LOS_MSK 0x0537[3:0] Enables the use of IN3 - IN0 LOS status in determining a val-
id clock for automatic input selection.
0: Use LOS in automatic clock switching logic (default)
1: Mask (ignore) LOS from the automatic clock switching log­ic
IN_OOF_MSK 0x0537[7:4] Determines the OOF status for IN3 - IN0 and is used in de-
termining a valid clock for the automatic input selection.
0: Use OOF in the automatic clock switching logic (default)
1: Mask (ignore) OOF from the automatic clock switching log­ic
IN0_PRIORITY 0x0538[2:0] IN0 - IN3 priority assignment for the automatic switching
IN1_PRIORITY 0x0538[6:4]
IN2_PRIORITY 0x0539[2:0]
IN3_PRIORITY 0x0539[6:4]
state machine. Priority assignments in descending impor­tance are:
1, 2, 3, 4, or 0 for never selected
5-7: Reserved
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3.2 Types of Inputs

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Each of
the four different inputs IN0-IN3/FB_IN can be configured as standard LVDS, LVPECL, HCL, CML, and AC-coupled single­ended LVCMOS formats, or as DC-coupled CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac­coupled and use the “Standard” Input Buffer selection as these pins are internally dc biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals, having a duty cycle much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be termi­nated near the device input pins as shown in the figure below. The resistor divider values given below will work with up to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance over Pulsed CMOS.
Standard AC Coupled Differential LVDS
Si5386
3.3V, 2.5V
L
VDS or CML
50
50
INx
100
INx
Standard
Pulsed CMOS
Standard AC Coupled Differential LVPECL
Si5386
3.3V, 2.5V LVPECL
50
50
INx
100
INx
Standard
Pulsed CMOS
3.3V, 2.5V, 1.8V LVCMOS
3.3V, 2.5V, 1.8V LVCMOS
IN_CMOS_USE1P8 = 1, at address 0x094F
Pulsed CMOS DC Coupled Single Ended
3.3V, 2.5V, 1.8V LVCMOS
VDD R1 ( ) R2 ( )
1.8V 324 665
2.5V 511 475
3.3V 634 365
Standard AC Coupled Single Ended
50
INx
INx
DC Coupled CMOS
50
50
R1
R
2
INx
X
INx
INx
INx
Standard
Pulsed CMOS
Standard
CMOS
Standard
Pulsed CMOS
Si5386
Si5386
Si5386
Figure 3.1. Input Termination for Standard and CMOS Inputs
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Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down shown in the figure above, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to con­nect the inverting INb input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.
and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as
Table 3.4. Input Clock Configuration Registers
Register Name Hex Address
Function
[Bit Field]
IN_EN 0x0949[3:0] Enable (or powerdown) the IN3 – IN0 input buffers.
0: Powerdown input buffer
1: Enable and Power-up input buffer
IN_PULSED_CMOS_EN 0x0949[7:4] Select Pulsed CMOS input buffer for IN3 – IN0.
0: Standard Input Format (default)
1: Pulsed CMOS Input Format
CMOS_HI_THR 0x094F[7:4] CMOS Clock input threshold select for inputs IN3 - IN0.
0: Low threshold (Pulsed CMOS)
1: Standard Threshold - Use with 1.8 V CMOS input clocks

3.2.1 Hitless Input Switching with Phase Buildout

Hitless Switching
is a feature that prevents the phase of an output clock from changing when switching to a new input clock that does not have the same phase as the original input clock. It only makes sense to enable phase buildout when switching between two clocks that are exactly the same frequency (i.e. are frequency locked). When hitless switching phase buildout is enabled (register 0x0536[2] =
1), the DSPLL absorbs the phase difference between the current input clock and the new input clock. When disabled (register 0x0536[2] = 0), the phase difference between the two input clocks will propagate to the output at a rate that is determined by the DSPLL loop bandwidth. Phase buildout hitless switching supports clock frequencies down to the minimum input frequency. Note that Hitless switching is not available in Zero Delay Mode. Input switching events on DSPLL B may affect the outputs of the other A/C/D DSPLLs. See AN1057: Hitless Switching using Si534x/8x Devices for more information on Hitless and Ramped Switching with Rev. E devices.
Table 3.5. Input Hitless Switching
Register Name Hex Address
Function
[Bit Field]
HSW_EN 0x0536[2] Enable Hitless Switching.
0: Disable Hitless switching
1: Enable Hitless switching (phase buildout enabled) (default)
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3.2.2 Ramped Input Switching

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
The DSPLL
has the ability to switch between two input clock frequencies that are up to ±20 ppm apart. When switching between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be enabled to ensure a smooth tran­sition between the two input frequencies. In this situation, it is also advisable to enable hitless switching phase buildout to minimize the input-to-output clock skew after the clock switch ramp has completed. See AN1057: Hitless Switching using Si534x/8x Devices for more information on Hitless and Ramped Switching with Rev. E devices.
When ramped clock switching is enabled, the DSPLL will very briefly go into holdover and then immediately exit from holdover. This means that ramped switching will behave the same as an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency because the transition between the two frequencies will be smooth and linear. Ramped switching should be turned off when switching between input clocks that are always frequency locked (i.e. are the same exact frequency). Because ramped switching avoids frequency transients and over shoot when switching between clocks that are not the same frequency, CBPro defaults to ramped clock switching. The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover, see 2.5 Holdover Mode.
Table 3.6. Ramped Switching Controls
Register Name Hex Address
Function
[Bit Field]
RAMP_SWITCH_EN 0x05A6[3] Enable Ramped Input Switching when HOLD_RAMP_BYP = 0.
0: Disable Ramped Input switching
1: Enable Ramped Input switching (Recommended)
HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass
0: Use Ramp when exiting from Holdover (default)
1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover
RAMP_STEP_INTERVAL 0x052C[7:5] Time Interval of the frequency ramp steps when ramping between in-
puts or exiting holdover. Set by CBPro.
RAMP_STEP_SIZE 0x05A6[2:0] Size of the frequency ramp steps when ramping between inputs or
exiting holdover. Set by CBPro.

3.2.3 Glitchless Input Switching

The DSPLL glitchlessly switches between two input clock frequencies that are up to ±20 ppm apart. The DSPLL will pull-in to the new frequency at a rate determined by either DSPLL loop bandwidth or, if enabled, the Fastlock bandwidth. Depending on the LOL configu­ration settings, the loss of lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency. However, there will never be abnormally shortened “runt” pulses generated at the output during this transition.

3.2.4 Unused Inputs

Unused inputs can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the bits for unused inputs will power down those inputs. For inputs that are enabled but have an inactive clock source, a weak pullup or pulldown resistor may be added to minimize noise pickup.
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3.3 Fault Monitoring

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
The four reference clock is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss of Lock (LOL) indicators asserted when the DSPLL loses synchronization within the feedback loop. The figure below shows the fault monitors for each input path going into the DSPLL.
input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF). Note that the XAXB
OSC
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P
÷P
÷P
÷P
Precision
LOS
0
LOS
1
LOS
2
LOS
3
OOF
OOF
OOF
OOF
Fast
Precision
Fast
Precision
Fast
Precision
Fast
LOL
Feedback
Clock
LOS
XAXB
÷M
DSPLL
LPFPD
÷5
Figure 3.2. Si5386 Fault Monitors

3.3.1 Input LOS (Loss-of-Signal) Detection

The loss the input LOS circuits has its own programmable sensitivity that allows missing edges or intermittent errors to be ignored. LOS sensitivi­ty is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading its status register bit. The live LOS register always displays the current LOS state. Also, there is a sticky flag register which stays asserted until cleared by the user.

3.3.2 XAXB Reference Clock LOSXAXB (Loss-of-Signal) Detection

A LOS detected. This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. The table below lists the loss of signal status indicators and fault monitoring control registers.
of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
Monitor
LOS
en
Figure 3.3. LOS Status Indicator
monitor is also available to ensure that the reference clock is valid. By default the output clocks are disabled when LOSXAXB is
Live
LOS
LOS
Sticky
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Table 3.7. LOS Monitoring and Control Registers
Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name Hex Address
LOS Status and Controls
LOS 0x000D[3:0] LOS status indicators for IN3 - IN0.
LOS_FLG 0x0012[3:0] LOS indicator sticky flag bits for IN3 - IN0. Remains asser-
LOS_INTR_MSK 0x0018[3:0] Masks LOS from generating INTRb interrupt for IN3 - IN0.
LOS_EN 0x002C[3:0] LOS enable bits for IN3 - IN0. Allows disabling LOS moni-
Function
[Bit Field]
0: Input signal detected or input buffer disabled or LOS dis­abled
1: Insufficient Input signal detected (LOS)
ted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
0: Allow LOS interrupt (default)
1: Mask (ignore) LOS for interrupt
tors on unused inputs.
0: Disable input LOS
1: Enable input LOS
LOS_VAL_TIME 0x002D[7:0] LOS clear validation time for IN3 - IN0. This sets the time
that an input must have a valid clock before the LOS condi­tion is cleared. 0: 2 ms, 1: 100 ms, 2: 200 ms, and 3: 1 s
LOS_TRIG_THR 0x002E[7:0]-0x0035[7:0] Sets the LOS trigger threshold and clear sensitivity for IN3 -
LOS_CLR_THR 0x0036[7:0]-0x003D[7:0]
IN0. These values are determined by ClockBuilder Pro.
LOS_EN 0x002C[3:0] Enable LOS detection on IN3 - IN0. 0: Disable LOS Detec-
tion 1: Enable LOS Detection (default)
LOSXAXB Status and Controls
LOSXAXB 0x000C[1] LOS indicator for the XAXB reference clock
0: Reference clock signal detected
1: Reference clock signal not detected
LOSXAXB_FLG 0x0011[1] LOSXAXB status indicator sticky flag bit. Remains asserted
after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
LOSXAXB_INTR_MSK 0x0017[1] Masks LOSXAXB from generating INTRb interrupt.
0: Allow LOSXAXB interrupt (default)
1: Mask (ignore) LOSXAXB for interrupt
LOSXAXB_DIS 0x002C[4] Enable LOS detection on the XAXB reference clock.
0: Enable LOS Detection (default).
1: Disable LOS Detection
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3.3.3 Input OOF (Out-of-Frequency) Detection

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Each input
clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its 0 ppm reference. This
OOF reference can be selected as either:
• XAXB reference clock
• IN0, IN1, IN2, IN3
The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky flag register bit stays asserted until cleared. Note that IN3 is only available as an OOF reference when the device is not in ZDM.
Sticky
OOF
Monitor
Precision
en
LOS
OOF
Fast
en
Figure 3.4. OOF Status Indicator
The Precision OOF monitor circuit measures the frequency of all input clocks to within up to ±1 ppm accuracy with respect to the selec­ted OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency range of up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XAXB reference clock is available. These options are all register configurable.
Live
OOF Declared
Hysteresis Hysteresis
f
IN
OOF Cleared
-6 ppm -4 ppm 0 ppm +4 ppm +6 ppm
(Clear)(Set)
OOF
(Clear) (Set)
Reference
Figure 3.5. Example of Precision OOF Status Monitor Set and Clear Thresholds
The table below lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of fre­quency measurement
accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. However, this may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds more quickly, and has larger thresholds.
Table 3.8. OOF Status Monitoring and Control Registers
Register Name Hex Address
Function
[Bit Field]
OOF Status and Controls
OOF 0x000D[7:4] OOF status indicators for IN3 - IN0.
0: Input signal detected or input buffer disabled or OOF disabled
1: Insufficient Input signal detected (OOF)
OOF_FLG 0x0012[7:4] OOF indicator sticky flag bits for IN3 - IN0. Remains
asserted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
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Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name Hex Address
OOF_INTR_MSK 0x0018[7:4] Masks OOF from generating INTRb interrupt for
Precision OOF Controls
OOF_EN 0x003F[3:0] Enable Precision OOF for IN3 - IN0.
OOF_REF_SEL 0x0040[2:0] Selects clock used for OOF as the 0 ppm refer-
OOF_SET_THR 0x0046[7:0]-0x0049[7:0] OOF Set threshold for IN3 – IN0. Range is up to
OOF_CLR_THR 0x004A[7:0]-0x004D[7:0] OOF Clear threshold for each input. Range is up to
Fast OOF Controls
Function
[Bit Field]
IN3 - IN0.
0: Allow OOF interrupt (default)
1: Mask (ignore) OOF for interrupt
0: Disable Precision OOF
1: Enable Precision OOF
ence. Selections are: XAXB, IN0, IN1, IN2, IN3. De­fault is XAXB. Note that IN3 may not be used when the device is in ZDM.
±500 ppm in steps of 1/16 ppm.
±500 ppm in steps of 1/16 ppm.
FAST_OOF_EN 0x003F[7:4] Enable Fast OOF for IN3 - IN0.
0: Disable Precision OOF
1: Enable Precision OOF
FAST_OOF_SET_THR 0x0051[7:0]-0x0054[7:0] Fast OOF Set threshold for IN3 - IN0. Range is
from ±1,000 ppm to ±16,000 ppm in 1000 ppm steps.
FAST_OOF_CLR_THR 0x0055[7:0]-0x0058[7:0] OOF Clear threshold for each input. Range is from
±1,000 ppm to ±16,000 ppm in 1,000 ppm steps.
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3.3.4 DSPLL LOL (Loss-of-Lock) Detection and the LOLb Output Indicator Pin

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
The Loss is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency differ­ence between the input and feedback clocks at the phase detector. There are four parameters to the LOL monitor.
1. Assert to set the LOL.
2. Fast assert to set the LOL.
3. De-assert to clear the LOL.
4. Clear delay.
A block diagram of the LOL monitor is shown in the figure below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL monitor.
of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There
a. User sets the threshold in ppm in CBPro.
a. CBPro sets this to ~100 times the assert threshold.
b. A very large ppm error in a short time will assert the LOL.
a. User sets the threshold in ppm in CBPro.
a. CBPro sets this based upon the project plan.
LOL Monitor
LOL
Clear
Timer
LOS
LOL
Sticky
LOL
Set
Live
LOLb
DSPLL
f
IN
LPFPD
Feedback
Clock
÷M
The LOL frequency monitor has an adjustable sensitivity which is register-configurable from ±1 ppm to ±10,000 ppm. Having two sepa­rate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is indica­ted when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there's more than 10 ppm frequency difference is shown in the figure below.
LOL Declared
Locked
Loss of
Lock
-10 ppm -0.1 ppm
÷5
Figure 3.6. Si5386 LOL Status Indicator
Lock
Acquisition
Hysteresis Hysteresis
0 ppm
(Clear)(Set)
Phase Detector Frequency Difference
+0.1 ppm +10 ppm
(Clear) (Set)
Loss of
Lock
f
DIFF
Figure 3.7. Example of LOL Set and Clear Thresholds
A timer delays clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the inpujt clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility. It is important to know that, in addition to being a status bit, LOL automatically enables Fastlock by default.
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Table 3.9. LOL Status Monitor and Control Registers
Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name Hex Address
Function
[Bit Field]
LOL 0x000E[1] LOL status indicator for the DSPLL.
0: DSPLL Locked to input clock
1: DSPLL Not locked to an input clock
LOL_FLG 0x0013[1] LOL indicator sticky flag bit. Remains as-
serted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
LOL_INTR_MSK 0x0019[1] Masks LOL from generating INTRb inter-
rupt.
0: Allow LOL interrupt (default)
1: Mask (ignore) LOL for interrupt
LOL_SLW_SET_THR 0x009E[7:4] Configures the loss of lock set thresholds.
Selectable as 1,3,10,30,100,300,1000,3000,10000. Val­ues are in ppm.
LOL_SLW_CLR_THR 0x00A0[7:4] Configures the loss of lock set thresholds.
Selectable as
0.1,0.3,1,3,10,30,100,300,1000,3000,1000
0. Values are in ppm.
LOL_CLR_DELAY_DIV256 0x00A9[7:0]-0x00AC[4:0] This is a 29-bit register that configures the
delay value for the LOL Clear delay. This value depends on the DSPLL frequency configuration and loop bandwidth. It is cal­culated using the ClockBuilder Pro utility.
LOL_TIMER_EN 0x00A2[1] Enable for the LOL Clear Timer.
0: Disable LOL clear timer
1: Enable LOL clear timer
LOL_FST_EN 0x0092[1] Fast LOL Enable. Large input frequency er-
rors will quickly assert LOL when enabled.
0: Disable Fast LOL
1: Enable Fast LOL (default)
The settings in the above table are handled by ClockBuilder Pro. Manual settings should be avoided.
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3.3.5 Device Status Monitoring

Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
In addition
to the input-driven LOS, LOSXAXB, OOF, LOL, and HOLD fault monitors discussed previously, there are several additional status monitors which may be useful in determining the device operating state. While some of these indicators may seem redundant, they are either taken from different locations in the device or are active in different operating modes. These indicators can provide fur­ther insight into the operating state of the device.
Table 3.10. Device Status Monitoring and Control Registers
Register Name
Hex Address
[Bit Field]
Function
Device in Calibration status indicator.
SYSINCAL 0x000C[0]
0: Normal Operation
1: Device in Calibration
LOS status indicator for XAXB reference clock.
LOSREF 0x000C[2]
0: Reference clock signal detected
1: Insufficient reference clock signal detec­ted
XAXB reference clock locking status indica­tor.
XAXB_ERR 0x000C[3]
0: Locked to reference clock
SMBUS_TMOUT 0x000C[5]
CAL 0x000F[5]
SYSINCAL_FLG 0x0011[0]
LOSREF_FLG 0x0011[2]
XAXB_ERR_FLG 0x0011[3]
1: Not locked to reference clock
SMB Bus Timeout Indicator.
0: SMB Bus Timeout has Not occurred
1: SMB Bus Timeout Has occurred
DSPLL in Calibration status indicator.
0: Normal Operation
1: DSPLL in Calibration
SYSINCAL indicator sticky flag bit. Re­mains asserted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
LOSREF indicator sticky flag bit. Remains asserted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
XAXB_ERR indicator sticky flag bit. Re­mains asserted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
SMBUS_TMOUT indicator sticky flag bit. Remains asserted after the indicator bit
SMBUS_TMOUT_FLG 0x0011[5]
shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
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Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name
CAL_FLG 0x0014[5]

3.3.6 INTRb Interrupt Configuration

The INTRb polling may also be used to monitor device status. Each of the status indicator flags is maskable to avoid unwanted assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the unmasked status flag register bit(s) that caused the interrupt. Note that the status flag register bits cannot be cleared if the corresponding status indicator is still showing a fault.
interrupt output pin is a convenient way to monitor a change in state of one or more status indicator flags, though direct
Hex Address
[Bit Field]
LOS_INTR_MSK[3-0]
Function
CAL indicator sticky flag bit. Remains as­serted after the indicator bit shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.
LOS_FLG[3-0]
OOF_INTR_MSK[3-0]
OOF_FLG[3-0]
LOL_INTR_MSK
LOL_FLG
HOLD_FLG
SYSINCAL_FLG
LOSXAXB_FLG
LOSREF_FLG
XAXB_ERR_FLG
SMB_TMOUT_FLG
HOLD_INTR_MSK
INTRb
CAL_INTR_MSK
CAL_FLG
SYSINCAL_INTR_MSK
LOSXAXB_INTR_MSK
LOSREF_INTR_MSK
XAXB_ERR_INTR_MSK
SMB_TMOUT_INTR_MSK
Figure 3.8. Interrupt Pin Source Masking Options
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Table 3.11. INTRb Pin Interrupt Mask Registers
Si5386 Rev. E Reference Manual
Clock Inputs (IN0, IN1, IN2, IN3)
Register Name Hex Address
Function
[Bit Field]
LOS_INTR_MSK 0x0018[3:0] Masks LOS from generating INTRb interrupt for IN3 - IN0.
0: Allow LOS interrupt (default)
1: Mask (ignore) LOS for interrupt
OOF_INTR_MSK 0x0018[7:4] Masks OOF from generating INTRb interrupt for IN3 - IN0.
0: Allow OOF interrupt (default)
1: Mask (ignore) OOF for interrupt
LOL_INTR_MSK 0x0019[1] Masks LOL from generating INTRb interrupt.
0: Allow LOL interrupt (default)
1: Mask (ignore) LOL for interrupt
HOLD_INTR_MSK 0x0019[5] Masks Holdover/Freerun from generating INTRb interrupt.
0: Allow Holdover/Freerun interrupt (default)
1: Mask (ignore) Holdover/Freerun for interrupt
CAL_INTR_MSK 0x001A[5] Masks CAL from generating INTRb interrupt.
0: Allow CAL interrupt (default)
1: Mask (ignore) CAL for interrupt
SYSINCAL_INTR_MSK 0x0017[0] Masks SYSINCAL from generating INTRb interrupt.
0: Allow SYSINCAL interrupt (default)
1: Mask (ignore) SYSINCAL for interrupt
LOSXAXB_INTR_MSK 0x0017[1] Masks LOSXAXB from generating INTRb interrupt.
0: Allow LOSXAXB interrupt (default)
1: Mask (ignore) LOSXAXB for interrupt
LOSREF_INTR_MSK 0x0017[2] Masks LOSREF from generating INTRb interrupt.
0: Allow LOSREF interrupt (default)
1: Mask (ignore) LOSREF for interrupt
XAXB_ERR_INTR_MSK 0x0017[3] Masks XAXB_ERR from generating INTRb interrupt.
0: Allow XAXB_ERR interrupt (default)
1: Mask (ignore) XAXB_ERR for interrupt
SMB_TMOUT_INTR_MSK 0x0017[5] Masks SMB_TMOUT from generating INTRb interrupt.
0: Allow SMB_TMOUT interrupt (default)
1: Mask (ignore) SMB_TMOUT for interrupt
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