ANY-RATE PRECISION CLOCKS
Si5316, Si5319,Si5322, Si5323, SI5324, Si5325,
Si5326, Si5365, Si5366, Si5367, Si5368
F
AMILY REFERENCE MANUAL
Rev. 0.41 10/09 Copyright © 2009 by Silicon Laboratories Si53xx-RM
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si53xx-RM
2 Rev. 0.41
Si53xx-RM
TABLE OF CONTENTS
Section Page
1. Any-Rate Precision Clock Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1. Si5324 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Narrowband Versus Wideband Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Any-Rate Clock Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Si5319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Si5322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4. Si5323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5. Si5325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.6. Si5326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.7. Si5365 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.8. Si5366 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.9. Si5367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.10. Si5368 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. DSPLL (All Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1. Clock Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.1. Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.2. Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.3. Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . .47
6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . .47
6.1.1. Clock Multiplication (Si5316) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.6. Narrowband Performance (Si5316, Si5323, Si5366). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.7. Wideband Performance (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.8. Lock Detect (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.9. Wideband Input-to-Output Skew (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5323, Si5366). . . . . . . . . . . . . 62
6.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)
62
6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366). . . . . . . . . . . . . . 62
6.2.4. Narrowband Input-to-Output Skew (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3. Pin Control Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.3.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4. Digital Hold/VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4.3. Wideband VCO Freeze (Si5322, Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5. Frame Synchronization (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.6. Output Phase Adjust (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.6.1. FSYNC Realignment (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.2. Including FSYNC Inputs in Clock Selection (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.3. FS_OUT Polarity and Pulse Width Control (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.4. Using FS_OUT as a Fifth Output Clock (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.5. Disabling FS_OUT (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366) . . . . 69
6.8. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.9. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . 70
6.9.2. FOS Alarms (Si5365 and Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L) . . . . . . . . . . . . . . . . . . . . . 71
6.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.10. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.11. DSPLLsim Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . 73
7.1. Clock Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.1.1. Jitter Tolerance (Si5319, Si5325, Si5326, Si5367, and Si5368) . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.2. Wideband Mode (Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1.3. Narrowband Mode (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.1.5. Lock Detect (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.2.1. Initiating Internal Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.2. Input Clock Stability during Internal Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.3. Self-Calibration Caused by Changes in Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3. Input Clock Configurations (Si5367 and Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4. Microprocessor Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.4.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.4.2. Automatic Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.4.3. Hitless Switching with Phase Build-Out (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5. Si5319, Si5326, and Si5368 Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.1. Free Run Mode Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.2. Use of LOS_A when in Free Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.3. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.5.4. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.6. Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.6.1. Narrowband Digital Hold (Si5316, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.6.2. Recovery from Digital Hold (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.6.3. VCO Freeze (Si5319, Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.7. Output Phase Adjust (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.7.1. Coarse Skew Control (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.7.2. Fine Skew Control (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.3. Independent Skew (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.4. Output-to-output Skew (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1) . . . . . . . 92
7.8.1. FSYNC Realignment (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.8.2. FSYNC Skew Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.8.3. Including FSYNC Inputs in Clock Selection (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.9. Output Clock Drivers (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . 97
7.9.1. Disabling CKOUTn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si536, Si5368) . . . . . . . . . . . . . . 97
7.10. PLL Bypass Mode (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . 97
7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.11.1. Loss-of-Signal Alarms (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . 98
7.11.2. FOS Algorithm (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.11.3. C1B, C2B (Si5319, Si5325, Si5326) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.11.4. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368 [CK_CONFIG_REG = 0]). . . . . . . . . . . . . . . . 101
7.11.5. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1]) . . . . . . . . . . . . . . . . . . . . . . 102
7.11.6. LOS Algorithm for Reference Clock Input (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.11.7. LOL (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.11.8. Device Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.12. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.13. I2C Serial Microprocessor Interface (Si5325, Si5326, Si5367, Si5368) . . . . . . . .103
7.14. Serial Microprocessor Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.14.1. Default Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.15. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.16. DSPLLsim Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368) . . . . . . . . . . . . 109
8.3. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5326, Si5366, &
Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . .113
8.5. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . 114
9. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10. Packages and Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Appendix A—Narrowband References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Appendix C—Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix D—Alarm Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Appendix E—Internal Pullup, Pulldown by Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Appendix F—Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Rev. 0.41 5
Si53xx-RM
LIST OF FIGURES
1. Any-Rate Precision Clock Product Family Overview
2. Narrowband Versus Wideband Overview
3. Any-Rate Clock Family Members
Figure 1. Si5316 Jitter Attenuator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Si5319 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. Si5322 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Si5323 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 17
Figure 5. Si5325 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 19
Figure 7. Si5365 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Si5366 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 21
Figure 9. Si5367 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . 23
4. Specifications
Figure 11. Differential Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Rise/Fall Time Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Frame Synchronization Timing in Level Sensitive Mode . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Frame Synchronization Timing in One-shot Mode. . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5. DSPLL (All Devices)
Figure 16. Any-Rate Precision Clock DSPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Clock Multiplication Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. PLL Jitter Transfer Mask/Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Jitter Tolerance Mask/Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
Figure 20. Si5316 Divisor Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)
Figure 21. Wideband PLL Divider Settings (Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. Narrowband PLL Divider Settings (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . 76
Figure 23. Si5325 and Si5326 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 24. Si5367 and Si5368 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 25. Free Run Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 26. Parameters in History Value of M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. Frame Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 28. FOS Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. I2C Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 30. SPI Write/Set Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 31. SPI Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8. High-Speed I/O
Figure 32. Differential LVPECL Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 33. Single-Ended LVPECL Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 34. CML/LVDS Termination (1.8, 2.5, 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35. CMOS Termination (1.8, 2.5, 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Si53xx-RM
Figure 36. Typical Output Circuit (Not CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together). . . . . . . 108
Figure 38. Differential Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 39. CKOUT Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 40. CMOS External Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. Sinewave External Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 42. Differential External Reference Input Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 43. Three Level Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 44. Three Level Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9. Power Supply
Figure 45. Typical Power Supply Bypass Network (TQFP Package) . . . . . . . . . . . . . . . . . . 114
Figure 46. Typical Power Supply Bypass Network (QFN Package) . . . . . . . . . . . . . . . . . . . 114
10. Packages and Ordering Guide
Appendix A—Narrowband References
Figure 47. Typical Reference Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Figure 48. Jitter vs. f3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 49. Jitter vs. f3 with FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 50. Reference vs. Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 51. Jitter vs. Reference Frequency (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 52. Jitter vs. Reference Frequency (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Appendix C—Typical Phase Noise Plots
Appendix D—Alarm Structure
Figure 53. Si5326 Alarm Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 54. Si5368 Alarm Diagram (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 55. Si5368 Alarm Diagram (2 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Appendix E—Internal Pullup, Pulldown by Pin
Appendix F—Typical Performance
Document Change List
Contact Information
Rev. 0.41 7
Si53xx-RM
LIST OF TABLES
1. Any-Rate Precision Clock Product Family Overview
Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. Narrowband Versus Wideband Overview
3. Any-Rate Clock Family Members
4. Specifications
Table 2. Recommended Operating Conditions
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage). . . . 25
Table 4. DC Characteristics—Microprocessor Devices (Si5319, Si5325, Si5326, Si5367, Si5368)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 5. DC Characteristics—Narrowband Devices (Si5316, Si5319, Si5323, Si5326, Si5366,
Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. AC Characteristics—All Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Jitter Generation (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) . . . . . . . . . . . . 39
Table 8. Jitter Generation (Si5322, Si5325, Si5365, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. SPI Specifications (Si5319, Si5325, Si5326, Si5367, and Si5368) . . . . . . . . . . . . . . 40
Table 10. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5. DSPLL (All Devices)
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
Table 11. Si5316, Si5322, Si5323, Si5365 and Si5366 Key Features . . . . . . . . . . . . . . . . . . 46
Table 12. Frequency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Input Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. Si5316 BW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) . . . . . . . . . . 53
Table 17. SONET to Datacom Clock Multiplication Settings (FRQTBL = H, CK_CONF = 0) . 57
Table 18. Clock Output Divider Control (DIV34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 19. Si5316, Si5322, and Si5323 Pins and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. Si5365 and Si5366 Pins and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 21. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL = L . . . . . . . . 63
Table 22. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL = L . . . . . . . . . . . . . . . 63
Table 23. Automatic/Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Clock Active Indicators (AUTOSEL = M or H) (Si5322 and Si5323) . . . . . . . . . . . . 64
Table 25. Clock Active Indicators (AUTOSEL = M or H) (Si5365 and Si5367) . . . . . . . . . . . . 64
Table 26. Input Clock Priority for Auto Switching (Si5322, Si5323) . . . . . . . . . . . . . . . . . . . . 64
Table 27. Input Clock Priority for Auto Switching (Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . 65
Table 28. FS_OUT Disable Control (DBLFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 29. Output Signal Format Selection (SFOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 30. DSBL2/BYPASS Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31. Frequency Offset Control (FOS_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. Alarm Output Logic Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 33. Lock Detect Retrigger Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)
Table 34. Si5325, Si5326, Si5367 and Si5368 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . 72
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Table 35. Device Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. Common Divider Settings (Wideband/µP Control Mode - Si5325 and Si5367) . . . 74
Table 37. Common Loop Bandwidth (MHz) (Si5325 and Si5367) . . . . . . . . . . . . . . . . . . . . . 75
Table 38. Narrowband Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 39. Dividers and Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Common Divider Settings (Si5319, Si5326, Si5368). . . . . . . . . . . . . . . . . . . . . . . . 78
Table 41. Common Loop Bandwidth Settings (Si5319, Si5326 and Si5368) . . . . . . . . . . . . . 79
Table 42. Input Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 43. Manual Input Clock Selection (Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. Manual Input Clock Selection (Si5325, Si5326) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 45. Automatic/Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 46. Input Clock Priority for Auto Switching in µP Control Mode . . . . . . . . . . . . . . . . . . 84
Table 47. Digital Hold History Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. Digital Hold History Averaging Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 49. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) . . . . . . . . . . . . . . . . . . . . . . . 92
Table 50. Common NC5 Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 51. Alignment Alarm Trigger Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 52. Output Signal Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. Loss-of-Signal Validation Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. Loss-of-Signal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 55. FOS Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 56. CLKnRATE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 57. Alarm Output Logic Equations (Si5367 and Si5368 [CONFIG_REG = 0]) . . . . . . 100
Table 58. Alarm Output Logic Equations [Si5368 and CKCONFIG_REG = 1] . . . . . . . . . . . 101
Table 59. Lock Detect Retrigger Time (LOCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 60. SPI Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8. High-Speed I/O
Table 61. Output Driver Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 62. Disabling Unused Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9. Power Supply
10. Packages and Ordering Guide
Appendix A—Narrowband References
Table 63. Approved Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 64. XA/XB Reference Sources and Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Table 65. Jitter Values for Figure 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 66. Jitter Values for Figure 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix C—Typical Phase Noise Plots
Appendix D—Alarm Structure
Appendix E—Internal Pullup, Pulldown by Pin
Table 67. Si5316 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 68. Si5322 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 69. Si5323 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 70. Si5325 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 71. Si5326 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Rev. 0.41 9
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Table 72. Si5365 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 73. Si5366 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 74. Si5367 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 75. Si5368 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Appendix F—Typical Performance
Table 76. Output Format vs. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Document Change List
Contact Information
10 Rev. 0.41
Si53xx-RM
1. Any-Rate Precision Clock Product Family Overview
Silicon Laboratories Any-Rate Precision Clock products provide jitter attenuation and clock multiplication/clock
division for applications requiring sub 1 ps rms jitter performance. The device product family is based on Silicon
Laboratories' 3rd generation DSPLL technology, which provides any-rate frequency synthesis and jitter attenuation
in a highly integrated PLL solution that eliminates the need for discrete VCXO/VCSOs and loop filter components.
These devices are ideally suited for applications which require low jitter reference clocks, including OC-48/STM-16,
OC-192/STM-64, OC-768/STM-256, wireless basestations, wireless point-point infrastructure, broadcast video/
HDTV, test & measurement, data acquisition systems, and FPGA/ASIC reference clocking.
Table 1 provides a product selector guide for the Silicon Laboratories Any-Rate Precision Clocks. Two product
families are available. The Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368 are jitter-attenuating clock
multipliers that provide ultra-low jitter generation as low as 0.30 ps RMS. The devices vary according to the number
of clock inputs, number of clock outputs, and control method. The Si5316 is a fixed-frequency, pin controlled jitter
attenuator that can be used in clock smoothing applications. The Si5323 and Si5366 are pin-controlled jitterattenuating clock multipliers. The frequency plan for these pin-controlled devices is selectable from frequency
lookup tables and includes common frequency translations for SONET/SDH, ITU G.709 Forward Error Correction
(FEC) applications (255/238, 255/237, 255/236, 238/255, 237/255, 236/255), Gigabit Ethernet, 10G Ethernet, 1G/
2G/4G/8G/10G Fibre Channel, ATM and HDTV. The Si5319, Si5326, and Si5368 are microprocessor-controlled
devices that can be controlled via an I
inputs ranging from 2 kHz to 710 MHz and generate multiple independent, synchronous clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. Virtually any frequency translation combination across this
operating range is supported. Independent dividers are available for every input clock and output clock, so the
Si5326 and Si5368 can accept input clocks at different frequencies and generate output clocks at different
frequencies. The Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368 support a digitally programmable loop
bandwidth that can range from 60 Hz to 8.4 kHz. An external (37–41 MHz, 55–61 MHz, 109–125.5 MHz, or 163–
180 MHz) reference clock or a low-cost 114.285 MHz 3rd overtone crystal is required for these devices to enable
ultra-low jitter generation and jitter attenuation. (See "Appendix A—Narrowband References" on page 118.)
The Si5323, Si5326, Si5366, and Si5368 support hitless switching between input clocks in compliance with GR253-CORE and GR-1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs
during an input clock transition (<200 ps typ). Manual, automatic revertive and non-revertive input clock switching
options are available. The devices monitor the input clocks for loss-of-signal and provide a LOS alarm when
missing pulses on any of the input clocks are detected. The devices monitor the lock status of the PLL and provide
a LOL alarm when the PLL is unlocked. The lock detect algorithm works by continuously monitoring the phase of
the selected input clock in relation to the phase of the feedback clock. The Si5326, Si5366, and Si5368 monitor the
frequency of the input clocks with respect to a reference frequency applied to an input clock or the XA/XB input,
and generates a frequency offset alarm (FOS) if the threshold is exceeded. This FOS feature is available for
SONET/SDH applications. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported.
The Si5319, Si5323, Si5326, Si5366, and Si5368 provide a digital hold capability that allows the device to continue
generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL
generates an output frequency based on a historical average that existed a fixed amount of time before the error
event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding
entry into digital hold.
The Si5322, Si5325, Si5365, and Si5367 are frequency flexible, low jitter clock multipliers that provide jitter
generation as low as 0.6 ps RMS. The devices vary according to the number of clock inputs, number of clock
outputs, and control method. The Si5322 and Si5365 are pin-controlled clock multipliers. The frequency plan for
these devices is selectable from frequency lookup tables. A wide range of settings are available, but they are a
subset of the frequency plans supported by the Si5323 and Si5366 jitter-attenuating clock multipliers. The Si5325
and Si5367 are microprocessor-controlled devices that can be controlled via an I
devices accept clock inputs ranging from 10 MHz to 710 MHz and generate multiple independent, synchronous
clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 and Si5367 support
a subset of the frequency translations available in the Si5319, Si5326, and Si5368 jitter-attenuating clock
multipliers. The Si5325 and Si5367 can accept input clocks at different frequencies and generate output clocks at
different frequencies. The Si5322, Si5325, Si5365, and Si5367 support a digitally programmable loop bandwidth
2
C or SPI interface. These microprocessor-controlled devices accept clock
2
C or SPI interface. These
Rev. 0.41 11
Si53xx-RM
that can range from 150 kHz to 1.3 MHz. No external components are required for these devices. LOS and FOS
monitoring is available for these devices, as described above.
The Any-Rate Precision Clocks have differential clock output(s) with programmable signal formats to support
LVPECL, LVDS, CML, and CMOS loads. If the CMOS signal format is selected, each differential output buffer
generates two in-phase CMOS clocks at the same frequency. For system-level debugging, a PLL Bypass Mode
drives the clock output directly from the selected input clock, bypassing the internal PLL.
Silicon Laboratories offers a PC-based software utility, DSPLLsim that can be used to determine valid frequency
plans and loop bandwidth settings for the Any-Rate Precision Clock product family. For the microprocessorcontrolled devices, DSPLLsim provides the optimum PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase noise and power consumption. DSPLLsim can also be used
to simplify device selection and configuration. This utility can be downloaded from http://www.silabs.com/timing.
Other useful documentation, including device data sheets and programming files for the microprocessor-controlled
devices are available from this website.
Table 1. Product Selection Guide
1
Device
Any-Rate Precision Clock Multipliers (Wideband)
Si5322 2 2 707 1050 0.6 ps rms typ
Si5325 2 2
Si5365 4 5 707 1050 0.6 ps rms typ
Si5367 4 5
Any-Rate Precision Clock Multipliers w/Jitter Attenuation2 (Narrowband)
Si5316 2 1 707 710 0.3 ps rms typ
Si5319 1 1
Si5323 2 2 707 1050 0.3 ps rms typ
Si5326 2 2
Si5366 4 5 707 1050 0.3 ps rms typ
Si5368 4 5
Notes:
1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering
information.
2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock. See "Table 64.XA/XB
Reference Sources and Frequencies" on page 118.
Clock Inputs
Clock Outputs
P Control
Max Input Freq (MHz)
Max Output Frequency (MHz)
Jitter Generation
(12 kHz – 20 MHz)
LOS
Hitless Switching
FOS Alarm
LOL Alarm
FSYNC Realignment
36 Lead 6 mm x 6 mm QFN
100 Lead 14 x 14 mm TQFP
710 1400 0.6 ps rms typ
710 1400 0.6 ps rms typ
710 1400 0.3 ps rms typ
710 1400 0.3 ps rms typ
710 1400 0.3 ps rms typ
1.8, 2.5, 3.3 V Operation
1.8, 2.5 V Operation
12 Rev. 0.41
Si53xx-RM
1.1. Si5324 Introduction
The Si5324 is a low loop BW version of the Si5326. As such, all of the descriptions and documentation associated
with the Si5326 that is found in the Any-Rate Precision Clocks Family Reference Manual (this document) can be
applied to directly to the Si5324 with some exceptions. The list below specifies sections that have additional or
replacement information regarding the Si5324:
Section 7.1.4 Loop BW
Section 7.7 Output Phase Adjust
Section 7.2 PLL Self-Calibration
Appendix A Resonator/External Clock Selection
To obtain answers to Si5324 technical questions, refer to the Si5326 data sheet as well as the sections in the list
above. Please note that the sections in the list above provide information that differs from the Si5326, but is specific
to the Si5324.
Rev. 0.41 13
Si53xx-RM
2. Narrowband Versus Wideband Overview
The narrowband (NB) devices offer a number of features and capabilities that are not available with the wideband
(WB) devices, as outlined in the below list:
Richer set of frequency plans due to more divisor options
Hitless switching
Lower minimum clock input frequency
Lower loop BW
Digital Hold (reference-based holdover instead of VCO freeze)
Frame Sync
CLAT and FLAT (input to output skew adjust)
INC or DEC pins
LOL output
14 Rev. 0.41
Si53xx-RM
2
DSPLL
®
C1B
CS
LOL
BWSEL[1:0]
DBL_BY
Xtal or Refclock
SFOUT[1:0]
CKOUT+
CKOUT–
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
Control
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
FRQSEL[1:0]
RST
0
1
RATE[1:0]
XA
XB
f
OSC
2
0
1
÷ N31
÷ N32
f
3_1
f
3_2
CK1DIV
CK2DIV
f
3
3. Any-Rate Clock Family Members
3.1. Si5316
The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or
622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of
these clock ranges, the device can be tuned approximately 14% higher than nominal SONET/SDH frequencies, up
to a maximum of 710 MHz in the 622 MHz range. The DSPLL loop bandwidth is digitally selectable, providing jitter
performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is
ideal for providing jitter attenuation in high performance timing applications. See "6. Pin Control Parts (Si5316,
Si5322, Si5323, Si5365, Si5366)" on page 48 for a complete description.
Figure 1. Si5316 Jitter Attenuator Block Diagram
Rev. 0.41 15
Si53xx-RM
DSPLL
®
Loss of Signal
Xtal or Refclock
CKIN
CKOUT
÷ N31
÷ N2
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Lock
Xtal/Clock Select
I
2
C/SPI Port
Control
Rate Select
÷ N32
XO
f
3
÷ N1_HS ÷ NC1
3.2. Si5319
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as
a clock source for frequency synthesis. The device provides virtually any frequency translation combination across
this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an
I2C or SPI interface. The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which
provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply,
the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete
description.
Figure 2. Si5319 Clock Multiplier Block Diagram
16 Rev. 0.41
Si53xx-RM
DSPLL
®
C1B
LOL
CS_CA
BWSEL[1:0]
DBL2_BY
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_2–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
RST
0
1
f
OSC
2
2
0
1
0
1
f
3
3.3. Si5322
The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz
and generates two frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency
and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel rates, and
broadcast video. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing clock
multiplication in high performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365,
Si5366)" on page 48 for a complete description.
Figure 3. Si5322 Clock Multiplier Block Diagram
Rev. 0.41 17
Si53xx-RM
DSPLL
®
C1B
LOL
CS/CA
BWSEL[1:0]
DBL2/BY
Xtal or Refclock
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_1–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
INC
DEC
RST
0
1
RATE[1:0]
XA
XB
f
OSC
2
2
0
1
0
1
f
3
3.4. Si5323
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to
707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock
frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel,
and broadcast video rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5323 is ideal for
providing clock multiplication and jitter attenuation in high-performance timing applications. See "6. Pin Control
Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 48 for a complete description.
Figure 4. Si5323 Clock Multiplier and Jitter Attenuator Block Diagram
18 Rev. 0.41
Si53xx-RM
÷ N31
INT_C1B
÷ NC1
÷ NC2
Signal
Detect
VDD
(1.8, 2.5, or 3.3 V)
GND
C2B
0
1
CKOUT_2 +
CKOUT_2 –
CKOUT_1 +
CKOUT_1 –
/
/
2
2
1
0
1
0
CS_CA
SDA_SDO
RST
SCL
Control
SDI
A[2]/SS
A[1:0]
CMODE
CKIN_1 +
CKIN_1 –
2
2
CKIN_2 +
CKIN_2 –
÷ N32
0
1
BYPASS
÷ N2
f
3
DSPLL
®
3.5. Si5325
The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5325 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5325 is ideal for providing clock multiplication in high performance timing applications. See
"7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete
description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 5. Si5325 Clock Multiplier Block Diagram
Rev. 0.41 19
Si53xx-RM
÷ N31
INT_C1B
Xtal or Refclock
÷ NC1
÷ NC2
Signal
Detect
VDD
(1.8, 2.5, or 3.3 V)
GND
C2B
0
1
f
3
CKOUT_2 +
CKOUT_2 –
CKOUT_1 +
CKOUT_1 –
/
/
2
2
1
0
1
0
f
OSC
RATE[1:0]
LOL
CS_CA
SDA_SDO
INC
DEC
RST
SCL
Control
SDI
A[2]/SS
A[1:0]
XAXB
CMODE
CKIN_1 +
CKIN_1 –
2
2
CKIN_2 +
CKIN_2 –
÷ N32
0
1
3
BYPASS
÷ N2
DSPLL
÷ N1_HS
DSPLL
®
3.6. Si5326
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high-performance
timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page
74 for a complete description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 6. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram
20 Rev. 0.41
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
ALRMOUT
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
VDD (1.8 V or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
f
3
DBL2_BY
DBL34
DBL5
BWSEL[1:0]
FRQSEL[3:0]
DIV34[1:0]
FOS_CTL
SFOUT[1:0]
RST
CMODE
AUTOSEL
BYPASS/DSBL2
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
÷ N2
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
FRQTBL
DIV34[1:0]
÷ N1_HS
DSPLL
®
3.7. Si5365
The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter
attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, broadcast video rates.
The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application level.
Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high
performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 48
for a complete description.
Figure 7. Si5365 Clock Multiplier Block Diagram
Rev. 0.41 21
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
ALRMOUT
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKIN_3
CKIN_4
CKOUT_2
VDD (1.8 V or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
Xtal or Refclock
RATE[1:0]
XA
XB
f
x
f
3
DBL2_BY
DBL34
DBL5
FSYNC
LOGIC/
ALIGN
CK_CONF
BWSEL[1:0]
FRQSEL[3:0]
DIV34[1:0]
FOS_CTL
SFOUT[1:0]
INC
DEC
FS_SW
FS_ALIGN
RST
CMODE
AUTOSEL
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
FSYNC
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
1
0
FRQTBL
DIV34[1:0]
÷ N1_HS
DSPLL
®
3.8. Si5366
The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to
707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock
frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel
rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application
level. Operating from a single 1.8 or 2.5 V supply, the Si5366 is ideal for providing clock multiplication and jitter
attenuation in high performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365,
Si5366)" on page 48 for a complete description.
Figure 8. Si5366 Clock Multiplier and Jitter Attenuator Block Diagram
22 Rev. 0.41
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
INT_ALM
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKOUT_2
VDD (1.8, or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
f
3
DSBL2/BYPASS
DSBL34
DSBL5
SDA_SDO
SCL
SDI
A[1:0]
RST
CMODE
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
A[2]/SS
÷ N1_HS
DSPLL
®
3.9. Si5367
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequencymultiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5367 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or
2.5 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. See "7.
Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 9. Si5367 Clock Multiplier Block Diagram
Rev. 0.41 23
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
INT_ALM
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKIN_3
CKIN_4
CKOUT_2
VDD (1.8, or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
Xtal or Refclock
RATE[1:0]
XA
XB
f
x
DSBL2/BYPASS
DSBL34
DSBL5
FSYNC
LOGIC/
ALIGN
SDA_SDO
SCL
SDI
A[1:0]
INC
DEC
FS_ALIGN
RST
CMODE
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
FSYNC
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
1
0
A[2]/SS
÷ N1_HS
DSPLL
®
f
3
3.10. Si5368
The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter
performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five
independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation combination across this operating range. The Si5368 input clock
frequency and clock multiplication ratio are programmable through an I
bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating
from a single 1.8 or 2.5 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high
performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367,
Si5368)" on page 74 for a complete description.
2
C or SPI interface. The DSPLL loop
24 Rev. 0.41
Figure 10. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram
4. Specifications
V
ISE
, V
OSE
VID,V
OD
Differential I/Os
V
ICM
, V
OCM
Single-Ended
Peak-to-Peak Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
V
ICM
, V
OCM
t
F
t
R
80%
20%
CKIN, CKOUT
Si53xx-RM
Table 2. Recommended Operating Conditions
Parameter Symbol Test Condition
Ambient Temperature TA
Supply Voltage
During Normal
Operation
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical
values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
2. See Sections 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
1
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Note 2Note 2Note 2Note
2
Min Typ Max Unit
–40 25 85 ºC
2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.71 1.8 1.89 V
Figure 11. Differential Voltage Characteristics
Figure 12. Rise/Fall Time Characteristics
Rev. 0.41 25
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage)
Parameter Symbol Test Condition
Supply Current I
CKIN_n Input Pins
Input Common
Mode Voltage
(Input Threshold
Voltage)
V
DD
ICM
1
LVPECL Format
622.08 MHz Out
All CKOUT’s Enabled
LVPECL Format
622.08 MHz Out
Only 1 CKOUT
Enabled
CMOS Format
19.44 MHz Out
All CKOUT’s Enabled
CMOS Format
19.44 MHz Out
Only CKOUT_1
Enabled
Sleep Mode
1.8 V ± 10%
2.5 V ± 10%
3.3 V ± 10%
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Min Typ Max Units
— 217 243 mA
— 251 279 mA
— 394 435 mA
— 217 243 mA
— 253 284 mA
— 194 220 mA
— 204 234 mA
— 278 321 mA
— 194 220 mA
— 229 261 mA
— 165 — mA
0.9 — 1.4 V
1.0 — 1.7
1.1 — 1.95
Input Resistance CKN
Input Voltage
Level Limits
Single-Ended
Input Voltage
Swing
Differential Input
Voltage Swing
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
26 Rev. 0.41
CKN
V
V
RIN
VIN
ISE
ID
Single-ended
See Note 3.
f
< 212.5 MHz
CKIN
See Figure 11.
f
> 212.5 MHz
CKIN
See Figure 11.
f
< 212.5 MHz
CKIN
See Figure 11.
f
> 212.5 MHz
CKIN
See Figure 11.
20 40 60 k
0—VDDV
0.2 — — V
0.25 — — V
0.2 — V
0.25 — V
PP
PP
PP
PP
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
Output Clocks
(CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS)
Common Mode V
Differential
Output Swing
Single Ended
Output Swing
Differential Out-
CKO
put Voltage
Common Mode
CKO
Output Voltage
Differential
CKO
Output Voltage
OCM
V
OD
V
SE
LVPECL 100 load
line-to-line
LVPECL 100 load
line-to-line
LVPECL 100 load
line-to-line
VD
CML 100 load
line-to-line
VCM
CML 100 load
line-to-line
VD
LVDS 100 load
line-to-line
Low swing LVDS
VDD–
1.42
1
1
1.1 — 1.9 V
0.5 — 0.93 V
350 425 500 mV
—VDD–
—VDD
1.25
—V
– .36
500 700 900 mV
350 425 500 mV
100 load
line-to-line
Common Mode
Output Voltage
Output Short to
GND
CKO
CKO
VCM
LVDS 100 load
line-to-line
1
ISC–
VDD =3.63V
CML, LVDS, LVPECL
1.125 1.2 1.275 V
—8090mA
V
PP
PP
PP
PP
PP
V
=1.89V
DD
—4550mA
CML, LVDS
V
= 3.63 V
DD
— 165 175 mA
CMOS
=1.89V
V
DD
—6570mA
CMOS
Disabled or Sleep
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
—0.10.2 µA
Rev. 0.41 27
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Output Short to
V
DD
Differential
Output
Resistance
Common Mode
Output
Resistance
(to V
Output Voltage
Low
Output Voltage
High
Notes:
)
DD
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
CKO
CKO
CKO
CKO-
VOLLH
CKO-
VOHLH
ISC+
RD
RCM
VDD =3.63V
CML, LVDS, LVPECL
V
=1.89V
DD
CML, LVDS
V
= 3.63 V
DD
CMOS
=1.89V
V
DD
CMOS
Disabled or Sleep
CML, LVP ECL, LVDS,
Disabled, Sleep
CML, LVPECL, LVDS
Disabled, Sleep
CMOS
VDD = 1.71 V
CMOS
Min Typ Max Units
Si5368
—2530mA
—2530mA
— 190 200 mA
—7080mA
—1.5 2 µA
170 200 230
85 100 115
1——M
——0.4 V
0.8 x
V
DD
—— V
28 Rev. 0.41
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Output Drive
Current
CKO
IO
for output low or CKO-
CMOS
Driving into CKO
for output high.
VOH
CKOUT+ and
CKOUT– shorted
externally.
V
= 1.71 V
DD
ICMOS[1:0] =11
ICMOS[1:0] =10
ICMOS[1:0] =01
ICMOS[1:0] =00
V
= 2.97 V
DD
ICMOS[1:0] =11
ICMOS[1:0] =10
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
VOL
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
7.5 — — mA
7.5 — — mA
5.5 — — mA
3.5 — — mA
1.75 — — mA
32 — — mA
32 — — mA
24 — — mA
ICMOS[1:0] =01
ICMOS[1:0] =00
2-Level LVCMOS Input Pins
Input Voltage
Low
Input Voltage
High
Input Low Current
Input High Current
Weak Internal
Input Pullup
Resistor
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
R
V
V
I
I
IH
PUP
IL
IH
IL
VDD=1.71V
V
=2.25V
DD
=2.97V
V
DD
VDD=1.89V
V
=2.25V
DD
V
=3.63V
DD
16 — — mA
8——mA
——0.5 V
——0.7 V
——0.8 V
1.4 — — V
1.8 — — V
2.5 — — V
——50µA
——50µA
24.6 — k
Rev. 0.41 29
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Weak Internal
R
PDN
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
Input Pulldown
Resistor
3-Level Input Pins
Input Voltage
V
ILL
— — 0.15 x
Low
Input Voltage Mid V
Input Voltage
High
Input Low
V
IMM
IHH
I
ILL
See note 2.
0.45 x
V
DD
0.85 x
V
DD
–20 — — µA
Current
Input Mid
I
IMM
See note 2.
–2 — 2 µA
Current
Input High
I
IHH
See note 2.
——20µA
Current
LVCMOS Output Pins
Output Voltage
Low
Output Voltage
High
Tri-State
V
OL
V
OH
I
OZ
IO=2mA
V
=1.62V
DD
=2mA
I
O
V
=2.97V
DD
IO=–2mA
V
=1.62V
DD
I
=–2mA
O
V
=2.97V
DD
RST =0
——0.4 V
——0.4 V
V
DD –
0.4
V
DD –
0.4
–100 — 100 µA
Leakage Current
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
24.6 — k
V
V
DD
—0.55x
V
V
DD
—— V
—— V
—— V
30 Rev. 0.41
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