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ANY-RATE PRECISION CLOCKS
Si5316, Si5319,Si5322, Si5323, SI5324, Si5325,
Si5326, Si5365, Si5366, Si5367, Si5368
F
AMILY REFERENCE MANUAL
Rev. 0.41 10/09 Copyright © 2009 by Silicon Laboratories Si53xx-RM
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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TABLE OF CONTENTS
Section Page
1. Any-Rate Precision Clock Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.1. Si5324 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Narrowband Versus Wideband Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Any-Rate Clock Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Si5319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.3. Si5322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.4. Si5323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.5. Si5325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.6. Si5326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.7. Si5365 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.8. Si5366 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.9. Si5367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.10. Si5368 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. DSPLL (All Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1. Clock Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.1. Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.2. Jitter Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.2.3. Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . .47
6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . .47
6.1.1. Clock Multiplication (Si5316) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.6. Narrowband Performance (Si5316, Si5323, Si5366). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.7. Wideband Performance (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.8. Lock Detect (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.1.9. Wideband Input-to-Output Skew (Si5322 and Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5323, Si5366). . . . . . . . . . . . . 62
6.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)
62
6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366). . . . . . . . . . . . . . 62
6.2.4. Narrowband Input-to-Output Skew (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3. Pin Control Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
6.3.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4. Digital Hold/VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.4.3. Wideband VCO Freeze (Si5322, Si5365) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5. Frame Synchronization (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.6. Output Phase Adjust (Si5323, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
6.6.1. FSYNC Realignment (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.2. Including FSYNC Inputs in Clock Selection (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.3. FS_OUT Polarity and Pulse Width Control (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.4. Using FS_OUT as a Fifth Output Clock (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6.5. Disabling FS_OUT (Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.7. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
6.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366) . . . . 69
6.8. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.9. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
6.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . 70
6.9.2. FOS Alarms (Si5365 and Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L) . . . . . . . . . . . . . . . . . . . . . 71
6.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.10. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.11. DSPLLsim Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . 73
7.1. Clock Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.1.1. Jitter Tolerance (Si5319, Si5325, Si5326, Si5367, and Si5368) . . . . . . . . . . . . . . . . . . . . . . . . 73
7.1.2. Wideband Mode (Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1.3. Narrowband Mode (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.1.5. Lock Detect (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.2.1. Initiating Internal Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.2. Input Clock Stability during Internal Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.3. Self-Calibration Caused by Changes in Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3. Input Clock Configurations (Si5367 and Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4. Microprocessor Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7.4.1. Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.4.2. Automatic Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.4.3. Hitless Switching with Phase Build-Out (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.5. Si5319, Si5326, and Si5368 Free Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.1. Free Run Mode Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.2. Use of LOS_A when in Free Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.5.3. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.5.4. Free Run Reference Frequency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.6. Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.6.1. Narrowband Digital Hold (Si5316, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.6.2. Recovery from Digital Hold (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.6.3. VCO Freeze (Si5319, Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.7. Output Phase Adjust (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
7.7.1. Coarse Skew Control (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.7.2. Fine Skew Control (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.3. Independent Skew (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.4. Output-to-output Skew (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
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7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1) . . . . . . . 92
7.8.1. FSYNC Realignment (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.8.2. FSYNC Skew Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.8.3. Including FSYNC Inputs in Clock Selection (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.9. Output Clock Drivers (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . 97
7.9.1. Disabling CKOUTn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si536, Si5368) . . . . . . . . . . . . . . 97
7.10. PLL Bypass Mode (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . 97
7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.11.1. Loss-of-Signal Alarms (Si5319, Si5325, Si5326, Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . 98
7.11.2. FOS Algorithm (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.11.3. C1B, C2B (Si5319, Si5325, Si5326) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.11.4. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368 [CK_CONFIG_REG = 0]). . . . . . . . . . . . . . . . 101
7.11.5. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1]) . . . . . . . . . . . . . . . . . . . . . . 102
7.11.6. LOS Algorithm for Reference Clock Input (Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.11.7. LOL (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.11.8. Device Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.12. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
7.13. I2C Serial Microprocessor Interface (Si5325, Si5326, Si5367, Si5368) . . . . . . . .103
7.14. Serial Microprocessor Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
7.14.1. Default Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.15. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7.16. DSPLLsim Configuration Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368) . . . . . . . . . . . . 109
8.3. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5326, Si5366, &
Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
8.4. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . .113
8.5. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . 114
9. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10. Packages and Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Appendix A—Narrowband References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Appendix C—Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix D—Alarm Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Appendix E—Internal Pullup, Pulldown by Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Appendix F—Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Rev. 0.41 5
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Si53xx-RM
LIST OF FIGURES
1. Any-Rate Precision Clock Product Family Overview
2. Narrowband Versus Wideband Overview
3. Any-Rate Clock Family Members
Figure 1. Si5316 Jitter Attenuator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Si5319 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. Si5322 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Si5323 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 17
Figure 5. Si5325 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 19
Figure 7. Si5365 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Si5366 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . . 21
Figure 9. Si5367 Clock Multiplier Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram. . . . . . . . . . . . . . . . . 23
4. Specifications
Figure 11. Differential Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Rise/Fall Time Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Frame Synchronization Timing in Level Sensitive Mode . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Frame Synchronization Timing in One-shot Mode. . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5. DSPLL (All Devices)
Figure 16. Any-Rate Precision Clock DSPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Clock Multiplication Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. PLL Jitter Transfer Mask/Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 19. Jitter Tolerance Mask/Template. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
Figure 20. Si5316 Divisor Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)
Figure 21. Wideband PLL Divider Settings (Si5325, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. Narrowband PLL Divider Settings (Si5319, Si5326, Si5368) . . . . . . . . . . . . . . . . . 76
Figure 23. Si5325 and Si5326 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 24. Si5367 and Si5368 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 25. Free Run Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 26. Parameters in History Value of M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 27. Frame Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 28. FOS Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 29. I2C Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 30. SPI Write/Set Address Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 31. SPI Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8. High-Speed I/O
Figure 32. Differential LVPECL Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 33. Single-Ended LVPECL Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 34. CML/LVDS Termination (1.8, 2.5, 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35. CMOS Termination (1.8, 2.5, 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Si53xx-RM
Figure 36. Typical Output Circuit (Not CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together). . . . . . . 108
Figure 38. Differential Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 39. CKOUT Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 40. CMOS External Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. Sinewave External Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 42. Differential External Reference Input Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 43. Three Level Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 44. Three Level Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9. Power Supply
Figure 45. Typical Power Supply Bypass Network (TQFP Package) . . . . . . . . . . . . . . . . . . 114
Figure 46. Typical Power Supply Bypass Network (QFN Package) . . . . . . . . . . . . . . . . . . . 114
10. Packages and Ordering Guide
Appendix A—Narrowband References
Figure 47. Typical Reference Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Figure 48. Jitter vs. f3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 49. Jitter vs. f3 with FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 50. Reference vs. Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 51. Jitter vs. Reference Frequency (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 52. Jitter vs. Reference Frequency (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Appendix C—Typical Phase Noise Plots
Appendix D—Alarm Structure
Figure 53. Si5326 Alarm Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 54. Si5368 Alarm Diagram (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 55. Si5368 Alarm Diagram (2 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Appendix E—Internal Pullup, Pulldown by Pin
Appendix F—Typical Performance
Document Change List
Contact Information
Rev. 0.41 7
Page 8
Si53xx-RM
LIST OF TABLES
1. Any-Rate Precision Clock Product Family Overview
Table 1. Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. Narrowband Versus Wideband Overview
3. Any-Rate Clock Family Members
4. Specifications
Table 2. Recommended Operating Conditions
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage). . . . 25
Table 4. DC Characteristics—Microprocessor Devices (Si5319, Si5325, Si5326, Si5367, Si5368)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 5. DC Characteristics—Narrowband Devices (Si5316, Si5319, Si5323, Si5326, Si5366,
Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. AC Characteristics—All Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Jitter Generation (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368) . . . . . . . . . . . . 39
Table 8. Jitter Generation (Si5322, Si5325, Si5365, Si5367) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. SPI Specifications (Si5319, Si5325, Si5326, Si5367, and Si5368) . . . . . . . . . . . . . . 40
Table 10. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5. DSPLL (All Devices)
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
Table 11. Si5316, Si5322, Si5323, Si5365 and Si5366 Key Features . . . . . . . . . . . . . . . . . . 46
Table 12. Frequency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Input Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. Si5316 BW Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) . . . . . . . . . . 53
Table 17. SONET to Datacom Clock Multiplication Settings (FRQTBL = H, CK_CONF = 0) . 57
Table 18. Clock Output Divider Control (DIV34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 19. Si5316, Si5322, and Si5323 Pins and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. Si5365 and Si5366 Pins and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 21. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL = L . . . . . . . . 63
Table 22. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL = L . . . . . . . . . . . . . . . 63
Table 23. Automatic/Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Clock Active Indicators (AUTOSEL = M or H) (Si5322 and Si5323) . . . . . . . . . . . . 64
Table 25. Clock Active Indicators (AUTOSEL = M or H) (Si5365 and Si5367) . . . . . . . . . . . . 64
Table 26. Input Clock Priority for Auto Switching (Si5322, Si5323) . . . . . . . . . . . . . . . . . . . . 64
Table 27. Input Clock Priority for Auto Switching (Si5365, Si5366) . . . . . . . . . . . . . . . . . . . . 65
Table 28. FS_OUT Disable Control (DBLFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 29. Output Signal Format Selection (SFOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 30. DSBL2/BYPASS Pin Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31. Frequency Offset Control (FOS_CTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. Alarm Output Logic Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 33. Lock Detect Retrigger Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)
Table 34. Si5325, Si5326, Si5367 and Si5368 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . 72
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Table 35. Device Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. Common Divider Settings (Wideband/µP Control Mode - Si5325 and Si5367) . . . 74
Table 37. Common Loop Bandwidth (MHz) (Si5325 and Si5367) . . . . . . . . . . . . . . . . . . . . . 75
Table 38. Narrowband Frequency Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 39. Dividers and Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Common Divider Settings (Si5319, Si5326, Si5368). . . . . . . . . . . . . . . . . . . . . . . . 78
Table 41. Common Loop Bandwidth Settings (Si5319, Si5326 and Si5368) . . . . . . . . . . . . . 79
Table 42. Input Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 43. Manual Input Clock Selection (Si5367, Si5368) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. Manual Input Clock Selection (Si5325, Si5326) . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 45. Automatic/Manual Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 46. Input Clock Priority for Auto Switching in µP Control Mode . . . . . . . . . . . . . . . . . . 84
Table 47. Digital Hold History Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. Digital Hold History Averaging Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 49. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) . . . . . . . . . . . . . . . . . . . . . . . 92
Table 50. Common NC5 Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 51. Alignment Alarm Trigger Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 52. Output Signal Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. Loss-of-Signal Validation Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. Loss-of-Signal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 55. FOS Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 56. CLKnRATE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 57. Alarm Output Logic Equations (Si5367 and Si5368 [CONFIG_REG = 0]) . . . . . . 100
Table 58. Alarm Output Logic Equations [Si5368 and CKCONFIG_REG = 1] . . . . . . . . . . . 101
Table 59. Lock Detect Retrigger Time (LOCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 60. SPI Command Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8. High-Speed I/O
Table 61. Output Driver Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 62. Disabling Unused Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9. Power Supply
10. Packages and Ordering Guide
Appendix A—Narrowband References
Table 63. Approved Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 64. XA/XB Reference Sources and Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B—Frequency Plans and Jitter Performance
(Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Table 65. Jitter Values for Figure 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 66. Jitter Values for Figure 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Appendix C—Typical Phase Noise Plots
Appendix D—Alarm Structure
Appendix E—Internal Pullup, Pulldown by Pin
Table 67. Si5316 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 68. Si5322 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 69. Si5323 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 70. Si5325 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 71. Si5326 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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Table 72. Si5365 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 73. Si5366 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 74. Si5367 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 75. Si5368 Pullup/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Appendix F—Typical Performance
Table 76. Output Format vs. Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Document Change List
Contact Information
10 Rev. 0.41
Page 11
Si53xx-RM
1. Any-Rate Precision Clock Product Family Overview
Silicon Laboratories Any-Rate Precision Clock products provide jitter attenuation and clock multiplication/clock
division for applications requiring sub 1 ps rms jitter performance. The device product family is based on Silicon
Laboratories' 3rd generation DSPLL technology, which provides any-rate frequency synthesis and jitter attenuation
in a highly integrated PLL solution that eliminates the need for discrete VCXO/VCSOs and loop filter components.
These devices are ideally suited for applications which require low jitter reference clocks, including OC-48/STM-16,
OC-192/STM-64, OC-768/STM-256, wireless basestations, wireless point-point infrastructure, broadcast video/
HDTV, test & measurement, data acquisition systems, and FPGA/ASIC reference clocking.
Table 1 provides a product selector guide for the Silicon Laboratories Any-Rate Precision Clocks. Two product
families are available. The Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368 are jitter-attenuating clock
multipliers that provide ultra-low jitter generation as low as 0.30 ps RMS. The devices vary according to the number
of clock inputs, number of clock outputs, and control method. The Si5316 is a fixed-frequency, pin controlled jitter
attenuator that can be used in clock smoothing applications. The Si5323 and Si5366 are pin-controlled jitterattenuating clock multipliers. The frequency plan for these pin-controlled devices is selectable from frequency
lookup tables and includes common frequency translations for SONET/SDH, ITU G.709 Forward Error Correction
(FEC) applications (255/238, 255/237, 255/236, 238/255, 237/255, 236/255), Gigabit Ethernet, 10G Ethernet, 1G/
2G/4G/8G/10G Fibre Channel, ATM and HDTV. The Si5319, Si5326, and Si5368 are microprocessor-controlled
devices that can be controlled via an I
inputs ranging from 2 kHz to 710 MHz and generate multiple independent, synchronous clock outputs ranging from
2 kHz to 945 MHz and select frequencies to 1.4 GHz. Virtually any frequency translation combination across this
operating range is supported. Independent dividers are available for every input clock and output clock, so the
Si5326 and Si5368 can accept input clocks at different frequencies and generate output clocks at different
frequencies. The Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368 support a digitally programmable loop
bandwidth that can range from 60 Hz to 8.4 kHz. An external (37–41 MHz, 55–61 MHz, 109–125.5 MHz, or 163–
180 MHz) reference clock or a low-cost 114.285 MHz 3rd overtone crystal is required for these devices to enable
ultra-low jitter generation and jitter attenuation. (See "Appendix A—Narrowband References" on page 118.)
The Si5323, Si5326, Si5366, and Si5368 support hitless switching between input clocks in compliance with GR253-CORE and GR-1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs
during an input clock transition (<200 ps typ). Manual, automatic revertive and non-revertive input clock switching
options are available. The devices monitor the input clocks for loss-of-signal and provide a LOS alarm when
missing pulses on any of the input clocks are detected. The devices monitor the lock status of the PLL and provide
a LOL alarm when the PLL is unlocked. The lock detect algorithm works by continuously monitoring the phase of
the selected input clock in relation to the phase of the feedback clock. The Si5326, Si5366, and Si5368 monitor the
frequency of the input clocks with respect to a reference frequency applied to an input clock or the XA/XB input,
and generates a frequency offset alarm (FOS) if the threshold is exceeded. This FOS feature is available for
SONET/SDH applications. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported.
The Si5319, Si5323, Si5326, Si5366, and Si5368 provide a digital hold capability that allows the device to continue
generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL
generates an output frequency based on a historical average that existed a fixed amount of time before the error
event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding
entry into digital hold.
The Si5322, Si5325, Si5365, and Si5367 are frequency flexible, low jitter clock multipliers that provide jitter
generation as low as 0.6 ps RMS. The devices vary according to the number of clock inputs, number of clock
outputs, and control method. The Si5322 and Si5365 are pin-controlled clock multipliers. The frequency plan for
these devices is selectable from frequency lookup tables. A wide range of settings are available, but they are a
subset of the frequency plans supported by the Si5323 and Si5366 jitter-attenuating clock multipliers. The Si5325
and Si5367 are microprocessor-controlled devices that can be controlled via an I
devices accept clock inputs ranging from 10 MHz to 710 MHz and generate multiple independent, synchronous
clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 and Si5367 support
a subset of the frequency translations available in the Si5319, Si5326, and Si5368 jitter-attenuating clock
multipliers. The Si5325 and Si5367 can accept input clocks at different frequencies and generate output clocks at
different frequencies. The Si5322, Si5325, Si5365, and Si5367 support a digitally programmable loop bandwidth
2
C or SPI interface. These microprocessor-controlled devices accept clock
2
C or SPI interface. These
Rev. 0.41 11
Page 12
Si53xx-RM
that can range from 150 kHz to 1.3 MHz. No external components are required for these devices. LOS and FOS
monitoring is available for these devices, as described above.
The Any-Rate Precision Clocks have differential clock output(s) with programmable signal formats to support
LVPECL, LVDS, CML, and CMOS loads. If the CMOS signal format is selected, each differential output buffer
generates two in-phase CMOS clocks at the same frequency. For system-level debugging, a PLL Bypass Mode
drives the clock output directly from the selected input clock, bypassing the internal PLL.
Silicon Laboratories offers a PC-based software utility, DSPLLsim that can be used to determine valid frequency
plans and loop bandwidth settings for the Any-Rate Precision Clock product family. For the microprocessorcontrolled devices, DSPLLsim provides the optimum PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase noise and power consumption. DSPLLsim can also be used
to simplify device selection and configuration. This utility can be downloaded from http://www.silabs.com/timing.
Other useful documentation, including device data sheets and programming files for the microprocessor-controlled
devices are available from this website.
Table 1. Product Selection Guide
1
Device
Any-Rate Precision Clock Multipliers (Wideband)
Si5322 2 2 707 1050 0.6 ps rms typ
Si5325 2 2
Si5365 4 5 707 1050 0.6 ps rms typ
Si5367 4 5
Any-Rate Precision Clock Multipliers w/Jitter Attenuation2 (Narrowband)
Si5316 2 1 707 710 0.3 ps rms typ
Si5319 1 1
Si5323 2 2 707 1050 0.3 ps rms typ
Si5326 2 2
Si5366 4 5 707 1050 0.3 ps rms typ
Si5368 4 5
Notes:
1. Maximum input and output rates may be limited by speed rating of device. See each device’s data sheet for ordering
information.
2. Requires external low-cost, fixed frequency 3rd overtone 114.285 MHz crystal or reference clock. See "Table 64.XA/XB
Reference Sources and Frequencies" on page 118.
Clock Inputs
Clock Outputs
P Control
Max Input Freq (MHz)
Max Output Frequency (MHz)
Jitter Generation
(12 kHz – 20 MHz)
LOS
Hitless Switching
FOS Alarm
LOL Alarm
FSYNC Realignment
36 Lead 6 mm x 6 mm QFN
100 Lead 14 x 14 mm TQFP
710 1400 0.6 ps rms typ
710 1400 0.6 ps rms typ
710 1400 0.3 ps rms typ
710 1400 0.3 ps rms typ
710 1400 0.3 ps rms typ
1.8, 2.5, 3.3 V Operation
1.8, 2.5 V Operation
12 Rev. 0.41
Page 13
Si53xx-RM
1.1. Si5324 Introduction
The Si5324 is a low loop BW version of the Si5326. As such, all of the descriptions and documentation associated
with the Si5326 that is found in the Any-Rate Precision Clocks Family Reference Manual (this document) can be
applied to directly to the Si5324 with some exceptions. The list below specifies sections that have additional or
replacement information regarding the Si5324:
Section 7.1.4 Loop BW
Section 7.7 Output Phase Adjust
Section 7.2 PLL Self-Calibration
Appendix A Resonator/External Clock Selection
To obtain answers to Si5324 technical questions, refer to the Si5326 data sheet as well as the sections in the list
above. Please note that the sections in the list above provide information that differs from the Si5326, but is specific
to the Si5324.
Rev. 0.41 13
Page 14
Si53xx-RM
2. Narrowband Versus Wideband Overview
The narrowband (NB) devices offer a number of features and capabilities that are not available with the wideband
(WB) devices, as outlined in the below list:
Richer set of frequency plans due to more divisor options
Hitless switching
Lower minimum clock input frequency
Lower loop BW
Digital Hold (reference-based holdover instead of VCO freeze)
Frame Sync
CLAT and FLAT (input to output skew adjust)
INC or DEC pins
LOL output
14 Rev. 0.41
Page 15
Si53xx-RM
2
DSPLL
®
C1B
CS
LOL
BWSEL[1:0]
DBL_BY
Xtal or Refclock
SFOUT[1:0]
CKOUT+
CKOUT–
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
Control
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
FRQSEL[1:0]
RST
0
1
RATE[1:0]
XA
XB
f
OSC
2
0
1
÷ N31
÷ N32
f
3_1
f
3_2
CK1DIV
CK2DIV
f
3
3. Any-Rate Clock Family Members
3.1. Si5316
The Si5316 is a low jitter, precision jitter attenuator for high-speed communication systems, including OC-48, OC192, 10G Ethernet, and 10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38, 77, 155, 311, or
622 MHz frequency range and generates a jitter-attenuated clock output at the same frequency. Within each of
these clock ranges, the device can be tuned approximately 14% higher than nominal SONET/SDH frequencies, up
to a maximum of 710 MHz in the 622 MHz range. The DSPLL loop bandwidth is digitally selectable, providing jitter
performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5316 is
ideal for providing jitter attenuation in high performance timing applications. See "6. Pin Control Parts (Si5316,
Si5322, Si5323, Si5365, Si5366)" on page 48 for a complete description.
Figure 1. Si5316 Jitter Attenuator Block Diagram
Rev. 0.41 15
Page 16
Si53xx-RM
DSPLL
®
Loss of Signal
Xtal or Refclock
CKIN
CKOUT
÷ N31
÷ N2
Signal Detect
Device Interrupt
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Lock
Xtal/Clock Select
I
2
C/SPI Port
Control
Rate Select
÷ N32
XO
f
3
÷ N1_HS ÷ NC1
3.2. Si5319
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output
ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as
a clock source for frequency synthesis. The device provides virtually any frequency translation combination across
this operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an
I2C or SPI interface. The Si5319 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which
provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable,
providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply,
the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete
description.
Figure 2. Si5319 Clock Multiplier Block Diagram
16 Rev. 0.41
Page 17
Si53xx-RM
DSPLL
®
C1B
LOL
CS_CA
BWSEL[1:0]
DBL2_BY
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_2–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
RST
0
1
f
OSC
2
2
0
1
0
1
f
3
3.3. Si5322
The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC48/OC-192, Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz
and generates two frequency-multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency
and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel rates, and
broadcast video. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing clock
multiplication in high performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365,
Si5366)" on page 48 for a complete description.
Figure 3. Si5322 Clock Multiplier Block Diagram
Rev. 0.41 17
Page 18
Si53xx-RM
DSPLL
®
C1B
LOL
CS/CA
BWSEL[1:0]
DBL2/BY
Xtal or Refclock
SFOUT[1:0]
CKOUT_2+
CKOUT_2–
CKIN_1+
CKIN_1–
CKOUT_1+
CKOUT_1–
CKIN_2+
CKIN_2–
Control
AUTOSEL
FRQTBL
Signal
Detect
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency
Control
Bandwidth
Control
C2B
2
2
FRQSEL[3:0]
INC
DEC
RST
0
1
RATE[1:0]
XA
XB
f
OSC
2
2
0
1
0
1
f
3
3.4. Si5323
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to
707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock
frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel,
and broadcast video rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance
optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5323 is ideal for
providing clock multiplication and jitter attenuation in high-performance timing applications. See "6. Pin Control
Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 48 for a complete description.
Figure 4. Si5323 Clock Multiplier and Jitter Attenuator Block Diagram
18 Rev. 0.41
Page 19
Si53xx-RM
÷ N31
INT_C1B
÷ NC1
÷ NC2
Signal
Detect
VDD
(1.8, 2.5, or 3.3 V)
GND
C2B
0
1
CKOUT_2 +
CKOUT_2 –
CKOUT_1 +
CKOUT_1 –
/
/
2
2
1
0
1
0
CS_CA
SDA_SDO
RST
SCL
Control
SDI
A[2]/SS
A[1:0]
CMODE
CKIN_1 +
CKIN_1 –
2
2
CKIN_2 +
CKIN_2 –
÷ N32
0
1
BYPASS
÷ N2
f
3
DSPLL
®
3.5. Si5325
The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5325 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5325 is ideal for providing clock multiplication in high performance timing applications. See
"7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete
description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 5. Si5325 Clock Multiplier Block Diagram
Rev. 0.41 19
Page 20
Si53xx-RM
÷ N31
INT_C1B
Xtal or Refclock
÷ NC1
÷ NC2
Signal
Detect
VDD
(1.8, 2.5, or 3.3 V)
GND
C2B
0
1
f
3
CKOUT_2 +
CKOUT_2 –
CKOUT_1 +
CKOUT_1 –
/
/
2
2
1
0
1
0
f
OSC
RATE[1:0]
LOL
CS_CA
SDA_SDO
INC
DEC
RST
SCL
Control
SDI
A[2]/SS
A[1:0]
XAXB
CMODE
CKIN_1 +
CKIN_1 –
2
2
CKIN_2 +
CKIN_2 –
÷ N32
0
1
3
BYPASS
÷ N2
DSPLL
÷ N1_HS
DSPLL
®
3.6. Si5326
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in high-performance
timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page
74 for a complete description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 6. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram
20 Rev. 0.41
Page 21
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
ALRMOUT
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
VDD (1.8 V or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
f
3
DBL2_BY
DBL34
DBL5
BWSEL[1:0]
FRQSEL[3:0]
DIV34[1:0]
FOS_CTL
SFOUT[1:0]
RST
CMODE
AUTOSEL
BYPASS/DSBL2
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
÷ N2
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
FRQTBL
DIV34[1:0]
÷ N1_HS
DSPLL
®
3.7. Si5365
The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC48/OC-192, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter
attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, broadcast video rates.
The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application level.
Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high
performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 48
for a complete description.
Figure 7. Si5365 Clock Multiplier Block Diagram
Rev. 0.41 21
Page 22
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
ALRMOUT
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKIN_3
CKIN_4
CKOUT_2
VDD (1.8 V or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
Xtal or Refclock
RATE[1:0]
XA
XB
f
x
f
3
DBL2_BY
DBL34
DBL5
FSYNC
LOGIC/
ALIGN
CK_CONF
BWSEL[1:0]
FRQSEL[3:0]
DIV34[1:0]
FOS_CTL
SFOUT[1:0]
INC
DEC
FS_SW
FS_ALIGN
RST
CMODE
AUTOSEL
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
FSYNC
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
1
0
FRQTBL
DIV34[1:0]
÷ N1_HS
DSPLL
®
3.8. Si5366
The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to
707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock
frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel
rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application
level. Operating from a single 1.8 or 2.5 V supply, the Si5366 is ideal for providing clock multiplication and jitter
attenuation in high performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365,
Si5366)" on page 48 for a complete description.
Figure 8. Si5366 Clock Multiplier and Jitter Attenuator Block Diagram
22 Rev. 0.41
Page 23
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
INT_ALM
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKOUT_2
VDD (1.8, or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
f
3
DSBL2/BYPASS
DSBL34
DSBL5
SDA_SDO
SCL
SDI
A[1:0]
RST
CMODE
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
A[2]/SS
÷ N1_HS
DSPLL
®
3.9. Si5367
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequencymultiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5367 input clock frequency and
clock multiplication ratio are programmable through an I
programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or
2.5 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. See "7.
Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)" on page 74 for a complete description.
2
C or SPI interface. The DSPLL loop bandwidth is digitally
Figure 9. Si5367 Clock Multiplier Block Diagram
Rev. 0.41 23
Page 24
Si53xx-RM
C2A
CS0_C3A
C2B
CS1_C4A
INT_ALM
C1A
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
C3B
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
C1B
CKIN_3
CKIN_4
CKOUT_2
VDD (1.8, or 2.5 V)
GND
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
f
OSC
Xtal or Refclock
RATE[1:0]
XA
XB
f
x
DSBL2/BYPASS
DSBL34
DSBL5
FSYNC
LOGIC/
ALIGN
SDA_SDO
SCL
SDI
A[1:0]
INC
DEC
FS_ALIGN
RST
CMODE
BYPASS/DSBL2
LOL
Control
÷ N3_2
÷ N3_1
Bandwidth
Control
FSYNC
÷ N2
3
÷ N3_3
÷ N3_4
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
1
0
A[2]/SS
÷ N1_HS
DSPLL
®
f
3
3.10. Si5368
The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter
performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five
independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation combination across this operating range. The Si5368 input clock
frequency and clock multiplication ratio are programmable through an I
bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating
from a single 1.8 or 2.5 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high
performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367,
Si5368)" on page 74 for a complete description.
2
C or SPI interface. The DSPLL loop
24 Rev. 0.41
Figure 10. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram
Page 25
4. Specifications
V
ISE
, V
OSE
VID,V
OD
Differential I/Os
V
ICM
, V
OCM
Single-Ended
Peak-to-Peak Voltage
Differential Peak-to-Peak Voltage
SIGNAL +
SIGNAL –
(SIGNAL +) – (SIGNAL –)
V
t
SIGNAL +
SIGNAL –
VID = (SIGNAL+) – (SIGNAL–)
V
ICM
, V
OCM
t
F
t
R
80%
20%
CKIN, CKOUT
Si53xx-RM
Table 2. Recommended Operating Conditions
Parameter Symbol Test Condition
Ambient Temperature TA
Supply Voltage
During Normal
Operation
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical
values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
2. See Sections 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
1
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Note 2Note 2Note 2Note
2
Min Typ Max Unit
–40 25 85 ºC
2.97 3.3 3.63 V
2.25 2.5 2.75 V
1.71 1.8 1.89 V
Figure 11. Differential Voltage Characteristics
Figure 12. Rise/Fall Time Characteristics
Rev. 0.41 25
Page 26
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage)
Parameter Symbol Test Condition
Supply Current I
CKIN_n Input Pins
Input Common
Mode Voltage
(Input Threshold
Voltage)
V
DD
ICM
1
LVPECL Format
622.08 MHz Out
All CKOUT’s Enabled
LVPECL Format
622.08 MHz Out
Only 1 CKOUT
Enabled
CMOS Format
19.44 MHz Out
All CKOUT’s Enabled
CMOS Format
19.44 MHz Out
Only CKOUT_1
Enabled
Sleep Mode
1.8 V ± 10%
2.5 V ± 10%
3.3 V ± 10%
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Min Typ Max Units
— 217 243 mA
— 251 279 mA
— 394 435 mA
— 217 243 mA
— 253 284 mA
— 194 220 mA
— 204 234 mA
— 278 321 mA
— 194 220 mA
— 229 261 mA
— 165 — mA
0.9 — 1.4 V
1.0 — 1.7
1.1 — 1.95
Input Resistance CKN
Input Voltage
Level Limits
Single-Ended
Input Voltage
Swing
Differential Input
Voltage Swing
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
26 Rev. 0.41
CKN
V
V
RIN
VIN
ISE
ID
Single-ended
See Note 3.
f
< 212.5 MHz
CKIN
See Figure 11.
f
> 212.5 MHz
CKIN
See Figure 11.
f
< 212.5 MHz
CKIN
See Figure 11.
f
> 212.5 MHz
CKIN
See Figure 11.
20 40 60 k
0—VDDV
0.2 — — V
0.25 — — V
0.2 — V
0.25 — V
PP
PP
PP
PP
Page 27
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
Output Clocks
(CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS)
Common Mode V
Differential
Output Swing
Single Ended
Output Swing
Differential Out-
CKO
put Voltage
Common Mode
CKO
Output Voltage
Differential
CKO
Output Voltage
OCM
V
OD
V
SE
LVPECL 100 load
line-to-line
LVPECL 100 load
line-to-line
LVPECL 100 load
line-to-line
VD
CML 100 load
line-to-line
VCM
CML 100 load
line-to-line
VD
LVDS 100 load
line-to-line
Low swing LVDS
VDD–
1.42
1
1
1.1 — 1.9 V
0.5 — 0.93 V
350 425 500 mV
—VDD–
—VDD
1.25
—V
– .36
500 700 900 mV
350 425 500 mV
100 load
line-to-line
Common Mode
Output Voltage
Output Short to
GND
CKO
CKO
VCM
LVDS 100 load
line-to-line
1
ISC–
VDD =3.63V
CML, LVDS, LVPECL
1.125 1.2 1.275 V
—8090mA
V
PP
PP
PP
PP
PP
V
=1.89V
DD
—4550mA
CML, LVDS
V
= 3.63 V
DD
— 165 175 mA
CMOS
=1.89V
V
DD
—6570mA
CMOS
Disabled or Sleep
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
—0.10.2 µA
Rev. 0.41 27
Page 28
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Output Short to
V
DD
Differential
Output
Resistance
Common Mode
Output
Resistance
(to V
Output Voltage
Low
Output Voltage
High
Notes:
)
DD
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
CKO
CKO
CKO
CKO-
VOLLH
CKO-
VOHLH
ISC+
RD
RCM
VDD =3.63V
CML, LVDS, LVPECL
V
=1.89V
DD
CML, LVDS
V
= 3.63 V
DD
CMOS
=1.89V
V
DD
CMOS
Disabled or Sleep
CML, LVP ECL, LVDS,
Disabled, Sleep
CML, LVPECL, LVDS
Disabled, Sleep
CMOS
VDD = 1.71 V
CMOS
Min Typ Max Units
Si5368
—2530mA
—2530mA
— 190 200 mA
—7080mA
—1.5 2 µA
170 200 230
85 100 115
1——M
——0.4 V
0.8 x
V
DD
—— V
28 Rev. 0.41
Page 29
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Output Drive
Current
CKO
IO
for output low or CKO-
CMOS
Driving into CKO
for output high.
VOH
CKOUT+ and
CKOUT– shorted
externally.
V
= 1.71 V
DD
ICMOS[1:0] =11
ICMOS[1:0] =10
ICMOS[1:0] =01
ICMOS[1:0] =00
V
= 2.97 V
DD
ICMOS[1:0] =11
ICMOS[1:0] =10
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
VOL
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
7.5 — — mA
7.5 — — mA
5.5 — — mA
3.5 — — mA
1.75 — — mA
32 — — mA
32 — — mA
24 — — mA
ICMOS[1:0] =01
ICMOS[1:0] =00
2-Level LVCMOS Input Pins
Input Voltage
Low
Input Voltage
High
Input Low Current
Input High Current
Weak Internal
Input Pullup
Resistor
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
R
V
V
I
I
IH
PUP
IL
IH
IL
VDD=1.71V
V
=2.25V
DD
=2.97V
V
DD
VDD=1.89V
V
=2.25V
DD
V
=3.63V
DD
16 — — mA
8——mA
——0.5 V
——0.7 V
——0.8 V
1.4 — — V
1.8 — — V
2.5 — — V
——50µA
——50µA
24.6 — k
Rev. 0.41 29
Page 30
Si53xx-RM
Table 3. DC Characteristics—All Parts (Current draw is independent of supply voltage) (Continued)
Parameter Symbol Test Condition
Weak Internal
R
PDN
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
Input Pulldown
Resistor
3-Level Input Pins
Input Voltage
V
ILL
— — 0.15 x
Low
Input Voltage Mid V
Input Voltage
High
Input Low
V
IMM
IHH
I
ILL
See note 2.
0.45 x
V
DD
0.85 x
V
DD
–20 — — µA
Current
Input Mid
I
IMM
See note 2.
–2 — 2 µA
Current
Input High
I
IHH
See note 2.
——20µA
Current
LVCMOS Output Pins
Output Voltage
Low
Output Voltage
High
Tri-State
V
OL
V
OH
I
OZ
IO=2mA
V
=1.62V
DD
=2mA
I
O
V
=2.97V
DD
IO=–2mA
V
=1.62V
DD
I
=–2mA
O
V
=2.97V
DD
RST =0
——0.4 V
——0.4 V
V
DD –
0.4
V
DD –
0.4
–100 — 100 µA
Leakage Current
Notes:
1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 43 on page 114.
3. No under- or overshoot is allowed.
24.6 — k
V
V
DD
—0.55x
V
V
DD
—— V
—— V
—— V
30 Rev. 0.41
Page 31
Si53xx-RM
Table 4. DC Characteristics—Microprocessor Devices (Si5319, Si5325, Si5326, Si5367, Si5368)
Parameter Symbol Test Condition
2
I
C Bus Lines (SDA, SCL)
Input Voltage Low V
Input Voltage High V
Input Current I
ILI2C
IHI2C
II2C
VIN = 0.1 x V
to 0.9 x V
Hysteresis of Schmitt
V
HYSI2C
VDD = 1.8 V
DD
DD
Si5319
Si5325
Si5326
Si5367
Min Typ Max Units
Si5368
——0.25xVDDV
0.7 x V
—VDDV
DD
–10 — 10 µA
0.1 x V
—— V
DD
trigger inputs
V
Output Voltage Low V
OHI2C
= 2.5 or 3.3 V
DD
VDD=1.8V
0.05 x V
—— V
DD
——0.2xVDDV
IO = 3 mA
= 2.5 or 3.3 V
V
DD
——0.4 V
IO = 3 mA
Table 5. DC Characteristics—Narrowband Devices (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Parameter Symbol Test Condition Min Typ Max Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)
Input Resistance XA
Input Voltage Level Limits XA
Input Voltage Swing XA
RIN
VIN
VPP
(RATE[1:0] = LM, ML, MH, or HM) 8.5 10 11.5 k
Differential Reference Clock Input Pins (XA/XB)
Input Resistance XA/XB
Differential Input Voltage
XA/XB
(RATE[1:0] = LM, ML, MH, or HM) 8.5 10 11.5 k
RIN
VIN
Level Limits
Input Voltage Swing XA
VPP
/XB
VPP
0—1.2 V
0.5 — 1.2 V
PP
0—1.2 V
0.5 — 1.2 V
PP, each
Rev. 0.41 31
Page 32
Si53xx-RM
CLKOUT_2
CLKIN_4*
FSYNC_ALIGN
FSYNCOUT*
* CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example
t
FSSU
t
FSH
t
LATF
t
1/f
FSYNC
LATF
CLKOUT_2
CLKIN_4*
FSYNC_ALIGN
FSYNCOUT*
* CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example
t
FSSU
t
FSH
t
1/f
FSYNC
Fixed number of CLKOUT_2
clock cycles.
LATF
Figure 13. Frame Synchronization Timing in Level Sensitive Mode
Figure 14. Frame Synchronization Timing in One-shot Mode
32 Rev. 0.41
Page 33
Table 6. AC Characteristics—All Parts
Si53xx-RM
Parameter Symbol Test Condition
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Input Frequency
CKN
F
When used as frame
synchronization input
CKIN_n Input Pins
Input Duty Cycle
(Minimum Pulse
Width) CKN
Input Capacitance CKN
Input Rise/Fall
Time
CKOUT_n Output Pins (See individual data sheets for speed grade limits)
Output Frequency
(Output not
configured for
CMOS or tri-state)
CKN
CK
Whichever is smaller
(i.e., the 40% / 60 %
limitation applies only
DC
to high frequency
clocks)
CIN
TRF
OF
20–80%
See Figure 12
Maximum Output
Frequency in
CMOS Format
Output Rise/Fall
(20–80%) at
622.08 MHz
Output Rise/Fall
(20–80%) at
212.5 MHz
Output Duty Cycle
Differential
Uncertainty
CKO
CKO
CKO
CKO
FMC
Output not config-
TRF
ured for CMOS See
Figure 12
CMOS Output
V
= 1.62
DD
TRF
DC
Cload = 5 pF
CMOS Output
= 2.97
V
DD
Cload = 5 pF
100 Load
Line to Line
Measured at 50%
Point (not for CMOS)
Min Typ Max Units
Si5366
Si5367
Si5368
19.38 — 710
19.43 — 707.35 MHz
0.002 — 707.35 MHz
10 — 710 MHz
—0.008 — MHz
2—512kHz
40 — 60 %
2——ns
—— 3pF
—— 11ns
19.38 — 710 MHz
19.43 — 1049 MHz
0.008 — 1049 MHz
10 — 945 MHz
0.002 — 945 MHz
970 — 1134 MHz
1.2125 — 1.4 GHz
— — 212.5 MHz
— 230 350 ps
—— 8 ns
—— 2 ns
——±40ps
Rev. 0.41 33
Page 34
Si53xx-RM
N3 1
Table 6. AC Characteristics—All Parts (Continued)
Parameter Symbol Test Condition
LVCMOS P i n s
Input Capacitance C
INC/DEC Pulse
Width
INC/DEC Time
Between
Consecutive
Pulses
LVCMOS Output Pins
Rise/Fall Times t
LOSn Trigger
Window
INC
INC
RF
in
PW
of INC or DEC to
DEL
of next INC or DEC
CLOAD = 20 pf
See Figure 12
FRQSEL[1:0] = LL
FRQSEL[1:0] = LM
FRQSEL[1:0] = LH
FRQSEL[1:0] = ML
FRQSEL[1:0] = MM
FRQSEL[1:0] = MH
From last CKIN_n
to internal detection
of LOSn
From last CKIN_n
to internal detection
of LOSn
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
Min Typ Max Units
—— 3pF
1——µs
16 — — ms
—25 —ns
8—45T
16 — 90 T
31 — 176 T
73 — 410 T
125 — 702 T
291 — 1638 T
100 x N3—570 x N3T
0.8 x
N3
— 4.5 x N3 T
CKIN
CKIN
CKIN
CKIN
CKIN
CKIN
CKIN
CKIN
LOS
TRIG
In narrowband mode
N3 = 1
FSYNC Mode
(CK_CONF = 1)
CKIN_3 and CKIN_4
From either edge of
CKIN_n to internal
detection of LOSn, in
Pin mode.
FSYNC Mode
(CK_CONF = 1)
CKIN_3 and CKIN_4
From either edge of
CKIN_n to internal
detection of LOSn, in
µP mode.
34 Rev. 0.41
250 ns — 4.5 T
1.8 — 2.2 T
1.8 — 4.5 T
CKIN
CKIN
CKIN
Page 35
Table 6. AC Characteristics—All Parts (Continued)
Si53xx-RM
Parameter Symbol Test Condition
LOSX Trigger
Window
Time to Clear LOS
Alarm
Time to Declare
LOL after LOS
Time to Clear LOL
after LOS Cleared
CKIN_n
Frequency for
FOS Monitoring
LOSX-
TRIG
t
LOSCLR
t
DECLOL
t
CLRLOL
FOS
From last XA clock
to internal detection
of LOSX
Measured from
appearance of valid
CKIN to of LOS
alarm
Measured from
appearance of valid
CKIN to of LOS
alarm
VALTIME[1:0] = 00
Measured from
appearance of valid
CKIN to of LOS
alarm
VALTIME[1:0] = 01
Measured from
appearance of valid
CKIN to of LOS
alarm
VALTIME[1:0] = 10
Measured from
appearance of valid
CKIN to of LOS
alarm
VALTIM E[1:0] = 11
LOS to LOL
LOS to LOL
Assume
Fold = Fnew,
Stable XA-XB
reference
CLK
Min Typ Max Units
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Si5368
100 — 285 T
1.8 — 4.4 ms
180 — 440 ms
XA
90 — 220 ms
90 — 220 ms
11 — 1 5 s
—— 2 µs
—10 —ms
10 — 710 MHz
Rev. 0.41 35
Page 36
Si53xx-RM
Table 6. AC Characteristics—All Parts (Continued)
Parameter Symbol Test Condition
FOS Trigger
Threshold
(Frequency offset
at which FOS is
declared)
Time to FOS
Alarm
FOS Clear
Threshold
(Frequency offset
at which FOS is
cleared)
FOS Hysteresis
FOS
FOS
FOS
FOS
FOS_THR[1:0] = 10
THR
(SMC Clock w/Stra-
3/3E reference)
FOS_THR[1:0] = 01
(SMC Compliant)
FOS_THR[1:0] = 00
(Stratum 3/3E
Compliant)
FOS_THR[1:0] = 11
Measured from shift
ALM
in input frequency to
FOS alarm
FOS_THR[1:0] = 10
(SMC Clock w/Stra-
3/3E reference)
FOS_THR[1:0] = 01
CLR
HYS
(SMC Compliant)
FOS_THR[1:0] = 00
(Stratum 3/3E
Compliant)
FOS_THR[1:0] = 11
FOS_THR[1:0] = 10
(SMC Clock w/Stra-
3/3E reference)
FOS_THR[1:0] = 01
(SMC Compliant)
FOS_THR[1:0] = 00
(Stratum 3/3E
Compliant)
FOS_THR[1:0] = 11
tum
tum
tum
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Min Typ Max Units
Si5367
Si5368
30 — 31 ±ppm
48 — 49 ±ppm
11 — 1 2 ±ppm
200 — 201 ±ppm
— 200 400 ms
27.5 — 28.5 ±ppm
45 — 46 ±ppm
9.5 — 10.5 ±ppm
192 — 193 ±ppm
1.5 — — ±ppm
2.0 — — ±ppm
0.5 — — ±ppm
7——±ppm
36 Rev. 0.41
Page 37
Table 6. AC Characteristics—All Parts (Continued)
Si53xx-RM
Parameter Symbol Test Condition
Time to Clear FOS
Alarm
t
FOSCLR
Measured from
appearance of valid
CKIN to of FOS
alarm
VALTIME[1:0] = 00,
Measured from
appearance of valid
CKIN to of FOS
alarm
VALTIME[1:0] = 10
Measured from
appearance of valid
CKIN to of FOS
alarm
VALTIM E[1:0] = 11
01
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
90 — 220 ms
180 — 440 ms
11 — 1 5 s
Rev. 0.41 37
Page 38
Si53xx-RM
Table 6. AC Characteristics—All Parts (Continued)
Parameter Symbol Test Condition
Device Skew
Output Clock
Skew,
see Section 7.7.4
t
SKEW
of CKOUT_n to of
CKOUT_m,
CKOUT_n and
CKOUT_m at same
frequency and signal
format
Coarse Skew
Adjust Resolution
t
PHRES
Using CLAT[7:0]
register
using INC/DEC pins
Coarse Skew
Adjust Range
t
PHSRNG
Using CLAT[7:0]
register
using INC/DEC pins
Time to Complete
t
CLAT
a Coarse Skew
Adjustment within
5% Using
CLAT[7:0] Register
Time Between
t
CLATDEL
Consecutive
CLAT[7:0] Writes
Fine Skew Adjust
Resolution
Fine Skew Adjust
Range
Time to Complete
t
FPHSRES
t
FPHSRNG
t
FLAT
using FLAT[14:0]
register
using FLAT[14:0]
register
a Fine Skew
Adjustment within
5% Using
FLAT[14:0]
Register4
Phase Offset
Resolution
Phase Offset
Range
FSYNC
Realignment
Accuracy
t
OFSTRES
t
OFSTRNG
t
LATF
using PHASEOFF-
SETn[7:0] registers
using PHASEOFF-
SETn[7:0] registers
Active edge of
CKIN_n (n = 3, 4)
when configured as
frame sync input to
active edge of
FS_OUT
FSYNC_SKEW[16:0]
=0
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
Si5367
Min Typ Max Units
Si5368
——100ps
—1/F
—1/F
–128 x
t
PHRES
VCO
VCO
—127 x
—ps
—ps
t
PHRES
– ——s
—— 22sec
83 — — µs
—9 —ps
–110 — 110 ps
—— 16ms
—N1_HS/
f
VCO
–128 x
t
OF-
STRES
—127 x
—
t
OF-
STRES
TBD — TBD ns
38 Rev. 0.41
Page 39
Table 6. AC Characteristics—All Parts (Continued)
Si53xx-RM
Parameter Symbol Test Condition
FSYNC Phase
Adjust Resolution
FS_OUT Phase
Adjust Range
PLL Performance
Lock Time t
Recovery Time
from Sleep Mode
Pin Reset or
Register Reset to
Microprocessor
Access Ready
Reset to first on
CKOUT
Minimum Reset
Pulse Width
Lock Time t
Maximum
Frequency
Deviation During
Self-Calibration
Power Supply
Rejection
Output Phase
Wander with
Temperature
Gradient
t
PHLSBF
t
PHRNGF
LOCKHW
t
SLP
t
READY
t
START
t
RSTMIN
LOCKMP
ICAL
DF
PSR
PH
DT
Usable settings lim-
ited to less than 1
period of FS_OUT
RST with valid
CKIN to LOL;
BW = 100 Hz
Exit Disable/Sleep
mode with valid CKIN
to LOL
FRQTBL=TBD and
Valid, stable clock on
CKIN
Start of ICAL to of
LOL
Sine wave noise on
V
to spur at output
DD
Differential clock
input @ 1.19 Vppd
with 0.5 ns rise/fall
time (20/80%) f
10 Hz to 10 kHz
(non-CMOS Output)
=10 kHz to
f
noise
10 MHz
Stable input clock
Temperature
gradient = 10 ºC/min
noise
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
Si5366
=
Si5367
Min Typ Max Units
Si5368
—1/
F
CKOUT2
— — 131,071
—1.2sec
——TBDms
—— 10ms
—— 1sec
1——µs
— 35 1000 ms
–20 — 5 %
— — –100 dB
——–75dBc/
——TBDps/C/
—s
s
x
t
PHLSBF
mV
RMS
min
Rev. 0.41 39
Page 40
Si53xx-RM
Table 6. AC Characteristics—All Parts (Continued)
Parameter Symbol Test Condition
Output Clock Initial
Phase Step
Output Clock
Phase Slope
Digital Hold Frequency Historical
Averaging Time
Digital Hold Frequency Historical
Delay Time
Digital Hold Initial
Frequency Error
Digital Hold
Frequency Stability
vs. Power Supply
Digital Hold
Frequency
Deviation vs.
Temperature
Closed Loop Jitter
Peaking
Jitter Tolerance
Spurious Noise
t
P_STEP
t
P_SLOPE
t
HISTAVG
t
HISTDEL
DH
DH
DH
J
PK
J
TOL
SP
SPUR
During clock switch
f3 >
f3 < 128 kHz
Wide band
During clock switch
Per GR-CORE-1244
VALTIME [1:0] >
External reference
clock Stable CKIN
selected until enter-
ing Digital Hold
DFI
External Resonator
Stable CKIN selected
until entering Digital
External Crystal
FVD
External Reference
Clock
External Crystal
External Reference
FVT
Clock
128 kHz
Hold
Si5316
Si5319
Si5322
Si5323
Si5325
Si5326
Si5365
01
Si5366
Min Typ Max Units
Si5367
Si5368
— 100 200 ps
—2.2 —ns
—1/f3 —
—— 61µs/s
—— 61µs/s
—6.7 —sec
—26.2 — ms
— — 50 ±ppb
—50 —±ppb
— 0.2 0.5 ppm/
Tracks External
Reference Clock
Tracks External Crystal
Tracks External
Reference Clock
— 0.05 0.1 dB
See "5.2.3. Jitter Tolerance" on
——–75dBc
page 47.
10%
in V
DD
40 Rev. 0.41
Page 41
Table 7. Jitter Generation (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)
Si53xx-RM
Parameter Symbol
Jitter Gen OC-192
J
Measurement
GEN
Test Condition
DSPLL BW
1,2,3,4,5
Min Typ Max GR-253 Spec Unit
2
Filter (MHz)
0.02–80 120 Hz — .34 .42 30 ps pp/0.3 UIpp ps
— .378 TBD N/A ps
7.85 kHz — TBD TBD 30 ps pp/0.3 UIpp ps
—.35.45 N/A ps
4–80 120 Hz — TBD TBD 10 ps pp/0.1 UIpp ps
—.20.31 N/A ps
7.85 kHz — TBD TBD 10 ps pp/0.1 UIpp ps
—.20.31 N/A ps
0.05–80 120 Hz — 2.4 TBD 10 ps pp/0.1 UIpp ps
— .31 .42 1.0 ps
(0.01 UI
rms
rms
7.85 kHz — TBD TBD 10 ps pp/
0.1 UIpp
— .36 .45 1.0 ps
(0.01 UI
rms
rms
0.012–20 120 Hz — 4.3 TBD 40.2 ps pp/
(0.1 UIpp)
ps
ps
ps
ps
PP
rms
PP
rms
PP
rms
PP
rms
PP
rms
PP
rms
PP
Jitter Gen OC-48
J
GEN
7.85 kHz — TBD TBD 40.2 ps pp/
.0008–80 120 Hz — TBD TBD N/A ps
Broadband Jitter
Generation
Notes:
1. Test condition: f
clock output.
2. BWSEL [1:0] loop bandwidth settings provided in Pin Descriptions.
3. 114.285 MHz 3rd OT crystal used as XA/XB input.
4. V
5. T
= 2.5 V
DD
= 85 °C
A
J
GEN
= f
IN
= 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL
OUT
7.85 kHz — TBD TBD N/A ps
—.32.40 4.02 ps
(0.01 UI
rms
rms
ps
ps
rms
PP
(0.1 UIpp)
—.35.46 4.02 ps
(0.01 UI
rms
rms
—.37.49 N/A ps
— .45 2.0 N/A ps
ps
rms
PP
rms
PP
rms
Rev. 0.41 41
Page 42
Si53xx-RM
Table 8. Jitter Generation (Si5322, Si5325, Si5365, Si5367)
Parameter Symbol
Jitter Gen OC-192 J
GEN
Test Condition
Measurement
Filter (MHz)
0.02–80 1096 — TBD TBD ps
1,2
DSPLL BW
(kHz)
Min Typ Max Unit
2
—.400TBDps
4–80 1096 — TBD TBD ps
—.190TBDps
0.05–80 1096 — TBD TBD ps
—.390TBDps
Jitter Gen OC-48 J
GEN
0.012–20 1096 — TBD TBD ps
—.387TBDps
Broadband Jitter
Generation
Notes:
1. Test condition: fIN = f
clock output.
2. BWSEL [1:0] loop bandwidth settings provided in Pin Descriptions.
J
GEN
0.0008–80 1096 — TBD TBD ps
—.405TBDps
= 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20–80%), LVPECL
OUT
Table 9. SPI Specifications (Si5319, Si5325, Si5326, Si5367, and Si5368)
PP
rms
PP
rms
PP
rms
PP
rms
PP
rms
Parameter Symbol Test Conditions Min Typ Max Unit
Duty Cycle, SCLK t
Cycle Time, SCLK t
Rise Time, SCLK t
Fall Time, SCLK t
Low Time, SCLK t
High Time, SCLK t
Delay Time, SCLK Fall to SDO Active t
Delay Time, SCLK Fall to SDO Transition t
Delay Time, SS Rise to SDO Tri-state t
Setup Time, SS to SCLK Fall t
Hold Time, SS to SCLK Rise t
Setup Time, SDI to SCLK Rise t
Hold Time, SDI to SCLK Rise t
Delay Time between Slave Selects t
Note: All timing is referenced to the 50% level of the waveform unless otherwise noted. Input test levels are VIH = VDD–4V,
VIL=0.4V.
DC
lsc
hsc
d1
d2
d3
su1
h1
su2
h2
cs
c
r
f
20–80% — — 25 ns
20–80% — — 25 ns
20–20% 30 — — ns
80–80% 30 — — ns
40 — 60 %
100 — — ns
——25ns
——25ns
——25ns
25 — — ns
20 — — ns
25 — — ns
20 — — ns
25 — — ns
42 Rev. 0.41
Page 43
Si53xx-RM
SCLK
SS
SDI
t
h1
t
d3
SDO
t
d1
t
d2
t
su1
t
r
t
f
t
c
t
su2
t
h2
t
cs
t
lsc
t
hsc
Figure 15. SPI Timing Diagram
Table 10. Thermal Characteristics
Parameter Symbol Test Condition Devices Value Unit
Thermal Resistance Junction to Ambient
JA
Still Air Si5316, Si5319,
Si5322, Si5323,
Si5325, Si5326
Si5365, Si5366,
Si5367, Si5368
32 ºC/W
40 ºC/W
Rev. 0.41 43
Page 44
Si53xx-RM
f
IN
DSPLL
Phase
Detector
Digital
DCO
Digital Filter Fvco
M
f
OUT
5. DSPLL (All Devices)
All members of the Any-Rate Precision Clocks family incorporate a phase-locked loop (PLL) that utilizes Silicon
Laboratories' third generation DSPLL technology to eliminate jitter, noise, and the need for external VCXO and
loop filter components found in discrete PLL implementations. This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly found in discrete PLL designs. Because external PLL
components are not required, sensitivity to board-level noise sources is minimized. This digital technology provides
highly stable and consistent operation over process, temperature, and voltage variations.
A simplified block diagram of the DSPLL is shown in Figure 16. This algorithm processes the phase detector error
term and generates a digital frequency control word M to adjust the frequency of the digitally-controlled oscillator
(DCO). The narrowband configuration devices (Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368) provide
ultra-low jitter generation and jitter attenuation. For applications where basic frequency multiplication of low jitter
clocks is all that is required, the wideband parts (Si5322, Si5325, Si5365, and Si5367) are available.
Figure 16. Any-Rate Precision Clock DSPLL Block Diagram
44 Rev. 0.41
Page 45
Si53xx-RM
Fin
DSPLL
Phase
Detector
Digital
DCO
Digital Filter
Divide By N2
Divide By N3
Divide By NC1 Fout
f
OUT
= (Fin/N3) x N2/NC1
f
vco
= (Fin/N3) x N2
f
3
f
VCO
5.1. Clock Multiplication
Fundamental to these parts is a clock multiplication circuit that is simplified in Figure 17. By having a large range of
dividers and multipliers, nearly any output frequency can be created from a fixed input frequency. For typical
telecommunications and data communications applications, the hardware control parts (Si5316, Si5322, Si5323,
Si5365, and Si5366) provide simple pin control.
The microprocessor controlled parts (Si5319, Si5325, Si5326, Si5367, and Si5368) provide a programmable range
of clock multiplications. To assist users in finding valid divider settings for a particular input frequency and clock
multiplication ratio, Silicon Laboratories offers PC-based software (DSPLLsim) that calculates these settings
automatically. When multiple divider combinations produce the same output frequency, the software recommends
the divider settings yielding the recommended settings for phase noise performance and power consumption.
Figure 17. Clock Multiplication Circuit
Rev. 0.41 45
Page 46
Si53xx-RM
Jitter
Transfer
0 dB
BW
f
Jitter
Peaking
–40 dB/dec.
Jitter Out
Jitter In
5.2. PLL Performance
All members of the Any-Rate Precision Clock family of devices provide extremely low jitter generation, a wellcontrolled jitter transfer function, and high jitter tolerance.
5.2.1. Jitter Generation
Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock.
Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of
the PLL bandwidth setting. Higher loop bandwidth settings may result in lower jitter generation, but may result in
less attenuation of jitter that might be present on the input clock signal.
5.2.2. Jitter Transfer
Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The
jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. The DSPLL
technology used in the Any-Rate Precision Clock devices provides tightly controlled jitter transfer curves because
the PLL gain parameters are determined largely by digital circuits which do not vary over supply voltage, process,
and temperature. In a system application, a well-controlled transfer curve minimizes the output clock jitter variation
from board to board and provides more consistent system level jitter performance.
The jitter transfer characteristic is a function of the loop bandwidth setting. Lower bandwidth settings result in more
jitter attenuation of the incoming clock, but may result in higher jitter generation. Section 1 Any-Rate Precision
Clock Product Family Overview also includes specifications related to jitter bandwidth and peaking. Figure 18
shows the jitter transfer curve mask.
Figure 18. PLL Jitter Transfer Mask/Template
46 Rev. 0.41
Page 47
Si53xx-RM
Input
Jitter
Amplitude
A
j0
–20 dB/dec.
f
Jitter In
Excessive Input Jitter Range
BW/100 BW/10
BW
A
j0
5000
BW
-------------
ns pk-pk=
A
j0
5000
100
-------------
50 ns pk-pk==
5.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 19 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value A
lower input jitter frequencies.
. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
j0
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth (i.e.,
BW):
For example, the jitter tolerance when f
Figure 19. Jitter Tolerance Mask/Template
= 155.52 MHz, f
in
= 622.08 MHz and the loop bandwidth (BW) is 100 Hz:
out
Rev. 0.41 47
Page 48
Si53xx-RM
6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)
These parts provide high-performance clock multiplication with simple pin control. Many of the control inputs are
three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply voltage:
V
and Ground. If the input pin is left floating, it is driven to nominally half of VDD. Effectively, this creates three
DD
logic levels for these controls.
These parts span a range of applications and I/O capacity as shown in Table 11.
Table 11. Si5316, Si5322, Si5323, Si5365 and Si5366 Key Features
Si5316 Si5322 Si5323 Si5365 Si5366
SONET Frequencies
DATACOM Frequencies
DATACOM/SONET internetworking
Fixed Ratio between input clocks
Flexible Frequency Plan
Number of Inputs 2 2 2 4 4
Number of Outputs 1 2 2 5 5
Jitter Attenuation
6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)
By setting the tri-level FRQSEL[3:0] pins these devices provide a wide range of standard SONET and data
communications frequency scaling, including simple integer frequency multiplication to fractional settings required
for error correction coding and decoding.
6.1.1. Clock Multiplication (Si5316)
The device accepts dual input clocks in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a dejittered output clock at the same frequency. The frequency range is set by the FRQSEL [1:0] pins, as shown in
Table 12.
Table 12. Frequency Settings
FRQSEL[1:0] Output Frequency (MHz)
LL 19.38–22.28
LM 38.75–44.56
LH 77.50–89.13
ML 155.00–178.25
MM 310.00–356.50
MH 620.00–710.00
48 Rev. 0.41
Page 49
Si53xx-RM
1, 4, 32
1, 4, 32
CKIN1
CKIN2
DSPLL
Core
F
out
f3 = F
out
f
3
One-to-one
frequency ratio
The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input
clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower
of the two clock inputs and is set via the FRQSEL [1:0] pins. The frequency applied at each clock input is divided
down by a pre-divider as shown in the "Detailed Block Diagram" on page 4. These pre-dividers must be set such
that the two resulting clock frequencies, f3_1 and f3_2 must be equal and are set by the FRQSEL [1:0] pins. Input
divider settings are controlled by the CK1DIV and CK2DIV pins, as shown in Table 13.
Table 13. Input Divider Settings
CKnDIV N3n Input Divider
L1
M4
H32
Table 14. Si5316 BW Values
FRQSEL[1:0] Nominal Frequency Values (MHz)
LL LM LH ML MM MH
19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz
BW[1:0]
HM 100 Hz 100 Hz 100 Hz 100 Hz 100 Hz 100 Hz
HL 210 Hz 210 Hz 200 Hz 200 Hz 200 Hz 200 Hz
MH 410 Hz 410 Hz 400 Hz 400 Hz 400 Hz 400 Hz
MM 1.7 kHz 1.7 kHz 1.6 kHz 1.6 kHz 1.6 kHz 1.6 kHz
ML 7.0 kHz 7.0 kHz 6.8 kHz 6.7 kHz 6.7 kHz 6.7 kHz
Figure 20. Si5316 Divisor Ratios
Rev. 0.41 49
Page 50
Si53xx-RM
6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366)
These parts provide flexible frequency plans for SONET, DATACOM, and interworking between the two (Table 15,
Table 16, and Table 17 respectively). For these parts, all of the CKINn inputs must be the same frequency as
specified in the tables. The outputs are the same frequency; however, in the Si5365 and Si5366, CKOUT3 and
CKOUT4 can be further divided down by using the DIV34 [1:0] pins.
The following notes apply to Tables 15, 16, and 17:
1. All entries are available for the Si5323 and Si5366. Only those marked entries under the WB column are
available for the Si5322 and Si5365.
2. The listed output frequencies appear on CKOUTn. For the Si5365 and Si5366, sub-multiples are available on
CKOUT3 and CKOUT4 using the DIV34[1:0] control pins.
3. All ratios are exact, but the frequency values are rounded.
4. For BW settings, f3 values, and frequency operating ranges, consult DSPLLsim.
5. For the Si5366 with CK_CONF = 1, CKIN3 and CKIN4 are the same frequency as FS_OUT.
Table 15. SONET Clock Multiplication Settings (FRQTBL=L)
No FRQSEL
[3:0]
0 LLLL 0.008 1 0.008 0.008 0.008
1 LLLM 2430 19.44 19.44 0.008
2 LLLH 4860 38.88 38.88 0.008
3 LLML 9720 77.76 77.76 0.008
4 LLMM 19440 155.52 155.52 0.008
5 LLMH 38880 311.04 311.04 0.008
6 LLHL 77760 622.08 622.08 0.008
fIN (MHz) Mult Factor Nominal
f
WB
OUT
* (MHz)
All Devices Si5366 Only
f
CKOUT5
(CK_CONF = 0)
(MHz)
FS_OUT (MHz)
(CK_CONF = 1)
50 Rev. 0.41
Page 51
Si53xx-RM
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
No FRQSEL
[3:0]
7LLHM
8LLHH
9LMLL
10 LMLM
11 LMLH 8 x (255/238) 166.63 166.63 NA
12 LMML 8 x (255/237) 167.33 167.33 NA
13 LMMM 8 x (255/236) 168.04 168.04 NA
14 LMMH
15 LMHL
16 LMHM 32 x (255/238) 666.51 666.51 NA
17 LMHH 32 x (255/237) 669.33 669.33 NA
18 LHLL 32 x (255/236) 672.16 672.16 NA
19 LHLM
fIN (MHz) Mult Factor Nominal
WB
19.44 1 19.44 19.44 0.008
2 38.88 38.88 0.008
4 77.76 77.76 0.008
8 155.52 155.52 0.008
16 311.04 311.04 0.008
32 622.08 622.08 0.008
48 933.12 933.12 0.008
f
OUT
* (MHz)
All Devices Si5366 Only
f
CKOUT5
(CK_CONF = 0)
(MHz)
FS_OUT (MHz)
(CK_CONF = 1)
20 LHLH
21 LHML
22 LHMM
23 LHMH
24 LHHL
25 LHHM 16 x (255/238) 666.51 666.51 NA
26 LHHH 16 x (255/237) 669.33 669.33 NA
27 MLLL 16 x (255/236) 672.16 672.16 NA
38.88 1 38.88 38.88 0.008
54 1049.76 1049.76 0.008
2 77.76 77.76 0.008
4 155.52 155.52 0.008
16 622.08 622.08 0.008
Rev. 0.41 51
Page 52
Si53xx-RM
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
No FRQSEL
[3:0]
28 MLLM
29 MLLH
30 MLML
31 MLMM
32 MLMH
33 MLHL 2 x (255/237) 167.33 167.33 NA
34 MLHM 2 x (255/236) 168.04 168.04 NA
35 MLHH
36 MMLL
37 MMLM
38 MMLH 8 x (255/237) 669.33 669.33 NA
39 MMML 8 x (255/236) 672.16 672.16 NA
40 MMMM
fIN (MHz) Mult Factor Nominal
f
* (MHz)
WB
77.76 1/4 19.44 19.44 0.008
1/2 38.88 38.88 0.008
1 77.76 77.76 0.008
2 155.52 155.52 0.008
2 x (255/238) 166.63 166.63 NA
4 311.04 311.04 0.008
8 622.08 622.08 0.008
8 x (255/238) 666.51 666.51 NA
155.52 1/8 19.44 19.44 0.008
OUT
All Devices Si5366 Only
f
CKOUT5
(CK_CONF = 0)
(MHz)
FS_OUT (MHz)
(CK_CONF = 1)
41 MMMH
42 MMHL
43 MMHM
44 MMHH
45 MHLL 255/237 167.33 167.33 NA
46 MHLM 255/236 168.04 168.04 NA
47 MHLH
48 MHML
49 MHMM
50 MHMH 4 x (255/237) 669.33 669.33 NA
51 MHHL 4 x (255/236) 672.16 672.16 NA
52 MHHM
53 MMHM
54 MHHH
55 MHML
166.63 238/255 155.52 155.52 NA
1/4 38.88 38.88 0.008
1/2 77.76 77.76 0.008
1 155.52 155.52 0.008
255/238 166.63 166.63 NA
2 311.04 311.04 0.008
4 622.08 622.08 0.008
4 x (255/238) 666.51 666.51 NA
1 166.63 166.63 NA
4 x (238/255) 622.08 622.08 NA
4 666.51 666.51 NA
52 Rev. 0.41
Page 53
Si53xx-RM
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
No FRQSEL
[3:0]
56 HLLL 167.33 237/255 155.52 155.52 NA
57 MMHM
58 HLLM 4 x (237/255) 622.08 622.08 NA
59 MHML
60 HLLH 168.04 236/255 155.52 155.52 NA
61 MMHM
62 HLML 4 x (236/255) 622.08 622.08 NA
63 MHML
64 HLMM
65 HLMH
66 HLHL
67 HLHM 2 x (255/237) 669.33 669.33 NA
68 HLHH 2 x (255/236) 672.16 672.16 NA
fIN (MHz) Mult Factor Nominal
f
* (MHz)
WB
311.04 1 311.04 311.04 0.008
1 167.33 167.33 NA
4 669.33 669.33 NA
1 168.04 168.04 NA
4 672.16 672.16 NA
2 622.08 622.08 0.008
2 x (255/238) 666.51 666.51 NA
OUT
All Devices Si5366 Only
f
CKOUT5
(CK_CONF = 0)
(MHz)
FS_OUT (MHz)
(CK_CONF = 1)
69 HMLL
70 HMLM
71 HMLH
72 HMML
73 HMMM
74 HMMH
75 HMHL
76 HMHM 255/237 669.33 669.33 NA
77 HMHH
78 HHLL
79 HMML
80 HHLM
81 HMMH
622.08 1/32 19.44 19.44 0.008
666.51 1/4 x 238/255 155.52 155.52 NA
1/16 38.88 38.88 0.008
1/8 77.76 77.76 0.008
1/4 155.52 155.52 0.008
1/2 311.04 311.04 0.008
1 622.08 622.08 0.008
255/238 666.51 666.51 NA
255/236 672.16 672.16 NA
1/4 166.63 166.63 NA
238/255 622.08 622.08 NA
1 666.51 666.51 NA
Rev. 0.41 53
Page 54
Si53xx-RM
Table 15. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)
No FRQSEL
[3:0]
82 HHLH 669.33 1/4 x 237/255 155.52 155.52 NA
83 HMML
84 HHML 237/255 622.08 622.08 NA
85 HMMH
86 HHMM 672.16 1/4 x 236/255 155.52 155.52 NA
87 HMML
88 HHMH 236/255 622.08 622.08 NA
89 HMMH
fIN (MHz) Mult Factor Nominal
WB
1/4 167.33 167.33 NA
1 669.33 669.33 NA
1/4 168.04 168.04 NA
1 672.16 672.16 NA
f
OUT
* (MHz)
All Devices Si5366 Only
f
CKOUT5
(CK_CONF = 0)
(MHz)
FS_OUT (MHz)
(CK_CONF = 1)
54 Rev. 0.41
Page 55
Si53xx-RM
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0)
Setting FRQSEL[3:0]
0LLLL
1LLLM
2 LLLH
3LLML
4LLMM
5 LLMH
6 LLHL 25/4 x 66/64 161.13
7 LLHM 51/8 x 66/64 164.36
8 LLHH 25/4 x 66/64 x 255/238 172.64
9 LMLL 25/4 x 66/64 x 255/237 173.37
10 LMLM 51/8 x 66/64 x 255/238 176.1
11 LMLH 51/8 x 66/64 x 255/237 176.84
12 LMML
13 LMMM
14 LMMH 25 x 66/64 644.53
15 LMHL 51/2 x 66/64 657.42
16 LMHM 25 x 66/64 x 255/238 690.57
17 LMHH 25 x 66/64 x 255/237 693.48
18 LHLL 51/2 x 66/64 x 255/238 704.38
19 LHLM 51/2 x 66/64 x 255/237 707.35
20 LHLH
21 LHML
22 LHMM
23 LHMH
24 LHHL
25 LHHM
26 LHHH
27 MLLL 3/2 x 66/64 x 255/238 176.1
28 MLLM 3/2 x 66/64 x 255/237 176.84
29 MLLH
30 MLML
31 MLMM
32 MLMH 6 x 66/64 x 255/238 704.38
33 MLHL 6 x 66/64 x 255/237 707.35
fIN (MHz) Mult Factor f
WB
15.625 2 31.25
25 17/4 106.25
31.25 2 62.5
53.125 2 106.25
106.25 3/2 x 66/64 164.36
462.5
8125
16 250
5125
17/2 212.5
17 425
4125
8250
4212.5
8425
2212.5
4425
6x66/64 657.42
OUT
* (MHz)
Rev. 0.41 55
Page 56
Si53xx-RM
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued)
Setting FRQSEL[3:0]
34 MLHM
35 MLHH 10/8 x 66/64 x 255/238 172.64
36 MMLL 10/8 x 66/64 x 255/237 173.37
37 MMLM
38 MMLH 5 x 66/64 x 255/238 690.57
39 MMML 5 x 66/64 x 255/237 693.48
40 MMMM
41 MMMH 66/64 x 255/238 172.64
42 MMHL 66/64 x 255/237 173.37
43 MMHM
44 MMHH 4 x 66/64 x 255/238 690.57
45 MHLL 4 x 66/64 x 255/237 693.48
46 MMMM
47 MMMH 66/64 x 255/238 176.1
48 MMHL 66/64 x 255/237 176.84
49 MMHM
50 MMHH 4 x 66/64 x 255/238 704.38
51 MHLL 4 x 66/64 x 255/237 707.35
52 MHLM
53 MHLH
54 MHML 255/237 173.37
55 MHMM
56 MHMH
57 MHHL 4 x 255/237 693.48
58 MHHM 164.36 2/3 x 64/66 106.25
59 MHLH
60 MHML 255/237 176.84
61 MHMM
62 MHMH
63 MHHL 4 x 255/237 707.35
64 MHHH 172.64 4/5 x 64/66 x 238/255 125
65 HLLL 64/66 x 238/255 156.25
66 HLLM
67 HLLH
68 MHMM
fIN (MHz) Mult Factor f
WB
125 10/8 x 66/64 161.13
5x66/64 644.53
156.25 66/64 161.13
4x66/64 644.53
159.375 66/64 164.36
4 x 66/64 657.4
161.13 4/5 x 64/66 125
255/238 172.64
4644.53
4 x 255/238 690.57
255/238 176.1
4657.42
4 x 255/238 704.38
238/255 161.13
4 x 238/255 644.53
4690.57
OUT
* (MHz)
56 Rev. 0.41
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Si53xx-RM
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued)
Setting FRQSEL[3:0]
69 HLML 173.37 4/5 x 64/66 x 237/255 125
70 HLMM 64/66 x 237/255 156.25
71 HLMH
72 HLHL 4 x 237/255 644.53
73 MHMM
74 HLHM 176.1 2/3 x 64/66 x 238/255 106.25
75 HLLL 64/66 x 238/255 159.375
76 HLLM
77 HLLH
78 MHMM
79 HLHH 176.84 2/3 x 64/66 x 237/255 106.25
80 HLMM 64/66 x 237/255 159.375
81 HLMH
82 HLHL 4 x 237/255 657.42
83 MHMM
84 HMLL
85 HMLM
86 HMLH
87 HMML
88 HMMM
89 HMMH
90 HMHL 255/237 693.48
91 HMHM
92 HMML
93 HMMM
94 HMMH
95 HMHL 255/237 707.35
96 HMHH 690.57 1/5 x 64/66 x 238/255 125
97 HHLL
98 HHLM
99 HMML
100 HHLH
101 HMMM
fIN (MHz) Mult Factor f
WB
212.5 2 425
425 1 425
644.53 1/5 x 64/66 125
657.42 1/6 x 64/66 106.25
237/255 161.13
4693.48
238/255 164.36
4 x 238/255 657.42
4704.38
237/255 164.36
4707.35
1/4 161.13
1644.53
255/238 690.57
1/4 164.36
1657.42
255/238 704.38
1/4 x 64/66 x 238/255 156.25
1/4 x 238/255 161.13
1/4 172.64
238/255 644.53
1690.57
OUT
* (MHz)
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Si53xx-RM
Table 16. Datacom Clock Multiplication Settings (FRQTBL = M, CK_CONF=0) (Continued)
Setting FRQSEL[3:0]
102 HHML 693.48 1/5 x 64/66 x 237/255 125
103 HHMM 1/4 x 64/66 x 237/255 156.25
104 HHMH
105 HMML
106 HHHL 237/255 644.53
107 HMMM
108 HHHM 704.38 1/6 x 64/66 x 238/255 106.25
109 HHLL 1/4 x 64/66 x 238/255 159.375
110 HHLM
111 H MML
112 HHLH
113 HMMM
114 HHHH 707.35 1/6 x 64/66 x 237/255 106.25
115 HHMM 1/4 x 64/66 x 237/255 159.375
116 HHMH
117 HMML
118 HHHL 237/255 657.42
119 HMMM
fIN (MHz) Mult Factor f
WB
1/4 x 237/255 161.13
1/4 173.37
1693.48
1/4 x (238/255) 164.36
1/4 176.1
238/255 657.42
1704.38
1/4 x (237/255) 164.36
1/4 176.84
1707.35
OUT
* (MHz)
58 Rev. 0.41
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Table 17. SONET to Datacom Clock Multiplication Settings
Setting FRQSEL[3:0]
0 LLLL 0.008 3125 25
1 LLLM 6480 51.84
2 LLLH 53125/8 53.125
3 LLML 15625/2 62.5
4 LLMM 53125/4 106.25
5 LLMH 15625 125
6 LLHL 78125/4 156.25
7 LLHM 159375/8 159.375
8 LLHH 53125/2 212.5
9 LMLL 53125 425
10 LMLM 19.440 625/486 25
11 LMLH 10625/3888 53.125
12 LMML 3125/972 62.5
13 LMMM 10625/1944 106.25
14 LMMH 3125/486 125
fIN (MHz) Mult Factor f
WB
OUT
* (MHz)
15 LMHL 15625/1944 156.25
16 LMHM 31875/3888 159.375
17 LMHH 15625/1944 x 66/64 161.13
18 LHLL 31875/3888 x 66/64 164.36
19 LHLM 15625/1944 x 66/
64 x 255/238
20 LHLH 31875/3888 x 66/
64 x 255/238
21 LHML 10625/972 212.5
22 LHMM 10625/486 425
23 LHMH 15625/486 x 66/64 644.53
24 LHHL 31875/972 x 66/64 657.42
25 LHHM 15625/486 x 66/
64 x 255/238
26 LHHH 31875/972 x 66/
64 x 255/238
27 MLLL 27.000 1 27
28 MLLM 250/91 74.17582
172.64
176.1
690.57
704.38
29 MLLH 11/4 74.25
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Si53xx-RM
Table 17. SONET to Datacom Clock Multiplication Settings (Continued)
Setting FRQSEL[3:0]
30 MLML
31 MLMM
32 MLMH 74.176 91/250 27
33 MLHL 1 74.17582
34 MLHM 91 x 11/250 x 4 74.25
35 MLHH 74.250 4/11 27
36 MMLL 4 x 250/11 x 91 74.17582
37 MMLM 1 74.25
38 MMLH 77.760 10625/7776 106.25
39 MMML 3125/1944 125
40 MMMM 15625/7776 156.25
41 MMMH 31875/15552 159.375
42 MMHL 15625/7776 x 66/64 161.13
43 MMHM 31875/15552 x 66/64 164.36
44 MMHH 15625/7776 x 66/
fIN (MHz) Mult Factor f
WB
62.500 2 125
4 250
64 x 255/238
OUT
172.64
* (MHz)
45 MHLL 31875/15552 x 66/
64 x 255/238
46 MHLM 10625/3888 212.5
47 MHLH 10625/1944 425
48 MHML 15625/1944 x 66/64 644.53
49 MHMM 31875/3888 x 66/64 657.42
50 MHMH 15625/1944 x 66/
64 x 255/238
51 MHHL 31875/3888 x 66/
64 x 255/238
176.1
690.57
704.38
60 Rev. 0.41
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Table 17. SONET to Datacom Clock Multiplication Settings (Continued)
Setting FRQSEL[3:0]
52 MHHM 155.520 15625/15552 156.25
53 MHHH 31875/31104 159.375
54 HLLL 15625/15552 x 66/64 161.13
55 HLLM 31875/31104 x 66/64 164.36
56 HLLH 15625/15552 x 66/
57 HLML 31875/31104 x 66/
58 HLMM 10625/7776 212.5
59 HLMH 10625/3888 425
60 HLHL 15625/3888 x 66/64 644.53
61 HLHM 31875/7776 x 66/64 657.42
62 HLHH 15625/3888 x 66/
63 HMLL 31875/7776 x 66/
fIN (MHz) Mult Factor f
WB
64 x 255/238
64 x 255/238
64 x 255/238
64 x 255/238
OUT
172.64
176.1
690.57
704.38
* (MHz)
64 HMLM 622.080 15625/15552 x 66/64 644.53
65 HMLH 31875/31104 x 66/64 657.42
66 HMML 15625/15552 x 66/
64 x 255/238
67 HMMM 31875/31104 x 66/
64 x 255/238
690.57
704.38
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A
j0
5e3
BW
----------
ns pk pk– BW is in Hz=
A
j0
5e3
100
----------
ns pk pk–50 ns pk-pk==
6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366)
Submultiples of the output frequency on CKOUT1 and CKOUT2 can be produced on the CKOUT3 and CKOUT4
outputs using the DIV34 [1:0] control pins as shown in Table 18.
Table 18. Clock Output Divider Control (DIV34)
DIV34[1:0] Output Divider Value
HH 32
HM 16
HL 10
MH 8
MM 6
ML 5
LH 4
LM 2
LL 1
6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)
The loop bandwidth (BW) is digitally programmable using the BWSEL [1:0] input pins. The device operating
frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of
the phase detector input frequency and the PLL feedback divider. See the PC-based software (DSPLLsim) that
calculates these values automatically. This utility is available for download from http://www.silabs.com/timing.
6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366)
The equation for the nominal high frequency jitter tolerance can be expressed as a function of the PLL loop
bandwidth:
Table 6, “AC Characteristics—All Parts,” on page 33 gives the worst case minimum tolerance that can be expected
given the nominal values calculated using the equation above.
For example, the DSPLL jitter tolerance when f
= 155.52 MHz, f
IN
= 622.08 MHz, and the loop bandwidth (BW)
OUT
is 100 Hz is:
6.1.6. Narrowband Performance (Si5316, Si5323, Si5366)
The DCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support
either a crystal oscillator or an input buffer (single-ended or differential) so that an external oscillator can become
the reference source. In both cases, there are wide margins in the absolute frequency of the reference input
because it is a fixed frequency and is used only as a jitter reference and as the reference frequency when in
holdover (see "6.4. Digital Hold/VCO Freeze" on page 68).
However, care must be exercised in certain areas for optimum performance. For details on this subject, refer to
"Appendix B—Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)" on
page 120. For examples of connections to the XA/XB pins, refer to "8.3. Crystal/Reference Clock Interfaces
(Si5316, Si5319, Si5323, Si5326, Si5366, & Si5368)" on page 112.
Note: The HH setting is not available for the Si5316.
62 Rev. 0.41
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6.1.7. Wideband Performance (Si5322 and Si5365)
These devices operate as wideband clock multipliers without an external resonator or reference clock. They are
ideal for applications where the input clock is already low jitter and only simple clock multiplication is required. A
limited selection of clock multiplication factors is available (See Table 15, Table 16, and Table 17).
6.1.8. Lock Detect (Si5322 and Si5365)
A PLL loss of lock indicator is not available in the wideband mode of operation.
6.1.9. Wideband Input-to-Output Skew (Si5322 and Si5365)
The input-to-output skew for wideband parts is not controlled.
6.2. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the selfcalibration state machine, and the LOL alarm will be active if in narrowband mode. The self-calibration time
t
LOCKHW
Any of the following events will trigger a self-calibration:
Power-on-reset (POR)
Release of the external reset pin RST (transition of RST from 0 to 1)
Change in FRQSEL, FRQTBL, BWSEL, or RATE pins
Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL.
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. For the Si5316, Si5323 and Si5366, the external crystal or
reference clock must also be present for the self-calibration to begin. If valid clocks are not present, the selfcalibration state machine will wait until they appear, at which time the calibration will start. All outputs are on during
the calibration process.
After a successful self-calibration has been performed with a valid input clock, no subsequent self-calibrations are
performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device
enters digital hold mode. When the input clock returns, the device relocks to the input clock without performing a
self-calibration.
6.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5323, Si5366)
An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is
within the operating range that is reported by DSPLLsim. The other CKINs must also either be stable in frequency
or squelched during a reset.
6.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366)
Follow the recommended RESET guidelines in Table 19 and Table 20 when reset should be applied to a device.
6.2.4. Narrowband Input-to-Output Skew (Si5316, Si5323, Si5366)
The input to output skew for narrowband devices is not controlled.
is given in Table 6, “AC Characteristics—All Parts”.
Rev. 0.41 63
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Table 19. Si5316, Si5322, and Si5323 Pins and Reset
Pin # Si5316 Pin
Name
2 N/A FRQTBL FRQTBL Yes
11 RATE 0 N/A RATE 0 Yes
14 DBL_BY DBL2_BY DBL2_BY No
15 RATE1 N/A RATE1 Yes
19 N/A N/A DEC No
20 N/A N/A INC No
22 BWSEL0 BWSEL0 BWSEL0 Yes
23 BWSEL1 BWSEL1 BWSEL1 Yes
24 FRQSEL0 FRQSEL0 FRQSEL0 Yes
25 FRQSEL1 FRQSEL1 FRQSEL1 Yes
26 N/A FRQSEL2 FRQSEL2 Yes
27 N/A FRQSEL3 FRQSEL3 Yes
30 SFOUT1 N/A SFOUT1 No, but skew not guaranteed without Reset
33 SFOUT0 N/A SFOUT0 No, but skew not guaranteed without Reset
Si5322 Pin
Name
Si5323 Pin
Name
Must Reset after Changing
Table 20. Si5365 and Si5366 Pins and Reset
Pin # Si5365 Pin Name Si5366 Pin Name Must Reset after Changing
4FRQTBL FRQTBL Yes
32 N/A RATE 0 Yes
42 N/A RATE 1 Yes
51 N/A CK_CONF Yes
54 N/A DEC No
55 N/A INC No
60 BWSEL0 BSWEL0 Yes
61 BWSEL1 BWSEL1 Yes
66 DIV34_0 DIV34_0 Yes
67 DIV34_1 DIV34_1 Yes
68 FRQSEL0 FRQSEL0 Yes
69 FRQSEL1 FRQSEL1 Yes
70 FRQSEL2 FRQSEL2 Yes
71 FRQSEL3 FRQSEL3 Yes
64 Rev. 0.41
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Si53xx-RM
Table 20. Si5365 and Si5366 Pins and Reset
Pin # Si5365 Pin Name Si5366 Pin Name Must Reset after Changing
80 N/A SFOUT1 No, but skew not guaranteed without Reset
95 N/A SFOUT0 No, but skew not guaranteed without Reset
6.3. Pin Control Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two
clocks differ in frequency by more than 100 ppm.
6.3.1. Manual Clock Selection
Manual control of input clock selection is chosen via the CS[1:0] pins according to Table 21 and Table 22.
Table 21. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL = L
CS (Si5316)
CS_CA (Si5322, Si5323)
0CKIN1
1CKIN2
The manual settings for the Si5365 and the Si5366 are shown in Table 22. The Si5366 has two modes of operation
(See Section “6.5. Frame Synchronization (Si5366)”). With CK_CONF = 0, any of the four input clocks may be
selected manually; however, when CK_CONF = 1 the inputs are paired, CKIN1 is paired with CKIN3 and likewise
for CKIN2 and CKIN4. Therefore, only two settings are available to select one of the two pairs.
Si5316 Si5322
AUTOSEL = L
Si75323
AUTOSEL = L
Table 22. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL = L
[CS1_CA4, CS0_CA3]_Pins Si5365 Si5366
CK_CONF = 0
(5 Output Clocks)
00 CKIN1 CKIN1 CKIN1/CKIN3
01 CKIN2 CKIN2 CKIN2/CKIN4
10 CKIN3 CKIN3 Reserved
11 CKIN4 CKIN4 Reserved
Notes:
1. To avoid clock switching based on intermediate states during a CS state change, the CS input pins are
internally deglitched (See Table 6, “AC Characteristics—All Parts”).
2. If the selected clock enters an alarm condition, the PLL enters digital hold mode.
CK_CONF = 1
(FS_OUT Configuration)
Rev. 0.41 65
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Si53xx-RM
6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)
The AUTOSEL input pin sets the input clock selection mode as shown in Table 23. Automatic switching is either
revertive or non-revertive. Setting AUTOSEL to M or H, changes the CSn_CAm pins to output pins that indicate the
state of the automatic clock selection (See Table 24 and Table 25). Digital hold is indicated by all CnB signals going
high after a valid ICAL.
Table 23. Automatic/Manual Clock Selection
AUTOSEL Clock Selection Mode
L Manual (See Previous Section)
M Automatic Non-revertive
H Automatic Revertive
Table 24. Clock Active Indicators (AUTOSEL = M or H) (Si5322 and Si5323)
CS_CA Active Clock
0CKIN1
1CKIN2
Table 25. Clock Active Indicators (AUTOSEL = M or H) (Si5365 and Si5367)
CA1 CA2 CS0_CA3 CS1_CA4 Active Clock
1000CKIN1
0100CKIN2
0010CKIN3
0001CKIN4
The prioritization of clock inputs for automatic switching is shown in Table 26 and Table 27. This priority is
hardwired in the devices.
Table 26. Input Clock Priority for Auto Switching (Si5322, Si5323)
Priority Input Clocks
1CKIN1
2CKIN2
3 Digital Hold
66 Rev. 0.41
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Table 27. Input Clock Priority for Auto Switching (Si5365, Si5366)
Priority Input Clock Configuration
Si5365 Si5366
4 Input Clocks
(CK_CONF = 0)
1 CKIN1 CKIN1/CKIN3
2 CKIN2 CKIN2/CKIN4
3 CKIN3 N/A
4 CKIN4 N/A
5 Digital Hold Digital Hold
At power-on or reset, the valid CKINn with the highest priority (1 being the highest priority) is automatically
selected. If no valid CKINn is available, the device suppresses the output clocks and waits for a valid CKINn signal.
If the currently selected CKINn goes into an alarm state, the next valid CKINn in priority order is selected. If no valid
CKINn is available, the device enters Digital Hold.
Operation in revertive and non- revertive is different when a signal becomes valid:
Revertive (AUTOSEL = H): The device constantly monitors all CKINn. If a CKINn with a higher priority than
the current active CKINn becomes valid, the active CKINn is changed to the
CKINn with the highest priority.
Non-revertive (AUTOSEL = M): The active clock does not change until there is an alarm on the active clock. The
device will then select the highest priority CKINn that is valid. Once in digital hold,
the device will switch to the first CKINn that becomes valid.
6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366)
Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase
transients to the clock outputs during input clock switching. All switching between input clocks occurs within the
input multiplexor and phase detector circuitry. The phase detector circuitry continually monitors the phase
difference between each input clock and the DSPLL output clock, f
clock signal at a specified phase offset relative to f
At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for
the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the
new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the
two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output.
The switching technology virtually eliminates the output clock phase transients traditionally associated with clock
rearrangement (input clock switching). The Maximum Time Interval Error (MTIE) and maximum slope for clock
output phase transients during clock switching are given in (Table 6, “AC Characteristics—All Parts”). These values
fall significantly below the limits specified in the Telcordia GR-1244-CORE and GR-253-CORE requirements.
so that the phase offset is maintained by the PLL circuitry.
OSC
FSYNC Switching
(CK_CONF = 1)
. The phase detector circuitry can lock to a
OSC
Rev. 0.41 67
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Si53xx-RM
6.4. Digital Hold/VCO Freeze
All Any-Rate Precision Clock devices feature a hold over or VCO freeze mode, whereby the DSPLL is locked to a
digital value.
6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366)
If an LOS or FOS condition exists on the selected input clock, the device enters digital hold. In this mode, the
device provides a stable output frequency until the input clock returns and is validated. When the device enters
digital hold, the internal oscillator is initially held to its last frequency value. Next, the internal oscillator slowly
transitions to a historical average frequency value that was taken over a time window of 6,711 ms in size that
ended 26 ms before the device entered digital hold. This frequency value is taken from an internal memory location
that keeps a record of previous DSPLL frequency values. By using a historical average frequency, input clock
phase and frequency transients that may occur immediately preceding loss of clock or any event causing digital
hold do not affect the digital hold frequency. Also, noise related to input clock jitter or internal PLL jitter is
minimized.
If a highly stable reference, such as an oven-controlled crystal oscillator, is supplied at XA/XB, an extremely stable
digital hold can be achieved. If a crystal is supplied at the XA/XB port, the digital hold stability will be limited by the
stability of the crystal; Table 6, “AC Characteristics—All Parts” gives the specifications related to the digital hold
function.
6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366)
When the input clock signal returns, the device transitions from digital hold to the selected input clock. The device
performs hitless recovery from digital hold. The clock transition from digital hold to the returned input clock includes
"phase buildout" to absorb the phase difference between the digital hold clock phase and the input clock phase.
See Table 6, “AC Characteristics—All Parts” for specifications.
6.4.3. Wideband VCO Freeze (Si5322, Si5365)
If an LOS condition exists on the selected input clock, the device freezes the VCO. In this mode, the device
provides a stable output frequency until the input clock returns and is validated. When the device enters VCO
freeze, the internal oscillator is initially held to its last frequency value.
6.5. Frame Synchronization (Si5366)
FSYNC is used in applications that require a synchronizing pulse that has an exact number of periods of a highrate clock, Frame Synchronization is selected by setting CK_CONF = 1 and FRQTBL = L). In a typical frame
synchronization application, CKIN1 and CKIN2 are high-speed input clocks from primary and secondary clock
generation cards and CKIN3 and CKIN4 are their associated primary and secondary frame synchronization
signals. The device generates four output clocks and a frame sync output FS_OUT. CKIN3 and CKIN4 control the
phase of FS_OUT.
The frame sync inputs supplied to CKIN3 and CKIN4 must be 8 kHz. Since the frequency of FS_OUT is derived
from CKOUT2, CKOUT2 must be a standard SONET frequency (e.g. 19.44 MHz, 77.76 MHz). Table 15 lists the
input frequency/clock multiplication ratio combinations supporting an 8 kHz output on FS_OUT.
68 Rev. 0.41
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6.6. Output Phase Adjust (Si5323, Si5366)
Overall device skew (CKINn to CKOUT_n phase delay) is controllable via the INC and DEC input pins. A positive
pulse applied at the INC pin increases the device skew by 1/f
the DEC pin decreases the skew by the same amount. Since f
control is approximately 200 ps. Using the INC and DEC pins, there is no limit to the range of skew adjustment that
can be made. Following a power-up or reset, the skew will revert to the reset value. See Table 6, “AC
Characteristics—All Parts” for specifications related to the phase adjust feature.
The INC pin function is not available for all frequency table selections. DSPLLsim reports this whenever it is used
to implement a frequency plan.
6.6.1. FSYNC Realignment (Si5366)
The FS_ALIGN pin controls the realignment of FS_OUT to the active CKIN3 or CKIN4 input. The currently active
frame sync input is determined by which input clock is currently being used by the PLL. For example, if CKIN1 is
being selected as the PLL input, CKIN3 is the currently-active frame sync input. If neither CKIN3 or CKIN4 are
currently active (digital hold), the realignment request is ignored. The active edge used for realignment is the
CKIN3 or CKIN4 rising edge.
FS_ALIGN operates in Level Sensitive mode (See Figure 13, “Frame Synchronization Timing in Level Sensitive
Mode,”). While FS_ALIGN is active, each active edge of the currently-active frame sync input (CKIN3 or CKIN4) is
used to control the NC5 output divider and therefore the FS_OUT phase. Note that while the realignment control is
active, it cannot be guaranteed that a fixed number of high-frequency clock (CKOUT2) cycles exists between each
FS_OUT cycle.
The resolution of the phase realignment is 1 clock cycle of CKOUT2. If the realignment control is not active, the
NC5 divider will continuously divide down its f
clock (CKOUT2) cycles between each FS_OUT cycle.
At power-up or any time after the PLL has lost lock and relocked, the device automatically performs a realignment
of FS_OUT using the currently active sync input. After this, as long as the PLL remains in lock and a realignment is
not requested, FS_OUT will include a fixed number of high-speed clock cycles, even if input clock switches are
performed. If many clock switches are performed in phase build-out mode, it is possible that the input sync to
output sync phase relationship will shift due to the accumulated residual phase transients of the phase build-out
circuitry. If the sync alignment error exceeds the threshold in either the positive or negative direction, an alignment
alarm becomes active. If it is then desired to reestablish the desired input-to-output sync phase relationship, a
realignment can be performed. A realignment request may cause FS_OUT to instantaneously shift its output edge
location in order to align with the active input sync phase.
6.6.2. Including FSYNC Inputs in Clock Selection (Si5366)
The frame sync inputs, CKIN3 and CKIN4, are both monitored for loss-of-signal (LOS3_INT and LOS4_INT)
conditions. To include these LOS alarms in the input clock selection algorithm, set FSYNC_SWTCH = 1. The
LOS3_INT is logically ORed with LOS1_INT and LOS4_INT is ORed with LOS2_INT as inputs to the clock
selection state machine. If it is desired not to include these alarms in the clock selection algorithm, set
FSYNC_SWTCH = 0. The frequency offset (FOS) alarms for CKIN1 and CKIN2 can also be included in the state
machine decision making as described in Section “6.9. Alarms”; however, in frame sync mode (CK_CONF = 1), the
FOS alarms for CKIN3 and CKIN4 are ignored. See Table 32 on page 72.
6.6.3. FS_OUT Polarity and Pulse Width Control (Si5366)
Additional output controls are available for FS_OUT. FS_OUT is active high, and the pulse width is equal to one
period of the CKOUT2 output clock. For example, if CKOUT2 is 622.08 MHz, the FS_OUT pulse width will be 1/
622.08e6 = 1.61 ns.
6.6.4. Using FS_OUT as a Fifth Output Clock (Si5366)
In applications where the frame synchronization functionality is not needed, FS_OUT can be used as a fifth clock
output. In this case, no realignment requests should be made to the NC5 divider. (This is done by holding
FS_ALIGN to 0.)
CKOUT2
input. This guarantees a fixed number of high-frequency
, one period of the DCO output clock. A pulse on
OSC
is close to 5 GHz, the resolution of the skew
OSC
Rev. 0.41 69
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Si53xx-RM
6.6.5. Disabling FS_OUT (Si5366)
The FS_OUT maybe disabled via the DBLFS pin, see Table 28. The additional state (M) provided allows for
FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the
SFOUT[1:0] pins.
Table 28. FS_OUT Disable Control (DBLFS)
DBLFS FS_OUT State
H Tri-State/Powerdown
M Active/CMOS Format
L Active/SFOUT[1:0] Format
6.7. Output Clock Drivers
The devices include a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS,
CML, and CMOS formats. The signal format is selected jointly for all outputs using the SFOUT [1:0] pins, which
modify the output common mode and differential signal swing. See Table 3, “DC Characteristics—All Parts
(Current draw is independent of supply voltage)” for output driver specifications. The SFOUT [1:0] pins are threelevel input pins, with the states designated as L (ground), M (V
Table 29 shows the signal formats based on the supply voltage and the type of load being driven. For the CMOS
setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be externally shorted
together to obtain the drive strength specified in Table 3, “DC Characteristics—All Parts (Current draw is
independent of supply voltage)”, see Section “8.2. Output Clock Drivers”.
/2), and H (VDD).
DD
Table 29. Output Signal Format Selection (SFOUT)
SFOUT[1:0] Signal Format
HL CML
HM LVDS
LH CMOS
LM Disabled
MH LVPECL
ML Low-swing LVDS
All Others Reserved
The SFOUT [1:0] pins can also be used to disable the output. Disabling the output puts the CKOUT+ and CKOUT–
pins in a high-impedance state relative to V
each other through a 200 on-chip resistance (differential impedance of 200 ). The maximum amount of internal
circuitry is powered down, minimizing power consumption and noise generation. Recovery from the disable mode
requires additional time as specified in Table 6, “AC Characteristics—All Parts”.
6.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)
The LVPECL and CMOS output formats draw more current than either LVDS or CML. However, the allowed output
format pin settings are restricted so that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When SFOUT[1:0] = MH or LH (for either LVPECL or CMOS), either DBL5 must be H or
DBL34 must be high.
(common mode tri-state) while the two outputs remain connected to
DD
70 Rev. 0.41
Page 71
Si53xx-RM
6.8. PLL Bypass Mode
The Device supports a PLL Bypass Mode in which the selected input clock is fed directly to all enabled output
buffers, bypassing the DSPLL. In PLL Bypass Mode, the input and output clocks will be at the same frequency. PLL
Bypass Mode is useful in a laboratory environment to measure system performance with and without the jitter
attenuation provided by the DSPLL.
The DSBL2/BYPASS pin is used to select the PLL Bypass Mode according to Table 30.
Table 30. DSBL2/BYPASS Pin Settings
DSBL2/BYPASS Function
L CKOUT2 Enabled
M CKOUT2 Disabled
H PLL Bypass Mode w/ CKOUT2 Enabled
Internally, the bypass path is implemented with high-speed differential signaling for low jitter.
6.9. Alarms
Summary alarms are available to indicate the overall status of the input signals and frame alignment (Si5366 only).
Alarm outputs stay high until all the alarm conditions for that alarm output are cleared.
6.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366)
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT output signal that is processed with other alarms to generate CnB.
An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active. Similarly, an LOS condition on
CKINn causes the LOSn_INT alarm to become active. Once a LOSn_INT alarm is asserted on one of the input
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT after a valid input clock appears is listed in Table 6, “AC Characteristics—All Parts”. If another error
condition on the same input clock is detected during the validation time then the alarm remains asserted and the
validation time starts over.
6.9.1.1. Narrowband LOS Algorithm (Si5316, Si5323, Si5366)
The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. (For the Si5316, the output
of divider N3 (See Figure 1) is used.) The LOS circuitry over samples this divided down input clock using a 40 MHz
clock to search for extended periods of time without input clock transitions. If the LOS monitor detects twice the
normal number of samples without a clock edge, a LOSn_INT alarm is declared. Table 6, “AC Characteristics—All
Parts” gives the minimum and maximum amount of time for the LOS monitor to trigger.
To facilitate automatic hitless switching, the LOS triggering time is significantly reduced while in narrowband mode.
6.9.1.2. Wideband LOS Algorithm (Si5322, Si5365)
Each input clock is divided down to produce a 78 kHz to 1.2 MHz signal before entering the LOS monitoring
circuitry. The same LOS algorithm as described in the above section is then used.
6.9.2. FOS Alarms (Si5365 and Si5366)
If FOS Alarms are enabled (See Table 31), the internal frequency offset alarms (FOSn_INT) indicate if the input
clocks are within a specified frequency band relative to the frequency of CKIN2. The frequency offset monitoring
circuitry compares the frequency of the input clock(s) with CKIN2. If the frequency offset of an input clock exceeds
a preset frequency offset threshold, an FOS alarm (FOSn_INT) is declared for that clock input. Note that FOS
monitoring is not available on CKIN3 and CKIN4 if CK_CONF = 1. The device supports FOS hysteresis per GR1244-CORE, making the device less susceptible to FOS alarm chattering. A TCXO or OCXO reference clock must
be used in conjunction with either the SMC or Stratum 3/3E settings. Note that the wander can cause false FOS
alarms.
Rev. 0.41 71
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Si53xx-RM
Table 31. Frequency Offset Control (FOS_CTL)
FOS_CNTL Meaning
L FOS Disabled.
M Stratum 3/3E FOS Threshold (12 ppm)
H SONET Minimum Clock Threshold (48 ppm)
6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L)
At power-up or any time after the PLL has lost lock and relocked, the device automatically performs a realignment
of FS_OUT using the currently active sync input. After this, as long as the PLL remains in lock and a realignment is
not requested, FS_OUT will include a fixed number of high-speed clock cycles, even if input clock switches are
performed. If many clock switches are performed in phase build-out mode, it is possible that the input sync to
output sync phase relationship will shift due to the accumulated residual phase transients of the phase build-out
circuitry. The internal ALIGN_INT signal is asserted when the accumulated phase errors exceeds two cycles of
CKOUT2.
6.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323)
The alarm outputs (C1B and C2B) are determined directly by the LOS1_INT and LOS2_INT internal indicators
directly. That is C1B = LOS1 and C2B = LOS2.
6.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366)
The alarm outputs (C1B, C2B, C3B, ALRMOUT) provide a summary of various alarm conditions on the input clocks
depending on the setting of the FOS_CNTL and CK_CONF pins.
The following internal alarm indicators are used in determining the output alarms:
LOSn_INT: See the previous section for a description of how LOSn_INT is determined
FOSn_INT: See the previous section for a description of how FOSn_INT is determined
ALIGN_INT: See the previous section for a description of how ALIGN_INT is determined
Based on the above internal signals and the settings of the CK_CONF and FOS_CTL pins, the outputs C1B, C2B,
C3B, ALRMOUT are determined (See Table 32). For details, see "Appendix D—Alarm Structure" on page 139.
Table 32. Alarm Output Logic Equations
CK_CONF FOS_CTL Alarm Output Equations
0
Four independent input
clocks
1
(FSYNC switching
mode)
72 Rev. 0.41
(Disables FOS)
(Disables FOS)
L
M or H C1B = LOS1_INT or FOS1_INT
C2B = LOS2_INT or FOS2_INT
C3B = LOS3_INT or FOS3_INT
ALRMOUT = LOS4_INT or FOS4_INT
L
M or H C1B = LOS1_INT or (LOS3_INT and FSYNC_SWTCH) or FOS1_INT
C2B = LOS2_INT or (LOS4_INT and FSYNC_SWTCH) or FOS2_INT
C1B = LOS1_INT or (LOS3_INT and FSYNC_SWTCH)
C2B = LOS2_INT or (LOS4_INT and FSYNC_SWTCH)
C1B = LOS1_INT
C2B = LOS2_INT
C3B = LOS3_INT
ALRMOUT = LOS4_INT
C3B = tri-state
ALRMOUT = ALIGN_INT
C3B = tri-state
ALRMOUT = ALIGN_INT
Page 73
Si53xx-RM
6.9.5.1. Lock Detect (Si5316, Si5323, Si5366)
The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time
between two consecutive phase cycle slips is greater than the Retrigger Time, the PLL is in lock. The LOL output
has a guaranteed minimum pulse width as shown in (Table 6, “AC Characteristics—All Parts”). The LOL pin is also
held in the active state during an internal PLL calibration.
The retrigger time is automatically set based on the PLL closed loop bandwidth (See Table 33).
Table 33. Lock Detect Retrigger Time
PLL Bandwidth Setting (BW) Retrigger Time (ms)
60–120 Hz 53
120–240 Hz 26.5
240–480 Hz 13.3
480–960 Hz 6.6
960–1920 Hz 3.3
1920–3840 Hz 1.66
3840–7680 Hz .833
6.9.5.2. Lock Detect (Si5322, Si5365)
A PLL loss of lock indicator is not available in the wideband mode of operation
6.10. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST
then performs a PLL Self-Calibration (See “6.2. PLL Self-Calibration”).
can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
6.11. DSPLLsim Configuration Software
To simplify frequency planning, loop bandwidth selection, and general device configuration of the Any-Rate
Precision Clocks. Silicon Laboratories has a configuration utility-DSPLLsim. This software is available to download
from http://www.silabs.com/timing.
Rev. 0.41 73
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Si53xx-RM
A
j0
5000
BW
-------------
ns pk-pk (BW is in Hz)=
A
j0
5000
100
-------------
ns pk pk–50""ns pk pk–==
7. Microprocessor Controlled Parts (Si5319, Si5325, Si5326, Si5367, Si5368)
The devices in this family provide a rich set of clock multiplication/clock division options, loop bandwidth selections,
output clock phase adjustment, and device control options (See Table 34).
Table 34. Si5325, Si5326, Si5367 and Si5368 Key Features
Si5319 Si5325 Si5326 Si5367 Si5368
SONET Frequencies
DATACOM Frequencies
DATACOM/SONET Internetworking
Programmable Frequency Plan
Number of Inputs 12244
Number of Outputs 12255
Jitter Attenuation (Narrowband)
Wide Band
Table 35. Device Control Modes
CMODE Control Mode
LI
H SPI
2
C
7.1. Clock Multiplication
The input frequency, clock multiplication ratio, and output frequency are set via register settings. Because the
DSPLL dividers settings are directly programmable, a wide range of frequency translations is available. In addition,
a wider range of frequency translations is available in narrowband mode than wideband mode due to the lower
phase detector frequency range in narrowband mode. To assist users in finding valid divider settings for a particular
input frequency and clock multiplication ratio, Silicon Laboratories offers PC-based software (DSPLLsim) that
calculates these settings automatically. When multiple divider combinations produce the same output frequency,
the software recommends the divider settings that yield the best combination of phase noise performance and
power consumption.
7.1.1. Jitter Tolerance (Si5319, Si5325, Si5326, Si5367, and Si5368)
The equation for the nominal high frequency jitter tolerance can be expressed as a function of the PLL loop
bandwidth (see Section “5.2.3. Jitter Tolerance”):
Table 6, “AC Characteristics—All Parts” gives the worst case minimum tolerance that can be expected given the
nominal values calculated using the equation above.
For example, the DSPLL jitter tolerance when f
is 100 Hz:
The values for BW can be calculated using the DSPLLsim software package.
74 Rev. 0.41
= 155.52 MHz, f
IN
= 622.08 MHz, and the loop bandwidth f
OUT
3dB
Page 75
Si53xx-RM
2
/
CKIN1
N31
/CKIN2 N32
2
2
N2
N2 = N2_LS
N2_LS = [32, 34, 36, …, 512]
NC1
NC2
/
CKOUT_1
/
CKOUT_2
2
4.85 – 5.67 GHz
f
IN
=
10 MHz–710 MHz
f
OUT
= 2 kHz -–1 . 4 GH z
/
CKIN3
N33
/
CKIN4
N34
2
2
10 MHz–
157.5 MHz
NC1 = N1_ HS x N1_ LS
N1_ HS = [4,5,6,...,11]
N1_LS = [1,2,4,6,...,2
20
]
NC5
/
CKOUT_5
2
f
3
f
3
N1
N3 =
[1,2,3,...,2
19
]
f
OSC
DSPLL
®
N1_HS
7.1.2. Wideband Mode (Si5325, Si5367)
These devices operate as wideband clock multipliers without an external resonator or reference clock. This mode
may be desirable if the input clock is already low jitter and only simple clock multiplication is required. A limited
selection of clock multiplication factors is available in this mode. The input-to-output skew for wideband parts is not
controlled.
Refer to Figure 21. The selected input clock passes through the N3 input divider and is provided to the DSPLL. The
input-to-output clock multiplication ratio is defined as follows:
f
= fIN x N2/(N1 x N3)
OUT
where:
N1 = output divider
N2 = feedback divider
N3 = input divider
Figure 21. Wideband PLL Divider Settings (Si5325, Si5367)
Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO
frequency, there are restrictions on the ratio of one output frequency to another output frequency. That is, there is
considerable freedom in the ratio between the input frequency and the first output frequency; but once the first
output frequency is chosen, there are restrictions on subsequent output frequencies. These restrictions are made
tighter by the fact that the N1_HS divider is shared among all of the outputs. DSPLLsim should be used to
determine if two different simultaneous outputs are compatible with one another.
The same issue exists for inputs of different frequencies: both inputs, after having been divided by their respective
N3 dividers, must result in the same f3 frequency because the phase/frequency detector can operate at only one
frequency at one time.
The DSPLL feedback divider value is read from the N2_LS register. Settings for several popular frequency plans
are shown in Table 36. The DSPLLsim program can be used to determine the settings for other frequency plans, as
well as settings for the output dividers.
Rev. 0.41 75
Page 76
Si53xx-RM
Table 36. Common Divider Settings (Wideband/µP Control Mode - Si5325 and Si5367)
fIN (MHz) f
(MHz) N1_HS N1_LS N2_LS N3
OUT
19.44 19.44 5 50 250 1
77.76 8 8 256 1
155.52 8 4 256 1
622.08 4 2 256 1
77.76 77.76 8 8 64 1
155.52 8 4 64 1
622.08 4 2 64 1
155.52 155.52 8 4 64 2
622.08 4 2 64 2
622.08 622.08 4 2 40 5
Note: For some input frequency/clock multiplication ratio combinations, multiple divider settings produce the same
output frequency. Divider settings listed above are based on Silicon Laboratories’ DSPLLsim software that
estimates which divider setting produces the best phase noise performance while minimizing power
consumption. See the Register Map documentation for the appropriate write values.
Example
Assume the input clock rate on CKIN1, CKIN2, CKIN3, and CKIN4 is 19.44 MHz and the desired input-to-output
multiplication factor is 32, producing an output clock frequency of 622.08 MHz. Using the desired output frequency
value, set N1 = 8 (N1_HS = 8 and N1_LS = 1) to put f
f
= 622.08 MHz x 8 = 4.98 GHz
OSC
within its operating range:
OSC
Next, set N3 = 1 to keep the phase detector rate within its operating range:
N3 = 1
Substituting these values in the input-to-output frequency multiplication equation and solving for N2 yields:
32 = N2/(8 x 1)
N2 = 256
Therefore,
N1_HS = 8
N1_LS = 1
N2_LS = 256
N3 = 1.
76 Rev. 0.41
Page 77
Si53xx-RM
7.1.2.1. Loop Bandwidth (Si5325, Si5367)
The loop bandwidth (BW) is digitally programmable using the BWSEL_REG
frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of
the phase detector input frequency and the PLL feedback divider.
Table 30 shows the loop bandwidth values available for common SONET frequency translations. Where values are
not shown, the corresponding loop bandwidth falls outside the valid device loop bandwidth range of 30 kHz to 1.3
MHz.
Table 37. Common Loop Bandwidth (MHz) (Si5325 and Si5367)
f
(MHz) f
IN
19.44 19.44 1.2 0.6 0.3
77.76 77.76 — — 1.2
(MHz) 0000 0001 0010
OUT
77.76
155.52
622.08
155.52
[3:0] register bits. The device operating
BWSEL_REG[3:0]
622.08
155.52 155.52 — — 1.2
622.08
622.08 622.08 — — 1.9
Note: Loop bandwidth is a function of phase detector frequency f3. For some input frequency/clock
multiplication ratio combinations, multiple divider settings produce the same output frequency. Loop
bandwidth settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates
which divider setting produces the best phase noise performance while minimizing power consumption.
7.1.2.2. Lock Detect (Si5325, Si5367)
A PLL loss of lock indicator is not available in the wideband mode of operation.
7.1.2.3. Input to Output Skew (Si5325, Si5367)
The input to output skew for wideband devices is not controlled.
Rev. 0.41 77
Page 78
Si53xx-RM
CKIN_1+
CKIN_1–
CKIN_2+
CKIN_2–
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
CKOUT_1+
CKOUT_1–
÷ NC1
1
0
CKOUT_2+
CKOUT_2–
÷ NC2
1
0
CKOUT_3+
CKOUT_3–
÷ NC3
1
0
CKOUT_4+
CKOUT_4–
÷ NC4
1
0
2
2
2
2
2
2
2
2
DCO
f
OSC
Xtal, or Refclock
(Si5319/Si5326/Si5368)
f
x
M
f
3
Digital
Phase
Detector/
Loop
Filter
BYPASS
f
3
SPI/I2C
Si5319, Si5326, Si5368
Control
÷ N32
÷ N31
Bandwidth
Control
FSYNC
(Si5368)
Si5368
Si5368
Note: See section 6.7 for
FSYNC details.
÷ N1_HS
CKOUT_5+
CKOUT_5–
÷ NC5
1
0
2
÷ N33
÷ N34
Note: There are multiple outputs at different frequencies because of limitations caused by the DCO and N1_HS.
÷ N2_LS
÷ N2_HS
7.1.3. Narrowband Mode (Si5319, Si5326, Si5368)
The DCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support
either a crystal oscillator or an input buffer (single-ended or differential) so that an external oscillator can become
the reference source. In both cases, there are wide margins in the absolute frequency of the reference input
because it is a fixed frequency and is used only as a jitter reference and as the reference frequency when in
holdover (see "7.6. Digital Hold" on page 90). See " Appendix A—Narrowband References" on page 118 for more
details.
However, care must be exercised in certain areas for optimum performance. For details on this subject, refer to
"Appendix B—Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5326, Si5366, Si5368)" on
page 120. For examples of connections to the XA/XB pins, refer to "8.3. Crystal/Reference Clock Interfaces
(Si5316, Si5319, Si5323, Si5326, Si5366, & Si5368)" on page 112.
Refer to Figure 22 Narrowband PLL Divider Settings (Si5319, Si5326, Si5368), a simplified block diagram of the
device and Table 38 and Table 39 for frequency and divider limits. The PLL dividers and their associated ranges
are listed in the diagram. Each PLL divider setting is programmed by writing to device registers. There are
additional restrictions on the range of the input frequency f
DSPLL output clock f
OSC
.
The selected input clock passes through the N3 input divider and is provided to the DSPLL. In addition, the
external crystal or reference clock provides a reference frequency to the DSPLL. The DSPLL output frequency,
f
, is divided down by each output divider to generate the clock output frequencies. The input-to-output clock
OSC
multiplication ratio is defined as follows:
f
= fIN x N2/(N1 x N3)
OUT
where:
N1 = output divider
N2 = feedback divider
N3 = input divider
, the DSPLL phase detector clock rate f3, and the
IN
Figure 22. Narrowband PLL Divider Settings (Si5319, Si5326, Si5368)
78 Rev. 0.41
Page 79
Table 38. Narrowband Frequency Limits
Signal Frequency Limits
CKINn 2 kHz–710 MHz
Si53xx-RM
f
OSC
f
OUT
f
3
2 kHz–2 MHz
4.85–5.67 GHz
2 kHz–1.475 GHz
Table 39. Dividers and Limits
Divider Equation Si5325, Si5367 Si5319, Si5326, Si5368
N1 N1 = N1_HS x NCn_LS N1_HS = [4, 5, …, 11]
NCn_LS = [1, 2, 4, 6, …, 2^20]
N2 N2 = N2_HS x N2_LS N2_HS = 1
N2_LS = [32, 34, 36, …, 2^9]
N3 N3 = N3n N3n = [1,2,3,..,2^19] N3n = [1,2,3,..,2^19]
The output divider, NC1, is the product of a high-speed divider (N1_HS) and a low-speed divider (N1_LS).
Similarly, the feedback divider N2 is the product of a high-speed divider N2_HS and a low-speed divider N2_LS.
When multiple combinations of high-speed and low-speed divider values are available to produce the desired
overall result, selecting the largest possible high-speed divider value will produce lower power consumption. With
the f
and N1 ranges given above, any output frequency can be achieved from 2 kHz to 945 MHz where NC1
OSC
ranges from (4 x 220) to 6. For NC1 = 5, the output frequency range 970 MHz to 1.134 GHz can be obtained. For
NC1 = 4, the output frequency range from 1.2125 to 1.4175 GHz is available.
Because there is only one DCO and all of the outputs must be frequencies that are integer divisions of the DCO
frequency, there are restrictions on the ratio of one output frequency to another output frequency. That is, there is
considerable freedom in the ratio between the input frequency and the first output frequency; but once the first
output frequency is chosen, there are restrictions on subsequent output frequencies. These restrictions are caused
by the fact that the N1_HS divider is shared among all of the outputs. DSPLLsim should be used to determine if two
different simultaneous outputs are compatible with one another.
The same issue exists for inputs of different Freudianism: both inputs, after having been divided by their respective
N3 dividers, must result in the same f3 frequency because the phase/frequency detector can operate at only one
frequency at one time.
Example
Assume the input clock rate on CKIN1, CKIN2, CKIN3, and CKIN4 is 19.44 MHz and the desired input-to-output
multiplication factor is (32 x 255/237), producing an output clock frequency of 669.33 MHz. Using the desired
output frequency value, set NC1 = 8 (N1_HS = 8 and N1_LS = 1) to put f
f
= 669.33 MHz x 8 = 5.355 GHz
OSC
Next, reduce the desired multiplication ratio by its greatest common factor (32 x 85/79) and set N3 = 79 to establish
the desired value in the denominator of the input-to-output frequency multiplication equation:
32 x 85/79 = N2/(8 x 79)
Solving for N2 yields:
N2 = 21760
N1_HS = [4, 5, …, 11]
NCn_LS = [1, 2, 4, 6, …, 2^20]
N2_HS = [4, 5, …, 11]
N2_LS = [2, 4, 6, …, 2^20]
within its operating range:
OSC
Rev. 0.41 79
Page 80
Si53xx-RM
Finally, select N2_HS = 10 and N2_LS = 2176 to implement N2 = 21760 with the lowest power consumption.
Therefore,
N1_HS = 8
N1_LS = 1
N2_HS = 10
N2_LS = 2176
N3 = 79.
See Table 40 for common SONET multiplication settings in narrowband/microprocessor control mode. For input
frequency/clock multiplication ratios not provided in this table, consult Silicon Laboratories' DSPLLsim PC-based
software to calculate the PLL divider settings.
Table 40. Common Divider Settings (Si5319, Si5326, Si5368)
fIN (MHz) f
19.44 19.44 5 50 10 250 10
77.76 77.76 8 8 8 312 39
155.52 155.52 8 4 8 364 91
622.08 622.08 4 2 8 364 364
Note: For some input frequency/clock multiplication ratio combinations, multiple divider settings produce the same output
frequency. Divider settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which
divider setting produces the best phase noise performance while minimizing power consumption. See the Register
Map documentation for the appropriate write values.
(MHz) N1_HS N1_LS N2_HS N2_LS N3
OUT
77.76 8 8 10 256 10
155.52 8 4 10 256 10
622.08 4 2 10 256 10
155.52 8 4 8 312 39
622.08 4 2 8 312 39
622.08 4 2 8 364 91
80 Rev. 0.41
Page 81
Si53xx-RM
7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368)
The device functions as a jitter attenuator with digitally programmable loop bandwidth (BW). The loop bandwidth
settings range from 60 Hz to 8.4 kHz and are set using the BWSEL_REG
frequency should be determined prior to loop bandwidth configuration because the loop bandwidth is a function of
the phase detector input frequency and the PLL feedback divider.
Table 41 show the loop bandwidth values available for common SONET frequency translations. Where values are
not shown, the loop bandwidth setting falls outside the valid narrowband loop bandwidth range of 60 Hz to 8.4 kHz.
Table 41. Common Loop Bandwidth Settings (Si5319, Si5326 and Si5368)
[3:0] register bits. The device operating
fIN (MHz) f
19.44 19.44 7.7 3.7 1.8 0.9 0.5 0.2 0.1 —
27 148.5 — 5.5 2.7 1.3 .66 .33 .17 .08
61.44 491.52 7.9 3.8 1.9 .93 .46 .23 .12 —
77.76 77.76 7.9 3.8 1.9 0.9 0.5 0.2 0.1 —
155.52 155.52 6.7 3.3 1.6 0.8 0.4 0.2 0.1 —
622.08 622.08 6.7 3.3 1.6 0.8 0.4 0.2 0.1 —
622.08 669.3 7.8 3.7 1.9 .92 .46 .23 .11 —
Note: Loop bandwidth is a function of phase detector frequency f3 and feedback divider N2 in narrowband mode. For some
input frequency/clock multiplication ratio combinations, multiple divider settings produce the same output frequency.
Loop bandwidth settings listed above are based on Silicon Laboratories’ DSPLLsim software that estimates which
divider setting produces the best phase noise performance while minimizing power consumption.
(MHz) BWSEL_REG[3:0] (kHz)
OUT
0100 0101 0110 0111 1000 1001 1010 1011
77.76
155.52
622.08
155.52
622.08
622.08
7.1.4.1. Loop BW (Si5324)
The loop BW of the Si5324 is significantly lower than the BW of the Si5326. The available Si5324 loop BW settings
and their register control values for a given frequency plan are listed by DSPLLsim (revision 4.0.1 or higher).
Compared to the Si5326, the BW Si5324 settings are roughly 16 times lower, which means that the Si5324 loop
BW ranges from about 4 to 525 Hz.
7.1.5. Lock Detect (Si5319, Si5326, Si5368)
The device has a PLL lock detection algorithm that indicates the lock status on the LOL output pin and the
LOL_INT
LOL algorithm.
read-only register bit. See Section “7.11.7. LOL (Si5319, Si5326, Si5368)” for a detailed description of the
Rev. 0.41 81
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Si53xx-RM
7.2. PLL Self-Calibration
The device performs an internal self-calibration before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DCO is being internally controlled by the selfcalibration state machine, and the LOL alarm will be active. The output clocks can either be active or disabled
depending on the SQ_ICAL
All Parts”. The procedure for initiating the internal self-calibration is described below.
7.2.1. Initiating Internal Self-Calibration
Any of the following events will trigger an automatic self-calibration:
Exit from SLEEP mode
Internal DCO registers out-of-range, indicating the need to relock the DCO
Setting the ICAL register bit to 1
In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin (LOSX_INT
When self-calibration is initiated the device generates an output clock if the SQ_ICAL
clock will appear when the device begins self-calibration. The frequency of the output clocks may be as high as 5%
above or as low as 20% below the final locked value. If SQ_ICAL
calibration and will appear after the self-calibration routine is completed.
After a successful self-calibration has been performed with a valid input clock, it is not necessary to reinitiate a selfcalibration for subsequent losses of input clock. If the input clock is lost following self-calibration, the device enters
digital hold mode. When the input clock returns, the device relocks to the input clock without performing a selfcalibration.
After power-up and writing of dividers or PLL registers, the user must set ICAL
will go low when self calibration is complete. Depending on the selected value of the loop BW, it may take a few
seconds more for the output frequency and phase to completely settle.
7.2.1.1. PLL Self-Calibration
Due to the low loop BW of the Si5324, the lock time of the Si5324 is significantly longer than the lock time of the
Si5326. As a method of reducing the lock time, a FAST_LOCK
data sheet indicates, FAST_LOCK
Because the Si5324 is initialized with FAST_LOCK
Time specification in Table 6 on page 33 of the FRM does not apply to the Si5324, with or without FAST_LOCK
Typical Si5324 lock times (as defined from the start of ICAL until LOL going low) with FAST_LOCK
seconds.
7.2.2. Input Clock Stability during Internal Self-Calibration
An ICAL must occur when the selected active CKINn clock is stable in frequency and with a frequency value that is
within the operating range that is reported by DSPLLsim. The other CKINs must be stable in frequency (< 100 ppm
from nominal) or squelched during an ICAL.
7.2.3. Self-Calibration Caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5326, Si5368)
The input-to-output skew is not controlled. External circuitry is required to control the input-to-output skew. Contact
Silicon Labs for further information.
bit setting. The self-calibration time t
= 0 [narrowband only]).
is the LSB of register 137. When FAST_LOCK is high, the lock time decreases.
low, it must be written before ICAL is set. Note that the Lock
LOCKHW
register bit was added to the Si5324. As the Si5324
is given in Table 6, “AC Characteristics—
bit is set to 0. The output
= 1, the output clocks are disabled during self-
= 1 to initiate a self-calibration. LOL
set are 60
.
82 Rev. 0.41
Page 83
Si53xx-RM
CKIN1
CKIN2
Clock priority logic
CK_PRIORn
0
1
CKSEL_REG
AUTOSEL_REG 0
1
CKSEL_PIN
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
decode
Auto
Manual
Selected
Clock
2
4
CS_CA pin
CK_ACTV_PIN
7.3. Input Clock Configurations (Si5367 and Si5368)
The device supports two input clock configurations based on the CK_CONFIG_REG register bit as shown in
Table 42:
Table 42. Input Clock Configurations
CK_CONFIG_REG Input Clock Configuration
0 CKIN1,2,3,4 Inputs
No FS_OUT Alignment
1 CKIN1,3 & CKIN2,4 Clock/FSYNC Pairs
FSYNC Switching/Realignment
For CK_CONFIG_REG
= 0, CKIN1, CKIN2, CKIN3, and CKIN4 serve as input clocks that can be selected via
manual or automatic control. In this mode, none of the clock inputs are designated as frame sync inputs usable for
output frame sync (FS_OUT) phase alignment.
For CK_CONFIG_REG
= 1, CKIN1 and CKIN3 form a high-speed clock/frame sync input pair with CKIN1 being the
clock and CKIN3 being frame sync. CKIN2 and CKIN4 form a second clock/frame sync pair. These two clock/frame
sync pairs can be switched in tandem via either manual or automatic control. See Section “6.5. Frame
Synchronization (Si5366)” for additional details.
7.4. Microprocessor Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). The Si5319 supports only pin-controlled manual clock selection. Figure 23 and
Figure 24 provide top level overviews of the clock selection logic, though they do not cover wideband or frame sync
applications. Register values are indicated by underscored italics. Note that, when switching between two clocks,
LOL may temporarily go high if the clocks differ in frequency by more than 100 ppm.
Figure 23. Si5325 and Si5326 Input Clock Selection
Rev. 0.41 83
Page 84
Si53xx-RM
CKIN1
CKIN2
CKIN3
CKIN4
Clock priority logicCK_PRIORn
0
1
CKSEL_REG
AUTOSEL_REG 0
1
CKSEL_PIN
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
decode
Auto
Manual
Selected
Clock
2
2
2
2
2
8
2
CS0_C3A,
CS1_C4A
pins
CKIN1
CKIN2
CKIN3
CKIN4
Clock priority logicCK_PRIORn
0
1
CKSEL_REG
AUTOSEL_REG 0
1
CKSEL_PIN
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
LOS/FOS
detect
decode
Auto
Manual
Selected
Clock
2
2
2
2
2
8
2
CS0_C3A,
CS1_C4A
pins
Figure 24. Si5367 and Si5368 Input Clock Selection
84 Rev. 0.41
Page 85
7.4.1. Manual Clock Selection
Manual control of input clock selection is available by setting the AUTOSEL_REG
mode, the active input clock is chosen via the CKSEL_REG
Table 44.
[1:0] register setting according to Table 43 and
Table 43. Manual Input Clock Selection (Si5367, Si5368)
Si53xx-RM
[1:0] register bits to 00. In manual
CKSEL_REG[1:0]
Register Bits
00 CKIN1 CKIN1/CKIN3
01 CKIN2 CKIN2/CKIN4
10 CKIN3 Not used
11 CKIN4 Not used
Note: Setting the CKSEL_PIN register bit to one allows the CS [1:0] pins to continue to control input clock selection.
If CS_PIN is set to zero, the CKSEL_REG[1:0] register bits perform the input clock selection function.
CK_CONFIG_REG
(CKIN1,2,3,4 inputs)
Active Input Clock
= 0
(CKIN1,3 & CKIN2,4 clock/FSYNC pairs)
CK_CONFIG_REG = 1
Table 44. Manual Input Clock Selection (Si5325, Si5326)
CKSEL_REG or CS pin Active Input Clock
0CKIN1
1CKIN2
If the selected clock enters an alarm condition, the PLL enters digital hold mode. The CKSEL_REG
are ignored if automatic clock selection is enabled.
7.4.2. Automatic Clock Selection
The AUTOSEL_REG
switching is either revertive or non-revertive.
[1:0] register bits sets the input clock selection mode as shown in Table 45. Automatic
[1:0] controls
Table 45. Automatic/Manual Clock Selection
AUTOSEL_REG[1:0] Clock Selection Mode
00 Manual
01 Automatic Non-revertive
10 Automatic Revertive
11 Reserv e d
CKSEL_PIN is of significance only when Manual is selected.
Rev. 0.41 85
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Si53xx-RM
7.4.2.1. Detailed Automatic Clock Selection Description (Si5325, Si5326)
Automatic switching is either revertive or non-revertive. The default prioritization of clock inputs when the device is
configured for automatic switching operation is CKIN1, followed by CKIN2, and finally, digital hold mode. The
inverse input clock priority arrangement is available through the CK_PRIOR bits, as shown in the Si5325 and
Si5326 Register Maps.
For the default priority arrangement, automatic switching mode selects CKIN1 at powerup, reset, or when in
revertive mode with no alarms present on CKIN1. If an alarm condition occurs on CKIN1 and there are no active
alarms on CKIN2, then the device switches to CKIN2. If both CKIN1 and CKIN2 are alarmed, then the device
enters digital hold mode. If automatic mode and microprocessor control mode are selected and the frequency
offset alarms (FOS1_INT
alarms. The loss-of-signal alarms (LOS1_INT
choices.
In non-revertive mode, once CKIN2 is selected, CKIN2 selection remains as long as it is valid even if alarms are
cleared on CKIN1.
7.4.2.2. Detailed Automatic Clock Selection Description (Si5367, Si5368)
The prioritization of clock inputs for automatic switching is shown in Table 46. For example, if
CK_CONFIG_REG
lowest priority clock, the user should set CK_PRIOR1
CK_PRIOR4
[1:0] = 00.
Table 46. Input Clock Priority for Auto Switching in µP Control Mode
and FOS2_INT) are disabled, automatic switching is not initiated in response to FOS
and LOS2_INT) are always used in making automatic clock selection
= 0 and the desired clock priority order is CKIN4, CKIN3, CKIN2, and then CKIN1 as the
[1:0] = 11, CK_PRIOR2[1:0] = 10, CK_PRIOR3[1:0] = 01, and
Selected Clock
CK_PRIORn
If CK_CONFIG_REG
set CK_PRIOR1
case).
The following discussion describes the clock selection algorithm for the case of four possible input clocks
(CK_CONFIG_REG
Automatic switching mode selects CKIN1 at powerup, reset, or when in revertive mode with no alarms present on
CKIN1. If an alarm condition occurs on CKIN1 and there are no active alarms on CKIN2, the device switches to
CKIN2. If both CKIN1 and CKIN2 are alarmed and there is no alarm on CKIN3, the device switches to CKIN3. If
CKIN1, CKIN2, and CKIN3 are alarmed and there is no alarm on CKIN4, the device switches to CKIN4. If alarms
exist on CKIN1, CKIN2, CKIN3, and CKIN4, the device enters digital hold mode. If automatic mode is selected and
the frequency offset alarms (FOS1_INT
not initiated in response to FOS alarms. The loss-of-signal alarms (LOS1_INT
are always used in making automatic clock selection choices. In non-revertive mode, once CKIN2 is selected,
CKIN2 selection remains as long as it is valid even if alarms are cleared on CKIN1.
= 1 and the desired clock priority is CKIN1/CKIN3 and then CKIN2/CKIN4, the user should
[1:0] = 00 and CK_PRIOR2[1:0] = 01 (CK_PRIOR3[1:0] and CK_PRIOR4[1:0] are ignored in this
= 0) in the default priority arrangement (priority order CKIN1, CKIN2, CKIN3, CKIN4).
[1:0] CK_CONFIG_REG = 0 CK_CONFIG_REG = 1
00 CKIN1 CKIN1/CKIN3
01 CKIN2 CKIN2/CKIN4
10 CKIN3 Not Used
11 CKIN4 Not Used
, FOS2_INT, FOS3_INT, FOS4_INT) are disabled, automatic switching is
, LOS2_INT, LOS3_INT, LOS4_INT)
86 Rev. 0.41
Page 87
Si53xx-RM
7.4.3. Hitless Switching with Phase Build-Out (Si5326, Si5368)
Silicon Laboratories switching technology performs phase build-out, which maintains the phase of the output when
the input clock is switched. This minimizes the propagation of phase transients to the clock outputs during input
clock switching. All switching between input clocks occurs within the input multiplexer and phase detector circuitry.
The phase detector circuitry continually monitors the phase difference between each input clock and the DSPLL
output clock, f
so that the phase offset is maintained by the PLL circuitry.
At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for
the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the
new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the
two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output.
The switching technology virtually eliminates the output clock phase transients traditionally associated with clock
rearrangement (input clock switching). The wander and maximum slope for clock output phase transients during
clock switching are given in Table 6, “AC Characteristics—All Parts”. These values fall significantly below the limits
specified in the Telcordia GR-1244-CORE and GR-253-CORE requirements.
Note that hitless switching between input clocks applies only when the input clock validation time is
VALTIME
[1:0] = 01 or higher.
. The phase detector circuitry can lock to a clock signal at a specified phase offset relative to f
OSC
OSC
Rev. 0.41 87
Page 88
Si53xx-RM
Crystal or an external oscillator
Si5319,
Si5326,
Si5368
CKOUT1
CKOUT2
Xtal osc
DSPLL
Core
CKIN1
I
2
C/SPI
CKIN2
Control
XA-XB
N31
N31
N32
N32
XAXB
7.5. Si5319, Si5326, and Si5368 Free Run Mode
Figure 25. Free Run Mode Block Diagram
CKIN2 has an extra mux with a path to the crystal oscillator output.
When in Free Run mode, CKIN2 is sacrificed (Si5326, Si5368).
Switching between the crystal oscillator and CLKIN1 is hitless.
Either a crystal or an external oscillator can be used.
External oscillator connection can be either single ended or differential.
All other features and specifications remain the same.
7.5.1. Free Run Mode Programming Procedure
Using DSPLLsim, determine the frequency plan:
Write to the internal dividers, including N31 and N32.
Enable Free Run Mode (the mux select line), FREE_RUN.
Select CKIN1 as the higher priority clock.
Establish revertive and autoselect modes.
Once properly programmed, the part will:
Initially lock to either the XA-XB or to CKIN1.
Automatically select CKIN1, if it is available.
Automatically and hitlessly switch to XA-XB if CKIN1 fails.
Automatically and hitlessly switch back to CKIN1 when it subsequently returns.
For the Si5319:
Clock selection is manual using an input pin.
Clock switching is not hitless.
CKIN2 is not available.
7.5.2. Use of LOS_A when in Free Run Mode
Because the two clock inputs will not be the same exact frequency, it is recommended that while in Free Run Mode
LOS_A be used instead of LOS. This will avoid false LOS assertions when the XA-XB frequency differs from the
other clock inputs by more than 100 ppm. See Section 7.11.1.3 for more information on LOS_A.
88 Rev. 0.41
Page 89
7.5.3. Free Run Reference Frequency Constraints
CKIN
N31
---------------
XA-XB
N32
------------------
f
3
==
CKOUT
XA-XB
----------------------
Integer
Si53xx-RM
XA-XB freq,
XA-XB freq, max Xtal
min
163 MHz 180 MHz 3rd overtone
109 MHz 125.5 MHz 3rd overtone
55 MHz 61 MHz 3rd overtone
37 MHz 41 MHz fundamental
All crystals and external oscillators must lie within these four bands
Not every crystal will work; they should be tested
An external oscillator can be used at all four bands
The frequency at the phase detector (f3) must be the same for both CKIN1 and XA-XB or else switching cannot
be hitless
To avoid spurs, avoid outputs that are an integer (or near integer) of the XA-XB frequency.
7.5.4. Free Run Reference Frequency Constraints
While in Free Run:
CKOUT frequency tracks the reference frequency.
For very low drift, a TCXO or OCXO reference is necessary.
CKOUT Jitter:
XA-XB to CKOUT jitter transfer function is roughly one-to-one.
For very low jitter, either use a high quality crystal or external oscillator.
3rd overtone crystals have lower close-in phase noise.
In general, higher XA-XB frequency > lower jitter.
XA-XB frequency accuracy:
For hitless switching, to meet all published specifications, the XA-XB frequency should match the CLKIN frequency. If the
XA-XB frequency does not match the CLKIN frequency, the clock switch will still be well-behaved.
Other than the above, the absolute accuracy of the XA-XB frequency is not important.
Rev. 0.41 89
Page 90
Si53xx-RM
Time
Digital Hold
@
t = 0
MM
HIST
t = –HIST_DEL
HIST_AVG
7.6. Digital Hold
All Any-Rate Precision Clock devices feature a holdover mode, whereby the DSPLL is locked to a digital value.
7.6.1. Narrowband Digital Hold (Si5316, Si5326, Si5368)
After the part's initial self-calibration (ICAL), when no valid input clock is available, the device enters digital hold.
Referring to the logical diagram in "Appendix D—Alarm Structure" on page 139, lack of clock availability is defined
by following boolean equation for the Si5326 and Si5325:
NOT(LOS1_INT OR FOS1_INT) AND (LOS2_INT OR FOS2_INT) = enter digital hold
The equivalent boolean equation for the Si5367 and Si5368 is as follows:
NOT(LOS1_INT OR FOS1_INT) AND (LOS2_INT OR FOS2_INT) AND
(LOS3_INT OR FOS3_INT) AND (LOS4_INT OR FOS4_INT) = enter digital hold
7.6.1.1. Digital Hold Detailed Description (Si5326, Si5368)
In this mode, the device provides a stable output frequency until the input clock returns and is validated. Upon
entering digital hold, the internal DCO is initially held to its last frequency value, M (See Figure 26). Next, the DCO
slowly transitions to a historical average frequency value supplied to the DSPLL, M
Values of M starting from time t = –(HIST_DEL
compute M
record of previous M values supplied to the DCO. By using a historical average frequency, input clock phase and
frequency transients that may occur immediately preceding digital hold do not affect the digital hold frequency.
Also, noise related to input clock jitter or internal PLL jitter is minimized.
. This historical average frequency value is taken from an internal memory location that keeps a
HIST
+ HIST_AVG) and ending at t = –HIST_DEL are averaged to
, as shown in Figure 26.
HIST
Figure 26. Parameters in History Value of M
The history delay can be set via the HIST_DEL[4:0] register bits as shown in Table 47 and the history averaging
time can be set via the HIST_AVG
used to determine if the information in HIST_AVG
hold. If DIGHOLDVALID
is not active, the part will enter VCO freeze instead of digital hold.
[4:0] register bits as shown in Table 48. The DIGHOLDVALID register can be
is valid and the device can enter SONET/SDH compliant digital
Table 47. Digital Hold History Delay
HIST_DEL[4:0] History Delay Time (ms) HIST_DEL[4:0] History Delay Time (ms)
00000 0.0001 10000 6.55
00001 0.0002 10001 13
00010 0.0004 10010 (default) 26
00011 0.0008 10011 52
00100 0.0016 10100 105
00101 0.0032 10101 210
00110 0.0064 10110 419
00111 0.01 10111 839
90 Rev. 0.41
Page 91
Si53xx-RM
Table 47. Digital Hold History Delay (Continued)
HIST_DEL[4:0] History Delay Time (ms) HIST_DEL[4:0] History Delay Time (ms)
01000 0.03 11000 1678
01001 0.05 11001 3355
01010 0.10 11010 6711
01011 0.20 11011 13422
01100 0.41 11100 26844
01101 0.82 11101 53687
01110 1.64 11110 107374
01111 3.28 11111 214748
Table 48. Digital Hold History Averaging Time
HIST_AVG[4:0] History Averaging Time (ms) HIST_AVG[4:0] History Averaging Time (ms)
00000 0.0000 10000 26
00001 0.0004 10001 52
00010 0.001 10010 105
00011 0.003 10011 210
00100 0.006 10100 419
00101 0.012 10101 839
00110 0.03 10110 1678
00111 0.05 10111 3355
01000 0.10 11000 (default) 6711
01001 0.20 11001 13422
01010 0.41 11010 26844
01011 0.82 11011 53687
01100 1.64 11100 107374
01101 3.28 11101 214748
01110 6.55 11110 429497
01111 1 3 11111 8 5 8 993
If a highly stable reference, such as an oven-controlled crystal oscillator (OCXO) is supplied at XA/XB, an
extremely stable digital hold can be achieved. If a crystal is supplied at the XA/XB port, the digital hold stability will
be limited by the stability of the crystal. Table 6, “AC Characteristics—All Parts” gives the specifications related to
the digital hold function.
7.6.2. Recovery from Digital Hold (Si5319, Si5326, Si5368)
When the input clock signal returns, the device transitions from digital hold to the selected input clock. The device
performs hitless recovery from digital hold. The clock transition from digital hold to the returned input clock includes
"phase buildout" to absorb the phase difference between the digital hold clock phase and the input clock phase.
Rev. 0.41 91
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Si53xx-RM
7.6.3. VCO Freeze (Si5319, Si5325, Si5367)
If an LOS or FOS condition exists on the selected input clock, the device enters VCO freeze. In this mode, the
device provides a stable output frequency until the input clock returns and is validated. When the device enters
digital hold, the internal oscillator is initially held to its last frequency value. VCO freeze is not compliant with
SONET/SDH MTIE requirements; applications requiring SONET/SDH MTIE requirements should use the Si5326
or Si5368. Unlike the Si5325 and Si5367, the Si5319’s VCO freeze is controlled by the XA-XB reference (which is
typically a crystal) for greater stability. For the Si5319, VCO freeze is similar to the Digital Hold function of the
Si5326 and Si5368, except that the HIST_AVG
7.7. Output Phase Adjust (Si5326, Si5368)
The device has a highly accurate, digitally controlled device skew capability. For more information on Output Phase
Adjustments, see both DSPLLsim and the Register Maps. Both can be downloaded by going to www.silabs.com/
timing and clicking on “Documentation” at the bottom of the page.
7.7.1. Coarse Skew Control (Si5326, Si5368)
With the INCDEC_PIN
register bits. This skew control has a resolution of 1/f
25.4 ns. Following a powerup or reset (RST
and then the value in the CLAT
made in the skew register will be read and compared to the previously held value. The difference will be calculated
and applied to the clock outputs. All skew changes are made in a glitch-free fashion.
When a phase adjustment is in progress, any new CLAT
CLATPROG
specifies the maximum amount of time required to complete a coarse skew phase adjustment. To verify a written
value into CLAT
of a CLAT change to complete is proportional to the size of the change, at 83.3 msec for every unit change. For
example, if CLAT is zero and has the value 100 written to it, the changes will complete in
100 x 83.3 msec = 8.33 sec.
If it is necessary to set the high-speed output clock divider N1_HS to divide-by-4 in order to achieve the desired
overall multiplication ratio and output frequency, only phase increments are allowed and negative settings in the
CLAT
restriction, when there is a choice between using N1_HS = 4 and another N1_HS value that can produce the
desired multiplication ratio, the other N1_HS value should be selected. This restriction also applies when using the
INC pin.
With the INCDEC_PIN register bit set to 1 (pin control on), the INC and DEC pins function the same as they do for
pin controlled parts. See "6.6. Output Phase Adjust (Si5323, Si5366)" on page 69.
7.7.1.1. Unlimited Coarse Skew Adjustment (Si5326, Si5368)
Using the following procedure, the CLAT
arbitrarily large value that is not limited by the size of the CLAT
1. Write a phase adjustment value to the CLAT
provides the size of a single step.
2. Wait until CLATPROGRESS
time for adjustment: 20 seconds for the Si5326 or Si5368).
3. Set INCDEC_PIN
4. Write 0 to CLAT
5. Wait until CLATPROGRESS
6. Set INCDEC
7. Repeat the above process as many times as desired.
Steps 3-6 will clear the CLAT
phase adjustment using the CLAT
register bit is set to 1 during a coarse skew adjustment. Table 6, “AC Characteristics—All Parts”
, the CLAT register should be read after the register is written. The time that it takes for the effects
register or attempts to decrement the phase via writes to the CLAT register will be ignored. Because of this
_PIN=0.
register bit set to 0 (pin control off), overall device skew is controlled via the CLAT[7:0]
register will be read and automatically applied to the outputs. Any further changes
= 0 (register 130, bit 7), which indicates that the adjustment is complete (Maximum
= 1 (register 21, bit 7).
register (register 16).
= 0.
register without changing the output phase. This allows for unlimited output clock
register and repeating steps 1-3 as many times as needed.
and HIST_DEL registers do not exist.
, approximately 200 ps, and a range from –25.6 to
pin or RST_REG register bit), the skew will revert to the reset value
register can be used to adjust the device clock output phase to an
register (register 16). The DSPLLsim configuration software
OSC
[7:0] values are ignored until the update is complete. The
register:
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7.7.2. Fine Skew Control (Si5326, Si5368)
An additional fine adjustment of the overall device skew can be used in conjunction with the INC and DEC pins or
the CLAT
using the FLAT
Range FLAT
Resolution FLAT
Before writing a new FLAT
while the new value is being written. Once the new value is written, set FLAT_VALID
Table 6, “AC Characteristics—All Parts” specifies the maximum amount of time required to complete a FLAT
adjustment. To verify a written value into FLAT
Because the FLAT resolution varies with the frequency plan and selected bandwidth, DSPLLsim reports the FLAT
resolution each time it creates a new frequency plan.
7.7.2.1. Output Phase Adjust (Si5324)
Because of its low loop BW, the output phase of the Si5324 is not adjustable. This means that the Si5324 does not
have any INC or DEC pins and that it does not have CLAT or FLAT registers.
7.7.3. Independent Skew (Si5326, Si5368)
The phase of each clock output may be adjusted in relation to the phase of the other clock outputs, respectively.
This feature is available when CK_CONFIG_REG
F
VCO
800 ps to 2.2 ns depending on the PLL divider settings. Silicon Laboratories' PC-based configuration software
(DSPLLsim) provides PLL divider settings for each frequency translation, if applicable. If more than one set of PLL
divider settings is available, selecting the combination with the lowest N1_HS value provides the finest resolution
for output clock phase offset control. The INDEPENDENTSKEWn
the device output clocks. By programming a different phase offset for each output clock, output-to-output delays
can easily be set.
7.7.4. Output-to-output Skew (Si5326, Si5368)
The output-to-output skew is guaranteed to be preserved only if the following two register bits are both high:
Register Bit: Location
CKOUT_ALWAYS_ON
SQICAL
In addition, if SFOUT
[7:0] register bits to provide finer resolution output phase adjustments. Fine phase adjustment is available
[14:0] bits. The nominal range and resolution of the FLAT[14:0] skew adjustment word are:
= ±110 ps
= 9 ps
[14:0] value, the FLAT_VALID bit must be set to 0 to hold the existing FLAT[14:0] value
= 1 to enable its use.
, the FLAT register should be read after the register is written.
= 0. The resolution of the phase adjustment is equal to [NI HS/
]. Since F
is approximately 5 GHz and N1_HS = (4, 5, 6, …, 11), the resolution varies from approximately
VCO
[7:0] (n = 1 to 5) register bits control the phase of
addr 0, bit 5
addr 3, bit 4
is changed, the output-to-output skew may be disturbed until after a successful ICAL.
phase
7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG =1)
Frame Synchronization Realignment is selected by setting CK_CONFIG_REG = 1. In a typical frame
synchronization application, CKIN1 and CKIN2 are high-speed input clocks from primary and secondary clock
generation cards and CKIN3 and CKIN4 are their associated primary and secondary frame synchronization
signals. The device generates four output clocks and a frame sync output FS_OUT. CKIN3 and CKIN4 control the
phase of FS_OUT. When CK_CONFIG_REG
CKIN4 are used only for purposes of frame synchronization.
The inputs supplied to CKIN3 and CKIN4 can range from 2 to 512 kHz. So that two different frame sync input
frequencies can be accommodated, CKIN3 and CKIN4 each have their own input divides, as shown in Figure 27.
The CKIN3 and CKIN4 frequencies are set by the CKIN3RATE
Table 49. The frequency of FS_OUT can range from 2 kHz to 710 MHz and is set using the NC5_LS divider
setting. FS_OUT must divide evenly into CKOUT2. For example, if CKOUT2 is 156.25 MHz, then 8 kHz would not
be an acceptable frame rate because 156.25 MHz/8 kHz = 19,531.25, which is not an integer. However, 2 kHz
would be an acceptable frame rate because 156.25 MHz/2 kHz = 78,125.
= 1, the Si5368 can lock onto only CKIN1 or CKIN2. CKIN3 and
[2:0] and CKIN4RATE[2:0] register bits, as shown in
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CKIN3
CKIN4
CLKIN3RATE
Clock select
DCO,
4.85 GHz
to 5.67 GHz
CKOUT2
N1_HS
NC2_LS
NC5_LS
FS_OUT
CLKIN4RATE
to align
Typically the same frequency
CKIN3
CKIN4
CLKIN3RATE
Clock select
DCO,
4.85 GHz
to 5.67 GHz
N1_HS
NC2_LS
NC5_LS
CLKIN4RATE
to align
Typically the same frequency
Table 49. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1)
CKLNnRATE[2:0] CKINn Frequency (kHz) Divisor
000 2–4 1
001 4–8 2
010 8–16 4
011 16–32 8
100 32–64 16
101 64–128 32
110 128–256 64
111 256–512 128
Figure 27. Frame Sync Frequencies
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The NC5_LS divider uses CKOUT2 as its clock input to derive FS_OUT. The limits for the NC5_LS divider are
NC5_LS = [1, 2, 4, 6, …, 2
f
CKOUT2
Note that when in frame synchronization realignment mode, writes to NC5_LS
section “7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)”.
Common NC5_LS
7.8.1. FSYNC Realignment (Si5368)
The FSYNC_ALIGN_PIN
controlled via the FSYNC_ALIGN_REG
the FSYNC_POL
The FSYNC realignment control can operate in level sensitive or one-shot mode as determined by the
FSYNC_ALIGN_MODE
FSYNC_ALIGN_REG
Level Sensitive Mode: While realignment control is high, each active edge of the currently-active frame
One Shot Mode: In the one-shot mode, after the FS_ALIGN pin or FSYNC_ALIGN_REG
In either FSYNC alignment control mode, the resolution of the phase realignment is 1 clock cycle of CKOUT2. If
the realignment control is not active, the NC5 divider will continuously divide down its f
guarantees a fixed number of high-frequency clock (CKOUT2) cycles between each FS_OUT cycle.
At power-up, the device automatically performs a realignment of FS_OUT using the currently active sync input.
After this, as long as the PLL remains in lock and a realignment is not requested, FS_OUT will include a fixed
number of high-speed clock cycles, even if input clock switches are performed. If many clock switches are
performed in phase build-out mode, it is possible that the input sync to output sync phase relationship will shift due
to the accumulated residual phase transients of the phase build-out circuitry. The ALIGN_ERR
reports the deviation of the input-to-output sync phase skew from the desired FSYNC_SKEW
f
CKOUT2
bits, whose settings are given in Table 51. If the sync alignment error exceeds the threshold in either the positive or
negative direction, the alarm becomes active. If it is then desired to reestablish the desired input-to-output sync
< 710 MHz
divider settings on FS_OUT are shown in Table 50.
register bit.
periods. A programmable threshold to trigger the ALIGN_INT alarm can be set via the ALIGN_THR[2:0]
19
]
are controlled by FPW_VALID. See
Table 50. Common NC5 Divider Settings
CKOUT2 Frequency (MHz) NC5 Divider Setting
2 kHz FS_OUT 8 kHz FS_OUT
19.44 9720 2430
77.76 38880 9720
155.52 77760 19440
622.08 311040 77760
bit determines if the realignment will be pin-controlled via the FS_ALIGN pin or register-
register bit. The active CKIN3 or CKIN4 edge to be used is controlled via
register bit. The realignment control can be either the FS_ALIGN pin or the
, as determined by the FSYNC_POL register bit.
sync input (CKIN_3 or CKIN_4) is used to control the NC5 output divider and
therefore the FS_OUT phase. Note that while the realignment control is active, it
cannot be guaranteed that a fixed number of high-frequency clock (CKOUT_2)
cycles exists between each FS_OUT cycle. See Figure 13, “Frame Synchronization
Timing in Level Sensitive Mode,” on page 32.
bit goes
active, the device will perform a one-time phase realignment on the next active edge
of the currently-active frame sync input. After the realignment, the FS_OUT will
always be a fixed number of CKOUT2 periods as determined by the NC5 setting as
the NC5 divider continuously divides down its CKOUT2 input. The one-shot mode of
operation is helpful if the user wants a single realignment performed without having
to exactly control the timing of the FS_ALIGN or FSYNC_ALIGN_REG
Figure 14, “Frame Synchronization Timing in One-shot Mode,” on page 32.
[16:0] value in units of
signals. See
CKOUT2
[8:0] status register
input. This
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phase relationship, a realignment can be performed. A realignment request may cause FS_OUT to
instantaneously shift its output edge location in order to align with the active input sync phase.
Table 51. Alignment Alarm Trigger Threshold
ALIGN_THR [2:0] Alarm Trigger Threshold (Units of T
000 4
001 8
010 16
011 32
100 48
101 64
110 96
111 128
For cases where phase skew is required, see Section “7.7. Output Phase Adjust (Si5326, Si5368)” for more details
on controlling the sync input to sync output phase skew via the FSYNC_SKEW
Clock Drivers” for information on the FS_OUT signal format, pulse width, and active logic level control.
7.8.2. FSYNC Skew Control
When CKIN3 and CKIN4 are configured as frame sync inputs (CK_CONFIG_REG
input active edge to FS_OUT active edge is controllable via the FSYNC_SKEW
has a resolution of 1/f
period of CKIN3, CKIN4, and FS_OUT.
The skew should not be changed more than once per FS_OUT period. If a FSYNC realignment is being made, the
skew should not be changed until the realignment is complete. The skew value and the FS_OUT pulse width
should not be changed within the same FS_OUT period.
Before writing the three bytes needed to specify a new FSYNC_SKEW
bit FSKEW_VALID
value, ignoring the new register values as they are being written. Once the new FSYNC_SKEW
been completely written, the user should set FSKEW_VALID
read the new skew alignment value. Note that when the new FSYNC_SKEW
occur in FS_OUT.
7.8.3. Including FSYNC Inputs in Clock Selection (Si5368)
The frame sync inputs, CKIN3 and CKIN4, are both monitored for loss-of-signal (LOS3_INT
conditions. To include these LOS alarms in the input clock selection algorithm, set FSYNC_SWTCH_REG
LOS3_INT
selection state machine. If it is desired not to include these alarms in the clock selection algorithm, set
FSYNC_SWTCH_REG
state machine decision making as described in Section “7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368)”;
however, in frame sync mode (CK_CONFIG_REG
is logically ORed with LOS1_INT and LOS4_INT is ORed with LOS2_INT as inputs to the clock
CKOUT2
= 0. This causes the alignment state machine to keep using the previous FSYNC_SKEW[16:0]
and a range of 131,071/f
= 0. The frequency offset (FOS) alarms for CKIN1 and CKIN2 can also be included in the
CKOUT2
= 1), the FOS alarms for CKIN3 and CKIN4 are ignored.
. The entered skew value must be less than the
[16:0] value, the user should set the register
= 1 at which time the alignment state machine will
CKOUT2
[16:0] bits. See Section “8.2. Output
[16:0] register bits. Skew control
[16:0] value is used, a phase step will
)
= 1), phase skew of the sync
[16:0] value has
and LOS4_INT)
=1. The
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7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)
Additional output controls are available for FS_OUT. The active polarity of FS_OUT is set via the FS_OUT_POL
register bit and the active duty cycle is set via the FSYNC_PW[9:0] register. Pulse width settings have a resolution
of 1/f
CKOUT2
periods, providing the full range of pulse width possibilities for a given NC5 divider setting.
The FS_OUT pulse should not be changed more than once per FS_OUT period. If a FSYNC realignment is being
made, the pulse width should not be changed until the realignment is complete. The FS_OUT pulse width and the
skew value should not be changed within the same FS_OUT period.
Before writing a new value into FSYNC_PW
the FS_OUT pulse width state machine to keep using the previous FSYNC_PW
register values as they are being written. Once the new FSYNC_PW
user should set FPW_VALID
width value.
Writes to NC5_LS
only when FPW_VALID = 0
Note that f
buffer and NC5 divider must be disabled.
7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)
In applications where the frame synchronization functionality is not needed (CK_CONFIG_REG
be used as a fifth clock output. In this case, no realignment requests should be made to the NC5 divider (hold
FS_ALIGN
available as described above. The 50% duty cycle setting would be used to generate a typical balanced output
clock.
, and a 50% duty cycle setting is provided. Pulse width settings can range from 1 to (NC5-1) CKOUT2
[9:0], the user should set the register bit FPW_VALID = 0. This causes
[9:0] value, ignoring the new
[9:0] value has been completely written, the
= 1, at which time the FS_OUT pulse width state machine will read the new pulse
should be treated the same as writes to FSYNC_PW. Thus, all writes to NC5_LS should occur
. Any such writes will not take effect until FPW_VALID = 1.
CKOUT2
must be less than or equal to 710 MHz when CK_CONFIG_REG = 1; otherwise, the FS_OUT
= 0), FS_OUT can
= 0 and FSYNC_ALIGN_REG = 0). Output pulse width and polarity controls for FS_OUT are still
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7.9. Output Clock Drivers (Si5319, Si5325, Si5326, Si5367, Si5368)
The device includes a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS,
CML, and CMOS formats. The signal format of each output is individually configurable through the
SFOUTn_REG
“DC Characteristics—All Parts (Current draw is independent of supply voltage)” for output driver specifications.
Table 52 shows the signal formats based on the supply voltage and the type of load being driven. For the CMOS
setting, both output pins drive single-ended in-phase signals and should be externally shorted together to obtain
the drive strength specified in Table 3, “DC Characteristics—All Parts (Current draw is independent of supply
voltage)”.
[2:0] register bits, which modify the output common mode and differential signal swing. See Table 3,
Table 52. Output Signal Format Selection
SFOUTn_REG[2:0] Signal Format
111 LV DS
110 CM L
101 LVPECL
011 Low-swing LVDS
010 CMOS
000 Disabled
All Others Reserved
The SFOUTn_REG
CKOUT+ and CKOUT– pins in a high-impedance state relative to V
outputs remain connected to each other through a 200 on-chip resistance (differential impedance of 200 ). The
clock output buffers and DSPLL output dividers NCn are powered down in disable mode.
The additional functions of "Hold Logic 1" and "Hold Logic 0," which create static logic levels at the outputs, are
available. For differential output buffer formats, the Hold Logic 1 state causes the positive output of the differential
signal to remain at its high logic level while the negative output remains at the low logic level. For CMOS output
buffer format, both outputs remain high during the Hold Logic 1 state. These functions are controlled by the
HLOG_n
generated on the outputs.
7.9.1. Disabling CKOUTn
Disabling CKOUTn output powers down the output buffer and output divider. Individual disable controls are
available for each output using the DSBLn_REG
7.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si536, Si5368)
The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are
restrictions in the allowed output format pin settings that limit the maximum power dissipation for the TQFP devices
when they are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be
disabled. When there are five enabled outputs, there can be no more than three outputs that are either LVPECL or
CMOS.
bits. When entering or exiting the "Hold Logic 1" or "Hold Logic 0" states, no glitches or runt pulses are
[2:0] register bits can also be used to disable the outputs. Disabling the outputs puts the
(common mode tri-state) while the two
DD
.
7.10. PLL Bypass Mode (Si5319, Si5325, Si5326, Si5367, Si5368)
The device supports a PLL bypass mode in which the selected input clock is fed directly to the output buffers,
bypassing the DSPLL. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass
mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation
provided by the DSPLL. The BYPASS_REG
Before going into bypass mode, it is recommended that the part enter Digital Hold by setting DHOLD. Internally, the
bypass path is implemented with high-speed differential signaling for low jitter.
bit controls enabling/disabling PLL bypass mode.
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7.11. Alarms (Si5319, Si5325, Si5326, Si5367, Si5368)
Summary alarms are available to indicate the overall status of the input signals and frame alignment (Si5368 only).
Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. The Register VALTIME
controls how long a valid signal is re-applied before an alarm clears. Table 53 shows the available settings. Note
that only for VALTIME
7.11.1. Loss-of-Signal Alarms (Si5319, Si5325, Si5326, Si5367, Si5368)
The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry
generates an internal LOSn_INT
ALARMOUT.
An LOS condition on CKIN1 causes the internal LOS1_INT
CKINn causes the LOSn_INT
clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear
LOSn_INT
condition on the same input clock is detected during the validation time then the alarm remains asserted and the
validation time starts over.
7.11.1.1. Narrowband LOS Algorithms (Si5319, Si5326, Si5368)
There are three options for LOS: LOS, LOS_A, and no LOS, which are selected using the LOSn_EN
The values for the LOSn_EN
after a valid input clock appears is listed in Table 6, “AC Characteristics—All Parts”. If another error
[1:0] = 00, hitless switching is not possible.
Table 53. Loss-of-Signal Validation Times
VALTI M E[1:0] Clock Validation Time
00 2 ms
(hitless switching not available)
01 100 ms
10 200 ms
11 1 3 s
output signal that is processed with other alarms to generate CnB and
alarm become active. Similarly, an LOS condition on
alarm become active. Once a LOSn_INT alarm is asserted on one of the input
registers.
registers are given in Table 54.
Table 54. Loss-of-Signal Registers
LOSn_EN[1:0] LOS Selection
00 Disable all LOS monitoring
01 Reserved
10 LOS_A enabled
11 LOS enabled
7.11.1.2. Standard LOS (Si5319, Si5326, Si5368)
To facilitate automatic hitless switching, the LOS trigger time can be significantly reduced while in narrowband
mode by using the default LOS option (LOSn_EN = 11). The LOS circuitry divides down each input clock to
produce a 2 kHz to 2 MHz signal. The LOS circuitry over samples this divided down input clock using a 40 MHz
clock to search for extended periods of time without input clock transitions. If the LOS monitor detects twice the
normal number of samples without a clock edge, an LOS alarm is declared. Table 6, “AC Characteristics—All
Parts” gives the minimum and maximum amount of time for the LOS monitor to trigger. The LOSn trigger window is
based on the value of the input divider N3. The value of N3 is reported by DSPLLsim.
The range over which LOS is guaranteed to not produce false positive assertions is 100 ppm. For example, if a
device is locked to an input clock on CKIN1, the frequency of CKIN2 should differ by no more than 100 ppm to
avoid false LOS2 assertions.
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7.11.1.3. LOSA (Si5319, Si5326, Si5368)
A slower response version of LOS called LOSA is available and should be used under certain conditions. Because
LOSA is slower and less sensitive than LOS, its use should be considered for applications with quasi-periodic
clocks (e.g., gapped clocks with one or more consecutive clock edges removed), when switching between input
clocks with a large difference in frequency and any other application where false positive assertions of LOS may
incorrectly cause the Any-Rate device to be forced into Digital Hold.
For example, it is recommended that while in Free Run Mode LOSA be used instead of LOS because the two clock
inputs will not be the same exact frequency. This will avoid false LOS assertions when the XA-XB frequency differs
from the other clock inputs by more than 100 ppm. See Section 7.11.1.3 for more information on LOSA.
7.11.1.4. LOS disabled (Si5319, Si5326, Si5368)
For situations where no form of LOS is desired, LOS can be disabled by writing 00 to LOSn_EN
provided to support applications which implement custom LOS algorithms off-chip. If this approach is taken, the
only remaining methods of entering Digital Hold will be FOS or by setting DHOLD
7.11.1.5. Wideband LOS Algorithm (Si5322, Si5365)
Each input clock is divided down to produce a 78 kHz to 1.2 MHz signal before entering the LOS monitoring
circuitry. The same LOS algorithm as described in the above section is then used. FOS is not available in WB
parts.
7.11.1.6. LOS Alarm Outputs (Si5319, Si5325, Si5326, Si5367, Si5368)
An LOS condition on CKIN1 causes LOS1_INT
LOS2_INT
until the input clock is validated over a designated time period. The time to clear LOSn_INT
appears is listed in Table 6, “AC Characteristics—All Parts”. If another error condition on the same input clock is
detected during the validation time then the alarm remains asserted and the validation time starts over.
7.11.2. FOS Algorithm (Si5326, Si5368)
The frequency offset (FOS) alarms indicate if the input clocks are within a specified frequency range relative to the
frequency of a reference clock. The reference clock can be provided by any of the four input clocks (two for Si5325
or Si5326) or the XA/XB input. The default FOS reference is CKIN2. The frequency monitoring circuitry compares
the frequency of the input clock(s) with the FOS reference clock If the frequency offset of an input clock exceeds a
selected frequency offset threshold, an FOS alarm (FOS_INT
that large amounts of wander can cause false FOS alarms.
Note: For the Si5368, If CK_CONFIG_REG = 1, only CKIN1 and CKIN2 are monitored; CKIN3 and CKIN4 are used for
The frequency offset threshold is selectable using the FOS_THR[1:0] bits. Settings are available for compatibility
with SONET Minimum Clock (SCMD) or Stratum 3/3E requirements. See Table 6 on page 33. The device supports
FOS hystereses per GR-1244-CORE, making the device less susceptible to FOS alarm chattering. A reference
clock with suitable accuracy and drift specifications to support the intended application should be used. The FOS
reference clock is set via the FOSREFSEL
against the FOS reference, i.e., there can be more than one monitored clock, but only one FOS reference. When
the XA/XB input is used as the FOS reference, there is only one reference frequency band that is allowed: from
37 MHz to 41 MHz.
to become active. Once a LOSn_INT alarm is asserted on one of the input clocks, it remains asserted
FSYNC and are not monitored.
to become active. Similarly, an LOS condition on CKIN2 causes
register bit) is declared for that clock input. Be aware
[2:0] bits as shown in Table 55. More than one input can be monitored
(register 3, bit 5).
after a valid input clock
. This mode is
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