Silicon Labs Si5348 Reference Manual

Si5348 Revision E Reference Manual

This Reference Manual is intended to provide system, PCB de-

signal integrity, and software engineers the necessary tech-

sign, nical information to successfully use the Si5348 Rev E devices in end applications. The official device specifications can be found in the Si5348 Rev E datasheet.

The Si5348 is a high performance jitter attenuating clock multiplier with capabilities to address Telecom Boundary Clock (T-BC), Synchronous Ethernet (SyncE), IEEE-1588 (PTP) slave clock synchronization, and Stratum 3/3E network synchronization applications. The Si5348 is well suited for both traditional and packet based network timing solutions. The device contains three independent DSPLLs of identical performance allowing for flexible single-chip timing architecture solutions. Each DSPLL contains a digitally controlled oscillator (DCO) for precise timing for IEEE 1588 (PTP) clock steering applications. The Si5348 requires both a crystal and a reference input. The TCXO/ OCXO reference input determines the frequency accuracy and stability, while the crystal determines the output jitter performance. The TCXO/OCXO input supports all standard frequencies. The Si5348 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up with a known configuration. Programming the Si5348 is made easy with Silicon Labs’ ClockBuilder Pro software available at http://www.silabs.com/CBPro. Factory preprogrammed devices are available.

1. Work Flow Using ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to the applications notes and Knowledge Base articles within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is to enable use of the device without an in-depth understanding of its complexities. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

1.1 Field Programming

To simplify design and software development of systems using the Si5348, a field programmer is available in addition to the evaluation board. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5348 sample devices. Refer to www.silabs.com/CBProgrammer for information about this kit.

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Si5348 Revision E Reference Manual

Family Product Comparison

2. Family Product Comparison

The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, outputs and package type.

Table 2.1. Family Feature Comparison

Part Number # of Inputs # of DSPLLs Number of Outputs Max Frequency Package Type

Si5348A 5 3 7 720 MHz 64-pin QFN

S5348B 5 3 7 350 MHz 64-pin QFN

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CSb

RSTb

REFb

REF

SPI/

NVM

VDD

DSPLL_B

VDDA

VDDS

Status

Monitors

48-54MHz XTAL

DSPLL_A

n_A

d_A

DSPLL_C

n_C

d_C

DSPLL_D

n_D

d_D

OSC

LPFPD

DCO

Si5348

Output

Crosspoint

A C

÷R

A C D

D C A

VDDO0 OUT0 OUT0b

VDDO1 OUT1 OUT1b

VDDO2 OUT2 OUT2b

VDDO3 OUT3 OUT3b

VDDO4 OUT4 OUT4b

VDDO5 OUT5 OUT5b

VDDO6 OUT6 OUT6b

INTRb

LOL_Cb

LOL_Db

LOS0b

LOL_Ab

LOS1b

LOS2b

FINC

FDEC

OE0b

OE1b

OE2b

Figure 2.1. Block Diagram Si5348

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Functional Description

3. Functional Description

The Si5348 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operated independently from each other and are controlled through a common serial interface. DSPLLs (A, C and D) all have access to any of the three inputs (IN0 to IN2), as well as the reference (REF) after having been divided down by the P dividers, which are either fractional or integer. DSPLL D has access to two additional CMOS inputs (IN3 and IN4). Clock selection can be either manual or automatic. There are some restrictions on the two additional CMOS inputs that are described in the input section. Any of the output clocks (OUT0 to OUT6) can be configured to connect to any of the DSPLLs using a flexible crosspoint connection. The reference oscillator uses DSPLL B. Both a Crystal and a Reference (OCXO/TCXO) must be installed for the device to operate. Each DSPLL contains a multisynth. DSPLLA contains MultiSynth N0, DSPLL C contains MultiSynth N2 and DSPLL D contains MultiSynth N3.

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Si5348 Revision E Reference Manual

Functional Description

3.1 DSPLL and MultiSynth

DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) al-

The low for integer or fractional division of the input frequency, but the input frequencies must be integer related to allow the DSPLL to perform hitless switching between input clocks (INx). Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the generated frequencies to any of the outputs. A single MultiSynth output can connect to one or more output drivers. Additional integer division (R) determines the final output frequency.

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CSb

RSTb

REFb

REF

SPI/

NVM

VDD

DSPLL_B

VDDA

VDDS

Status

Monitors

48-54MHz XTAL

DSPLL_A

n_A

d_A

DSPLL_C

n_C

d_C

DSPLL_D

n_D

d_D

OSC

LPFPD

DCO

Si5348

Output

Crosspoint

A C

÷R

A C D

D C A

VDDO0 OUT0 OUT0b

VDDO1 OUT1 OUT1b

VDDO2 OUT2 OUT2b

VDDO3 OUT3 OUT3b

VDDO4 OUT4 OUT4b

VDDO5 OUT5 OUT5b

VDDO6 OUT6 OUT6b

INTRb

LOL_Cb

LOL_Db

LOS0b

LOL_Ab

LOS1b

LOS2b

FINC

FDEC

OE0b

OE1b

OE2b

Figure 3.1. DSPLL and Multisynth System Flow Diagram

The frequency configuration of the DSPLL is programmable through the SPI or I2C

serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

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Si5348 Revision E Reference Manual

Functional Description

3.1.1 Dividers

are several divider classes within the Si5348. See Figure 2.1 Block Diagram Si5348 on page 6 for a block diagram that shows

There them. Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 7. Digitally-Controlled Os-

cillator (DCO) Mode for more information and block diagrams on DCO mode.

1. PXAXB: Xtal Reference input divider (0x0206)

• Divide reference clock by 1, 2, 4, or 8 to obtain an internal reference 48MHz - 54 MHz

2. P0-P3: Input clock and Reference wide range dividers (0x0208-0x022F)

• Integer or Fractional divide values

• Min. value is 1, Max. value is 2

• 48-bit numerator, 32-bit denominator

• Practical P divider range of (Fin/2 MHz) < P < (Fin/8 kHz)

• Each P divider has a separate update bit for the new divider value to take effect

• Note that P3 (0x0226-0x022F) is used for the Reference OCXO/TCXO.

• P0, P1 and P2 are used for the inputs.

3. MA-MD: DSPLL feedback dividers (0x0415-0x041F, 0x0515-0x051F, 0x0615-0x061F, 0x0716-0x0720))

• Integer or Fractional divide values

• Min. value is 1, Max. value is 2

• 56-bit numerator, 32-bit denominator

• Practical M divider range of (Fdco/2 MHz) < M < (Fdco/8 kHz)

• Each M divider has a separate update bit for the new divider value to take effect

• Soft reset will also update M divider values

• MB divider is used for the Reference OCXO/TCXO

4. Output N dividers N0, N2, N3 (0x0302-0x032D)

• Multisynth divider

• Integer or fractional divide values

• 44-bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

5. FSTEPW: DSPLL DCO step words for PLLA, C, D (0x0423-0x0429, 0x0623-0x0629, 0x0724-0x072A)

• Positive Integers, where FINC/FDEC select direction

• Min. value is 0, Max. value is 2

• 56-bit step size, relative to 32-bit M numerator

6. R0-R6: Output dividers (0x0250-0x026A)

• Even integer divide values: 2, 4, 6, etc.

• Min. value is 2, Max. value is 2

• 24-bit word where Value = 2 x (Word + 1), for example Word=3 gives an R value of 8

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Functional Description

3.1.2 DSPLL Loop Bandwidth

DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL

The loop bandwidth settings in the range of 1 mHz up to 4 kHz are available for selection. Tthe loop bandwidth is controlled digitally and remains stable with less than 0.1 dB of peaking for the loop bandwidth selected. The DSPLL loop bandwidth is set in registers 0x0408-0x040D, 0x0508-0x050D, 0x0608-0x060D, 0x0709-0x070E, and are determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (f

), the more chance that f

pfd

will cause a spur in the

pfd

Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase noise/jitter it is recommended that the normal PLL bandwidth be kept less than f

/160 although ratios of f

pfd

/100 will typically work fine.

pfd

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414[0], 0x0514[0], 0x0614[0], 0x0715[0]) must be set high to latch the new values into operation. The update bits will latch both nominal and fastlock bandwidths.

Table 3.1. PLL Bandwidth Registers

Setting Name Hex Address [Bit Field] Function

Si5348

BW_PLLA 0408[7:0] - 040D[7:0] This group of registers determine the loop

BW_PLLC 0608[7:0] - 060D[7:0]

BW_PLLD 0709[7:0] - 070E[7:0]

BW_PLLB 0508[7:0] - 050D[7:0]

bandwidth for DSPLL A, C, D and B (OCXO/TCXO Reference). They are all independently selectable in the range from 1 mHz up to 4 kHz. Register values are determined by ClockBuilderPro. Generally PLL B is set to 100 Hz, while PLLs A, C, and D are set 10x lower (10Hz and below).

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3.1.2.1 Fastlock Feature

Si5348 Revision E Reference Manual

Functional Description

Selecting

a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the nominal DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in the fault monitoring section.

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414[0], 0x0514[0], 0x0614[0], 0x0715[0]) must be set hight to latch the new values into operation. This update bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.2. PLL Fastlock Registers

Setting Name Hex Address [Bit Field] Function

Si5348

FASTLOCK_AUTO_EN_PLLA 0x042B[0] Auto Fastlock Enable/Disable. Manual

FASTLOCK_AUTO_EN_PLLC 0x062B[0]

FASTLOCK_AUTO_EN_PLLD 0x072C[0]

FASTLOCK_AUTO_EN_PLLB 0x052B[0]

Fastlock must be 0 for this bit to have effect.

0: Disable Auto Fastlock

1: Enable Auto Fastlock (default)

FAST_BW_PLLA 0x040E[7:0] -0x0413[7:0] Fastlock bandwidth is selectable in the

FAST_BW_PLLC 0x060E[7:0] - 0x0613[7:0]

range of 10 Hz up to 4 kHz. Register values determined using ClockBuilder Pro.

FAST_BW_PLLD 0x070F[7:0] -0x0714[7:0]

FAST_BW_PLLB 0x050E[7:0] - 0x0513[7:0] The reference fastlock bandwidth is select-

able in the range of 100Hz to 4kHz

FASTLOCK_EXTEND_EN_PLL(A,B,C,D) 0x00E5[4:7] Set by CBPro: Enables FASTLOCK_EX-

TEND, an optional extension to fast-lock timer.

FASTLOCK_EXTEND_PLLA

FASTLOCK_EXTEND_PLLB

[ 0x00E9[4:0] 0x00E8[7:0] 0x00E7[7:0]

0x00E6[7:0] ]

[ 0x00ED[4:0] 0x00EC[7:0] 0x00EB[7:0]

Set by CBPro to minimize phase transients when switching the PLL bandwidth

0x00EA[7:0] ]

FASTLOCK_EXTEND_PLLC

[ 0x00F1[4:0] 0x00F0[7:0] 0x00EF[7:0]

0x00EE[7:0] ]

FASTLOCK_EXTEND_PLLD

[ 0x00F5[4:0] 0x00F4[7:0] 0x00F3[7:0]

0x00F2[7:0] ]

FASTLOCK_EXTEND_SCL_PLLA

FASTLOCK_EXTEND_SCL_PLLB

FASTLOCK_EXTEND_SCL_PLLC

0x0294[3:0]

0x0294[7:4]

0x0295[3:0]

Set by CBPro

FASTLOCK_EXTEND_SCL_PLLD

0x0295[7:4]

HOLDEXIT_BW_SEL0 0x059B[6] Set by CBPro

HOLDEXIT_BW_SEL1 0x052C[4] Set by CBPro

LOL_SLW_VALWIN_SELX_PLL(A,B,C,D) 0x0296[3:0] Set by CBPro

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Setting Name Hex Address [Bit Field] Function

Si5348

Si5348 Revision E Reference Manual

Functional Description

FASTLOCK_DLY_ONSW_PLLA

FASTLOCK_DLY_ONSW_PLLB

FASTLOCK_DLY_ONSW_PLLC

FASTLOCK_DLY_ONSW_PLLD

FASTLOCK_DLY_ON-

0x02A6[19:0]

0x02A9[19:0]

0x02AC[19:0]

0x02AF[19:0]

0x0299[3:0] Set by CBPro

Set by CBPro

LOL_EN_PLL(A,B,C,D)

FASTLOCK_DLY_ONLOLA

FASTLOCK_DLY_ONLOLB

FASTLOCK_DLY_ONLOLC

FASTLOCK_DLY_ONLOLD

0x029A[19:0]

0x029D[19:0]

0x02A0[19:0]

0x02A3[19:0]

Set by CBPro

3.1.2.2 Holdover Exit Bandwidth

addition to the operating loop and fastlock bandwidths, there is also a user-selectable bandwidth when exiting holdover and locking or relocking to an input clock, available when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the loop bandwidth by default.

Note: The BW_UPDATE_PLLx bit bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.3. DSPLL Holdover Exit Bandwidth Registers

HOLDEXIT_BWx_PLLx

0x049D–0x04A2

0x069D–0x06A2 0x079D–0x07A2

Determines the Holdover Exit BW for DSPLL A, C and D. Parameters are generated by ClockBuilder Pro. See CBPro for the generated values and corresponding bandwidths.

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Modes of Operation

4. Modes of Operation

Once initialization is complete, the DSPLL operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail.

Power-Up

Reset and

Initialization

No valid input

clocks available

for selection

No valid

input clocks

selected

An input is

qualified and

available for

selection

Holdover

Mode

Free-run

Lock Acquisition

(Fast Lock)

Input Clock

Yes

Holdover

History

Valid?

Figure 4.1. Modes of Operation

Valid input clock

selected

Switch

Yes

Phase lock on selected

clock is achieved

Locked

Mode

Other Valid

Clock Inputs

Available?

input

Selected input

clock

fails

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Modes of Operation

4.1 Reset and Initialization

power is applied, the device begins an initialization period where it downloads default register values and configuration data from

Once internal non-volatile memory (NVM) and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

NVM

OTP

RAM

Figure 4.2. Si5348 Memory Configuration

Table 4.1. Reset Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

HARD_RST 0x001E[1] Performs the same function as power cy-

cling the device. All registers will be restored to their default values.

SOFT_RST_ALL 0x001C[0] Resets the device without re-downloading

the register configuration from NVM.

SOFT_RST_PLLA 0x001C[1] Performs a soft reset on DSPLL A only.

SOFT_RST_PLLB 0x001C[2] Performs a soft reset on DSPLL B, affect-

ing all PLLs.

SOFT_RST_PLLC 0x001C[3] Performs a soft reset on DSPLL C only.

SOFT_RST_PLLD 0x001C[4] Performs a soft reset on DSPLL D only.

Power-Up

NVM download

Initialization

Serial interface

ready

Hard Reset

bit asserted

Soft Reset

bit asserted

RST

pin asserted

Figure 4.3. Initialization from Hard Reset and Soft Reset

The Si5348 is

fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from NVM. Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins. Neither VDDOx or VDDS supplies are required to write the NVM.

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4.2 Dynamic PLL Changes

Si5348 Revision E Reference Manual

Modes of Operation

ClockBuilder

Pro generates all necessary control register writes to update settings for the entire device, including the ones described below. This is the case for both “Export” generated files as well as when using the GUI. This is sufficient to cover most applications. However, in some applications it is desirable to modify only certain sections of the device while maintaining unaffected clocks on the remaining outputs. If this is the case CBPro provides some frequency on the fly examples.

If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefinitely). Additionally, making single frequency step changes greater than ±350 ppm, either by using the DCO or by directly updating the M dividers, may also cause the PLL to become unresponsive. Changes to the following registers require this special sequence of writes:

Control Register(s)

PXAXB 0x0206[1:0]

MXAXB_NUM 0x0235 – 0x023A

MXAXB_DEN 0x023B – 0x023E

PLL lockup can easily be avoided by using the following the preamble and postamble write sequence below when one of these regis-

is modified or large frequency steps are made. Clockbuilder Pro software adds these writes to the output file by default when Ex-

ters porting Register Files.

To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC0

0x0B25 0x04

0x0540 0x01

Wait 300 ms for the device state to stabilize.

Then, modify all desired control registers.

Write 0x01 to Register 0x001C (SOFT_RST_ALL) to perform a Soft Reset once modifications are complete.

Write the postamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0540 0x00

0x0B24 0xC3

0x0B25 0x06

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4.3 NVM Programming

Si5348 Revision E Reference Manual

Modes of Operation

Devices

have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Table 4.2. NVM Bank Burning Values

Active NVM BANK Value (Deci-

Number of User Banks Burned Number of User Banks Available to Burn

mal)

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:

VDD and VDDA power must both be stable throughout the process.

•

• No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01. DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed. Verify device operation before writing registers to NVM.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Poll DEVICE_READY until DEVICE_READY=0x0F.

5. Set NVM_READ_BANK 0x00E4[0]=1. This will load the NVM contents into non-volatile memory.

6. Poll DEVICE_READY until DEVICE_READY=0x0F.

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 4.3. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

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Modes of Operation

Warning:

Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the PAGE register.

4.4 Free Run Mode

Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode, generating the frequencies determined by the NVM. The frequency accuracy and stability of the generated output clocks in freerun mode is entirely dependent on the reference clock (REF/REFb), while the external crystal at the XA/XB pins determines the jitter performance of the output clocks. For example, if the reference frequency is ±10 ppm, then all the output clocks will be generated at their configured frequency ±10ppm in freerun mode. Any drift of the reference frequency will be tracked at the output clock frequencies in this mode.

4.5 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

4.6 Locked Mode

Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOL pin and status bit to indicate when lock is achieved. See Section 5.3.3 Loss of Lock (LOL) Fault Monitoring for more details on the operation of the loss of lock circuit.

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Modes of Operation

4.7 Holdover Mode

of the DSPLLs will automatically enter holdover when its associated input clock becomes invalid (i.e., when either OOF or LOS are

Any asserted) and no other valid input clocks are available for selection. Note that IN0-IN2 monitor OOF and LOS, but IN3 and IN4 only monitor LOS since there is no OOF monitor for these inputs. Each DSPLL calculates a historical average of the input frequency while in locked mode to minimize the initial frequency offset when entering the holdover mode. The averaging circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window with the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value is used to ignore frequency data that may be corrupt just before the input clock failure. Each DSPLL computes its own holdover frequency average to maintain complete holdover independence between the DSPLLs.

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

time

120s

Programmable historical data window

used

to determine the final holdover value

1s,10s, 30s, 60s

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

Figure 4.4. Programmable Holdover Window

When entering holdover, a DSPLL will pull its output clock frequency to the calculated average holdover frequency. While in holdover,

output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. If a clock input be-

the comes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves adjusting the output clock to achieve frequency and phase lock with the new input clock.

The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the output frequency while in holdover and the desired, new output frequency is measured. It is likely that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the XTAL drift might have changed the output frequency. The ramp logic calculates the difference in frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop bandwidth values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit from holdover is also used for ramped input clock switching. See Section 5.2.3 Ramped Input Switching for more information.

As shown in Section 4. Modes of Operation, the Holdover and Freerun modes are closely related. The device will only enter Holdover if a valid clock has been selected long enough for the holdover history to become valid. If the clock fails before the combined holdover history length and holdover history delay time has been met, then holdover history won't be valid and the device will enter Freerun mode instead. Reducing the holdover history length and holdover history delay times will allow Holdover in less time, limited by the source clock failure and wander characteristics. Note that the Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.

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Modes of Operation

Table 4.4. Holdover Mode Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

HOLD_HIST_LEN_PLLA 042E[4:0] Window Length time for historical average

HOLD_HIST_LEN_PLLC 062E[4:0]

HOLD_HIST_LEN_PLLD 072F[4:0]

HOLD_HIST_DELAY_PLLA 042F[4:0] Delay Time to ignore data for historical

HOLD_HIST_DELAY_PLLC 062F[4:0]

HOLD_HIST_DELAY_PLLD 0730[4:0]

FORCE_HOLD_PLLA 0435[0] These bits allow forcing any of the DSPLLs

FORCE_HOLD_PLLC 0635[0]

FORCE_HOLD_PLLD 0736[0]

HOLD_EXIT_BW_SEL_PLLA 042C[4] Selects the exit from holdover bandwidth.

HOLD_EXIT_BW_SEL_PLLC 062C[4]

HOLD_EXIT_BW_SEL_PLLD 072D[4]

frequency used in Holdover mode. Window Length in seconds (s): Window Length =

LEN

-1)*268ns

average frequency in Holdover mode. Delay Time in seconds (s):

Delay Time = (2

DELAY

)*268ns

into holdover.

Options are:

0: Exit of holdover using the fastlock bandwith

1: Exit of holdover using the DSPLL loop bandwidth

Holdover Status

HOLD_PLLA

HOLD_PLLC

HOLD_PLLD

000E[4]

000E[6]

000E[7]

Holdover status indicator. Indicates when a DSPLL is in holdover or free-run mode and is not synchronized to the input reference. The DSPLL goes into holdover only when the historical frequency data is valid, otherwise the DSPLL will be in free-run mode.

HOLD_FLG_PLLA

HOLD_FLG_PLLC

HOLD_FLG_PLLD

0013[4]

0013[6]

0013[7]

Holdover status monitor sticky bits. Sticky bits will remain asserted when a holdover event occurs. Writing a zero to a sticky bit will clear it.

HOLD_HIST_VALID_PLLA 043F[1] Holdover historical frequency data valid in-

HOLD_HIST_VALID_PLLC 063F[1]

HOLD_HIST_VALID_PLLD 0740[1]

dicates if there is enough historical frequency data collected for valid holdover history.

Holdover Control and Settings

HOLD_RAMP_BYP_PLLA 042C[3] Enable Frequency

HOLD_RAMP_BYP_PLLC 062C[3]

Ramping on Holdover Exit

HOLD_RAMP_BYP_PLLD 072D[3]

RAMP_STEP_SIZE_PLLA 04A6[2:0] During frequency ramping, size of a DCO

RAMP_STEP_SIZE_PLLC 06A6[2:0]

frquency step in ppm.

RAMP_STEP_SIZE_PLLD 07A6[2:0]

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Modes of Operation

Setting Name Hex Address [Bit Field] Function

Si5348

RAMP_STEP_INTERVAL_PLLA 042C[4] During frequency ramping, this is how often

RAMP_STEP_INTERVAL_PLLC 042C[6]

RAMP_STEP_INTERVAL_PLLD 042C[7]

a DCO step in frequency occurs.

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Clock Inputs

5. Clock Inputs

There are four inputs that can be used to synchronize DSPLLs A, and C and six inputs that can be used to synchronize to DSPLL D. The inputs (IN0-IN2 and REF) accept both differential and single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs (IN0, IN1, IN2, REF) to be connected to DSPLLA, DSPLLC and/or DSPLLD as shown in the figure below. DSPLL D has two additional inputs (IN3 and IN4) that support LVCMOS input format only. If both IN3 and IN4 are used they must be the exact same frequency. Automatic clock selection and/or hitless switching can be used on any four inputs for any of the PLLs including PLLD. This includes IN3/IN4. The restriction is that only 4 inputs can be used. If PLL D uses more than 4 inputs, then only manually selection is available and hitless switching is not available. IN3/IN4 can support automatic holdover entry/exit based on LOS. IN0-IN2 can support automatic holdover entry/exit based on OOF and LOS, while IN3 and IN4 support automatic holdover entry/exit based only on LOS because OOF is not supported. Note that there is no OOF status for IN3 or IN4 CMOS inputs.

A reference (REF) must be connected to DSPLLB as a minimum but may be shared to the other DSPLLs as well. The device will not operate without a reference to PLLB.

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

Si5348

REFb

REF

Input

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

Figure 5.1. Clock Inputs Example

Crosspoint

0 1 2

4 5

DSPLL

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Clock Inputs

5.1 Input Source Selection

source selection for each of the DSPLLs can be made manually through register control or automatically for up to 4 inputs using

Input the internal state machine.

Table 5.1. Manual or Automatic Input Clock Selection Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

CLK_SWITCH_MODE_PLLA 0436[1:0] Selects manual or automatic switching

CLK_SWITCH_MODE_PLLC 0636[1:0]

CLK_SWITCH_MODE_PLLD 0737[1:0]

CONFIGx_CMOS_PLLD 07AA[5:4] and [2:0] Selects the routing for the IN3/IN4 CMOS

mode for DSPLL A, C, D.

0: For manual

1: For automatic, non-revertive

2: For automatic, revertive

3: Reserved

inputs when 4 inputs (max) are used in automatic clock selection in PLL D when IN3/IN4 are used.

5.1.1 Manual Input Switching

manual mode the input selection is made by writing to the IN_SEL_PLLx register, or via pin control. If there is no clock signal on the

In selected input, the DSPLL will automatically enter holdover mode.

Table 5.2. Manual Input Select Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

IN_SEL_PLLA 042A[1:0] Selects the clock input used to synchronize

IN_SEL_PLLC 062A[1:0]

IN_SEL_PLLD 072B[2:0]

DSPLL A, C, or D. Selections are: IN0, IN1, IN2, REF corresponding to the values 0, 1, 2, 3. Note that for PLL A and PLL C the selections are IN0-IN2, REF while for PLL D the selections are IN0(0), IN1 (1), IN2 (2), REF (3), IN3 (4), IN4(5).

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5.1.2 Automatic Input Switching

Si5348 Revision E Reference Manual

Clock Inputs

Automatic

input switching is available in addition to the manual selection described previously. When configured in automatic mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority arrangement is independently configurable for each DSPLL and supports revertive or non-revertive selection. When the currently selected clock is no longer valid, the highest priority clock that is valid will be selected. All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). By default, inputs asserting either or both LOS or OOF cannot be selected as a source for any DSPLL. However, these restrictions may be removed by writing to the registers described below. If there is no valid input clock, the DSPLL will enter either Holdover or Free Run mode depending on whether the holdover history is valid at that time or not.

Note: PLLA and PLLC have 4 available inputs IN0, IN1, IN2 and REF and all can be used in automatic selection. PLLD has 6 available inputs IN0, IN1, IN2, REF, IN3 and IN4 of which 4 can be selected using automatic input control. If more than 4 clock inputs are used in a PLLD application, then manual clock selection must be used.

Table 5.3. Automatic Input Select Control Registers

Setting Name Function

IN(3,2,1,0)_PRIORITY_PLLA Selects the automatic selection priority for [REF, IN2, IN1, IN0] for

IN(3,2,1,0)_PRIORITY_PLLC

each DSPLL A, C, D. Selections are: 1st, 2nd, 3rd, or never select. Default is IN0=1st, IN1=2nd, IN2=3rd, REF never selected.

IN(3,2,1,0)_PRIORITY_PLLD

IN(3,2,1,0)_LOS_MSK_PLLA Determines if the LOS status for [REF, IN2, IN1, IN0] is used in

IN(3,2,1,0)_LOS_MSK_PLLC

IN(3,2,1,0)_LOS_MSK_PLLD

determining a valid clock for the automatic input selection state machine for DSPLL A, C, D. Default is LOS is enabled (unmasked).

IN(3,2,1,0)_OOF_MSK_PLLA Determines if the OOF status for [REF, IN2, IN1, IN0] is used in

IN(3,2,1,0)_OOF_MSK_PLLC

determining a valid clock for the automatic input selection state machine for DSPLL A, C, D. Default is enabled (un-masked).

IN(3,2,1,0)_OOF_MSK_PLLD

IN_OOF_MSK_PLLB Default is set to mask the Reference Input.

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Clock Inputs

5.2 Types of Inputs

of the differential inputs IN0-IN2, and REF are compatible with standard LVDS, LVPECL, HCSL, CML, and single-ended

Each LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be accoupled and use the “Standard” Input Buffer selection as these pins are internally dc-biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown in the figure below. The resistor divider values given below will work with up to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance.

Note: For best common mode rejection it is recommended to use the split input termination for the LVDS/LVPECL differential inputs.

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Clock Inputs

Standard Differential AC-Coupled Input Buffer (IN0-IN2)

0.1uF*

Si5348

STANDARD

LVCMOS /

3.3/2.5/1.8V

VDS, LVPECL

or CML

caps should have < ~5 ohms capacitive reactance at the clock input frequency.

* These

0.1uF*

INx

100

INxb

PULSED CMOS

Standard Single-ended AC-Coupled Input Buffer (IN0-IN2)

3.3/2.5/1.8 V VCMOS

RS matches the CMOS

driver to a 50 ohm

transmission line (if used)

When 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if needed to

the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the output jitter due to

keep

faster input slew rate at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm

and omit C1, R2 and the capacitor below R2. * This cap should have less than ~20 ohms of

capacitive reactance at the clock input frequency

0.1uF*

0.1uF

INx

INxb

Si5348

STANDARD

LVCMOS /

PULSED CMOS

LVCMOS DC-coupled Single-ended, (IN0-IN2)

3.3 V, 2.5 V, 1.8 V VCMOS

RS matches the CMOS

driver

to a 50 ohm

transmission line (if used)

VDD R1 Ω

1.8V

2.5V

3.3V

324 511 634

R2 Ω

665 475 365

INx

INxb

PULSED CMOS

0x094F[4] IN_CMOS_USE1P8 = 1

Si5348

STANDARD

LVCMOS /

Pulsed CMOS, < 1MHz, DC-coupled Single-ended, (IN0-IN2)

3.3 V, 2.5 V, 1.8 V LVCMOS

3.3 V, 1.8 V LVCMOS

For 3.3V input R1 and R2 resistor values should be set to equal values for

RS matches the CMOS

transmission line (if used)

VDD R1 Ω

1.8V

2.5V

3.3V

driver

to a 50 ohm

324 511 634

R2 Ω

665 475 365

INx

INxb

PULSED CMOS

Pulsed CMOS input is only

used for inputs

STANDARD

LVCMOS DC coupled, (IN3-IN4)

RS matches the CMOS

driver to a 50 ohm

transmission

50% of VDDS max

line (if used)

voltage at the input pin.

Figure 5.2. Recommended Input Terminations

Si5348

LVCMOS /

< 1 Mhz

INx

LVCMOS

Si5348

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Clock Inputs

Floating clock inputs are noise sensitive. Add a cap to ground for all non-CMOS unused clock inputs. Input clock buffers are enabled by

the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected

setting at the system level. IN3 and IN4 must be terminated when unused. For standard mode inputs, both input pins must be properly connected as shown in Figure 5.2 Recommended Input Terminations on page 25, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to connect the inverting INx input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.

Table 5.4. Input Clock Control and Configuration Registers

Setting Name Hex Address [Bit Field] Function

Si5348

IN_EN 0x0949[3:0] Enable each of the input clock buffers for

reference (REF) and IN2 through IN0.

IN_PULSED_CMOS_EN 0x0949[7:4] Enable Pulsed CMOS mode for each input

reference (REF) and IN2 through IN0.

IN_CMOS_USE1P8 0x094F[4] 0: Device uses 0.95V CMOS input buffer,

1: Devices uses 1.8V CMOS input buffer. CBPro sets this to 1 in Standard LVCMOS mode.

5.2.1 Unused Inputs

Unused inputs can be disabled and left unconnected. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the unused input bits will disable them. Enabled inputs not actively being driven by a clock may benefit from pull up or pull down resistors to avoid them responding to system noise.

5.2.2 Hitless Clock Switching with Phase Build Out

Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between two clock inputs with an integer related frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a nonzero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. Lower PLL loop bandwidth provides more filtering.

Hitless Switching with Phase Buildout should be used for applications where the input clocks are all locked to a common upstream clock, as in most synchronization systems. Hitless switching is supported for input frequencies down to 8 kHz. Gapped clocks are not recommended for use with Hitless Switching, as this may increase the phase transient on the outputs.

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Clock Inputs

5.2.3 Ramped Input Switching

switching between input clocks that are not synchronized to the same upstream clock source (i.e. are plesiochronous) there will

When be differences in frequency between clocks. Ramped switching should be enabled in these cases to ensure a smooth frequency transition on the outputs. In this situation, it is also advisable to enable phase buildout, as discussed in the previous section to minimize the input-to-output clock skew after the frequency ramp has completed.

When ramped clock switching is enabled, the Si5348 will enter into holdover and then exit from holdover when the exit ramp has been calculated. This means that ramped switching behaves like an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency so that the transition between the two frequencies will be smooth and linear. Ramped switching is not needed for cases where the input clocks are locked to the same upstream clock source. The CBPro 'DSPLL Configure' page defaults to enable 'Ramped Exit from Holdover', but the user needs to select the 'Ramped Input Switching & Exit from Holdover' option when switching between non-synchronized input clocks.The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see Section .

Table 5.5. Ramped Switching Decision Matrix

Frequency Difference be-

tween Input Frequencies

Zero PPM Select "Ramped Exit from Holdover"

Non-Zero PPM

Setting Name Hex Address [Bit Field] Function

HSW_EN_PLLA 0436[2] Hitless Switching Enable/Disable for

HSW_EN_PLLC 0636[2]

HSW_EN_PLLD 0737[2]

RAMP_SWITCH_EN_PLLA 04A6[3] Enable frenquency ramping on an input

RAMP_SWITCH_EN_PLLC 06A6[3]

RAMP_SWITCH_EN_PLLD 07A6[3]

> 500 kHz f

Pfd

If difference is:

Less than 10 ppm, select "Ramped Exit from Hold-

• over".

•

More than 10 ppm, select "Ramped input switching and Ramped Exit from Holdover".

Table 5.6. Ramped Input Switching Control Registers

Si5348

< 500 kHz

Pfd

Select "Ramped input switching and Ramped

Exit from Holdover".

DSPLL A, C, D. Hitless switching is ena-

bled by default.

switch.

HSW_MODE_PLLA 043A[1:0] Hitless switching mode select.

HSW_MODE_PLLC 063A[1:0]

HSW_MODE_PLLD 073A[1:0]

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

When

doing a clock switch between clock inputs that are frequency locked, LOL may be momentarily asserted. In such cases, the assertion of LOL will invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter parameters into the DSPLL’s closed loop, there may be transients at the clock outputs when Fastlock is entered or exited. For this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN at 0x52B[0] whenever a clock switch might occur.

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Clock Inputs

5.2.5 External Clock Switching

applications require an external switch, it is difficult for the the PLL to predict when that switch will occur. The Si5348 will tempo-

When rarily go into holdover and then exit in a controlled manner to have a minimum phase/frequency transient. If expansion beyond the maximum number of inputs is required, please see AN1111: DSPLL Input Clock Expander which describes how an external FPGA can be used for this purpose.

5.2.6 Synchronizing to Gapped Input Clocks

The DSPLL supports locking to an input clock with missing clock edges. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its edges. Gapping a clock significantly increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8. Gapped input clocks are not recommended for use with Hitless Switching, as the output phase transients may be significantly higher.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transient, when the switch occurs during a gap in either input clocks. The following figure shows a 100 MHz clock with one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock.

Gapped Input Clock Periodic Output Clock

100 MHz clock

1 missing period

100 ns 100 ns

1 2 3 4 5 6 7 8 9 10

10 ns

every 10

Period Removed

90 MHz non-gapped clock

DSPLL

1 2 3 4 5 6 7 8 9

11.11111... ns

Figure 5.3. Gapped Input Clock Use

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Clock Inputs

5.2.7 Rise Time Considerations

is well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of

It the Si5348 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase. The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input. It shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values.

IN_X Slew Rate in Differential Mode

4.5

3.5

2.5

Relateive Jitter

1.5

TYP

0.5

0 100 200 300 400 500 600

Input Slew (V/us)

Figure 5.4. Effect of Low Slew Rate on RMS Jitter

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Clock Inputs

5.3 Fault Monitoring

clocks (IN0, IN1, IN2, IN3, IN4) and the reference input REF/REFb are monitored for loss of signal (LOS) and input clocks (IN0,

Input IN1, IN2) are monitored for out-of-frequency (OOF) as shown in the figure below. The REF/REFB input is used as the "reference monitor" to help determine an OOF on IN0, IN1, or IN2. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs have a Loss Of Lock (LOL) indicator, which is asserted when synchronization is lost with their selected input clock.

XBXA

OSC

IN0b

IN1b

IN2b

Si5348

REF

REFb

IN0

IN1

IN2

IN3

IN4

LOS

OOF

Precision

Fast

Precision

Fast

Precision

Fast

DSPLL B

REF

Input

Crosspoint

LOS

0 1 2

4 5

LOL

LOS

DSPLL A

LPF

÷M

DSPLL C

LPF

÷M

DSPLL D

LPF

÷M

Figure 5.5. Fault Monitors

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+ 137 hidden pages

Silicon Labs Si5348 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Work Flow Using ClockBuilder Pro and the Register Map

1.1 Field Programming

2. Family Product Comparison

3. Functional Description

3.1 DSPLL and MultiSynth

3.1.1 Dividers

3.1.2 DSPLL Loop Bandwidth

3.1.2.1 Fastlock Feature

3.1.2.2 Holdover Exit Bandwidth

4. Modes of Operation

4.1 Reset and Initialization

4.2 Dynamic PLL Changes

4.3 NVM Programming

4.4 Free Run Mode

4.5 Lock Acquisition Mode

4.6 Locked Mode

4.7 Holdover Mode

5. Clock Inputs

5.1 Input Source Selection

5.1.1 Manual Input Switching

5.1.2 Automatic Input Switching

5.2 Types of Inputs

5.2.1 Unused Inputs

5.2.2 Hitless Clock Switching with Phase Build Out

5.2.3 Ramped Input Switching

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

5.2.5 External Clock Switching

5.2.6 Synchronizing to Gapped Input Clocks

5.2.7 Rise Time Considerations

5.3 Fault Monitoring