Silicon Labs Si5348 Reference Manual

Si5348 Revision E Reference Manual

This Reference Manual is intended to provide system, PCB de-

signal integrity, and software engineers the necessary tech-

sign, nical information to successfully use the Si5348 Rev E devices in end applications. The official device specifications can be found in the Si5348 Rev E datasheet.

The Si5348 is a high performance jitter attenuating clock multiplier with capabilities to address Telecom Boundary Clock (T-BC), Synchronous Ethernet (SyncE), IEEE-1588 (PTP) slave clock synchronization, and Stratum 3/3E network synchronization applications. The Si5348 is well suited for both traditional and packet based network timing solutions. The device contains three independent DSPLLs of identical performance allowing for flexible single-chip timing architecture solutions. Each DSPLL contains a digitally controlled oscillator (DCO) for precise timing for IEEE 1588 (PTP) clock steering applications. The Si5348 requires both a crystal and a reference input. The TCXO/ OCXO reference input determines the frequency accuracy and stability, while the crystal determines the output jitter performance. The TCXO/OCXO input supports all standard frequencies. The Si5348 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up with a known configuration. Programming the Si5348 is made easy with Silicon Labs’ ClockBuilder Pro software available at http://www.silabs.com/CBPro. Factory preprogrammed devices are available.

1. Work Flow Using ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to the applications notes and Knowledge Base articles within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is to enable use of the device without an in-depth understanding of its complexities. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

1.1 Field Programming

To simplify design and software development of systems using the Si5348, a field programmer is available in addition to the evaluation board. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5348 sample devices. Refer to www.silabs.com/CBProgrammer for information about this kit.

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Si5348 Revision E Reference Manual

Family Product Comparison

2. Family Product Comparison

The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, outputs and package type.

Table 2.1. Family Feature Comparison

Part Number # of Inputs # of DSPLLs Number of Outputs Max Frequency Package Type

Si5348A 5 3 7 720 MHz 64-pin QFN

S5348B 5 3 7 350 MHz 64-pin QFN

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CSb

RSTb

REFb

REF

SPI/

NVM

VDD

DSPLL_B

VDDA

VDDS

Status

Monitors

48-54MHz XTAL

DSPLL_A

n_A

d_A

DSPLL_C

n_C

d_C

DSPLL_D

n_D

d_D

OSC

LPFPD

DCO

Si5348

Output

Crosspoint

A C

÷R

A C D

D C A

VDDO0 OUT0 OUT0b

VDDO1 OUT1 OUT1b

VDDO2 OUT2 OUT2b

VDDO3 OUT3 OUT3b

VDDO4 OUT4 OUT4b

VDDO5 OUT5 OUT5b

VDDO6 OUT6 OUT6b

INTRb

LOL_Cb

LOL_Db

LOS0b

LOL_Ab

LOS1b

LOS2b

FINC

FDEC

OE0b

OE1b

OE2b

Figure 2.1. Block Diagram Si5348

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Functional Description

3. Functional Description

The Si5348 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operated independently from each other and are controlled through a common serial interface. DSPLLs (A, C and D) all have access to any of the three inputs (IN0 to IN2), as well as the reference (REF) after having been divided down by the P dividers, which are either fractional or integer. DSPLL D has access to two additional CMOS inputs (IN3 and IN4). Clock selection can be either manual or automatic. There are some restrictions on the two additional CMOS inputs that are described in the input section. Any of the output clocks (OUT0 to OUT6) can be configured to connect to any of the DSPLLs using a flexible crosspoint connection. The reference oscillator uses DSPLL B. Both a Crystal and a Reference (OCXO/TCXO) must be installed for the device to operate. Each DSPLL contains a multisynth. DSPLLA contains MultiSynth N0, DSPLL C contains MultiSynth N2 and DSPLL D contains MultiSynth N3.

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Si5348 Revision E Reference Manual

Functional Description

3.1 DSPLL and MultiSynth

DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) al-

The low for integer or fractional division of the input frequency, but the input frequencies must be integer related to allow the DSPLL to perform hitless switching between input clocks (INx). Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the generated frequencies to any of the outputs. A single MultiSynth output can connect to one or more output drivers. Additional integer division (R) determines the final output frequency.

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CSb

RSTb

REFb

REF

SPI/

NVM

VDD

DSPLL_B

VDDA

VDDS

Status

Monitors

48-54MHz XTAL

DSPLL_A

n_A

d_A

DSPLL_C

n_C

d_C

DSPLL_D

n_D

d_D

OSC

LPFPD

DCO

Si5348

Output

Crosspoint

A C

÷R

A C D

D C A

VDDO0 OUT0 OUT0b

VDDO1 OUT1 OUT1b

VDDO2 OUT2 OUT2b

VDDO3 OUT3 OUT3b

VDDO4 OUT4 OUT4b

VDDO5 OUT5 OUT5b

VDDO6 OUT6 OUT6b

INTRb

LOL_Cb

LOL_Db

LOS0b

LOL_Ab

LOS1b

LOS2b

FINC

FDEC

OE0b

OE1b

OE2b

Figure 3.1. DSPLL and Multisynth System Flow Diagram

The frequency configuration of the DSPLL is programmable through the SPI or I2C

serial interface and can also be stored in non-volatile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

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Si5348 Revision E Reference Manual

Functional Description

3.1.1 Dividers

are several divider classes within the Si5348. See Figure 2.1 Block Diagram Si5348 on page 6 for a block diagram that shows

There them. Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 7. Digitally-Controlled Os-

cillator (DCO) Mode for more information and block diagrams on DCO mode.

1. PXAXB: Xtal Reference input divider (0x0206)

• Divide reference clock by 1, 2, 4, or 8 to obtain an internal reference 48MHz - 54 MHz

2. P0-P3: Input clock and Reference wide range dividers (0x0208-0x022F)

• Integer or Fractional divide values

• Min. value is 1, Max. value is 2

• 48-bit numerator, 32-bit denominator

• Practical P divider range of (Fin/2 MHz) < P < (Fin/8 kHz)

• Each P divider has a separate update bit for the new divider value to take effect

• Note that P3 (0x0226-0x022F) is used for the Reference OCXO/TCXO.

• P0, P1 and P2 are used for the inputs.

3. MA-MD: DSPLL feedback dividers (0x0415-0x041F, 0x0515-0x051F, 0x0615-0x061F, 0x0716-0x0720))

• Integer or Fractional divide values

• Min. value is 1, Max. value is 2

• 56-bit numerator, 32-bit denominator

• Practical M divider range of (Fdco/2 MHz) < M < (Fdco/8 kHz)

• Each M divider has a separate update bit for the new divider value to take effect

• Soft reset will also update M divider values

• MB divider is used for the Reference OCXO/TCXO

4. Output N dividers N0, N2, N3 (0x0302-0x032D)

• Multisynth divider

• Integer or fractional divide values

• 44-bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

5. FSTEPW: DSPLL DCO step words for PLLA, C, D (0x0423-0x0429, 0x0623-0x0629, 0x0724-0x072A)

• Positive Integers, where FINC/FDEC select direction

• Min. value is 0, Max. value is 2

• 56-bit step size, relative to 32-bit M numerator

6. R0-R6: Output dividers (0x0250-0x026A)

• Even integer divide values: 2, 4, 6, etc.

• Min. value is 2, Max. value is 2

• 24-bit word where Value = 2 x (Word + 1), for example Word=3 gives an R value of 8

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Functional Description

3.1.2 DSPLL Loop Bandwidth

DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL

The loop bandwidth settings in the range of 1 mHz up to 4 kHz are available for selection. Tthe loop bandwidth is controlled digitally and remains stable with less than 0.1 dB of peaking for the loop bandwidth selected. The DSPLL loop bandwidth is set in registers 0x0408-0x040D, 0x0508-0x050D, 0x0608-0x060D, 0x0709-0x070E, and are determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (f

), the more chance that f

pfd

will cause a spur in the

pfd

Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase noise/jitter it is recommended that the normal PLL bandwidth be kept less than f

/160 although ratios of f

pfd

/100 will typically work fine.

pfd

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414[0], 0x0514[0], 0x0614[0], 0x0715[0]) must be set high to latch the new values into operation. The update bits will latch both nominal and fastlock bandwidths.

Table 3.1. PLL Bandwidth Registers

Setting Name Hex Address [Bit Field] Function

Si5348

BW_PLLA 0408[7:0] - 040D[7:0] This group of registers determine the loop

BW_PLLC 0608[7:0] - 060D[7:0]

BW_PLLD 0709[7:0] - 070E[7:0]

BW_PLLB 0508[7:0] - 050D[7:0]

bandwidth for DSPLL A, C, D and B (OCXO/TCXO Reference). They are all independently selectable in the range from 1 mHz up to 4 kHz. Register values are determined by ClockBuilderPro. Generally PLL B is set to 100 Hz, while PLLs A, C, and D are set 10x lower (10Hz and below).

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3.1.2.1 Fastlock Feature

Si5348 Revision E Reference Manual

Functional Description

Selecting

a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the nominal DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled. The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in the fault monitoring section.

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414[0], 0x0514[0], 0x0614[0], 0x0715[0]) must be set hight to latch the new values into operation. This update bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.2. PLL Fastlock Registers

Setting Name Hex Address [Bit Field] Function

Si5348

FASTLOCK_AUTO_EN_PLLA 0x042B[0] Auto Fastlock Enable/Disable. Manual

FASTLOCK_AUTO_EN_PLLC 0x062B[0]

FASTLOCK_AUTO_EN_PLLD 0x072C[0]

FASTLOCK_AUTO_EN_PLLB 0x052B[0]

Fastlock must be 0 for this bit to have effect.

0: Disable Auto Fastlock

1: Enable Auto Fastlock (default)

FAST_BW_PLLA 0x040E[7:0] -0x0413[7:0] Fastlock bandwidth is selectable in the

FAST_BW_PLLC 0x060E[7:0] - 0x0613[7:0]

range of 10 Hz up to 4 kHz. Register values determined using ClockBuilder Pro.

FAST_BW_PLLD 0x070F[7:0] -0x0714[7:0]

FAST_BW_PLLB 0x050E[7:0] - 0x0513[7:0] The reference fastlock bandwidth is select-

able in the range of 100Hz to 4kHz

FASTLOCK_EXTEND_EN_PLL(A,B,C,D) 0x00E5[4:7] Set by CBPro: Enables FASTLOCK_EX-

TEND, an optional extension to fast-lock timer.

FASTLOCK_EXTEND_PLLA

FASTLOCK_EXTEND_PLLB

[ 0x00E9[4:0] 0x00E8[7:0] 0x00E7[7:0]

0x00E6[7:0] ]

[ 0x00ED[4:0] 0x00EC[7:0] 0x00EB[7:0]

Set by CBPro to minimize phase transients when switching the PLL bandwidth

0x00EA[7:0] ]

FASTLOCK_EXTEND_PLLC

[ 0x00F1[4:0] 0x00F0[7:0] 0x00EF[7:0]

0x00EE[7:0] ]

FASTLOCK_EXTEND_PLLD

[ 0x00F5[4:0] 0x00F4[7:0] 0x00F3[7:0]

0x00F2[7:0] ]

FASTLOCK_EXTEND_SCL_PLLA

FASTLOCK_EXTEND_SCL_PLLB

FASTLOCK_EXTEND_SCL_PLLC

0x0294[3:0]

0x0294[7:4]

0x0295[3:0]

Set by CBPro

FASTLOCK_EXTEND_SCL_PLLD

0x0295[7:4]

HOLDEXIT_BW_SEL0 0x059B[6] Set by CBPro

HOLDEXIT_BW_SEL1 0x052C[4] Set by CBPro

LOL_SLW_VALWIN_SELX_PLL(A,B,C,D) 0x0296[3:0] Set by CBPro

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Setting Name Hex Address [Bit Field] Function

Si5348

Si5348 Revision E Reference Manual

Functional Description

FASTLOCK_DLY_ONSW_PLLA

FASTLOCK_DLY_ONSW_PLLB

FASTLOCK_DLY_ONSW_PLLC

FASTLOCK_DLY_ONSW_PLLD

FASTLOCK_DLY_ON-

0x02A6[19:0]

0x02A9[19:0]

0x02AC[19:0]

0x02AF[19:0]

0x0299[3:0] Set by CBPro

Set by CBPro

LOL_EN_PLL(A,B,C,D)

FASTLOCK_DLY_ONLOLA

FASTLOCK_DLY_ONLOLB

FASTLOCK_DLY_ONLOLC

FASTLOCK_DLY_ONLOLD

0x029A[19:0]

0x029D[19:0]

0x02A0[19:0]

0x02A3[19:0]

Set by CBPro

3.1.2.2 Holdover Exit Bandwidth

addition to the operating loop and fastlock bandwidths, there is also a user-selectable bandwidth when exiting holdover and locking or relocking to an input clock, available when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the loop bandwidth by default.

Note: The BW_UPDATE_PLLx bit bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.3. DSPLL Holdover Exit Bandwidth Registers

HOLDEXIT_BWx_PLLx

0x049D–0x04A2

0x069D–0x06A2 0x079D–0x07A2

Determines the Holdover Exit BW for DSPLL A, C and D. Parameters are generated by ClockBuilder Pro. See CBPro for the generated values and corresponding bandwidths.

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Modes of Operation

4. Modes of Operation

Once initialization is complete, the DSPLL operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in the figure below. The following sections describe each of these modes in greater detail.

Power-Up

Reset and

Initialization

No valid input

clocks available

for selection

No valid

input clocks

selected

An input is

qualified and

available for

selection

Holdover

Mode

Free-run

Lock Acquisition

(Fast Lock)

Input Clock

Yes

Holdover

History

Valid?

Figure 4.1. Modes of Operation

Valid input clock

selected

Switch

Yes

Phase lock on selected

clock is achieved

Locked

Mode

Other Valid

Clock Inputs

Available?

input

Selected input

clock

fails

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Modes of Operation

4.1 Reset and Initialization

power is applied, the device begins an initialization period where it downloads default register values and configuration data from

Once internal non-volatile memory (NVM) and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

NVM

OTP

RAM

Figure 4.2. Si5348 Memory Configuration

Table 4.1. Reset Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

HARD_RST 0x001E[1] Performs the same function as power cy-

cling the device. All registers will be restored to their default values.

SOFT_RST_ALL 0x001C[0] Resets the device without re-downloading

the register configuration from NVM.

SOFT_RST_PLLA 0x001C[1] Performs a soft reset on DSPLL A only.

SOFT_RST_PLLB 0x001C[2] Performs a soft reset on DSPLL B, affect-

ing all PLLs.

SOFT_RST_PLLC 0x001C[3] Performs a soft reset on DSPLL C only.

SOFT_RST_PLLD 0x001C[4] Performs a soft reset on DSPLL D only.

Power-Up

NVM download

Initialization

Serial interface

ready

Hard Reset

bit asserted

Soft Reset

bit asserted

RST

pin asserted

Figure 4.3. Initialization from Hard Reset and Soft Reset

The Si5348 is

fully configurable using the serial interface (I2C or SPI). At power up the device downloads its default register values from NVM. Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins. Neither VDDOx or VDDS supplies are required to write the NVM.

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4.2 Dynamic PLL Changes

Si5348 Revision E Reference Manual

Modes of Operation

ClockBuilder

Pro generates all necessary control register writes to update settings for the entire device, including the ones described below. This is the case for both “Export” generated files as well as when using the GUI. This is sufficient to cover most applications. However, in some applications it is desirable to modify only certain sections of the device while maintaining unaffected clocks on the remaining outputs. If this is the case CBPro provides some frequency on the fly examples.

If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefinitely). Additionally, making single frequency step changes greater than ±350 ppm, either by using the DCO or by directly updating the M dividers, may also cause the PLL to become unresponsive. Changes to the following registers require this special sequence of writes:

Control Register(s)

PXAXB 0x0206[1:0]

MXAXB_NUM 0x0235 – 0x023A

MXAXB_DEN 0x023B – 0x023E

PLL lockup can easily be avoided by using the following the preamble and postamble write sequence below when one of these regis-

is modified or large frequency steps are made. Clockbuilder Pro software adds these writes to the output file by default when Ex-

ters porting Register Files.

To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC0

0x0B25 0x04

0x0540 0x01

Wait 300 ms for the device state to stabilize.

Then, modify all desired control registers.

Write 0x01 to Register 0x001C (SOFT_RST_ALL) to perform a Soft Reset once modifications are complete.

Write the postamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0540 0x00

0x0B24 0xC3

0x0B25 0x06

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4.3 NVM Programming

Si5348 Revision E Reference Manual

Modes of Operation

Devices

have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Table 4.2. NVM Bank Burning Values

Active NVM BANK Value (Deci-

Number of User Banks Burned Number of User Banks Available to Burn

mal)

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:

VDD and VDDA power must both be stable throughout the process.

•

• No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01. DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed. Verify device operation before writing registers to NVM.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Poll DEVICE_READY until DEVICE_READY=0x0F.

5. Set NVM_READ_BANK 0x00E4[0]=1. This will load the NVM contents into non-volatile memory.

6. Poll DEVICE_READY until DEVICE_READY=0x0F.

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 4.3. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

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Modes of Operation

Warning:

Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the PAGE register.

4.4 Free Run Mode

Once power is applied to the Si5348 and initialization is complete, all three DSPLLs will automatically enter freerun mode, generating the frequencies determined by the NVM. The frequency accuracy and stability of the generated output clocks in freerun mode is entirely dependent on the reference clock (REF/REFb), while the external crystal at the XA/XB pins determines the jitter performance of the output clocks. For example, if the reference frequency is ±10 ppm, then all the output clocks will be generated at their configured frequency ±10ppm in freerun mode. Any drift of the reference frequency will be tracked at the output clock frequencies in this mode.

4.5 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

4.6 Locked Mode

Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOL pin and status bit to indicate when lock is achieved. See Section 5.3.3 Loss of Lock (LOL) Fault Monitoring for more details on the operation of the loss of lock circuit.

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Modes of Operation

4.7 Holdover Mode

of the DSPLLs will automatically enter holdover when its associated input clock becomes invalid (i.e., when either OOF or LOS are

Any asserted) and no other valid input clocks are available for selection. Note that IN0-IN2 monitor OOF and LOS, but IN3 and IN4 only monitor LOS since there is no OOF monitor for these inputs. Each DSPLL calculates a historical average of the input frequency while in locked mode to minimize the initial frequency offset when entering the holdover mode. The averaging circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window with the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value is used to ignore frequency data that may be corrupt just before the input clock failure. Each DSPLL computes its own holdover frequency average to maintain complete holdover independence between the DSPLLs.

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

time

120s

Programmable historical data window

used

to determine the final holdover value

1s,10s, 30s, 60s

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

Figure 4.4. Programmable Holdover Window

When entering holdover, a DSPLL will pull its output clock frequency to the calculated average holdover frequency. While in holdover,

output frequency drift is entirely dependent on the external reference clock connected to the REF/REFb pins. If a clock input be-

the comes valid, a DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This process involves adjusting the output clock to achieve frequency and phase lock with the new input clock.

The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the output frequency while in holdover and the desired, new output frequency is measured. It is likely that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the XTAL drift might have changed the output frequency. The ramp logic calculates the difference in frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop bandwidth values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit from holdover is also used for ramped input clock switching. See Section 5.2.3 Ramped Input Switching for more information.

As shown in Section 4. Modes of Operation, the Holdover and Freerun modes are closely related. The device will only enter Holdover if a valid clock has been selected long enough for the holdover history to become valid. If the clock fails before the combined holdover history length and holdover history delay time has been met, then holdover history won't be valid and the device will enter Freerun mode instead. Reducing the holdover history length and holdover history delay times will allow Holdover in less time, limited by the source clock failure and wander characteristics. Note that the Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.

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Modes of Operation

Table 4.4. Holdover Mode Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

HOLD_HIST_LEN_PLLA 042E[4:0] Window Length time for historical average

HOLD_HIST_LEN_PLLC 062E[4:0]

HOLD_HIST_LEN_PLLD 072F[4:0]

HOLD_HIST_DELAY_PLLA 042F[4:0] Delay Time to ignore data for historical

HOLD_HIST_DELAY_PLLC 062F[4:0]

HOLD_HIST_DELAY_PLLD 0730[4:0]

FORCE_HOLD_PLLA 0435[0] These bits allow forcing any of the DSPLLs

FORCE_HOLD_PLLC 0635[0]

FORCE_HOLD_PLLD 0736[0]

HOLD_EXIT_BW_SEL_PLLA 042C[4] Selects the exit from holdover bandwidth.

HOLD_EXIT_BW_SEL_PLLC 062C[4]

HOLD_EXIT_BW_SEL_PLLD 072D[4]

frequency used in Holdover mode. Window Length in seconds (s): Window Length =

LEN

-1)*268ns

average frequency in Holdover mode. Delay Time in seconds (s):

Delay Time = (2

DELAY

)*268ns

into holdover.

Options are:

0: Exit of holdover using the fastlock bandwith

1: Exit of holdover using the DSPLL loop bandwidth

Holdover Status

HOLD_PLLA

HOLD_PLLC

HOLD_PLLD

000E[4]

000E[6]

000E[7]

Holdover status indicator. Indicates when a DSPLL is in holdover or free-run mode and is not synchronized to the input reference. The DSPLL goes into holdover only when the historical frequency data is valid, otherwise the DSPLL will be in free-run mode.

HOLD_FLG_PLLA

HOLD_FLG_PLLC

HOLD_FLG_PLLD

0013[4]

0013[6]

0013[7]

Holdover status monitor sticky bits. Sticky bits will remain asserted when a holdover event occurs. Writing a zero to a sticky bit will clear it.

HOLD_HIST_VALID_PLLA 043F[1] Holdover historical frequency data valid in-

HOLD_HIST_VALID_PLLC 063F[1]

HOLD_HIST_VALID_PLLD 0740[1]

dicates if there is enough historical frequency data collected for valid holdover history.

Holdover Control and Settings

HOLD_RAMP_BYP_PLLA 042C[3] Enable Frequency

HOLD_RAMP_BYP_PLLC 062C[3]

Ramping on Holdover Exit

HOLD_RAMP_BYP_PLLD 072D[3]

RAMP_STEP_SIZE_PLLA 04A6[2:0] During frequency ramping, size of a DCO

RAMP_STEP_SIZE_PLLC 06A6[2:0]

frquency step in ppm.

RAMP_STEP_SIZE_PLLD 07A6[2:0]

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Modes of Operation

Setting Name Hex Address [Bit Field] Function

Si5348

RAMP_STEP_INTERVAL_PLLA 042C[4] During frequency ramping, this is how often

RAMP_STEP_INTERVAL_PLLC 042C[6]

RAMP_STEP_INTERVAL_PLLD 042C[7]

a DCO step in frequency occurs.

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Clock Inputs

5. Clock Inputs

There are four inputs that can be used to synchronize DSPLLs A, and C and six inputs that can be used to synchronize to DSPLL D. The inputs (IN0-IN2 and REF) accept both differential and single-ended clocks. A crosspoint between the inputs and the DSPLLs allows any of the inputs (IN0, IN1, IN2, REF) to be connected to DSPLLA, DSPLLC and/or DSPLLD as shown in the figure below. DSPLL D has two additional inputs (IN3 and IN4) that support LVCMOS input format only. If both IN3 and IN4 are used they must be the exact same frequency. Automatic clock selection and/or hitless switching can be used on any four inputs for any of the PLLs including PLLD. This includes IN3/IN4. The restriction is that only 4 inputs can be used. If PLL D uses more than 4 inputs, then only manually selection is available and hitless switching is not available. IN3/IN4 can support automatic holdover entry/exit based on LOS. IN0-IN2 can support automatic holdover entry/exit based on OOF and LOS, while IN3 and IN4 support automatic holdover entry/exit based only on LOS because OOF is not supported. Note that there is no OOF status for IN3 or IN4 CMOS inputs.

A reference (REF) must be connected to DSPLLB as a minimum but may be shared to the other DSPLLs as well. The device will not operate without a reference to PLLB.

5 MHz – 250 MHz

TCXO/OCXO

or REFCLK

Si5348

REFb

REF

Input

IN0

IN0b

IN1

IN1b

IN2

IN2b

IN3

IN4

Figure 5.1. Clock Inputs Example

Crosspoint

0 1 2

4 5

DSPLL

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Clock Inputs

5.1 Input Source Selection

source selection for each of the DSPLLs can be made manually through register control or automatically for up to 4 inputs using

Input the internal state machine.

Table 5.1. Manual or Automatic Input Clock Selection Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

CLK_SWITCH_MODE_PLLA 0436[1:0] Selects manual or automatic switching

CLK_SWITCH_MODE_PLLC 0636[1:0]

CLK_SWITCH_MODE_PLLD 0737[1:0]

CONFIGx_CMOS_PLLD 07AA[5:4] and [2:0] Selects the routing for the IN3/IN4 CMOS

mode for DSPLL A, C, D.

0: For manual

1: For automatic, non-revertive

2: For automatic, revertive

3: Reserved

inputs when 4 inputs (max) are used in automatic clock selection in PLL D when IN3/IN4 are used.

5.1.1 Manual Input Switching

manual mode the input selection is made by writing to the IN_SEL_PLLx register, or via pin control. If there is no clock signal on the

In selected input, the DSPLL will automatically enter holdover mode.

Table 5.2. Manual Input Select Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

IN_SEL_PLLA 042A[1:0] Selects the clock input used to synchronize

IN_SEL_PLLC 062A[1:0]

IN_SEL_PLLD 072B[2:0]

DSPLL A, C, or D. Selections are: IN0, IN1, IN2, REF corresponding to the values 0, 1, 2, 3. Note that for PLL A and PLL C the selections are IN0-IN2, REF while for PLL D the selections are IN0(0), IN1 (1), IN2 (2), REF (3), IN3 (4), IN4(5).

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5.1.2 Automatic Input Switching

Si5348 Revision E Reference Manual

Clock Inputs

Automatic

input switching is available in addition to the manual selection described previously. When configured in automatic mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority arrangement is independently configurable for each DSPLL and supports revertive or non-revertive selection. When the currently selected clock is no longer valid, the highest priority clock that is valid will be selected. All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). By default, inputs asserting either or both LOS or OOF cannot be selected as a source for any DSPLL. However, these restrictions may be removed by writing to the registers described below. If there is no valid input clock, the DSPLL will enter either Holdover or Free Run mode depending on whether the holdover history is valid at that time or not.

Note: PLLA and PLLC have 4 available inputs IN0, IN1, IN2 and REF and all can be used in automatic selection. PLLD has 6 available inputs IN0, IN1, IN2, REF, IN3 and IN4 of which 4 can be selected using automatic input control. If more than 4 clock inputs are used in a PLLD application, then manual clock selection must be used.

Table 5.3. Automatic Input Select Control Registers

Setting Name Function

IN(3,2,1,0)_PRIORITY_PLLA Selects the automatic selection priority for [REF, IN2, IN1, IN0] for

IN(3,2,1,0)_PRIORITY_PLLC

each DSPLL A, C, D. Selections are: 1st, 2nd, 3rd, or never select. Default is IN0=1st, IN1=2nd, IN2=3rd, REF never selected.

IN(3,2,1,0)_PRIORITY_PLLD

IN(3,2,1,0)_LOS_MSK_PLLA Determines if the LOS status for [REF, IN2, IN1, IN0] is used in

IN(3,2,1,0)_LOS_MSK_PLLC

IN(3,2,1,0)_LOS_MSK_PLLD

determining a valid clock for the automatic input selection state machine for DSPLL A, C, D. Default is LOS is enabled (unmasked).

IN(3,2,1,0)_OOF_MSK_PLLA Determines if the OOF status for [REF, IN2, IN1, IN0] is used in

IN(3,2,1,0)_OOF_MSK_PLLC

determining a valid clock for the automatic input selection state machine for DSPLL A, C, D. Default is enabled (un-masked).

IN(3,2,1,0)_OOF_MSK_PLLD

IN_OOF_MSK_PLLB Default is set to mask the Reference Input.

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Clock Inputs

5.2 Types of Inputs

of the differential inputs IN0-IN2, and REF are compatible with standard LVDS, LVPECL, HCSL, CML, and single-ended

Each LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be accoupled and use the “Standard” Input Buffer selection as these pins are internally dc-biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown in the figure below. The resistor divider values given below will work with up to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance.

Note: For best common mode rejection it is recommended to use the split input termination for the LVDS/LVPECL differential inputs.

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Clock Inputs

Standard Differential AC-Coupled Input Buffer (IN0-IN2)

0.1uF*

Si5348

STANDARD

LVCMOS /

3.3/2.5/1.8V

VDS, LVPECL

or CML

caps should have < ~5 ohms capacitive reactance at the clock input frequency.

* These

0.1uF*

INx

100

INxb

PULSED CMOS

Standard Single-ended AC-Coupled Input Buffer (IN0-IN2)

3.3/2.5/1.8 V VCMOS

RS matches the CMOS

driver to a 50 ohm

transmission line (if used)

When 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if needed to

the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the output jitter due to

keep

faster input slew rate at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm

and omit C1, R2 and the capacitor below R2. * This cap should have less than ~20 ohms of

capacitive reactance at the clock input frequency

0.1uF*

0.1uF

INx

INxb

Si5348

STANDARD

LVCMOS /

PULSED CMOS

LVCMOS DC-coupled Single-ended, (IN0-IN2)

3.3 V, 2.5 V, 1.8 V VCMOS

RS matches the CMOS

driver

to a 50 ohm

transmission line (if used)

VDD R1 Ω

1.8V

2.5V

3.3V

324 511 634

R2 Ω

665 475 365

INx

INxb

PULSED CMOS

0x094F[4] IN_CMOS_USE1P8 = 1

Si5348

STANDARD

LVCMOS /

Pulsed CMOS, < 1MHz, DC-coupled Single-ended, (IN0-IN2)

3.3 V, 2.5 V, 1.8 V LVCMOS

3.3 V, 1.8 V LVCMOS

For 3.3V input R1 and R2 resistor values should be set to equal values for

RS matches the CMOS

transmission line (if used)

VDD R1 Ω

1.8V

2.5V

3.3V

driver

to a 50 ohm

324 511 634

R2 Ω

665 475 365

INx

INxb

PULSED CMOS

Pulsed CMOS input is only

used for inputs

STANDARD

LVCMOS DC coupled, (IN3-IN4)

RS matches the CMOS

driver to a 50 ohm

transmission

50% of VDDS max

line (if used)

voltage at the input pin.

Figure 5.2. Recommended Input Terminations

Si5348

LVCMOS /

< 1 Mhz

INx

LVCMOS

Si5348

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Clock Inputs

Floating clock inputs are noise sensitive. Add a cap to ground for all non-CMOS unused clock inputs. Input clock buffers are enabled by

the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected

setting at the system level. IN3 and IN4 must be terminated when unused. For standard mode inputs, both input pins must be properly connected as shown in Figure 5.2 Recommended Input Terminations on page 25, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to connect the inverting INx input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.

Table 5.4. Input Clock Control and Configuration Registers

Setting Name Hex Address [Bit Field] Function

Si5348

IN_EN 0x0949[3:0] Enable each of the input clock buffers for

reference (REF) and IN2 through IN0.

IN_PULSED_CMOS_EN 0x0949[7:4] Enable Pulsed CMOS mode for each input

reference (REF) and IN2 through IN0.

IN_CMOS_USE1P8 0x094F[4] 0: Device uses 0.95V CMOS input buffer,

1: Devices uses 1.8V CMOS input buffer. CBPro sets this to 1 in Standard LVCMOS mode.

5.2.1 Unused Inputs

Unused inputs can be disabled and left unconnected. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the unused input bits will disable them. Enabled inputs not actively being driven by a clock may benefit from pull up or pull down resistors to avoid them responding to system noise.

5.2.2 Hitless Clock Switching with Phase Build Out

Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between two clock inputs with an integer related frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a nonzero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. Lower PLL loop bandwidth provides more filtering.

Hitless Switching with Phase Buildout should be used for applications where the input clocks are all locked to a common upstream clock, as in most synchronization systems. Hitless switching is supported for input frequencies down to 8 kHz. Gapped clocks are not recommended for use with Hitless Switching, as this may increase the phase transient on the outputs.

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Clock Inputs

5.2.3 Ramped Input Switching

switching between input clocks that are not synchronized to the same upstream clock source (i.e. are plesiochronous) there will

When be differences in frequency between clocks. Ramped switching should be enabled in these cases to ensure a smooth frequency transition on the outputs. In this situation, it is also advisable to enable phase buildout, as discussed in the previous section to minimize the input-to-output clock skew after the frequency ramp has completed.

When ramped clock switching is enabled, the Si5348 will enter into holdover and then exit from holdover when the exit ramp has been calculated. This means that ramped switching behaves like an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency so that the transition between the two frequencies will be smooth and linear. Ramped switching is not needed for cases where the input clocks are locked to the same upstream clock source. The CBPro 'DSPLL Configure' page defaults to enable 'Ramped Exit from Holdover', but the user needs to select the 'Ramped Input Switching & Exit from Holdover' option when switching between non-synchronized input clocks.The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see Section .

Table 5.5. Ramped Switching Decision Matrix

Frequency Difference be-

tween Input Frequencies

Zero PPM Select "Ramped Exit from Holdover"

Non-Zero PPM

Setting Name Hex Address [Bit Field] Function

HSW_EN_PLLA 0436[2] Hitless Switching Enable/Disable for

HSW_EN_PLLC 0636[2]

HSW_EN_PLLD 0737[2]

RAMP_SWITCH_EN_PLLA 04A6[3] Enable frenquency ramping on an input

RAMP_SWITCH_EN_PLLC 06A6[3]

RAMP_SWITCH_EN_PLLD 07A6[3]

> 500 kHz f

Pfd

If difference is:

Less than 10 ppm, select "Ramped Exit from Hold-

• over".

•

More than 10 ppm, select "Ramped input switching and Ramped Exit from Holdover".

Table 5.6. Ramped Input Switching Control Registers

Si5348

< 500 kHz

Pfd

Select "Ramped input switching and Ramped

Exit from Holdover".

DSPLL A, C, D. Hitless switching is ena-

bled by default.

switch.

HSW_MODE_PLLA 043A[1:0] Hitless switching mode select.

HSW_MODE_PLLC 063A[1:0]

HSW_MODE_PLLD 073A[1:0]

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

When

doing a clock switch between clock inputs that are frequency locked, LOL may be momentarily asserted. In such cases, the assertion of LOL will invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter parameters into the DSPLL’s closed loop, there may be transients at the clock outputs when Fastlock is entered or exited. For this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN at 0x52B[0] whenever a clock switch might occur.

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Clock Inputs

5.2.5 External Clock Switching

applications require an external switch, it is difficult for the the PLL to predict when that switch will occur. The Si5348 will tempo-

When rarily go into holdover and then exit in a controlled manner to have a minimum phase/frequency transient. If expansion beyond the maximum number of inputs is required, please see AN1111: DSPLL Input Clock Expander which describes how an external FPGA can be used for this purpose.

5.2.6 Synchronizing to Gapped Input Clocks

The DSPLL supports locking to an input clock with missing clock edges. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its edges. Gapping a clock significantly increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8. Gapped input clocks are not recommended for use with Hitless Switching, as the output phase transients may be significantly higher.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transient, when the switch occurs during a gap in either input clocks. The following figure shows a 100 MHz clock with one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock.

Gapped Input Clock Periodic Output Clock

100 MHz clock

1 missing period

100 ns 100 ns

1 2 3 4 5 6 7 8 9 10

10 ns

every 10

Period Removed

90 MHz non-gapped clock

DSPLL

1 2 3 4 5 6 7 8 9

11.11111... ns

Figure 5.3. Gapped Input Clock Use

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Clock Inputs

5.2.7 Rise Time Considerations

is well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of

It the Si5348 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase. The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input. It shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values.

IN_X Slew Rate in Differential Mode

4.5

3.5

2.5

Relateive Jitter

1.5

TYP

0.5

0 100 200 300 400 500 600

Input Slew (V/us)

Figure 5.4. Effect of Low Slew Rate on RMS Jitter

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Clock Inputs

5.3 Fault Monitoring

clocks (IN0, IN1, IN2, IN3, IN4) and the reference input REF/REFb are monitored for loss of signal (LOS) and input clocks (IN0,

Input IN1, IN2) are monitored for out-of-frequency (OOF) as shown in the figure below. The REF/REFB input is used as the "reference monitor" to help determine an OOF on IN0, IN1, or IN2. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs have a Loss Of Lock (LOL) indicator, which is asserted when synchronization is lost with their selected input clock.

XBXA

OSC

IN0b

IN1b

IN2b

Si5348

REF

REFb

IN0

IN1

IN2

IN3

IN4

LOS

OOF

Precision

Fast

Precision

Fast

Precision

Fast

DSPLL B

REF

Input

Crosspoint

LOS

0 1 2

4 5

LOL

LOS

DSPLL A

LPF

÷M

DSPLL C

LPF

÷M

DSPLL D

LPF

÷M

Figure 5.5. Fault Monitors

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Clock Inputs

5.3.1 Input Loss of Signal (LOS) Fault Detection

loss of signal monitor qualifies the input signal with the following criteria to determine if a valid signal is present. The loss of signal

The monitor measures the period of each phase detector input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits compares the measured phase detector input period to a maximum (set) and minimum (clear) period thresholds. LOS asserts if the maximum input period threshold is exceeded or if the input period is less than the minimum input period threshold. The thresholds for assert and de-assert of LOS are specified in a number of corresponding clock cycles at the input to the phase detector which is the input clock divided by it's corresponding P divider. This is translated to a time based on the frequency of the corresponding phase detetor input clock. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility.

Figure 5.6. LOS Clock Maximum (Trigger) and Minimum (Clear) Period Thresholds

Monitor

LOS

Live

LOS

Sticky

Figure 5.7. LOS Status Indicators

A LOS monitor is also available to ensure that the external crystal is valid. By default the output clocks are disabled when LOSXAXB is detected.

This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. Single-ended inputs to XA/XB must be connected to the XA input pin with the XB pin terminated properly for LOSXAXB to function correctly. The table below lists the loss of signal status indicators and fault monitoring control registers.

Table 5.7. Loss of Signal Status Monitoring and Control Registers

Setting Name Hex Address [Bit

Function

Field]

LOS (REF, 2,1,0) 000D[3:0] LOS Status monitor for Reference (REF), IN2, IN1, IN0. Indicates if a valid

clock is detected or if a LOS condition is present

LOS_CMOS (1,0) 000C[7:6] LOS Status monitor for IN3 and IN4. Indicates if a valid clock is detected or if

a LOS condition is present

LOSXAXB 000C[1] LOS status monitor for the XTAL at the XAXB pins.

LOS (REF, 2,1,0)_FLG 0012[3:0] LOS Status monitor sticky bits for Reference (REF), IN2, IN1, IN0. Sticky bits

will remain asserted when an LOS event occurs until cleared. Writing a zero

to a sticky bit will clear it.

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Clock Inputs

Setting Name Hex Address [Bit

Function

Field]

LOS_CMOS_FLG (1,0) 0011[7:6] LOS Status monitor sticky bits for IN3 and IN4. Sticky bitss will remain asser-

ted when an LOS event occurs until cleared. Writing a zero to a sticky bit will

clear it.

LOSXAXB_FLG 0011[1] LOS Status monitor sticky bits for XAXB. Sticky bitss will remain asserted

when an LOS event occurs until cleared. Writing a zero to a sticky bit will

clear it.

LOS Fault Monitor Controls and Settings

LOS (REF,2,1,0)_EN 002C[3:0] LOS monitor enable for Reference (REF), IN2, IN1, IN0. Allows disabling the

monitor if unused

LOS_CMOS_EN (4,3) 02BC[2:1] LOS monitor enable for IN3 and IN4. Allows disabling the monitor if unused

LOS(REF,2,1,0)_TRG_THR 002E[7:0]-0035[7:0] LOS trigger threshold for Reference (REF), IN2, IN1, IN0.

LOS_CMOS(1,0)_TRG_THR 02BE[7:0]-02C0[7:0] LOS trigger threshold for CMOS IN3 and IN4.

LOS(REF,2,1,0)_CLR_THR 0036[7:0]-003D[7:0] Sets the LOS trigger clear sensitivity for the Reference, IN2,IN1,and IN0 and

LOS_CMOS(1,0)_CLR_THR 02C2[7:0]-02C4[7:0]

additionally the CMOS IN3, IN4. These 16 bit values are determined in Clock-

Builder Pro.

LOS_CMOS_VAL_TIME 02BD[3:0] LOS validation time for IN3 and IN4. This sets the time that an input must

have a valid clock before the LOS conditions are cleared. Setting 2 ms, 100

ms, 300 ms and 2 s are available.

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Clock Inputs

5.3.2 Out of Frequency (OOF) Fault Detection

input clock (with the exception of IN3/IN4) is monitored for frequency accuracy with respect to a OOF reference which it considers

Each as its "0 ppm" reference. The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared. The OOF reference is the REF input because it will be more accurate and stable than the crystal at the XAXB pins. Because of this there is no OOF alarm for DSPLLB.

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure directly below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared.

Sticky

OOF

Monitor

Precision

LOS

OOF

Fast

Figure 5.8. OOF Status Indicator

The Precision OOF monitor circuit measures the frequency of all input clocks to within up to ±0.0625 ppm accuracy with respect to the selected range of from ±0.0625 ppm to ±512 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis.

OOF Declared

Because the precision OOF monitor needs to provide up to 1/16 ppm of frequency measurement accuracy, it must measure the monitored in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds more quickly because it can be programmed to larger thresholds.

OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency

Hysteresis Hysteresis

OOF Cleared

-6 ppm

(Set)

Figure 5.9. Example of Precise OOF Monitor Assertion and De-assertion Triggers

input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping

-4 ppm

(Clear

)

0 ppm

OOF

Reference

Live

+4 ppm

(Clear)

+6 ppm

(Set)

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Clock Inputs

5.3.3 Loss of Lock (LOL) Fault Monitoring

Loss of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There

The is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are four parameters to the LOL monitor.

1. Assert to set the LOL

• User sets the threshold in ppm in CBPro.

2. Fast assert to set the LOL

• CBPro sets this to ~100 times the slow assert threshold.

• A very large ppm error in a short time will assert the LOL.

3. De-assert to clear the LOL

• User sets the threshold in ppm in CBPro.

4. Clear delay

• CBPro set this based upon the project plan.

A block diagram of the LOL monitor is shown below. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor.

Si5348

LOL Monitor

LOL

Clear

LOL

Set

LOL Status Registers

Live

DSPLL A

LPF

÷M

Sticky

LOS

DSPLL D

DSPLL C

LOL_Db

LOL_Cb

LOL_Ab

Figure 5.10. LOL Status Indicators

The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. CBPro provides

wide range of set and clear thresholds for the LOL function. Having two separate frequency monitors allows for hysteresis to help

a prevent chattering of LOL status. An example configuration of the LOL set and clear thresholds is shown below.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

LOL

LOCKED

Hysteresis

0.1 1

Lost Lock

10,000

Phase Detector Frequency Difference (ppm)

Figure 5.11. LOL Set and Clear Thresholds

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Clock Inputs

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

clock. configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility. It is important to know that, in addition to being status bits, LOL optionally enables Fastlock. The settings in the table below are handled by ClockBuilder Pro. Manual settings should be avoided.

Table 5.8. Loss of Lock Status Monitor and Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

LOL Status Indicators

LOL_PLL(D,C,B,A) 000E[3:0] Status bit that indicates if DSPLL A, B (Ref-

erence), C, or D is locked to an input clock.

LOL_FLG_PLL(D,C,B,A) 0013[3:0] Sticky bits for LOL_[D,C,B,A]_STATUS

LOL Fault Monitor Controls and Settings

LOL_SET_THR_PLL(D,C,B,A) 009E[7:0] - 009F[7:0] Configures the loss of lock set thresholds

for DSPLL A, B, C, D. Selectable as 0.2,

0.6, 2, 6, 20, 60, 200, 600, 2000, 6000,

20000. Values in ppm. Default value is 0.2 ppm.

LOL_CLR_THR_PLL(D,C,B,A) 00A0[7:0] - 00A1[7:0] Configures the loss of lock clear thresholds

for DSPLL A, B, C, D. Selectable as 0.2,

0.6, 2, 6, 20, 60, 200, 600, 2000, 6000,

20000. Values in ppm. Default value is 2 ppm.

LOL_CLR_DELAY_PLL(D,C,B,A) 00A3[7:0] - 00B6[7:0] This is a 35-bit register that configures the

delay value for the LOL Clear delay. Selectable from 4 ns over 500 seconds. This value depends on the DSPLL frequency configuration and loop bandwidth. It is calculated using ClockBuilder Pro utility.

LOL_TIMER_EN_PLL(D,C,B,A) 00A2[3:0] Allows bypassing the LOL Clear timer for

DSPLL A, B, C, D. 0- bypassed, 1-enabled.

When enabled, the LOL_CLR_DELAY is active.

LOL_NOSIG_TIME_PLL(D,C,B,A) 0x02B7 ([7:6],[5:4],[3:2],[1:0]) Sets 417 ms as time without an input to as-

sert LOL. Set by CBPro

FASTLOCK_EXTEND_EN_PLL(D,C,B,A) 0x00E5 [7:4] Enable FASTLOCK_EXTEND

FASTLOCK_EXTEND_PLL(D,C,B,A) 0x00F2 [28:0] - 0x00E6 [28:0] Set by CBPro to minimize phase transients

when switching the PLL bandwidth

FASTLOCK_EXTEND_SCL_PLL(D,C,B,A) 0x0295 [7:4], [3:0], 0x0294 [7:4], [3:0] Set by CBPro

LOL_SLW_VALWIN_SELX_PLL(D,C,B,A) 0x0296 [3:0] Set by CBPro

FAST-

0x0297 [3:0] Set by CBPro

LOCK_DLY_ONSW_EN_PLL(D,C,B,A)

FASTLOCK_DLY_ONSW_PLL(D,C,B,A) 0x02AF[19:0] - 0x02A6[19:0] Set by CBPro

FASTLOCK_DLY_ON-

0x0299 [3:0] Set by CBPro

LOL_EN_PLL(D,C,B,A)

FASTLOCK_DLY_ONLOL_PLL(D,C,B,A) 0x02A3[19:0] - 0x029A[19:0] Set by CBPro

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Clock Inputs

5.3.4 Interrupt Pin (INTR)

interrupt pin (INTR) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are

An maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the sticky status registers.

Table 5.9. Interrupt Mask Registers

Setting Name Hex Address [Bit Field] Function

Si5348

LOS(REF, 2, 1, 0)_INTR_MSK 0018[3:0] Prevents Reference (REF), IN2, IN1, IN0

LOS from asserting the INTRb pin

OOF(REF,2, 1, 0)_INTR_MSK 0018[7:4] Prevents REF, IN2, IN1, IN0 OOF from as-

serting the INTRb pin

LOSXAXB_INTR_MSK 0017[1] Prevents XAXB LOS from asserting the

INTRb pin

LOS_CMOS_INTR_MSK 0017[7:6] Prevents IN3 and IN4 from asserting the

INTRb pin

LOL_INTR_MSK_PLL(D,B,C,A) 0019[3:0] Prevents DSPLL D, B,C, A LOL from as-

serting the INTRb pin

HOLD_INTR_MSK_PLL(D,C,A) 0019[7:4] Prevents DSPLL D, C, A HOLD from as-

serting the INTRb pin

CAL_FLG_PLL(D,C,B,A)_MSK 001A[7:4] Prevents DSPLL D, C, B, A calibration from

asserting the INTRb pin.

SMBUS_TIMEOUT_INTR_MKS 0017[5] Prevents SMBUS Timeout from asserting

the INTRb pin.

SYSINCAL_INTR_MSK 0017[0] Prevents SYSINCAL from asserting the

INTRb pin.

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LOSXAXB_INTR_MSK 0x0017[1]

LOSXAXB_FLG 0x0011[1]

(IN0)LOS_INTR_MSK 0x0018[0]

(IN0) LOS_FLG[0] 0x0012[0]

(IN1)LOS_INTR_MSK 0x0018[1]

(IN1) LOS_FLG[1] 0x0012[1]

(IN2)LOS_INTR_MSK 0x0018[2]

(IN2) LOS_FLG[2] 0x0012[2]

(REF)LOS_INTR_MSK 0x0018[3]

(REF) LOS_FLG[3] 0x0012[3]

(IN3)LOS_INTR_MSK 0x0017[6]

(IN3) LOS_CMOS_FLG 0x0011[6]

(IN4)LOS_INTR_MSK 0x0017[7]

(IN4) LOS_CMOS_FLG 0x0011[7]

OOF_INTR_MSK 0x0018[4]

OOF_FLG[0] 0x0012[4]

OOF_INTR_MSK 0x0018[5]

OOF_FLG[1] 0x0012[5]

OOF_INTR_MSK 0x0018[6]

OOF_FLG[2] 0x0012[6]

LOL_INTR_MSK_PLLA 0x0019[0]

LOL_FLG_PLLA 0x0013[0]

LOL_INTR_MSK_PLLB 0x0019[1]

LOL_FLG_PLLB 0x0013[1]

LOL_INTR_MSK_PLLC 0x0019[2]

LOL_FLG_PLLC 0x0013[2]

LOL_INTR_MSK_PLLD 0x0019[3]

LOL_FLG_PLLD 0x0013[3]

HOLD_INTR_MSK_PLLA 0x0019[4]

HOLD_FLG_PLLA 0x0013[4]

HOLD_INTR_MSK_PLLB 0x0019[5]

HOLD_FLG_PLLB 0x0013[5]

HOLD_INTR_MSK_PLLC 0x0019[6]

HOLD_FLG_PLLC 0x0013[6]

HOLD_INTR_MSK_PLLD 0x0019[7]

HOLD_FLG_PLLD 0x0013[7]

CAL_INTR_MSK_PLLA 0x001A[4]

CAL_FLG_PLLA 0x0014[4]

CAL_INTR_MSK_PLLB 0x001A[5]

CAL_FLG_PLLB 0x0014[5]

CAL_INTR_MSK_PLLC 0x001A[6]

CAL_FLG_PLLC 0x0014[6]

CAL_INTR_MSK_PLLD 0x001A[7]

CAL_FLG_PLLD 0x0014[7]

SMBUS_TIMEOUT_INTR_MSK 0x0017[5]

SMBUS_TIMEOUT_FLG 0x0011[5]

SYSINCAL_INTR_MSK 0x0017[0]

SYSINCAL_FLG 0x0011[0]

LOS

LOS_

CMOS

HOLD

LOL

CAL

Si5348 Revision E Reference Manual

Clock Inputs

OOF

INTR

Figure 5.12. Interrupt Triggers and Masks

The _FLG bits are “sticky” versions of the alarm bits and will stay high until cleared. A _FLG bit can be cleared by writing a zero to the _FLG bit. When a _FLG bit is high and its corresponding alarm bit is low, the _FLG bit can be cleared.

During run time, the source of an interrupt can be determined by reading the _FLG register values and logically ANDing them with the corresponding _MSK register bits (after inverting the _MSK bit values). If the result is a logic one, then the _FLG bit will cause an interrupt.

For example, if LOS_FLG[0] is high and LOS_INTR_MSK[0] is low, then the INTR pin will be active (low) and cause an interrupt. If LOS[0] is zero and LOS_MSK[0] is one, writing a zero to LOS_MSK[0] will clear the interrupt (assuming that there are no other interrupt sources). If LOS[0] is high, then LOS_FLG[0] and the interrupt cannot be cleared.

Note: The INTR pin may toggle during reset

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Outputs

6. Outputs

The Si5348 supports seven differential output drivers. Each driver has a configurable voltage amplitude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML compatible amplitudes. In addition to supporting differential signals, any of the outputs can be configured as dual single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing up to 14 single-ended outputs, or any combination of differential and single-ended outputs.

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Outputs

6.1 Output Crosspoint Switch

crosspoint allows any of the output drivers to connect with any of the DSPLLs as shown in the figure below. The crosspoint configura-

A tion is programmable and can be stored in NVM so that the desired output configuration is ready at power up.

Si5348

DSPLL

Output

Crosspoint

A C D

÷R

VDDO0 OUT0 OUT0b

VDDO1

OUT1 OUT1b

VDDO2

OUT2 OUT2b

VDDO3

OUT3 OUT3b

VDDO4

OUT4 OUT4b

VDDO5

OUT5 OUT5b

A C D

÷R

VDDO6

OUT6 OUT6b

Figure 6.1. MultiSynth to Output Driver Crosspoint

The figure above is used to set up the routing from the MultiSynth frequency selection to the output.

Table 6.1. Output Driver Crosspoint Configuration Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_MUX_SEL

0115[2:0]

Selects the DSPLL that each of the outputs are connected to. Options are DSPLL_A,

OUT1_MUX_SEL

OUT2_MUX_SEL

OUT3_MUX_SEL

OUT4_MUX_SEL

OUT5_MUX_SEL

011A[2:0]

011F[2:0]

0129[2:0]

012E[2:0]

0133[2:0]

DSPLL_C, or DSPLL_D.

OUT6_MUX_SEL

013D[2:0]

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Outputs

6.2 Output Divider (R) Synchronization

the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable

All phase alignment. Resetting the device using the RSTb pin or asserting the hard reset bit 0x001E[1] will give the same result. Soft reset does not affect output alignment.

6.3 Support for 1 Hz Output (1 pps)

Output 6 of the Si5348 can be configured to generate a 1 Hz clock by cascading the R5 and R6 dividers. Output 5 is still usable in this case but is limited to a frequency of 33.5 MHz or less. ClockBuilder Pro automatically determines the optimum configuration when generating a 1 Hz output.

A C D

Figure 6.2. Generating a 1 Hz Output using the Si5348

÷R

VDDO4

OUT4 OUT4b

VDDO5

OUT5 OUT5b

VDDO6

OUT6 OUT6b

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6.4 Performance Guidelines for Outputs

Si5348 Revision E Reference Manual

Outputs

Whenever

a number of high frequency, fast rise time, large amplitude signals are all close to one another there will be some amount of crosstalk. The jitter generation of the Si5348 is so low that crosstalk can become a significant portion of the final measured output jitter. Some of the crosstalk will come from the Si5348, and some will be introduced by the PCB. It is difficult (and possibly irrelevant) to allocate the jitter portions between these two sources since the Si5348 must be attached to a board in order to measure jitter.

For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying the arrangements of different output clocks. For example, consider the following lineup of output clocks in following table.

Table 6.2. Example of Output Clock Placement

Output Not Recommended

(Frequency MHz)

Recommended

(Frequency MHz)

0 155.52 155.52

1 156.25 155.52

2 155.52 622.08

3 156.25 Not used

4 622.08 156.25

5 625 156.25

6 Not used 625

Using this example, a few guidelines are illustrated:

1. Avoid adjacent frequency values that are close. For example, a 155.52 MHz clock should not be placed next to a 156.25 MHz clock. If the jitter integration bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart.

2. Adjacent frequency values that are integer multiples of one another are allowed, and these outputs should be grouped together when possible. Noting that because 155.52 MHz x 4 = 622.08 MHz and 156.25 MHz x 4 = 625 MHz, it is okay to place each pair of these frequency values close to one another.

3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. In this case, see OUT3 and OUT4.

If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible to crosstalk. These guidelines need to be followed by those applications that wish to achieve the highest possible levels of jitter performance. Because CMOS outputs have large pk-pk swings, are single ended, and do not present a balanced load to the VDDO supplies, they generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided in jitter-sensitive applications. When CMOS clocks are unavoidable, even greater care must be taken with respect to the above guidelines. For more information on these issues, see application note, "AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.”

The ClockBuilder Pro Clock Placement Wizard is an easy way to reduce crosstalk for a given frequency plan. This feature can be accessed on the “Define Output Frequencies” page of ClockBuilder Pro in the lower left hand corner of the GUI. It is recommended to use this tool after each project frequency plan change.

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Outputs

6.5 Output Signal Format

differential output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including

The LVDS, LVPECL, and HCSL. For CML applications, see Section 6.5.9 Setting the Differential Output Driver to Non-Standard Amplitudes. The differential formats can be either normal or low power. Low power format uses less power for the same amplitude but has the drawback of slower rise/fall times. The source impedance in low power format is much higher than 100 Ω. See Section 6.5.9 Setting the

Differential Output Driver to Non-Standard Amplitudes for register settings to implement variable amplitude differential outputs. In addi-

tion to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 14(for the Si5348) single-ended outputs, or any combination of differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins. See AN862: Optimizing Jitter Performance in Next Generation Internet Infrastructure Systems for additional information.

Table 6.3. Output Signal Format Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_FORMAT

OUT1_FORMAT

OUT2_FORMAT

OUT3_FORMAT

OUT4_FORMAT

OUT5_FORMAT

OUT6_FORMAT

0113[2:0]

0118[2:0]

011D[2:0]

0127[2:0]

012C[2:0]

0131[2:0]

013B[2:0]

Selects the output signal format as differential or LVCMOS.

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6.5.1 Output Terminations

The differential output drivers support both ac coupled and dc coupled terminations as shown in the figure below.

Outputs

= 3.3V, 2.5V, 1.8V

LVDS: V

DDO

OUTx

OUTxb

100

AC Coupled LVDS/LVPECL

= 3.3V

DDO

, 2.5V, 1.8V

= 3.3V, 2.5V

DDO

OUTx

OUTxb

0.1uF*

100

0.1uF*

Internally self-biased

LVDS: V

LVPECL: V

*All caps should have < 5 ohms capacitive reactance at the clock output frequency

= 3.3V

DDO

= 3.3V, 2.5V. 1.8V

DDO

For V

VDD

3.3 V

2.5 V

1.8 V

AC Coupled CMLDC Coupled LVDS

, 2.5V

OUTx

OUTxb

AC Coupled HCSL

0.1uF*

OUTx

OUTxb

0.1uF*

= 0.35 V

R1 Ω R2 Ω

442

332

243

56.2

59.0

63.4

VDD – 1.3V

0.1uF*

5050

VDD

Standard

HCSL

Receiver

Figure 6.3. Output Terminations for Differential Outputs

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Outputs

6.5.2 Differential Output Swing Modes

are two selectable differential output swing modes: Normal and High (also called low power mode). Each output can support a

There unique mode.

Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific reason to do otherwise. When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. Differential Output Voltage Swing Control Registers lists the registers that control the output voltage swing. The output impedance in the Normal Swing Mode is 100 Ω differential. Any of the terminations shown in are supported in this mode.

Differential High Swing Mode—When an output driver is configured in high swing mode, its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 Ω PCB traces. Any of the terminations shown in are supported. The use of High Swing mode will result in larger pk-pk output swings that draw less power. The trade off will be slower rise and fall times.

Vpp_diff is 2 x Vpp_se as shown below.

OUTx

Vcm

Vpp_se

Vcm

OUTx

Figure 6.4. Vpp_se and Vpp_diff

Table 6.4. Differential Output Voltage Swing Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_AMPL

OUT1_AMPL

OUT2_AMPL

OUT3_AMPL

OUT4_AMPL

OUT5_AMPL

0114[6:4]

0119[6:4]

011E[6:4]

0128[6:4]

012D[6:4]

0132[6:4]

Sets the differential voltage swing (amplitude) for the output drivers in both normal and low-power modes.: See Section

6.5.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML recommended set-

tings.

Vpp_diff = 2*Vpp_se

OUT6_AMPL

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013C[6:4]

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Outputs

6.5.3 Programmable Common Mode Voltage for Differential Outputs

common mode voltage (VCM) for the differential Normal and High Swing modes is programmable in 100 mV increments from 0.7

The to 2.3 V depending on the voltage available at the output's VDDO pin. Setting the common mode voltage is useful when dc coupling the output drivers. High swing mode may also cause an increase in the rise/fall time.

Table 6.5. Differential Output Common Mode Voltage Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_CM

OUT1_CM

OUT2_CM

OUT3_CM

OUT4_CM

OUT5_CM

OUT6_CM

0114[3:0]

0119[3:0]

011E[3:0]

0128[3:0]

012D[3:0]

0132[3:0]

013C[3:0]

6.5.4 LVCMOS Output Terminations

LVCMOS outputs are dc-coupled as shown in Figure 6.5 LVCMOS Output Terminations

DC Coupled LVCMOS

= 3.3V

DDO

, 2.5V, 1.8V

OUTx

Sets the common mode voltage for the differential output driver. See Section

6.5.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML recommended set-

tings.

on page 45.

3.3V, 2.5V, 1.8V LVCMOS

Figure 6.5. LVCMOS Output Terminations

6.5.5 LVCMOS Output Impedance and Drive Strength Selection

LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source

Each termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO option as shown below. The value for the OUTx_CMOS_DRIVE bits are given.

Table 6.6. Output Impedance and Drive Strength Selections

VDDO OUTx_CMOS_DRV Source Impedance Drive Strength (Iol/Ioh)

0x01 38 Ω 10 mA

3.3 V

0x02 30 Ω 12 mA

0x03

22 Ω 17 mA

0x01 43 Ω 6 mA

2.5 V

0x02 35 Ω 8 mA

0x03

24 Ω 11 mA

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VDDO OUTx_CMOS_DRV Source Impedance Drive Strength (Iol/Ioh)

1.8 V

0x03

31 Ω 5 mA

Note:

Use of the lowest impedance setting is recommended for all supply voltages.

Table 6.7. LVCMOS Drive Strength Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

Outputs

OUT0_CMOS_DRV

0113[7:6]

LVCMOS output impedance. See the table

above.

OUT1_CMOS_DRV

OUT2_CMOS_DRV

OUT3_CMOS_DRV

OUT4_CMOS_DRV

OUT5_CMOS_DRV

OUT6_CMOS_DRV

0118[7:6]

011D[7:6]

0127[7:6]

012C[7:6]

0131[7:6]

013B[7:6]

6.5.6 LVCMOS Output Signal Swing

The

signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

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6.5.7 LVCMOS Output Polarity

a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on

When the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTxb pin. The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.

Table 6.8. LVCMOS Output Polarity Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_INV

OUT1_INV

OUT2_INV

OUT3_INV

OUT4_INV

OUT5_INV

OUT6_INV

OUTx_INV

00 CLK CLK Both in phase (default)

01 CLK CLKb OUTxb inverted

10 CLKb CLK OUTx and OUTxb inverted

11 CLKb CLKb OUTx inverted

0115[7:6]

Controls output polarity of the OUTx and OUTxb pins when in LVCMOS mode. Se-

011A[7:6]

lections are below:

011F[7:6]

0129[7:6]

012E[7:6]

0133[7:6]

013D[7:6]

Table 6.9. Output Polarity of OUTx and OUTxb Pins in LVCMOS Mode

OUTx OUTxb Comment

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6.5.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

Each differential output has four settings for control:

Normal or Low Power Format

•

• Amplitude (sometimes called Swing)

• Common Mode Voltage

• Stop High or Stop Low

The normal Format setting has a 100 Ω internal resistor between the plus and minus output pins. The Low Power Format setting removes this 100 Ω internal resistor and then the differential output resistance will be > 500 Ω. However as long as the termination impedance matches the differential impedance of the pcb traces the signal integrity across the termination impedance will be good. For the same output amplitude the Low Power Format will use less power than the Normal Format. The Low Power Format also has a lower rise/fall time than the Normal Format. See the Si5348 data sheet for the rise/fall time specifications. For LVPECL and LVDS standards, ClockBuilder Pro does not support the Low Power Differential Format. Stop High means that when the output driver is disabled the plus output will be high and the minus output will be low. Stop Low means that when the output driver is disabled the plus output will be low and the minus output will be high.

The Format, Amplitude and Common Mode settings for the various supported standards are shown in Table 6.10 Settings for LVDS,

LVPECL, and HCSL on page 48.

Table 6.10. Settings for LVDS, LVPECL, and HCSL

OUTx_FORMAT

Standard VDDO Volts OUTx_CM (Deci-

mal)

OUTx_AMPL

(Decimal)

001 = Normal Differential LVPECL 3.3 11 6

001 = Normal Differential LVPECL 2.5 11 6

002 = Low Power Differential LVPECL 3.3 11 3

002 = Low Power Differential LVPECL 2.5 11 3

001 = Normal Differential LVDS 3.3 3 3

001 = Normal Differential LVDS 2.5 11 3

001 = Normal Differential

Sub-LVDS

1.8 13 3

002 = Low Power Differential LVDS 3.3 3 1

002 = Low Power Differential LVDS 2.5 11 1

002 = Low Power Differential

Sub-LVDS

HCSL

1.8 13 1

3.3 11 3

2.5 11 3

1.8 13 3

Note:

The low-power format will cause the rise/fall time to increase by approximately a factor of two. See the Si5348 data sheet for more information.

2. The common-mode voltage produced is not compliant with LVDS standards; therefore ac coupling the driver to an LVDS receiver is highly recommended.

3. Creates HCSL compatible signal. See Section 5.3 Fault Monitoring.

The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes. See Section 6.5.9 Setting

the Differential Output Driver to Non-Standard Amplitudes for additional information.

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Outputs

6.5.9 Setting the Differential Output Driver to Non-Standard Amplitudes

some applications, it may be desirable to have larger or smaller differential amplitudes than those produced by the standard LVPECL

In and LVDS settings, as selected by CBPro. In these cases, the following information describes how to implement these amplitudes by writing to the OUTx_CM and OUTx_AMPL setting names. Contact Silicon Labs for assistance if you want your custom configured device to be programmed for any of the settings described here.

The differential output driver has a variable output amplitude capability and two basic formats, normal and low-power format. The difference between these two formats is that the normal format has an output impedance of ~100 Ω differential, and the low-power format has an output impedance of > 500 Ω differential. Note that the rise/fall time is slower when using the Low Power Differential Format. See the Si5348 data sheet for rise/fall time specifications.

If the standard LVDS or LVPECL compatible output amplitudes will not work for a particular application, the variable amplitude capability can be used to achieve higher or lower amplitudes. For example, a “CML” format is sometimes desired for an application. However, CML is not a defined standard, and hence the amplitude of a CML signal for one receiver may be different than that of another receiver.

When the output amplitude needs to be different than standard LVDS or LVPECL, the Common Mode Voltage settings must be set as shown in Table 6.11 Output Differential Common Mode Voltage Settings on page 49. No settings other than these are supported as the signal integrity could be compromised. In addition, the output driver should be ac-coupled to the load so that the common-mode voltage of the driver is not affected by the load.

Table 6.11. Output Differential Common Mode Voltage Settings

VDDOx (Volts) Differential

OUTx_FORMAT Common

Format

3.3 Normal 0x1 2.0 0xB

3.3 Low Power 0x2 1.6 0x7

2.5 Normal 0x1 1.3 0xC

2.5 Low Power 0x2 1.1 0xA

1.8 Normal 0x1 0.8 0xD

1.8 Low Power 0x2 0.8 0xD

The differential amplitude can be set as shown in the following table.

Table 6.12. Typical Differential Amplitudes

OUTx_AMPL Normal Differential Format

(Vpp SE mV – Typical)

0 130 200

1 230 400

2 350 620

OUTx_CM

Mode Voltage (Volts)

Low-Power Differential Format

(Vpp SE mV – Typical)

3 450 820

4 575 1010

5 700 1200

6 810

7 920

1350

1600

Note:

These amplitudes are based upon a 100 Ω differential termination.

2. In low-power mode and VDDOx = 1.8 V, OUTx_AMPL may not be set to 6 or 7.

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Outputs

See the register map portion of this document for additional information about OUTx_FORMAT, OUTx_CM and OUTx_AMPL. Contact

Silicon

above.

6.6 Output Enable/Disable

The Si5348 allows enabling/disabling outputs by either pin, register control, or a combination of both. Three output enable pins are available (OE0b, OE1b, OE2b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0b controls all of the outputs while OE1b and OE2b pins are unmapped and have no affect until configured. The figure below shows an example of a output enable mapping scheme that is register configurable and can be stored in NVM as the default at powerup.

Labs for assistance if you require a factory-programmed device to be configured for any of the output driver settings listed

Si5348

DSPLL

Output

Crosspoint

A C D

÷R

OUT0 OUT0b

OUT1 OUT1b

OUT2 OUT2b

OUT3 OUT3b

OUT4 OUT4b

OUT5 OUT5b

A C D

÷R

OUT6 OUT6b

OE0b

OE1b

OE2b

Figure 6.6. Example 1 Configuring Output Enable Pins

In its default state the OE0b pin enables/disables all outputs. The OE1b and OE2b pins are not mapped and have no effect on outputs.

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Outputs

Si5348

DSPLL

Output

Crosspoint

A C D

÷R

OUT0 OUT0b

OUT1 OUT1b

OE0b

OUT2 OUT2b

OUT3 OUT3b

OE1b

OUT4 OUT4b

DSPLL

A C D

÷R

OUT5 OUT5b

A C D

÷R

Figure 6.7. Example 2 Configuring Output Enable Pins

In this case, OE0b controls the outputs associated with DSPLL A, OE1b controls the outputs for DSPLL C, and OE2b controls the outputs for DSPLL D.

Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s) has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control.

OUT6 OUT6b

OE2b

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6.6.1 Output Disable State Selection

the output driver is disabled, the outputs will drive either logic high or logic low, selectable by the user. The output common mode

When voltage is maintained while the driver is disabled, reducing enable/disable transients.

By contrast, powering down the driver rather than disabling it increases output impedance and shuts off the output common mode voltage. For all output drivers connected in the system, it is recommended to use Disable rather than Powerdown to reduce enable/disable common mode transients. Unused outputs may be left unconnected, powered down to reduce current draw, and, with the corresponding VDDOx, left unconnected.

6.6.2 Output Disable During LOL

By default a DSPLL that is out of lock will generate an output clock. There is an option to disable the outputs when a DSPLL is out of lock (LOL). This option can be useful to force a downstream PLL into holdover.

6.6.3 Output Disable During XAXB_LOS

The internal oscillator circuit, in combination with the external crystal, provides a critical function for the operation of the DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during assertion of the XAXB_LOS alarm.

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Outputs

6.6.4 Output Driver State When Disabled

disabled state of an output driver is configurable as disable low or disable high. When the output driver is disabled, the outputs will

The drive either logic high or logic low, selectable by the user. The output common mode voltage is maintained while the driver is disabled, reducing enable/disable transients. By contrast, powering down the driver rather than disabling it increases output impedance and shuts off the output common mode voltage. For all output drivers connected in the system, it is recommended to use Disable rather than Powerdown to reduce enable/disable common mode transients. Unused outputs may be left unconnected, powered down to reduce current draw, and, with the corresponding VDDOx, left unconnected.

Table 6.13. Output Driver State Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUTALL_DISABLE_LOW 0102[0] Allows disabling all output drivers: 0 - all

outputs disabled, 1 - all outputs controlled by the OUTx_OE bits. Note that if the OEb pin is held high (disabled), then all assigned outputs will be disabled regardless of the state of this register bit.

OUT0_OE

0112[1]

Allows enabling/disabling individual output drivers. Note that the OEb pin must be held

OUT1_OE

OUT2_OE

OUT3_OE

OUT4_OE

OUT5_OE

OUT6_OE

0117[1]

011C[1]

0126[1]

012B[1]

0130[1]

013A[1]

low in order to enable an output with these register bits.

OUT_DIS_MASK_LOL_PLL(D,C,B,A) 0142[3:0] Determines if the outputs are disabled dur-

ing an LOL condition. 0 = outputs disable on LOL, 1 = outputs remain enabled during LOL (default). This option is independently configured for each DSPLL. See DRVx_DIS_SRC registers.

OUT_DIS_MSK_LOSXAXB 0141[6] Determines if outputs are disabled during

an LOSXAXB condition. 0 = all outputs disabled on LOSXAXB (default), 1 = outputs remain enabled during LOSXAXB condition.

OUT0_DIS_STATE

0113[5:4]

Sets the state for the outputs when they are disabled.

OUT1_DIS_STATE

0118[5:4]

OUT2_DIS_STATE

OUT3_DIS_STATE

OUT4_DIS_STATE

OUT5_DIS_STATE

OUT6_DIS_STATE

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011D[5:4]

0127[5:4]

012C[5:4]

0131[5:4]

013B[5:4]

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Outputs

6.6.5 Synchronous Output Enable/Disable Feature

output drivers provide a selectable synchronous enable/disable feature when OUTx_SYNC_EN = 1. Output drivers with this feature

The turned on will wait until a clock period has completed before the driver is disabled or enabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off OUTx_SYNC_EN = 0, the output clock will disable immediately without waiting for the period to complete and will enable immediately without waiting a period to complete. The default state is for the synchronous output disable/enable to be turned on OUTx_SYNC_EN = 1 .

Table 6.14. Synchronous Disable Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

OUT0_SYNC_EN

0113[3]

Selects Synchronous or Asynchronous output disable. 1= synchronous, 0 = asynchro-

OUT1_SYNC_EN

OUT2_SYNC_EN

OUT3_SYNC_EN

OUT4_SYNC_EN

OUT5_SYNC_EN

OUT6_SYNC_EN

0118[3]

011D[3]

0127[3]

012C[3]

0131[3]

013B[3]

nous. Default is asynchronous mode.

6.6.6 Output Driver Disable Source Summary

There

are a number of conditions that may cause the outputs to be automatically disabled. The user may mask out unnecessary disable sources to match the system requirements. Any one of the unmasked sources may cause the outputs to be disabled; this is more powerful but similar in concept to open source “wired-OR” configurations. The table below summarizes the output disable sources with additional information for each source.

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Table 6.15. Output Driver Disable Sources Summary

Si5348 Revision E Reference Manual

Outputs

Output Driver Disa-

ble Source

Disable Outputs

when Source

Individually As-

signable?

Maskable? Related Regis-

ters[Bits]

Si5348

OUTALL_DISA-

Low N N 0102[0] User Controllable

BLE_LOW

OUT0_OE

OUT1_OE

OUT2_OE

OUT3_OE

OUT4_OE

OUT5_OE

OUT6_OE

Low Y N 0112[1]

0117[1]

011C[1]

0126[1]

012B[1]

0130[1]

013A1]

LOL_PLL[D:A] High Y Y 000D[3:0],

0142[3:0]

LOS_XAXB High N Y 000C[1],

0141[6]

Comments

(Hex)

User Controllable

Maskable separately

for each DSPLL

Maskable

SYSINCAL High N N 000C[0] Automatic, not user-

controllable or mask-

able

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6.6.7 Output Buffer Voltage Selection

power supply setting is used to calculate VCM and amplitude levels for the various output logic options. The OUTx_VDD_SEL_EN

The is always enabled and set to a logic 1. The power supply voltages on the VDDOx pins should match the voltage settings used in CBPro. Register values should be updated if any changes are made to the VDDOx voltages.

Table 6.16. Output Driver Voltage Selection

Setting Name Reg Address Descrption

OUT0_VDD_SEL_EN

OUT1_VDD_SEL_EN

OUT2_VDD_SEL_EN

OUT3_VDD_SEL_EN

OUT4_VDD_SEL_EN

OUT5_VDD_SEL_EN

OUT6_VDD_SEL_EN

OUT0_VDD_SEL

OUT1_VDD_SEL

OUT2_VDD_SEL

OUT3_VDD_SEL

OUT4_VDD_SEL

OUT5_VDD_SEL

OUT6_VDD_SEL

0x0115 [3]

0x011A [3]

0x011F [3]

0x0129 [3]

0x012E [3]

0x0133 [3]

0x013D [3]

0x0115 [5:4]

0x011A [5:4]

0x011F [5:4]

0x0129 [5:4]

0x012E [5:4]

0x0133 [5:4]

0x013D [5:4]

These bits are set to 1 and should not be changed.

These bits are set by CBPro to match the expected VDDOx voltage. 0: 3.3V, 1: 1.8V, 2: 2.5V, 3: Reserved.

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Digitally-Controlled Oscillator (DCO) Mode

7. Digitally-Controlled Oscillator (DCO) Mode

The DSPLLs support a DCO mode where their output frequencies are adjustable in pre-defined steps defined by frequency step words (FSTEPW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increments (FINC) or decrements (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO mode is available when the DSPLL is locked. The DCO mode is mainly used in IEEE1588 (PTP) applications where a clock needs to be generated based on recovered timestamps. In this case timestamps are recovered by the PHY/MAC. A processor containing servo software controls the DCO to close the timing loop between the master and slave IEEE1588 nodes. The processor has the option of using the FINC/FDEC pin controls to update the DCO frequency or by controlling it through the serial interface. Note that the maximum FINC/FDEC update rate, by either hardware or software, is 1 MHz. See AN909 for additional details.

Note: DCO mode is not available when in free run or when in holdover. A large freq step can assert LOL on the relevant DSPLL. The step sizes and frequency of operation need to be considered with the LOL settings and BW.

7.1 DCO with Direct Register Writes

In addition to the register-based FINC/FDEC described above, updated values for the DSPLL feedback M divider value may be updated directly by the user. When the M divider numerator (Mx_NUM) and its corresponding update bit (Mx_UPDATE) is written, the new numerator value will take effect and the output frequency will change without any glitches. The M divider numerator and denominator terms (Mx_NUM and Mx_DEN) can be left and right-shifted so that the least significant bit of the numerator word represents the exact step resolution that is needed for your application. Each individual M divider has its own update bit (Mx_UPDATE) that must be written to cause the new numerator value to take effect. All M dividers can be updated at the same time by issuing a Soft Reset.

Changing the DSPLL feedback M divider value while the device is operating will not generate any glitches on affected outputs. The frequency settling to the new value will be determined by the Loop BW of the DSPLL. All other outputs generated by other DSPLLs will be unaffected by this update. It is generally recommended to avoid dynamically changing the M divider denominator (Mx_DEN) as, in some cases, a small output phase shift may be observed when the update becomes active. However, by using the proper combination of settings for the particular frequency plan, it is possible to avoid this entirely. If your application requires dynamic changes to an M divider denominator, contact Silicon Labs at https://www.silabs.com/support/pages/contacttechnicalsupport.aspx.

Table 7.1. Direct DCO Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

M_NUM_PLLA 0x0415–0x041B 56-bit DSPLL feedback M divider Numerator.

M_NUM_PLLC 0x0615–0x061B

M_NUM_PLLD 0x0716–0x071C

M_DEN_PLLA 0x041C–0x041F 32-bit DSPLL feedback M divider Denominator.

M_DEN_PLLC 0x061C–0x061F

M_DEN_PLLD 0x071D–0x0720

M_UPDATE_PLLA 0x0420[0] Must write a 1 to this bit to cause the individual M divider

M_UPDATE_PLLC 0x0620[0]

M_UPDATE_PLLD 0x0721[0]

changes to take effect. Note that a corresponding SOFT_RST_PLLx or device SOFT_RST will also update the M divider values.

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7.2 Frequency Increment/Decrement Using Pin Controls

Si5348 Revision E Reference Manual

Digitally-Controlled Oscillator (DCO) Mode

Controlling

the output frequency with pin controls (FINC/FDEC) is available on the Si5348. This feature involves asserting the FINC or FDEC pins to increment or decrement the DSPLL frequency. The DSPLL selection is done through SPI commands M_FSTEP_MSK_PLLx. A set of mask bits selects the DSPLL(s) that is affected by the frequency change. The frequency step words (FSTEPW) defines the amount of frequency change for each FINC or FDEC. The FSTEPW may be written once or may be changed after every FINC/FDEC assertion. Both the FINC and FDEC inputs are rising-edge-triggered and must meet the minimum pulse width specifications. The FINC and FDEC pins can also be used to trigger a frequency change. Note that both the FINC and FDEC register bits are rising-edge-triggered and self-clearing.

Note: When the FINC/FDEC pins on the Si5348 are unused, the FDEC pin must be pulled down with an external pull-down resistor or jumper. The FINC pin has an internal pull-down and may be left unconnected when not in use.

Si5348

LPF

n_A

DSPLL A

LPF

n_C

DSPLL C

FINC

FDEC

0x001D

FSW_MASK_A

0x0422

FSW_MASK_C

0x0622

Frequency

Step Word

0x0423 – 0x0429

Frequency

Step Word

0x0623 – 0x0629

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CSb

LPF

n_D

DSPLL D

SPI/

FINC

FDEC

FSW_MASK_D

0x0723

Frequency

Step Word

0x0724 – 0x072A

Figure 7.1. Controlling the DCO Mode by Serial Interface

Table 7.2. Frequency Increment/Decrement Control Registers

Setting Name Hex Address [Bit Field] Function

Si5348

FINC 001D[0] Asserting this bit will increase the DSPLL

output frequency by the frequency step word.

FDEC 001D[1] Asserting this bit will decrease the DSPLL

output frequency by the frequency step word.

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Digitally-Controlled Oscillator (DCO) Mode

Setting Name Hex Address [Bit Field] Function

Si5348

M_FSTEPW_PLLA 0423[7:0] - 0429[7:0] This is a 56-bit frequency step word for

M_FSTEPW_PLLC 0623[7:0] - 0629[7:0]

M_FSTEPW_PLLD 0724[7:0] - 072A[7:0]

M_FSTEP_MSK_PLLA 0422[0] This mask bit determines if a FINC or

M_FSTEP_MSK_PLLC 0622[0]

M_FSTEP_MSK_PLLD 0723[0]

Each DSPLL being used in DCO mode should have fractional M division enabled by setting the appropriate M_FRAC_EN_PLLx = 0x3B for proper operation.

Table 7.3. Fractional M Divider Enable Controls

DSPLL A, C, D. The FSTEPW will be added or subtracted to the DSPLL output frequency during assertion of the FINC/FDEC bits or pins. The FSTEPW is calculated based on the frequency configuration and is easily calculated using ClockBuilder Pro utility.

FDEC affects DSPLL A, C, D. 0 = FINC/ FDEC will increment/decrement the FSTEPW to the DSPLL. 1 = Ignores FINC/ FDEC.

Setting Name Hex Address [Bit Field] Function

Si5348

M_FRAC_EN_PLLA 0x0421[5:0] DSPLL feedback M divider fractional enable.

M_FRAC_EN_PLLC 0x0621[5:0]

M_FRAC_EN_PLLD 0x0721[5:0]

0x2B: Integer-only division

0x3B Fractional (or Integer) division

Required for DCO operation.

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Frequency-On-The-Fly for Si5348

8. Frequency-On-The-Fly for Si5348

Some applications require characteristics like input frequency to be modified while leaving clocks from other DSPLLs unaffected. This Frequency-On-The-Fly functionality is fully supported by Si5348 hardware with the help of CBPro Command Line Interface (CLI) tool. Frequency-On-The-Fly allows user to:

• Reconfigure the input frequency, output frequency, bandwidth, and LOL/OOF thresholds of a certain DSPLL. The clock output of the target DSPLL is disabled during the reconfiguration, but the functionalities (for example, freerun, holdover, lock acquisition, hitless switching) remain the same after it is done.

• Leave all other DSPLLs undisturbed, which means that all clock functions, like phase noise and lock status, remain the same.

Detailed explanation on how to set up Frequency-On-The-Fly with CLI tool is included in these two documents: “CBPro Tools & Support for In-System Programming” & “CLI User’s Guide”

Figure 8.1. CBPro Tools & Support for In-System Programming

The following steps outline the procedure to initiate Frequency-On-The-Fly:

1. Create CBPro project as base frequency plan.

Create text files detailing the input/output frequency, bandwidth, and/or LOL/OOF thresholds of new plans. Plans are defined inde-

2. pendently for each PLL.

3. Use CLI FOTF tool (create a batch script) to auto generate register files for switching among different plans.

The CLI FOTF tool optimizes the VCO frequency for all of the plans “CLI User’s Guide” includes more in-depth and detailed syntax explanation and function definition. Example files are bundled in CBPro at C:\Program Files (x86)\Silicon Laboratories\ClockBuilder Pro \CLI\Samples\FOTF-For-Multi-PLL-Device.

For a more detailed information on this procedure, refer to “CBPro Tools & Support for In-System Programming” on the CBPro main page. Note that the frequency plan cannot allow an input to be shared with multiple PLLs. If an input is shared across multiple PLLs an error will be raised. The tool enforces this restriction.

FOTF can technically mean not changing input or output frequencies and instead only reconfiguring one of OOF, LOS or badwidth. A plan file only has to reconfigure *at least one* of the following:

Clock output frequency

Clock input frequency

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Frequency-On-The-Fly for Si5348

DSPLL bandwidth

LOL thresholds

OOF thresholds

multi-DSPLL devices, frequency-on -the-fly can only be performed on a PLL that has exclusive clock inputs. That is, an input to the

On FOTF PLL cannot also be MUXed to another DSPLL. For example, given the following configuration:

8.1 Example

Given the following configuration:

IN0 → DSPLL A

IN1 → DSPLL A

IN2 → DSPLL C

IN2 → DSPLL D

FOTF can be performaed on DSPLL A only in this case. FOTF would not be supported on DSPLL C/D because IN2 is shared between DSPLL C & D. The tool enforces the restriction and will raise an error if FOTF is attempted on PLL C or D in this configuration.

DSPLL B inputs, outputs, bandwidth etc cannot be adjusted on the Si5348 for FOTF.

A 1 Hz output frequency cannot be set in a plan file. It can only be present in the base project. It can however be switched to a non 1Hz output in a plan file.

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Serial Interface

9. Serial Interface

Configuration and operation of the Si5348 is controlled by reading and writing registers using the I2C or SPI serial interface. The I2C_SEL pin selects between I2C or SPI operation. The Si5348 supports communication with either a 3.3 V or 1.8 V host by setting the

IO_VDD_SEL (0x0943[0]) configuration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. See the figure below for supported modes of operation and settings. The I2C pins are open drain and are ESD clamped to 3.3 V, regardless of the host supply level. The I2C pins are clamped to 3.3 V so that they may be externally pulled up to 3.3 V regardless of IO_VDD_SEL

(in register 0x0943).

The table below lists register settings of interest for the I2C/SPI.

SPI 4-Wire SPI 3-Wire

Host = 1.8V

Host = 3.3V

I2C_SEL pin = High

1.8V

SDA

HOST

SCLK

IO_VDD_SEL = 1 IO_VDD_SEL = 1 IO_VDD_SEL = 1

3.3V

SDA

HOST

SCLK

I2C_SEL pin = Low

SPI_3WIRE = 0

IO_VDD_SEL = 0

(Default) (Default)

1.8V

VDDA

1.8V3.3V

VDD

Clock IC

1.8V3.3V

VDD

Clock IC

SPI

HOST

SPI

HOST

CSb

SDO

SDI

SCLK

3.3V

CSb

SDO

SDI

SCLK

1.8V

SDA

SCLK

3.3V

SDA

SCLK

Figure 9.1. I2C/SPI Device Connectivity Configurations

I2C_SEL pin = Low

SPI_3WIRE

IO_VDD_SEL = 0

(Default)

1.8V3.3V

VDD

VDDA

CSb

SDI

SDO

SCLK

Clock IC Clock IC

1.8V3.3V

VDD

VDDA

CSb

SDI

SDO

SCLK

Clock IC

SPI

HOST

SPI

HOST

1.8V

CSb

SDIO

SCLK

3.3V

CSb

SDIO

SCLK

= 1

VDDA

CSb

SDIO SCLK

VDDA

CSb

SDIO SCLK

1.8V3.3V

VDD

1.8V3.3V

VDD

Clock IC

If neither serial interface is used, leave I2C_SEL unconnected. Pull pins SDA/SDIO, SCLK, A1/SDO, and A0/CS all low.

Note that the

Si5348 is not I2C fail-safe upon loss of power. Applications that require fail-safe operation should isolate the device from a

shared I2C bus.

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Serial Interface

Table 9.1. I2C/SPI Register Settings

Setting Name Hex Address [Bit Field] Function

Si5348

IO_VDD_SEL 0x0943[0] The IO_VDD_SEL configuration bit optimizes the VIL, VIH, VOL,

and VOH thresholds to match the VDDS voltage. By default the IO_VDD_SEL bit is set to the VDD option. The serial interface

pins are always 3.3 V tolerant even when the device's VDD pin is supplied from a 1.8 V source. When the I2C or SPI host is operat-

ing at 3.3 V and the Si5348 the IO_VDD_SEL configuration bit to the VDDA option. This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds.

SPI_3WIRE 0x002B[3] The SPI_3WIRE configuration bit selects the option of 4-wire or 3-

wire SPI communication. By default, this configuration bit is set to the 4-wire option. In this mode the mands from a 4-wire or 3- wire SPI host allowing configuration of device registers. For full bidirectional communication in 3-wire mode, the host must write the SPI_3WIRE configuration bit to “1”.

at VDD = 1.8 V, the host must write

Si5348 will accept write com-

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Serial Interface

9.1 I2C Interface

When

in I2C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or

Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in the figure below. Both the SDA and SCL pins must be connected to a supply via

an external pull-up (4.7 kΩ) as recommended by the I2C specification as shown in the figure below. Two address select bits (A0, A1) are provided allowing up to four Si5348 devices to communicate on the same bus. This also allows four choices in the I2C address for systems that may have other overlapping addresses for other I2C devices.

VDDI2C

VDD

I2C_SEL

To I

C Bus

or Host

LSBs of I

Address

Figure 9.2. I2C Configuration

The 7-bit slave device address of the Si5348 shown in the following figure.

Data is transferred MSB first in 8-bit words as specified by the I2C address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9.6 SPI Interface Connections on page 66. A write burst operation is also shown where subsequent data words are written using to an auto-incremented address.

consists of a 5-bit fixed address plus 2 pins which are selectable for the last two bits, as

Slave Address

Figure 9.3. 7-bit I2C Slave Address Bit-Configuration

1 1 0 1 1 A0

SDA

SCLK

Clock IC

0123456

specification. A write command consists of a 7-bit device (slave)

Write Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] PA

Write Operation - Burst (Auto Address Increment)

S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] A Data [7:0] PA

Reg Addr +1

1 – Read

Host

Clock IC

0 – Write A – Acknowledge (SDA LOW)

Host

Clock IC

N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition

Figure 9.4. I2C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in the following figure.

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Read Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

S 1 ASlv Addr [6:0] Data [7:0] PN

Read Operation - Burst (Auto Address Increment)

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

S 1 ASlv Addr [6:0] Data [7:0] A PNData [7:0]

Reg Addr +1

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Serial Interface

Host

Clock IC

1 – Read 0 – Write

Host

Clock IC

A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition

Figure 9.5. I2C Read Operation

The SMBUS interface requires a timeout. The error flags are found in the registers listed below.

Table 9.2. SMBus Timeout Error Bit Indicators

Field]

SMBUS_TIMEOUT 0x000C[5] 1 if there is a SMBus timeout error.

SMBUS_TIME-

OUT_FLG

0x0011[5] 1 if there is a SMBus timeout error.

Function

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Serial Interface

9.2 SPI Interface

in SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit. The 4-

When wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input (SDI), and serial data output (SDO). The 3wire interface combines the SDI and SDO signals into a single bidirectional data pin (SDIO). Both 4-wire and 3-wire interface connections are shown in the following figure.

SPI 3-Wire

SPI_3WIRE = 1

I2C_SEL

SPI 4-Wire

SPI_3WIRE = 0

I2C_SEL

CSb

To SPI

Host

SDI

SDO

To SPI

Host

SDIO

SCLK

Clock IC

Figure 9.6. SPI Interface Connections

Table 9.3. SPI Command Format

Instruction

Set Address 000x xxxx 8-bit Address — —

Write Data 010x xxxx 8-bit Data — —

Ist Byte

2nd Byte 3rd Byte Nth Byte

Clock IC

2,3

Read Data 100x xxxx 8-bit Data — —

Write Data + Address Increment 011x xxxx 8-bit Data — —

Read Data + Address Increment 101x xxxx 8-bit Data — —

Burst Write Data 1110 0000 8-bit Address 8-bit Data 8-bit Data

Note:

X = don’t care (1 or 0).

2. The Burst Write Command is terminated by de-asserting CSb (CSb = high).

3. There is no limit to the number of data bytes that follow the Burst Write Command, but the address will wrap around to zero in the byte after address 255 is written.

Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data” command. The 'Write Data

+ Address Increment' or “Read Data + Address Increment” commands are available for cases where multiple byte operations in sequential address locations is necessary. The “Burst Write Data” instruction provides a compact command format for writing data since it uses a single instruction to define starting address and subsequent data bytes. Figure 9.7 Example Writing Three Data Bytes

using the SPI Write Commands on page 67 shows an example of writing three bytes of data using the write commands. As can be

seen, the “Write Burst Data” command is the most efficient method for writing data to sequential address locations. Figure 9.8 Example

of Reading Three Data Bytes Using the SPI Read Commands on page 67 provides a similar comparison for reading data with the

read commands. Note that there is no equivalent burst read; the read increment function is used in this case.

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‘Set Address’ and ‘Write Data’

‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0]

‘Set Address’ and ‘Write Data + Address Increment’

‘Set Addr’ Addr [7:0] ‘Write Data + Addr Inc’ Data [7:0]

‘Write Data + Addr Inc’ Data [7:0]

‘Burst Write Data’

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Serial Interface

‘Burst Write Data’ Addr [7:0] Data [7:0] Data [7:0] Data [7:0]

Clock ICHost

Figure 9.7. Example Writing Three Data Bytes using the SPI Write Commands

Clock ICHost

‘Set Address’ and ‘Read Data’

‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0]

‘Set Address’ and ‘Read Data + Address Increment’

‘Set Addr’ Addr [7:0] ‘Read Data + Addr Inc’ Data [7:0]

‘Read Data + Addr Inc’ Data [7:0]

Clock ICHost

Figure 9.8. Example of Reading Three Data Bytes Using the SPI Read Commands

The timing diagrams for the SPI commands are shown in Figures Figure

9.10 SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing on page 69, Figure 9.11 SPI “Read Data” and “Read Data + Address Increment” Instruction Timing on page 70, and Figure 9.12 SPI “Burst Data Write” Instruction Timing on page 70.

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Clock ICHost

9.9 SPI “Set Address” Command Timing on page 68, Figure

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Serial Interface

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Set Address’ Command

2 Cycle

Wait

Set Address Instruction Base Address

01234567

>1.9

SCLK

periods

0123456

Command

Clock ICHost

Figure 9.9. SPI “Set Address” Command Timing

Clock ICHost

Don’t Care

High Impedance

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Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Write Data’

2 Cycle

Wait

Write Data instruction

01234567

Data byte @ base address

Data byte @ base address + 1

>1.9

SCLK

periods

01234567

Command

Clock ICHost

Figure 9.10. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing

Clock ICHost

Don’t Care

High Impedance

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Serial Interface

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Read Data’

Command

>1.9

2 Cycle

Wait

Read Data instruction

01234567

Read byte @ base address

+ 1

01234567

SCLK

periods

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

Clock ICHost

Don’t Care

High Impedance

Figure 9.11. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing

‘Burst Data Write’ Command

>1.9

2 Cycle

Wait

Burst Write Instruction Base address

Clock ICHost

01234567

7 7 7

Clock ICHost

Don’t Care

data byte @ base address

0123456 0123456 01234567

0123456 0123456 0123456

High Impedance

data byte @ base address +n

SCLK

periods

Command

Figure 9.12. SPI “Burst Data Write” Instruction Timing

Note that for all SPI communication the chip select (CS) must be high for the minimum time period between commands. When chip select

goes high it indicates the termination of the command. The SCLK can be turned off between commands, particularly if there are

very long delays between commands.

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Recommended Crystals and External Oscillators

10. Recommended Crystals and External Oscillators

10.1 External Reference (XA/XB, REF/REFb)

The external crystal at the XA/XB pins determines jitter performance of the output clocks, and the external reference clock at the REF/ REFb pins determines the frequency accuracy, wander and stability during free-run or holdover modes. Jitter from the external clock on the REF/REFb pins will have little effect on the output jitter performance, depending upon the selected bandwidth.

XTAL + OSC

Determines Output

Jitter Performance

48-54MHz

XTAL

TCXO

XBXA

REFbREF

External Reference

Clock Determines Output Frequency

Accuracy and Stability

OSC

Si5348

Figure 10.1. External Reference Connections

10.1.1 External Crystal (XA/XB)

The

external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLLs. The device includes internal XTAL loading capacitors which eliminate the need for external capacitors and also has the benefit of reduced noise coupling from external sources. A crystal in the range of 48 to 54 MHz is recommended for best jitter performance. Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accommodated. Although not recommended, the device can also accommodate an external clock at the XA/XB pins instead of a crystal. Selection between the external crystal or clock is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in this mode. Chapter 11. Crystal and Device Circuit Layout Recommendations provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. Please see the Jitter Attenuator Recommended Crystal, TCXO and

OCXO Reference Manual for information on how to select a crystal.

48-54 MHz

XTAL

Note: See Pin

Descriptions for

X1/X2 connections

2xC

XB XA

OSC

÷ P

REF

Si5348

Crystal Resonator

Connection

Figure 10.2. Crystal Resonator Connections

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Recommended Crystals and External Oscillators

10.1.2 External Reference (REF/REFb)

external reference at the REF/REFb pins is used to determine output frequency accuracy and stability during free-run and holdover

The modes. This reference is usually from a TCXO or OCXO and can be connected differentially or single-ended as shown in the figure below. Please see the Jitter Attenuator Recommended Crystal, TCXO and OCXO Reference Manual for information on how to select a TCXO or OCXO for the reference.

Standard Differential AC-Coupled Input Buffer

5 – 250 MHz TCXO/OCXO

0.1 uF

REF

100

REFb

5 – 250 MHz TCXO/

OCXO

3.3/2.5/1.8 V LVCMOS

0.1 uF

Si5348

Standard Single-Ended - AC-Coupled Input Buffer

RS matches the CMOS driver to

a 50

ohm transmission line (if

used)

0.1 uF *

0.1 uF

REF

REFb

0.1 uF

When 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 =

ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including

267 C1 = 6 pf may improve the output jitter due to faster input slew rate

at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0

ohm and omit C1, R2 and the capacitor below R2. * This cap

should have less than ~20 ohms of capacitive reactance at the

clock input frequency

Si5348

Figure 10.3. External Reference Connections

10.2 Recommended Crystals and External Oscillators

Please refer to the Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual

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Crystal and Device Circuit Layout Recommendations

11. Crystal and Device Circuit Layout Recommendations

The main layout issues that should be carefully considered include the following:

•

Number and size of the ground vias for the Epad

• Output clock trace routing

• Input clock trace routing

• Control and Status signals to input or output clock trace coupling

• Xtal signal coupling

• Xtal layout

If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to the X1 and X2 pins to provide the best possible performance. The shield should not be connected to the ground plane(s), and the layers underneath should have as little area under the shield as possible. It may be difficult to do this for all the layers, but it is important to do this for the layers that are closest to the shield.

Go to the Silicon Labs Clock Development Tool webpage to obtain Si5348 evaluation board schematics, layouts, and component BOM files.

11.1 64-Pin QFN Si5348 Layout Recommendations

This section details the recommended guidelines for the crystal layout of the 64-pin Si5348 device using an example 8-layer PCB. The following are the descriptions of each of the eight layers.

• Layer 1: device layer, with low speed CMOS control/status signals

• Layer 2: crystal shield

• Layer 3: ground plane

• Layer 4: power distribution

• Layer 5: power routing layer

• Layer 6: input clocks

• Layer 7: output clocks layer

• Layer 8: ground layer

The 64 pin QFN crystal guidelines show the top layer layout of the Si5348 device mounted on the top PCB layer. This particular layout was designed to implement either a crystal or an external oscillator as the XAXB reference. The crystal/ oscillator area is outlined with the white box around it. In this case, the top layer is flooded with ground. Note that this layout has a resistor in series with each pin of the crystal. In typical applications, these resistors should be removed.

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Crystal and Device Circuit Layout Recommendations

11.1.1 Si5348 Crystal Guidelines

The following are five recommended crystal guidelines:

1. Place the crystal as close as possible to the XA/XB pins.

2. DO NOT connect the crystal's GND pins to PCB gnd.

Connect the crystal's GND pins to the DUT's X1 and X2 pins via a local crystal GND shield placed around and under the crystal. See

Figure 11.1 64-pin Si5348 Crystal Layout Recommendations Top Layer (Layer 1) on page 74 at the bottom left for an illustration of

how to create a crystal GND shield by placing vias connecting the top layer traces to the shield layer underneath. Note that a zoom view of the crystal shield layer on the next layer down is shown in Figure 11.2 Zoom View Crystal Shield Layer, Below the Top Layer

(Layer 2) on page 75.

4. Minimize traces adjacent to the crystal/oscillator area especially if they are clocks or frequently toggling digital signals.

5. In general do not route GND, power planes/traces, or locate components on the other side, below the crystal GND shield. As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing, then place the next reference plane in the stack-up at least two layers away or at least 0.05 inches away. The Si5348 should have all layers underneath the ground shield removed if possible.

Figure 11.1. 64-pin Si5348 Crystal Layout Recommendations Top Layer (Layer 1)

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Figure 11.2. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2)

Figure 11.2 Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) on page 75 shows the layer that implements the shield

underneath the crystal. The shield extends underneath the entire crystal and the X1 and X2 pins. This layer also has the clock input pins. The clock input pins go to layer 2 using vias to avoid crosstalk. As soon as the clock inputs are on layer 2, they have a ground shield above, below, and on the sides for protection.

Figure 11.3 Crystal Ground Plane (Layer 3) on page 76 is the ground plane and shows a void underneath the crystal shield. Figure

11.4 Power Plane (Layer 4) on page 77 is a power plane and shows the clock output power supply traces. The void underneath the

crystal shield is continued.

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Crystal and Device Circuit Layout Recommendations

Figure 11.3. Crystal Ground Plane (Layer 3)

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Figure 11.4. Power Plane (Layer 4)

Figure 11.5 Layer 5 Power Routing on Power Plane (Layer 5) on page 78 shows layer 5, which is the power plane with the power

routed to the clock output power pins.

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Figure 11.5. Layer 5 Power Routing on Power Plane (Layer 5)

Figure 11.6 Ground Plane (Layer 6) on page 79 is another ground plane similar to layer 3.

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Figure 11.6. Ground Plane (Layer 6)

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Crystal and Device Circuit Layout Recommendations

11.1.2 Si5348 Output Clocks

11.7 Output Clock Layer (Layer 7) on page 80 shows the output clocks. Similar to the input clocks the output clocks have vias

Figure

that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding between the clock output pairs to avoid crosstalk. There should be a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6.

Figure 11.7. Output Clock Layer (Layer 7)

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Figure 11.8. Bottom Layer Ground Flooded (Layer 8)

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Power Management

12. Power Management

12.1 Power Management Features

Several unused functions can be powered down to minimize power consumption. The registers listed below are used for powering down different features.

Table 12.1. Power-Down Registers

Setting Name Hex Address [Bit Field] Function

Si5348

PDN 0x001E[0] This bit allows powering down the device.

The serial interface remains powered during power down mode and the registers are available to be read and written.

OUT0_PDN

OUT1_PDN

OUT2_PDN

OUT3_PDN

OUT4_PDN

OUT5_PDN

OUT6_PDN

OUT_PDN_ALL 0x0145[0] Power down all output drivers

12.2 Power Supply Recommendations

power supply filtering generally is important for optimal timing performance. The Si5348 devices have multiple stages of on-chip

The regulation to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will further minimize signal degradation from the power supply.

It is recommended to use a 1 μF 0402 ceramic capacitor on each VDD for optimal performance. It is also suggested to include an optional, single 0603 (resistor/ferrite) bead in series with each supply to enable additional filtering if needed.

12.3 Power Supply Sequencing

Four classes of supply voltages exist on the Si5348:

1. VDD = 1.8 V (Core digital supply)

2. VDDA = 3.3 V (Analog supply)

3. VDDOx = 1.8/2.5/3.3 V ± 5% (Clock output supply)

4. VDDS = 1.8/3.3V ± 5% (Digital I/O supply)

0x0112[0]

0x0117[0]

0x011C[0]

0x0126[0]

0x012B[0]

0x0130[0]

0x013A[0]

Powers down unused clock outputs.

There is no requirement for power supply sequencing unless the output clocks are required to be phase aligned with each other. In this case, the VDDO of each clock which needs to be aligned must be powered up before VDD and VDDA. VDDS has no effect on output clock alignment.

If output-to-output alignment is required for applications where it is not possible to properly sequence the power supplies, then the output clocks can be aligned by asserting the SOFT_RST 0x001C[0] or Hard Reset 0x001E[1] register bits or driving the RSTB pin. Note that using a hard reset will reload the register with the contents of the NVM and any unsaved changes will be lost.

One may observe that when powering up the VDD = 1.8 V rail first, that the VDDA = 3.3 V rail will initially follow the 1.8 V rail. Likewise, if the VDDA rail is powered down first then it will not drop far below VDD until VDD itself is powered down. This is due to the pad I/O circuits which have large MOSFET switches to select the local supply from either the VDD or VDDA rails. These devices are relatively large and yield a parasitic diode between VDD and VDDA. Please allow for both VDD and VDDA to power-up and power-down before measuring their respective voltages.

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Power Management

12.4 Grounding Vias

pad on the bottom of the device functions as both the sole electrical ground and primary heat transfer path. Hence it is important to

The minimize the inductance and maximize the heat transfer from this pad to the internal ground plane of the PCB. Use no fewer than 25 vias from the center pad to a ground plane under the device. In general, more vias will perform better. Having the ground plane near the top layer will also help to minimize the via inductance from the device to ground and maximize the heat transfer away from the device.

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13. Register Map

13.1 Base vs. Factory Preprogrammed Devices

The Si5348 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”) versions.

13.2 “Base” Devices (a.k.a. “Blank” Devices)

Example “base” orderable part numbers (OPNs) are of the form “Si5348A-E-GM” or “Si5348B-E-GM”.

Base devices are available for applications where volatile reads and writes are used to program and configure the device for a particular application.

Base devices do not power up in a usable state (all output clocks are disabled).

Base devices are, however, configured by default to use a 48 MHz crystal on the XA/XB reference and a 1.8 V compatible I/O voltage setting for the host I2C/SPI interface.

Additional programming of a base device is mandatory to achieve a usable configuration.

See the on-line lookup utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clockbuilder-lookup.aspx to access the default configuration plan and register settings for any base OPN.

13.3 “Factory Preprogrammed” (Custom OPN) Devices

Factory preprogammed devices use a “custom OPN”, such as Si5348A-E-xxxxx-GM, where xxxxx is a sequence of characters assigned by Silicon Labs for each customer-specific configuration. These characters are referred to as the “OPN ID”. Customers must initiate custom OPN creation using the ClockBuilder Pro software.

Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the XA/XB reference frequency/type, the clock input frequencies, the clock output frequencies, as well as the other options, such as automatic clock selection, loop BW, etc. The ClockBuilder software is required to select among all of these options and to produce a project file which Silicon Labs uses to preprogram all devices with custom orderable part number (“custom OPN”).

Custom OPN devices contain all of the initialization information in their non-volatile memory (NVM) so that it powers up fully configured and ready to go.

Because preprogrammed device applications are inherently quite different from one another, the default power up values of the register settings can be determined using the custom OPN utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clock-

builder-lookup.aspx.

Custom OPN devices include a device top mark which includes the unique OPN ID. Refer to the device data sheet's Ordering Guide and Top Mark sections for more details.

Both “base” and “factory preprogrammed” devices can have their operating configurations changed at any time using volatile reads and writes to the registers. Both types of devices can also have their current register configuration written to the NVM by executing an NVM bank burn sequence (see Section 4.3 NVM Programming.)

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Si5348 Revision E Reference Manual

The Si5348

family parts have large register maps that are divided into separate “Pages” of register banks. This allows more register

addresses than either the I2C or SPI serial interface standards 8-bit addressing provide. Each page has a maximum of 256 addresses, however not all addresses are used on every page. Every register has a maximum data size of 8-bits, or 1 byte. Writing the page number to the 8-bit serial interface address of 0x01 on any page (0x0001, 0x0101, 0x0201, etc.) updates the page selection for subsequent register reads and writes. For example, to access the value in register 0x040E, it is first necessary to write the page value 0x04 to serial interface register address 0x01. At this point, the value of serial interface address 0x0E (0x040E) may be read or written. Note that is it not necessary to write the page select register again when accessing other registers on the same page. Similarly, the read-only DEVICE_READY status is available from every page at serial interface address 0xFE (0x00FE, 0x01FE, 0x02FE, etc.).

It is recommended to use dynamic Read-Modify-Write methods when writing to registers which contain multiple settings, such as register 0x0011. To do this, first read the current contents of the register. Next, update only the select bit or bits that are being modified. This may involve using both logical AND and logical OR operations. Finally, write the updated contents back to the register. Writing to pages, registers, or bits not documented below may cause undesired behavior in the device.

Details of the register and settings information are organized hierarchically below. To find the relevant information for your application, first choose the section corresponding to the base part number, Si5348 for your design. Then, choose the section under that for the page containing the desired register(s).

Default register contents and settings differ for each device part number, or OPN. This information may be found by searching for the Custom OPN for your device using the link below. Both Base/Blank and Custom OPNs are available there. See the previous section on “Base vs. Factory Preprogrammed Devices" for more information on part numbers. The Private Addendum to the datasheet lists the default settings and frequency plan information. You must be logged into the Silicon Labs website to access this information. The Public addendum gives only the general frequency plan information (www.silabs.com/products/clocksoscillators/pages/clockbuilderlook-

up.aspx).

Table 13.1. Register Map Paging Descriptions

Page Start Address (Hex) Start Address (Dec-

Contents

imal)

Page 0 0000h 0 Alarms, interrupts, reset, and other configuration

Page 1 0100h 256 Output clock configuration

Page 2 0200h 512 P and R dividers, user scratch area

Page 3 0300h 768 Internal divider value updates

Page 4 0400h 1024 DSPLLA

Page 5 0500h 1280 DSPLLB

Page 6 0600h 1536 DSPLLC

Page 7 0700h 1792 DSPLLD

Page 9 0900h 2304 Control IO configuration

Page A 0A00h 2560 Internal divider enables

Page B 0B00h 2816 Internal clock disables and control

R = Read Only

R/W = Read Write

S = Self Clearing

self-clearing bit will be cleared by the device once the operation initiated by this bit is complete. Registers with “sticky” flag bits, such

A as LOS0_FLG, are cleared by writing “0” to the bit that has been automatically set high by the device.

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14. Si5348-E Register Map

14.1 Page 0 Registers Si5348

Table 14.1. Register 0x0001 Page

Reg Address Bit Field Type Setting Name Description

0x0001 7:0 R/W PAGE Selects one of 256 possible pages.

The “Page Select” register is located at address 0x01 on every page. When read, it indicates the current page. When written, it will change the page to the value entered. There is a page register at address 0x0001, 0x0101, 0x0201, 0x0301, … etc.

Table 14.2. Register 0x0002-0x0003 Base Part Number

Reg Address Bit Field Type Setting Name Value Description

0x0002 7:0 R PN_BASE 0x48 Four-digit "base" part num-

0x0003 15:8 R PN_BASE 0x53

ber, one nibble per digit.

Example: Si5348A-E-GM. The base part number (OPN) is 5348, which is stored in this register.

Table 14.3. Register 0x0004 Device Grade

Reg Address Bit Field Type Setting Name Description

0x0004 7:0 R GRADE One ASCII character indicating the

device speed/synthesis mode.

0 = A

1 = B

2 = C

3 = D

4 = E

Refer to the device data sheet Ordering Guide section for more information about device grades.

Table 14.4. Register 0x0005 Device Revision

Reg Address Bit Field Type Setting Name Description

0x0005 7:0 R DEVICE_REV One ASCII character indicating the

device revision level.

0 = A; 1 = B, etc.

Example Si5348A-E12345-GM, the device revision is E and stored as

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Table 14.5. Register 0x0006-0x000A NVM Identifier, Pkg ID

Reg Address Bit Field Type Setting Name Description

0x0006 3:0 R SPECIAL ClockBuilder Pro version that was

0x0006 7:4 R REVISION

0x0007 7:0 R MINOR

0x0008 0 R MINOR

0x0008 4:1 R MAJOR

0x0008 7:5 R TOOL

0x0009 7:0 R TEMP_GRADE Device temperature grading

0x000A 7:0 R PKG_ID Package ID

used to generate the NVM image.

Major.Minor.Revision.Special

0 = Industrial (-40 °C to 85 °C) ambient conditions.

0 = 9x9 mm 64 QFN

Part numbers are of the form:

Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>

Examples:

Si5348A-D12345-GM.

Applies

to a factory pre-programmed OPN (Ordering Part Number) device. These devices are factory pre-programmed with the fre-

quency plan and all other operating characteristics defined by the user’s ClockBuilder Pro project file.

Si5348A-D-GM.

Applies to a “base” or “blank” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5348 but

exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro.

Table 14.6. Register 0x000B I2C Address

Reg Address Bit Field Type Setting Name Description

0x000B 6:0 R/W I2C_ADDR 7-bit I2C Address. Note this regis-

ter is not bank burnable.

I2C Base Address Value = 0x6C

Table 14.7. Register 0x000C Internal Status Bits

Reg Address Bit Field Type Setting Name Description

0x000C 0 R SYSINCAL 1 if the device is calibrating.

0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB

pins.

0x000C 3 R XAXB_ERR 1 if there is a problem locking to

the XAXB input signal.

0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout er-

ror.

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Reg Address Bit Field Type Setting Name Description

0x000C 7:6 R LOS_CMOS 01 is a LOS on IN3

10 is a LOS on IN4

11 is a LOS on IN3 and IN4

Bit 1 is the LOS status monitor for the XTAL at the XA/XB pins. Bit 3 is the XAXB problem status monitor and may indicate the XAXB input signal has excessive jitter, ringing, or low amplitude. Bit 5 indicates a timeout error when using SMBUS with the I2C serial port.

Table 14.8. Register 0x000D Loss-of Signal (LOS) Alarms

Reg Address Bit Field Type Setting Name Description

0x000D 3:0 R LOS 1 if the clock input [Ref, 2, 1, 0] is

currently LOS.

0x000D 7:4 R OOF 1 if the clock input [Ref, 2, 1, 0] is

currently OOF.

Note that each bit corresponds to the input. The LOS bits are not sticky.

•

Input 0 (IN0) corresponds to LOS 0x000D [0], OOF 0x000D[4]

• Input 1 (IN1) corresponds to LOS 0x000D [1], OOF 0x000D[5]

• Input 2 (IN2) corresponds to LOS 0x000D [2], OOF 0x000D[6]

• Reference Input (REF) corresponds to LOS 0x000D [3], OOF 0x000D[7]

Table 14.9. Register 0x000E Holdover and LOL Status

Reg Address Bit Field Type Setting Name Description

0x000E 3:0 R LOL_PLL[D:A] 1 if the DSPLL is out of lock.

0x000E 7:4 R HOLD_PLL[D:A] 1 if the DSPLL is in holdover (or

free run).

DSPLL_A corresponds to bit 0,4.

DSPLL_B (Reference) corresponds to bit 1,5.

DSPLL_C corresponds to bit 2,6.

DSPLL_D corresponds to bit 3,7.

Table 14.10. Register 0x000F INCAL Status

Reg Address Bit Field Type Setting Name Description

0x000F 7:4 R CAL_PLL[D:A] 1 if the DSPLL internal calibration

is busy.

DSPLL_A corresponds to bit 4.

DSPLL_B (Reference) corresponds to bit 5.

DSPLL_C corresponds to bit 6.

DSPLL_D corresponds to bit 7.

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Table 14.11. Register 0x0011 Internal Error Flags

Reg Address Bit Field Type Setting Name Description

0x0011 0 R/W SYSINCAL_FLG Sticky version of SYSINCAL. Write

a 0 to this bit to clear.

0x0011 1 R/W LOSXAXB_FLG Sticky version of LOSXAXB. Write

a 0 to this bit to clear.

0x0011 3 R/W XAXB_ERR_FLG Sticky version of XAXB_ERR.

Write a 0 to this bit to clear.

0x0011 5 R/W SMBUS_TIME-

OUT_FLG

Sticky version of SMBUS_TIMEOUT. Write a 0 to this bit to clear.

0x0011 7:6 R/W LOS_CMOS_FLG 01 LOS has been detected on IN3

in the past.

10 LOS has been detected on IN4 in the past.

These are sticky flag versions of 0x000C. They are cleared by writing zero to the bit that has been set.

Table 14.12. Register 0x0012 Sticky OOF and LOS Flags

Reg Address Bit Field Type Setting Name Description

0x0012 3:0 R/W LOS_FLG Sticky version of LOS. Write a 0 to

this bit to clear.

0x0012 7:4 R/W OOF_FLG Sticky version of OOF. Write a 0 to

this bit to clear.

These are sticky flag versions of 0x000D.

•

Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012[4].

• Input 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012[5].

• Input 2 (IN2) corresponds to LOS_FLG 0x0012 [2], OOF_FLG 0x0012[6].

• Reference (REF) corresponds to LOS_FLG 0x0012 [3].

Table 14.13. Register 0x0013 Holdover and LOL Flags

Reg Address Bit Field Type Setting Name Description

0x0013 3:0 R/W LOL_FLG_PLL[D:A] 1 if the DSPLL was unlocked.

0x0013 7:4 R/W HOLD_FLG_PLL[D:A] 1 if the DSPLL was in holdover (or

freerun).

Sticky flag versions of address 0x000E.

DSPLL_A corresponds to bit 0,4.

•

• DSPLL_B (Reference) corresponds to bit 1,5.

• DSPLL_C corresponds to bit 2,6.

• DSPLL_D corresponds to bit 3,7.

Table 14.14. Register 0x0014 INCAL Flags

Reg Address Bit Field Type Setting Name Description

0x0014 7:4 R/W CAL_FLG_PLL[D:A] 1 if the DSPLL internal calibration

was busy.

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These are sticky-flag versions of 0x000F.

DSPLL A corresponds to bit 4

DSPLL B (Reference) corresponds to bit 5

DSPLL C corresponds to bit 6

DSPLL D corresponds to bit 7

Table 14.15. Register 0x0016

Reg Address Bit Field Type Setting Name Description

0x0016 3:0 R/W LOL_ON_HOLD_PLL[

Set by CBPro.

D:A]

Table 14.16. Register 0x0017 Fault Masks

Reg Address Bit Field Type Setting Name Description

0x0017 0 R/W SYSIN-

CAL_INTR_MSK

0x0017 1 R/W LOS-

XAXB_INTR_MSK

0x0017 3 R/W XAXB_ERR_INTR_M

1 to mask SYSINCAL_FLG from causing an interrupt.

1 to mask the LOSXAXB_FLG from causing an interrupt.

1 to mask the XAXB error

0x0017 5 R/W SMB_TMOUT_INTR_

MSK

1 to mask SMBUS_TIMEOUT_FLG from causing an interrupt.

0x0017 7:6 R/W LOS_CMOS_INTR_MSK1 to mask the

LOS_CMOS_INTR_MSK from causing an interrupt.

The interrupt mask bits for the fault flags in register 0x011. If the mask bit is set, the alarm will be blocked from causing an interrupt. The default for this trigger is 0x035.

Table 14.17. Register 0x0018 OOF and LOS Masks

Reg Address Bit Field Type Setting Name Description

0x0018 3:0 R/W LOS_INTR_MSK 1: To mask the clock input LOS

flag.

0x0018 7:4 R/W OOF_INTR_MSK 1: To mask the clock input OOF

flag.

• Input 0 (IN0) corresponds to LOS_IN_INTR_MSK 0x0018[0], OOF_IN_INTR_MSK 0x0018[4]

Input 1 (IN1) corresponds to LOS_IN_INTR_MSK 0x0018[1], OOF_IN_INTR_MSK 0x0018[5]

•

• Input 2 (IN2) corresponds to LOS_IN_INTR_MSK 0x0018[2], OOF_IN_INTR_MSK 0x0018[6]

• Reference (REF) corresponds to LOS_IN_INTR_MSK 0x0018[3] These are the interrupt mask bits for the OOF and LOS flags in register 0x0012. If a mask bit is set, the alarm will be blocked from causing an interrupt.

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Table 14.18. Register 0x0019 Holdover and LOL Masks

Reg Address Bit Field Type Setting Name Description

0x0019 3:0 R/W LOL_INTR_MSK_PLL[

D:A]

0x0019 7:4 R/W HOLD_INTR_MSK_PL

1: To mask the clock input LOL flag.

1: To mask the holdover flag.

L[D:A]

• DSPLL A corresponds to LOL_INTR_MSK_PLL 0x0019[0], HOLD_INTR_MSK_PLL 0x0019[4]

DSPLL B (Reference) corresponds to LOL_INTR_MSK_PLL 0x0019[1]

•

• DSPLL C corresponds to LOL_INTR_MSK_PLL 0x0019[2], HOLD_INTR_MSK_PLL 0x0019[6]

• DSPLL D corresponds to LOL_INTR_MSK_PLL 0x0019[3], HOLD_INTR_MSK_PLL 0x0019[7] These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set, the alarm will be blocked from causing an interrupt.

Table 14.19. Register 0x001A INCAL Masks

Reg Address Bit Field Type Setting Name Description

0x001A 7:4 R/W CAL_INTR_MSK_DSP

LL[D:A]

1: To mask the DSPLL internal calibration busy flag.

DSPLL A corresponds to bit 0

DSPLL B (Reference) corresponds to bit 1

DSPLL C corresponds to bit 2

DSPLL D corresponds to bit 3

Table 14.20. Register 0x001C Soft Reset and Calibration

Reg Address Bit Field Type Setting Name Description

0x001C 0 S SOFT_RST_ALL 0: No effect.

1: Initialize and calibrate the entire device. This will also align the outputs from the four DSPLLs.

The calibration range is ±2000 ppm.

0x001C 1 S SOFT_RST_PLLA 1 initialize and calibrate DSPLLA.

0x001C 2 S SOFT_RST_PLLB 1 initialize and calibrate DSPLLB

(Reference).

0x001C 3 S SOFT_RST_PLLC 1 initialize and calibrate DSPLLC.

0x001C 4 S SOFT_RST_PLLD 1 initialize and calibrate DSPLLD.

These bits are of type “S”, which means self-clearing. Unlike SOFT_RST_ALL, the SOFT_RST_PLLx bits do not update the loop BW values.

If these have changed, the update can be done by writing to BW_UPDATE_PLLA, BW_UPDATE_PLLB, BW_UPDATE_PLLC, and BW_UPDATE_PLLD at addresses 0x0414, 0x514, 0x0614, and 0x0715. Note that unlike the other SOFT_RST_PLLx bits, a SOFT_RST_PLL_B will affect all of the DSPLLs.

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Table 14.21. Register 0x001D FINC, FDEC

Reg Address Bit Field Type Setting Name Description

0x001D 0 S FINC 0: No effect

1: A rising edge will cause an frequency increment.

0x001D 1 S FDEC 0: No effect

1: A rising edge will cause an frequency decrement.

FINC and FDEC will affect the M dividers depending on how their corresponding M_FSTEP_MSK_PLLx bits are programmed.

Table 14.22. Register 0x001E Sync, Power Down and Hard Reset

Reg Address Bit Field Type Setting Name Description

0x001E 0 R/W PDN 1: To put the device into low power

mode.

0x001E 1 R/W HARD_RST 0: No reset.

1: Causes hard reset. The same as power up except that the serial port access is not held at reset.

0x001E 2 S SYNC Resets all output R dividers to the

same state.

Table 14.23. Register 0x002B SPI 3 vs 4 Wire

Reg Address Bit Field Type Setting Name Description

0x002B 3 R/W SPI_3WIRE 0: For 4-wire SPI

1: For 3-wire SPI.

Table 14.24. Register 0x002C LOS Enable

Reg Address Bit Field Type Setting Name Description

0x002C 3:0 R/W LOS_EN 0: For disable.

1: To enable LOS for a clock input.

0x002C 4 R/W LOSXAXB_DIS 0: For disable.

1: To enable LOS for the XAXB input.

• Input 0 (IN0): LOS_EN[0]

• Input 1 (IN1): LOS_EN[1]

• Input 2 (IN2): LOS_EN[2]

• Reference (REF): LOS_EN[3]

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Table 14.25. Register 0x002D Loss of Signal Re-Qualification Value

Reg Address Bit Field Type Setting Name Description

0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0

0: For 2 msec.

1: For 100 msec.

2: For 200 msec.

3: For one second.

0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above.

0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above.

0x002D 7:6 R/W LOS3_VAL_TIME Reference Clock, same as above.

When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME.

Table 14.26. Register 0x002E-0x002F LOS0 Trigger Threshold

Reg Address Bit Field Type Setting Name Description

0x002E 7:0 R/W LOS0_TRG_THR Calculated by CBPro based on val-

0x002F 15:8 R/W LOS0_TRG_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan.

Table 14.27. Register 0x0030-0x0031 LOS1 Trigger Threshold

Reg Address Bit Field Type Setting Name Description

0x0030 7:0 R/W LOS1_TRG_THR Calculated by CBPro based on val-

0x0031 15:8 R/W LOS1_TRG_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan.

Table 14.28. Register 0x0032-0x0033 LOS2 Trigger Threshold

Reg Address Bit Field Type Setting Name Description

0x0032 7:0 R/W LOS2_TRG_THR Calculated by CBPro based on val-

0x0033 15:8 R/W LOS2_TRG_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency plan.

Table 14.29. Register 0x0034-0x0035 LOS3 Trigger Threshold

Reg Address Bit Field Type Setting Name Description

0x0034 7:0 R/W LOS3_TRG_THR Calculated by CBPro based on val-

0x0035 15:8 R/W LOS3_TRG_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register threshold trigger value for the Reference given a particular frequency plan.

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Table 14.30. Register 0x0036-0x0037 LOS0 Clear Threshold

Reg Address Bit Field Type Setting Name Description

0x0036 7:0 R/W LOS0_CLR_THR Calculated by CBPro based on val-

0x0037 15:8 R/W LOS0_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan.

Table 14.31. Register 0x0038-0x0039 LOS1 Clear Threshold

Reg Address Bit Field Type Setting Name Description

0x0038 7:0 R/W LOS1_CLR_THR Calculated by CBPro based on val-

0x0039 15:8 R/W LOS1_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan.

Table 14.32. Register 0x003A-0x003B LOS2 Clear Threshold

ue selected.

Reg Address Bit Field Type Setting Name Description

0x003A 7:0 R/W LOS2_CLR_THR Calculated by CBPro based on val-

0x003B 15:8 R/W LOS2_CLR_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan.

Table 14.33. Register 0x003C-0x003D LOS3 Clear Threshold

Reg Address Bit Field Type Setting Name Description

0x003C 7:0 R/W LOS3_CLR_THR Calculated by CBPro based on val-

0x003D 15:8 R/W LOS3_CLR_THR

ue selected.

ClockBuilder Pro calculates the correct LOS register clear threshold value for the Reference, given a particular frequency plan.

Table 14.34. Register 0x003F OOF Enable

Reg Address Bit Field Type Setting Name Description

0x003F 3:0 R/W OOF_EN 0: To disable.

0x003F 6:4 R/W FAST_OOF_EN

1: To enable.

Table 14.35. Register 0x0040 OOF Reference Select

Reg Address Bit Field Type Setting Name Description

0x0040 2:0 R/W OOF_REF_SEL 0: for IN0

1: for IN1

2: for IN2

3: for Ref

4: for XAXB

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Table 14.36. 0x0041–0x0045 OOF Divider Select

Reg Address Bit Field Type Name Description

0x0041 4:0 R/W OOF0_DIV_SEL CBPro sets these dividers.

0x0042 4:0 R/W OOF1_DIV_SEL

0x0043 4:0 R/W OOF2_DIV_SEL

0x0044 4:0 R/W OOF3_DIV_SEL

0x0045 4:0 R/W OOFXO_DIV_SEL

Table 14.37. Register 0x0046-0x0049 Out of Frequency Set Threshold

Reg Address Bit Field Type Setting Name Description

0x0046 7:0 R/W OOF0_SET_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x0047 7:0 R/W OOF1_SET_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x0048 7:0 R/W OOF2_SET_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x0049 7:0 R/W OOF3_SET_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

Table 14.38. Register0x004A-0x004D Out of Frequency Clear Threshold

Reg Address Bit Field Type Setting Name Description

0x004A 7:0 R/W OOF0_CLR_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x004B 7:0 R/W OOF1_CLR_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x004C 7:0 R/W OOF2_CLR_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

0x004D 7:0 R/W OOF3_CLR_THR OOF Set Threshold. Range is up to

+/-500 ppm in steps of 1/16 ppm.

Table 14.39. Register 0x0050 OOF_ON_LOS

Reg Address Bit Field Type Setting Name Description

0x0050 3:0 R/W OOF_ON_LOS Set by CBPro

Table 14.40. Register 0x0051-0x0053 Fast Out of Frequency Set Threshold

Reg Address Bit Field Type Setting Name Description

0x0051 7:0 R/W FAST_OOF0_SET_THR(1+ value) x 1000 ppm

0x0052 7:0 R/W FAST_OOF1_SET_THR(1+ value) x 1000 ppm

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Reg Address Bit Field Type Setting Name Description

0x0053 7:0 R/W FAST_OOF2_SET_THR(1+ value) x 1000 ppm

0x0054 7:0 R/W FAST_OOF3_SET_THR(1+ value) x 1000 ppm

These registers determine the OOF alarm set threshold for the reference, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers.

Table 14.41. Register 0x0055-0x0058 Fast Out of Frequency Clear Threshold

Reg Address Bit Field Type Setting Name Description

0x0055 7:0 R/W FAST_OOF0_CLR_THR(1+ value) x 1000 ppm

0x0056 7:0 R/W FAST_OOF1_CLR_THR(1+ value) x 1000 ppm

0x0057 7:0 R/W FAST_OOF2_CLR_THR(1+ value) x 1000 ppm

0x0058 7:0 R/W FAST_OOF3_CLR_THR(1+ value) x 1000 ppm

These registers determine the OOF alarm clear threshold for the reference, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers.

OOF needs a frequency reference. ClockBuilder Pro provides the OOF register values for a particular frequency plan.

Table 14.42. Register 0x0059 FAST OOFx_DETWIN_SEL

Reg Address Bit Field Type Setting Name Description

0x0059 1:0 R/W FAST_OOF0_DET-

WIN_SEL

0x0059 2:3 R/W FAST_OOF1_DET-

WIN_SEL

0x0059 4:5 R/W FAST_OOF2_DET-

WIN_SEL

0x0059 6:7 R/W FAST_OOF3_DET-

WIN_SEL

The fast OOF0 detection window selection. Set by CBPro.

The fast OOF1 detection window selection. Set by CBPro

The fast OOF2 detection window selection. Set by CBPro

The fast OOF3 detection window

selection. Set by CBPro

Table 14.43. Register 0x005A-0x006 OOFx_RATIO_REF

Reg Address Bit Field Type Setting Name Description

0x005A 25:0 R/W OOF0_RATIO_REF Set by CBPro.

0x005E 25:0 R/W OOF1_RATIO_REF Set by CBPro.

0x0062 25:0 R/W OOF2_RATIO_REF Set by CBPro.

0x0066 25:0 R/W OOF3_RATIO_REF Set by CBPro.

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Si5348-E Register Map

Table 14.44. Register 0x0092

Reg Address Bit Field Type Setting Name Description

0x0092 0 R/W LOL_FST_EN_PLLA 0: To disable.

1: To enable.

0x0092 1 R/W LOL_FST_EN_PLLB 0: To disable.

1: To enable.

0x0092 2 R/W LOL_FST_EN_PLLC 0: To disable.

1: To enable.

0x0092 3 R/W LOL_FST_EN_PLLD 0: To disable.

1: To enable.

Table 14.45. Register 0x0092 Fast LOL Detection Window Selection

Reg Address Bit Field Type Setting Name Description

0x0093 3:0 R/W LOL_FST_DET-

WIN_SEL_PLLA

0x0093 7:4 R/W LOL_FST_DET-

WIN_SEL_PLLB

0x0094 3:0 R/W LOL_FST_DET-

WIN_SEL_PLLC

0x0094 7:4 R/W LOL_FST_DET-

WIN_SEL_PLLD

Sets detection window for the Fast LOLA.

Sets detection window for the Fast LOLB.

Sets detection window for the Fast LOLC.

Sets detection window for the Fast LOLD.

Table 14.46. Register 0x0095 Fast LOL Detectection Value Selection

Reg Address Bit Field Type Setting Name Description

0x0095 1:0 R/W LOL_FST_VAL-

WIN_SELL_PLLA

0: 1

1: 16

0x0095 3:2 R/W LOL_FST_VAL-

WIN_SELL_PLLB

0x0095 5:4 R/W LOL_FST_VAL-

2:128

3: 1024

WIN_SELL_PLLC

0x0095 7:6 R/W LOL_FST_VAL-

WIN_SELL_PLLD

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Si5348-E Register Map

Table 14.47. Register 0x0096-0x0097 Fast LOL Set Threshold Selection

Reg Address Bit Field Type Setting Name Description

0x0096 3:0 R/W LOL_FST_SET_THR_SE

L_PLLA

0: 0.2 ppm

1: 0.6 ppm

0x0096 7:4 R/W LOL_FST_SET_THR_SE

L_PLLB

0x0097 3:0 R/W LOL_FST_SET_THR_SE

L_PLLC

0x0097 7:4 R/W LOL_FST_SET_THR_SE

L_PLLD

2: 2 ppm

3: 6 ppm

4: 20 ppm

5: 60 ppm

6: 200 ppm

7: 600 ppm

8: 2000 ppm

9: 6000 ppm

10: 20000 ppm

Table 14.48. Register 0x0098-0x0099 Fast LOL Clear Threshold Selection

Reg Address Bit Field Type Setting Name Description

0x0098 3:0 R/W LOL_FST_CLR_THR_S

EL_PLLA

0: 0.2 ppm

1: 0.6 ppm

0x0098 7:4 R/W LOL_FST_CLR_THR_S

EL_PLLB

0x0099 3:0 R/W LOL_FST_CLR_THR_S

EL_PLLC

0x0099 7:4 R/W LOL_FST_CLR_THR_S

EL_PLLD

2: 2 ppm

3: 6 ppm

4: 20 ppm

5: 60 ppm

6: 200 ppm

7: 600 ppm

8: 2000 ppm

9: 6000 ppm

10: 20000 ppm

Table 14.49. Register 0x009A LOL Enable

Reg Address Bit Field Type Setting Name Description

0x009A 3:0 R/W LOL_SLW_EN_PLL[D:A]0: To disable LOL.

1: To enable LOL.

DSPLL A corresponds to bit 0

DSPLL B (Reference) corresponds to bit 1

DSPLL C corresponds to bit 2

DSPLL D corresponds to bit 3

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Si5348-E Register Map

ClockBuilder Pro provides the LOL register values for a particular frequency plan.

Table 14.50. Register 0x009B-0x009C Slow LOL Detection Window Selection

Reg Address Bit Field Type Setting Name Description

0x009B 3:0 R/W LOL_SLW_DET-

WIN_SEL_PLLA

0x009B 7:4 R/W LOL_SLW_DET-

WIN_SEL_PLLB

0x009C 3:0 R/W LOL_SLW_DET-

WIN_SEL_PLLC

0x009C 7:4 R/W LOL_SLW_DET-

WIN_SEL_PLLD

Sets detection window for the Slow LOLA

Sets detection window for the Slow LOLB

Sets detection window for the Slow LOLC

Sets detection window for the Slow LOLD

Table 14.51. Register 0x009D Slow LOL Detection Value Selection

Reg Address Bit Field Type Setting Name Description

0x009D 1:0 R/W LOL_SLW_VAL-

WIN_SEL_PLLA

Sets the number of detection windows in slow LOL validation window.

Set by CBPro.

0x009D 3:2 R/W LOL_SLW_VAL-

WIN_SEL_PLLB

Sets the number of detection windows in slow LOL validation window.

Set by CBPro.

0x009D 5:4 R/W LOL_SLW_VAL-

WIN_SEL_PLLC

Sets the number of detection windows in slow LOL validation window.

Set by CBPro.

0x009D 7:6 R/W LOL_SLW_VAL-

WIN_SEL_PLLD

Sets the number of detection windows in slow LOL validation window.

Set by CBPro.

Table 14.52. Register 0x009E LOL Set Thresholds

Reg Address Bit Field Type Setting Name Description

0x009E 3:0 R/W LOL_SLW_SET_THR

_PLLA

Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,2000

0. Values are in ppm.

0x009E 7:4 R/W LOL_SLW_SET_THR

_PLLB

Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,2000

0. Values are in ppm.

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Si5348-E Register Map

Table 14.53. Register 0x009F LOL Set Thresholds

Reg Address Bit Field Type Setting Name Description

0x009F 3:0 R/W LOL_SLW_SET_THR

_PLLC

0x009F 7:4 R/W LOL_SLW_SET_THR

_PLLD

The following are the thresholds for the value that is placed in the four bits for DSPLLs.

0=0.2 ppm

•

• 1=0.6 ppm

• 2=2 ppm

• 3=6 ppm

• 4=20 ppm

• 5=60 ppm

• 6=200 ppm

• 7=600 ppm

• 8=2000 ppm

• 9=6000 ppm

• 10=20000 ppm

Table 14.54. Register 0x00A0 LOL Clear Thresholds

Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2,6,20,60,200,600,2000,6000,2000

0. Values are in ppm.

Configures the loss of lock set thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000,

20000. Values are in ppm.

Reg Address Bit Field Type Setting Name Description

0x00A0 3:0 R/W LOL_SLW_CLR_THR

_PLLA

Configures the loss of lock clear thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000,

20000.

Values in ppm.

0x00A0 7:4 R/W LOL_SLW_CLR_THR

_PLLB

Configures the loss of lock clear thresholds for the reference. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000, 20000. Values in ppm.

Table 14.55. Register 0x00A1 LOL Clear Thresholds

Reg Address Bit Field Type Setting Name Description

0x00A1 3:0 R/W LOL_SLW_CLR_THR

_PLLC

Configures the loss of lock clear thresholds. Selectable as 0.2, 0.6, 2, 6, 20, 60, 200, 600, 2000, 6000,

20000.

Values in ppm.

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Specifications and Main Features

Frequently Asked Questions

User Manual

1. Work Flow Using ClockBuilder Pro and the Register Map

1.1 Field Programming

2. Family Product Comparison

3. Functional Description

3.1 DSPLL and MultiSynth

3.1.1 Dividers

3.1.2 DSPLL Loop Bandwidth

3.1.2.1 Fastlock Feature

3.1.2.2 Holdover Exit Bandwidth

4. Modes of Operation

4.1 Reset and Initialization

4.2 Dynamic PLL Changes

4.3 NVM Programming

4.4 Free Run Mode

4.5 Lock Acquisition Mode

4.6 Locked Mode

4.7 Holdover Mode

5. Clock Inputs

5.1 Input Source Selection

5.1.1 Manual Input Switching

5.1.2 Automatic Input Switching

5.2 Types of Inputs

5.2.1 Unused Inputs

5.2.2 Hitless Clock Switching with Phase Build Out

5.2.3 Ramped Input Switching

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock

5.2.5 External Clock Switching

5.2.6 Synchronizing to Gapped Input Clocks

5.2.7 Rise Time Considerations

5.3 Fault Monitoring

5.3.1 Input Loss of Signal (LOS) Fault Detection

5.3.2 Out of Frequency (OOF) Fault Detection

5.3.3 Loss of Lock (LOL) Fault Monitoring

5.3.4 Interrupt Pin (INTR)

6. Outputs

6.1 Output Crosspoint Switch

6.2 Output Divider (R) Synchronization

6.3 Support for 1 Hz Output (1 pps)

6.4 Performance Guidelines for Outputs

6.5 Output Signal Format

6.5.1 Output Terminations

6.5.2 Differential Output Swing Modes

6.5.3 Programmable Common Mode Voltage for Differential Outputs

6.5.4 LVCMOS Output Terminations

6.5.5 LVCMOS Output Impedance and Drive Strength Selection

6.5.6 LVCMOS Output Signal Swing

6.5.7 LVCMOS Output Polarity

6.5.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

6.5.9 Setting the Differential Output Driver to Non-Standard Amplitudes

6.6 Output Enable/Disable

6.6.1 Output Disable State Selection

6.6.2 Output Disable During LOL

6.6.3 Output Disable During XAXB_LOS

6.6.4 Output Driver State When Disabled

6.6.5 Synchronous Output Enable/Disable Feature

6.6.6 Output Driver Disable Source Summary

6.6.7 Output Buffer Voltage Selection

7. Digitally-Controlled Oscillator (DCO) Mode

7.1 DCO with Direct Register Writes

7.2 Frequency Increment/Decrement Using Pin Controls

8. Frequency-On-The-Fly for Si5348

8.1 Example

9. Serial Interface

9.1 I2C Interface

9.2 SPI Interface

10. Recommended Crystals and External Oscillators

10.1 External Reference (XA/XB, REF/REFb)

10.1.1 External Crystal (XA/XB)

10.1.2 External Reference (REF/REFb)

10.2 Recommended Crystals and External Oscillators

11. Crystal and Device Circuit Layout Recommendations

11.1 64-Pin QFN Si5348 Layout Recommendations

11.1.1 Si5348 Crystal Guidelines

11.1.2 Si5348 Output Clocks

12. Power Management

12.1 Power Management Features