Silicon Labs Si5347, Si5346 Reference Manual

Si5347, Si5346 Revision D Reference Manual

Quad/Dual DSPLL Any-frequency, Any-output Jitter Attenuators Si5347, Si5346 Family Reference Manual

1. Overview

The Si5347 is a high performance jitter attenuating clock multiplier that integrates four any-frequency DSPLLs for applications that require maximum integration and independent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each DSPLL has

access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on 4th generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance of <100 fs in integer mode or <150 fs in fractional frequency synthesis mode. Each DSPLL supports independent free-run, holdover modes of operation, and offers automatic and hitless input clock switching. The Si5347/46 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up with a known configuration. Programming the Si5347/46 is made easy with Silicon Labs’ ClockBuilder Pro software. Factory preprogrammed devices are available.

1.1 Work Flow Using ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to the applications notes and Knowledge Base articles within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is to enable use of the device without an in-depth understanding of its complexities. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

1.2 Family Product Comparison

The Table 1.1 Device Selector Guide on page 5 lists the differences between the devices in this family.

Table 1.1. Device Selector Guide

Grade PLLs/OUTs Max Output Freq Frequency Synthesis Modes

Si5347A 4/8 712.5 MHz Integer + Fractional

Si5347C 4/4 712.5 MHz Integer + Fractional

Si5346A 2/4 712.5 MHz Integer + Fractional

Si5347B 4/8 350 MHz Integer + Fractional

Si5347D 4/4 350 MHz Integer + Fractional

Si5346B 2/4 350 MHz Integer + Fractional

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Functional Description

2. Functional Description

The Si5347 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) after having been divided down by the P dividers, which are either fractional or integer. Clock selection can be either manual or automatic. Any of the output clocks can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller form factor dual DSPLL version with four inputs and four outputs.

IN0

IN1

IN2

IN3

Si5347

÷FRAC

NVM

C/SPI

Control/

Status

XTAL/

REFCLK

OSC

DSPLL

XTAL/

REFCLK

XBXA

÷INT

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

Si5347C/D

Si5347A/B

÷INT

OUT6

OUT7

IN0

IN1

IN2

IN3

Si5346

÷FRAC

NVM

C/SPI

Control/

Status

OSC

DSPLL

XBXA

÷INT

OUT0

OUT1

OUT2

OUT3

Figure 2.1. Block Diagrams

2.1 DSPLL

DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pdc) al-

The low the DSPLL to perform hitless switching between input clocks (INx). Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference that determines output frequency stability and accuracy while the device is in free-run or holdover mode. A crosspoint switch connects any of the DSPLLs to any of the outputs. An additional integer divisor (R) determines the final output frequency.

The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-volatile memory or RAM. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md) and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined by using the ClockBuilder Pro software.

Because a jitter reference is required for all applications, either a crystal or an external clock source needs to be connected to the XAXB pins. See 9. XAXB External References and 10. Crystal and Device Circuit Layout Recommendations for more information.

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Functional Description

2.2 DSPLL Loop Bandwidth

DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-

The tings of from 0.1 Hz up to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally, each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. Note that after changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414, 0x0514, 0x0614, 0x0715) must be set high to latch the new values into operation. Note that each of these update bits will latch both nominal and fastlock bandwidths.

Table 2.1. DSPLL Loop Bandwidth Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

BW_PLLA 0408[7:0] -

040D[7:0]

BW_PLLB 0508[7:0] -

050D[7:0]

BW_PLLC 0608[7:0] -

0408[7:0] -

040D[7:0]

0508[7:0] -

050D[7:0]

—

This group of registers determine the loop bandwidth for DSPLL A, B, C, D. They are all independently selectable in the range from 0.1 Hz up to 4 kHz. Register values determined by ClockBuilderPro.

060D[7:0]

BW_PLLD 0709[7:0] -

—

070E[7:0]

2.2.1 Fastlock

Selecting

a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range from 100 Hz up to 4 kHz are available for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The fastlock feature can be enabled or disabled independently for each of the DSPLLs. If enabled, when LOL is asserted, Fastlock is enabled. When LOL is not asserted, Fastlock is disabled. Note that after changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x0414, 0x0514, 0x0614, 0x0715) must be set high to latch the new values into operation. Note that each of these update bits will latch all Loop, Fastlock and Holdover bandwidths.

Table 2.2. Fastlock Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

FASTLOCK_AUTO_EN_PLLA 042B[0] 042B[0] Fastlock enable/disable. Fastlock is enabled by default

FASTLOCK_AUTO_EN_PLLB 052B[0] 052B[0]

with a bandwidth of 4 kHz.

FASTLOCK_AUTO_EN_PLLC 062B[0] —

FASTLOCK_AUTO_EN_PLLD 072C[0] —

FAST_BW_PLLA 040E[7:0] -

0413[7:0]

FAST_BW_PLLB 050E[7:0] -

0513[7:0]

FAST_BW_PLLC 060E[7:0] -

040E[7:0] -

0413[7:0]

050E[7:0] -

0513[7:0]

—

Fastlock bandwidth is selectable in the range of 100 Hz up to 4 kHz. Register values determined using ClockBuilderPro.

0613[7:0]

FAST_BW_PLLD 070F[7:0] -

—

0714[7:0]

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Functional Description

2.3 Dividers Overview

are five main divider classes within the Si5347/46. See Figure 2.1 Block Diagrams on page 6 for a block diagram that shows

There them. Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See 6. Digitally Controlled Oscillator

(DCO) Mode for more information and block diagrams on DCO mode.

• 1. PXAXB: Reference input divider (0x0206)

• Divide reference clock by 1, 2, 4, or 8 to obtain an internal reference < 125 MHz

• 2. P0-P3: Input clock wide range dividers (0x0208-0x022F)

• Integer or Fractional divide values

•

Min. value is 1, Max. value is 224 (Fractional-P divisors must be > 5)

• 48-bit numerator, 32-bit denominator

• Practical P divider range of (Fin / 2 MHz) < P < (Fin / 8 kHz)

• Each P divider has a separate update bit for the new divider value to take effect

• 3. MA-MD: DSPLL feedback dividers (0x0415-0x041F, 0x0515-0x051F, 0x0615-0x061F, 0x0716-0x0720)

• Integer or Fractional divide values

•

Min. value is 1, Max. value is 224 (Fractional-M divisors must be > 10)

• 56-bit numerator, 32-bit denominator

• Practical M divider range of (Fdco / 2 MHz) < M < (Fdco / 8 kHz)

• Each M divider has a separate update bit for the new divider value to take effect

• Soft reset will also update M divider values

• 4. Output N dividers N0-N3(0x0302-0x032D)

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

• 5. R0-R7: Output dividers (0x024A-0x026A)

• 24-bit field

•

Min. value is 2, Max. value is 225-2

• Only even integer divide values: 2, 4, 6, etc.

• R Divisor = 2 x (Field + 1). For example, Field = 3 gives an R divisor of 8

• FSTEPW: DSPLL DCO step words (0x0423-0x0429, 0x0523-0x0529, 0x0623-0x0629, 0x0724-0x072A)

• Positive Integers, where FINC/FDEC select direction

•

Min. value is 0, Max. value is 2

• 56-bit step size, relative to 32-bit M denominator

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Modes of Operation

3. Modes of Operation

Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation

on page 9. The following sections describe each of these modes in greater detail.

Power-Up

Reset and

Initialization

Is holdover

history valid?

No valid

input clocks

selected

An input is qualified

and available

selection

Holdover

Mode

Yes

Selected input

clock fails

Figure 3.1. Modes of Operation

for

Free-run

Valid input clock

Lock Acquisition

(Fast Lock)

Locked

Mode

selected

Phase lock on selected input

clock is achieved

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Modes of Operation

3.1 Reset and Initialization

power is applied, the device begins an initialization period where it downloads default register values and configuration data from

Once NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all DSPLLs, while a soft reset can affect all or each DSPLL individually.

Table 3.1. Reset Control Registers

Setting Name Hex Address

Function

[Bit Field]

Si5347 Si5346

HARD_RST 001E[1] 001E[1] Performs the same function as power cycling the device. All registers

will be restored to their default values.

SOFT_RST_ALL 001C[0] 001C[0] Resets the device without re-downloading the register configuration

from NVM.

SOFT_RST_PLLA 001C[1] 001C[1] Performs a soft reset on DSPLL A only.

SOFT_RST_PLLB 001C[2] 001C[2] Performs a soft reset on DSPLL B only.

SOFT_RST_PLLC 001C[3] — Performs a soft reset on DSPLL C only.

SOFT_RST_PLLD 001C[4] — Performs a soft reset on DSPLL D only.

Power-Up

NVM download

Initialization

Hard Reset

bit asserted

Soft Reset

bit asserted

RST

pin asserted

Serial interface

ready

Figure 3.2. Initialization from Hard Reset and Soft Reset

The Si547/46 is fully configurable using the serial interface (I2C

or SPI). At power up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins. Neither VDDOx or VDDS supplies are required to write the NVM.

3.1.1 Updating Registers during Device Operation

ClockBuilder Pro generates all necessary control register writes to update settings for the entire device, including the ones described below. This is the case for both “Export” generated files as well as when using the GUI. This is sufficient to cover most applications. However, in some applications it is desirable to modify only certain sections of the device while maintaining unaffected clocks on the remaining outputs. If this is the case CBPro provides some frequency changes on the fly examples.

If certain registers are changed while the device is in operation, it is possible for the PLL to become unresponsive (i.e. lose lock indefinitely). Additionally, making single frequency step changes greater than ±350 ppm, either by using the DCO or by directly updating the M dividers, may also cause the PLL to become unresponsive. Changes to the following registers require this special sequence of writes:

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Modes of Operation

Control Register(s)

PXAXB 0x0206[1:0]

MXAXB_NUM 0x0235 – 0x023A

MXAXB_DEN 0x023B – 0x023E

PLL lockup can easily be avoided by using the following the preamble and postamble write sequence below when one of these regis-

is modified or large frequency steps are made. Clockbuilder Pro software adds these writes to the output file by default when Ex-

ters porting Register Files.

3.1.1.1 Dynamic PLL Changes

To start, write the preamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC0

0x0B25 0x00

0x0B4E 0x1A

Wait 300 ms for the device state to stabilize.

Then, modify all desired control registers.

Write 0x01 to Register 0x001C (SOFT_RST_ALL) to perform a Soft Reset once modifications are complete.

Write the postamble by updating the following control bits using Read/Modify/Write sequences:

Address Value

0x0B24 0xC3

0x0B25 0x02

Note, however, that this procedure affects all DSPLLs and outputs on the device.

Note: This

programming sequence applies only to Rev D and later revisions. The preamble and postamble values for updating certain registers during device operation are different for earlier revisions. Either the new or old values below may be written to revision D or later devices without issue. No system software changes are necessary for legacy systems. When writing old values, note that reading back these registers will not give the written old values, but will reflect the new values. Silicon Labs recommends using the new values for all revision D (described above) and later designs, since the write and read values will match. Please contact Silicon Labs if you need information about an earlier revision. Please always ensure to use the correct sequence for the correct revision of the device. Also check for the latest information online. This information is updated from time to time. The latest information is always posted online.

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3.1.2 NVM Programming

Si5347, Si5346 Revision D Reference Manual

Modes of Operation

Devices

have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Active NVM BANK Value (Deci-

Number of User Banks Burned Number of User Banks Available to Burn

mal)

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:

VDD and VDDA power must both be stable throughout the process.

•

• No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01. DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed. Verify device operation before writing registers to NVM.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Poll DEVICE_READY until DEVICE_READY=0x0F.

5. Set NVM_READ_BANK 0x00E4[0]=1. This will load the NVM contents into non-volatile memory.

6. Poll DEVICE_READY until DEVICE_READY=0x0F.

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 3.2. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

Warning:

Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the PAGE register.

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Modes of Operation

3.2 Free Run Mode

power is applied to the Si5347 and initialization is complete, all DSPLLs will automatically enter freerun mode, generating the

Once frequencies determined by the NVM. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes.

3.3 Lock Acquisition Mode

Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchronization, a DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

3.4 Locked Mode

Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOL pin and status bit to indicate when lock is achieved. See 4.3.4 LOL Detection for more details on the operation of the loss of lock circuit.

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Modes of Operation

3.5 Holdover Mode

of the DSPLLs programmed for holdover mode automatically enter holdover when the selected input clock becomes invalid (i.e.

Any when either OOF or LOS are asserted) and no other valid input clocks are available for selection. Each DSPLL calculates a historical average of the input frequency while in locked mode to minimize the initial frequency offset when entering the holdover mode.

The averaging circuit for each DSPLL stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window with the stored historical frequency data. The window size determines the amount of holdover frequency averaging. The delay value is used to ignore frequency data that may be corrupt just before the input clock failure. Both the window size and the delay are programmable as shown in the figure below. Each DSPLL computes its own holdover frequency average to maintain complete holdover independence between the DSPLLs.

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

Time

120s

Programmable historical data window

to determine the final holdover value

used

1s,10s, 30s, 60s

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

Figure 3.3. Programmable Holdover Window

When entering holdover, a DSPLL will pull its output clock frequency to the calculated average holdover frequency. While in holdover,

output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If a

the clock input becomes valid, a DSPLL will automatically exit holdover mode and re-acquire lock to the new input clock. This process involves adjusting the output clock to achieve frequency and phase lock with the new input clock.

The recommended holdover exit mode is a frequency ramp. Just before the exit begins, the difference between the current holdover output frequency and the desired, new output frequency is measured. It is likely that the new output clock frequency and the holdover output frequency will not be the same - the new input clock frequency might have changed and/or the holdover history circuit may have changed the holdover output frequency.

Using the calculated frequency difference (holdover v. new frequency) and the user-selectable ramp rate a ramp time is calculated. The output ramp rate is then applied for this ramp time ensuring a smooth and linear transition between the holdover and the final desired frequency. The ramp rate can be very slow (0.2 ppm/s), very fast (40,000 ppm/s) or any of about 40 values in between. The loop BW values do not limit or affect the ramp rate selections (and vice versa). CBPro defaults to ramped exit from holdover.

Note that the same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped clock switching, see 4.2.2 Ramped Input Switching.

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Modes of Operation

Table 3.3. DSPLL Holdover Control and Status Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

Holdover Status

HOLD_PLL(D,C,B,A) 000E[7:4] 000E[5:4] Holdover status indicator. Indicates when a DSPLL is in

holdover or free-run mode and is not synchronized to the input reference. The DSPLL goes into holdover only when the historical frequency data is valid, otherwise the DSPLL will be in free-run mode.

HOLD_FLG_PLL(D,C,B,A) 0013[7:4] 0013[5:4] Holdover status monitor sticky bits. Sticky bits will re-

main asserted when an holdover event occurs until cleared. Writing a zero to a sticky bit will clear it.

HOLD_HIST_VALID_PLLA 043F[1] 043F[1] Holdover historical frequency data valid. Indicates if

HOLD_HIST_VALID_PLLB 053F[1] 053F[1]

HOLD_HIST_VALID_PLLC 063F[1] —

there is enough historical frequency data collected for valid holdover value.

HOLD_HIST_VALID_PLLD 0740[1] —

Holdover Control and Settings

HOLD_HIST_LEN_PLLA 042E[4:0] 042E[4:0] Window Length time for historical average frequency

HOLD_HIST_LEN_PLLB 052E[4:0] 052E[4:0]

used in Holdover mode. Window Length in seconds (s): Window Length = ((2

LEN

) – 1)*268nsec

HOLD_HIST_LEN_PLLC 062E[4:0] —

HOLD_HIST_LEN_PLLD 072F[4:0] —

HOLD_HIST_DELAY_PLLA 042F[4:0] 042F[4:0] Delay Time to ignore data for historical average frequen-

HOLD_HIST_DELAY_PLLB 052F[4:0] 052F[4:0]

cy in Holdover mode. Delay Time in seconds (s): Delay Time = (2

DELAY

) x268nsec

HOLD_HIST_DELAY_PLLC 062F[4:0] —

HOLD_HIST_DELAY_PLLD 0730[4:0] —

FORCE_HOLD_PLLA 0435[0] 0435[0] These bits allow forcing any of the DSPLLs into hold-

FORCE_HOLD_PLLB 0535[0] 0535[0]

over

FORCE_HOLD_PLLC 0635[0] —

FORCE_HOLD_PLLD 0736[0] —

HOLD_EXIT_BW_SEL1_PLLA 042C[4] 042C[4] Selects the exit from holdover bandwidth. Options are:

HOLD_EXIT_BW_SEL1_PLLB 052C[4] 052C[4]

0: Exit of holdover using the fastlock bandwidth

HOLD_EXIT_BW_SEL1_PLLC 062C[4] —

1: Exit of holdover using the DSPLL loop bandwidth

HOLD_EXIT_BW_SEL1_PLLD 072D[4] —

HOLD_EXIT_BW_SEL0_PLLA 049B[6] 049B[6]

HOLD_EXIT_BW_SEL0_PLLB 059B[6] 059B[6]

HOLD_EXIT_BW_SEL0_PLLC 069B[6] —

HOLD_EXIT_BW_SEL0_PLLD 079B[6] —

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Modes of Operation

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

HOLD_RAMP_EN_PLLA 042C[3] 042C[3] Must be set to 1 for normal operation.

HOLD_RAMP_EN_PLLB 052C[3] 052C[3]

HOLD_RAMP_EN_PLLC 062C[3] —

HOLD_RAMP_EN_PLLD 072D[3] —

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Clock Inputs

4. Clock Inputs

There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both standard format inputs and low duty cycle pulsed CMOS clocks. The input P dividers can be either fractional or integer. A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs as shown in Figure 4.1 DSPLL Input Selection Crosspoint on page 17.

Si5347

Input

Crosspoint

IN0

IN1

IN2

IN3

0 1 2 3

Figure 4.1. DSPLL Input Selection Crosspoint

DSPLL

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Clock Inputs

4.1 Input Source Selection

source selection for each of the DSPLLs can be made manually through register control or automatically using an internal state

Input machine.

Table 4.1. Manual or Automatic Input Clock Selection Control Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

CLK_SWITCH_MODE_PLLA 0436[1:0] 0436[1:0] Selects manual or automatic switching mode for DSPLL

CLK_SWITCH_MODE_PLLB 0536[1:0] 0536[1:0]

CLK_SWITCH_MODE_PLLC 0636[1:0] —

CLK_SWITCH_MODE_PLLD 0737[1:0] —

In manual mode the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will automatically enter holdover mode if the holdover history is valid or Freerun if it is not.

A, B, C, D.

0: For manual

1: For automatic, non-revertive

2: For automatic, revertive

3: Reserved

Table 4.2. Manual Input Select Control Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

IN_SEL_PLLA 042A[2:0] 042A[2:0] Selects the clock input used to synchronize DSPLL A, B,

IN_SEL_PLLB 052A[3:1] 052A[3:1]

IN_SEL_PLLC 062A[2:0] —

C, or D. Selections are: IN0, IN1, IN2, IN3, corresponding to the values 0, 1, 2, and 3. Selections 4–7 are reserved.

IN_SEL_PLLD 072B[2:0] —

Automatic input switching is available in addition to the manual selection described previously. In automatic mode, the switching criteria is

based on input clock qualification, input priority and the revertive option. The IN_SEL_PLLx register bits are not used in automatic input switching. Also, only input clocks that are valid (i.e., with no active fault indicators) can be selected by the automatic clock switching. If there are no valid input clocks available, the DSPLL will enter Holdover or Freerun mode. With Revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With Non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid, an automatic switchover to the highest priority valid input will be initiated.

Table 4.3. Automatic Input Select Control Registers

Setting Name Hex Address Function

Si5347 Si5346

IN(3,2,1,0)_PRIORITY_PLLA 0x0438–0x0439 0x0438–0x0439 Selects the automatic selection priority for [IN3, IN2,

IN(3,2,1,0)_PRIORITY_PLLB 0x0538–0x0539 0x0538–0x0539

IN(3,2,1,0)_PRIORITY_PLLC 0x0638–0x0639 —

IN1, IN0] for each DSPLL A, B, C, D. Selections are: 1st, 2nd, 3rd, 4th, or never select. Default is IN0=1st, IN1=2nd, IN2=3rd, IN3=4th.

IN(3,2,1,0)_PRIORITY_PLLD 0x0739–0x073A —

IN(3,2,1,0)_LOS_MSK_PLLA 0x0437 0x0437 Determines if the LOS status for [IN3, IN2, IN1, IN0] is

IN(3,2,1,0)_LOS_MSK_PLLB 0x0537 0x0537

IN(3,2,1,0)_LOS_MSK_PLLC 0x0637 —

used in determining a valid clock for the automatic input selection state machine for DSPLL A, B, C, D. Default is LOS is enabled (un-masked).

IN(3,2,1,0)_LOS_MSK_PLLD 0x0738 —

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Clock Inputs

Setting Name Hex Address Function

Si5347 Si5346

IN(3,2,1,0)_OOF_MSK_PLLA 0x0437 0x0437 Determines if the OOF status for [IN3, IN2, IN1, IN0] is

IN(3,2,1,0)_OOF_MSK_PLLB 0x0537 0x0537

IN(3,2,1,0)_OOF_MSK_PLLC 0x0637 —

IN(3,2,1,0)_OOF_MSK_PLLD 0x0738 —

used in determining a valid clock for the automatic input selection state machine for DSPLL A, B, C, D. Default is OOF enabled (un-masked).

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Clock Inputs

4.2 Types of Inputs

of the four different inputs IN0-IN3 can be configured as standard LVDS, LVPECL, HCL, CML, and single-ended LVCMOS for-

Each mats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled and use the “Standard” Input Buffer selection as these pins are internally dc-biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals having a duty cycle much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown below in Figure 4.2 Input Termination for Standard and Pulsed CMOS Inputs on page 20. The resistor divider values given below will work with up to 1 MHz pulsed inputs. In general, following the “Standard AC Coupled Single Ended” arrangement shown below will give superior jitter performance.

Standard AC-Coupled Differential (IN0-IN3)

0.1uF *

100

LVDS, LVPECL, CML

* These caps should have < ~5 ohms capacitive reactance at the

0.1uF *

lock input frequency.

Standard AC-Coupled Single-Ended (IN0-IN3)

INx

INxb

Standard

Pulsed CMOS

3.3/2.5/1.8V LVCMOS

RS matches the CMOS driver to a 50 ohm

transmission line (if

used)

0.1uF *

0.1uF

INx

INxb

Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267

ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf

may improve the output jitter due to faster input slew rate at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1, and R2 should be physically placed

as close as practicle to the device input pins. *This cap should have less than

~20 ohms of capacitive reactance at the clock input frequency

DC-Coupled Pulsed CMOS only for Frequencies

< 1MHz (IN0-IN3)

RS matches the CMOS driver to a 50 ohm

3.3V, 2.5V, 1.8V

transmission

LVCMOS

line (if used)

INx

INxb

Standard

Pulsed CMOS

Standard

Pulsed CMOS

Note: See Datasheet for input clock specifications

Figure 4.2. Input Termination for Standard and Pulsed CMOS Inputs

Floating clock inputs are noise sensitive. Add a cap to ground for all non-CMOS unused clock inputs. Input clock buffers are enabled by setting

the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as shown in Figure 4.2 Input Termination for

Standard and Pulsed CMOS Inputs on page 20, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is

not necessary to connect the inverting INx input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.

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Clock Inputs

Table 4.4. Input Clock Control and Configuration Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

IN_EN 0x0949[3:0] 0x0949[3:0] Enable each of the input clock buffers for IN3 through

IN0.

IN_PULSED_CMOS_EN 0x0949[7:4] 0x0949[7:4] Enable Pulsed CMOS mode for each input IN3 through

IN0.

4.2.1 Hitless Input Switching with Phase Buildout

buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between

Phase two clock inputs with the exact same frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a nonzero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. The phase buildout feature can be enabled on a per DPSLL basis. It supports a minimum input frequency of 8 kHz, but if a fractional P input divider is used, the input frequency must be 300 MHz or higher in order to ensure proper operation.

Table 4.5. DSPLL Phase Buildout Switching Control Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

HSW_EN_PLLA 0436[2] 0436[2] Phase Buildout Switching Enable/Disable for DSPLL A,

HSW_EN_PLLB 0536[2] 0536[2]

B, C, D. Phase Buildout Switching is enabled by default.

HSW_EN_PLLC 0636[2] —

HSW_EN_PLLD 0737[2] —

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Clock Inputs

4.2.2 Ramped Input Switching

switching between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be ena-

If bled to ensure a smooth transition between the two inputs. In this situation, it is also advisable to enable phase buildout to minimize the input-to-output clock skew after the clock switch ramp has completed.

When ramped clock switching is enabled, the Si5347/46 will very briefly go into holdover and then immediately exit from holdover. This means that ramped switching will behave the same as an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency because the transition between the two frequencies will be smooth and linear. Ramped switching should be turned off when switching between input clocks that are always frequency locked (i.e. are the same exact frequency). Because ramped switching avoids frequency transients and overshoot when switching between clocks that are not the same frequency, CBPro defaults to ramped clock switching. The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see section 3.5 Holdover Mode.

Table 4.6. Ramped Input Switching Control Registers

Setting Name Hex Address [Bit Field] Function

RAMP_SWITCH_EN_PLLA 0x04A6[3] Enable frequency ramping on an input switch

RAMP_SWITCH_EN_PLLB 0x05A6[3]

RAMP_SWITCH_EN_PLLC 0x06A6[3]

RAMP_SWITCH_EN_PLLD 0x07A6[3]

HSW_MODE_PLLA 0x043A[1:0] Input switching mode select

HSW_MODE_PLLB 0x053A[1:0]

HSW_MODE_PLLC 0x063A[1:0]

HSW_MODE_PLLD 0x073A[1:0]

4.2.3 Hitless Switching, LOL (loss of lock) and Fastlock

When

doing a clock switch between clock inputs that are frequency locked, LOL might momentarily be asserted. If so programmed, the assertion of LOL will invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter parameters into the DSPLL’s closed loop, there may be transients at the clock outputs when Fastlock is either entered or exited. For this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN at 0x52B[0] whenever a clock switch might occur. For more details on hitless switching please refer to AN1057: Hitless Switching using Si534x/8x Devices.

4.2.4 External Clock Switching

External clock switches should be avoided because the Si5347/6 has no way of knowing when a clock switch will or has occurred. Because of this, neither the phase buildout engine or the ramp logic can be used. If expansion beyond the four clock inputs is an important issue, please see AN1111: Si534x/8x Input Clock Expander which describes how an external FPGA can be used for this purpose.

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Clock Inputs

4.2.5 Synchronizing to Gapped Input Clocks

DSPLL supports locking to a gapped input clock with missing clock edges. The purpose of gapped clocking is to modulate the

The frequency of a periodic clock by selectively removing some of its edges. Gapping a clock significantly increases its jitter so a phaselocked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transient, when the switch occurs during a gap in either input clocks. Figure 4.3 Gapped Input Clock Use on page 23 shows a 100 MHz clock with one cycle removed every 10 cycles that results in a 90 MHz periodic non-gapped output clock.

Gapped Input Clock Periodic Output Clock

100 MHz clock

1 missing period

every 10

100 ns 100 ns

90 MHz non-gapped clock

DSPLL

1 2 3 4 5 6 7 8 9 10

10 ns

Period Removed

1 2 3 4 5 6 7 8 9

11.11111... ns

Figure 4.3. Gapped Input Clock Use

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Clock Inputs

4.2.6 Rise Time Considerations

is well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of

It the Si5347/46 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase. The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input. The figure shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values.

IN_X Slew Rate in Differential Mode

4.5

3.5

2.5

Relateive Jitter

1.5

TYP

0.5

0 100 200 300 400 500 600

Input Slew (V/us)

Figure 4.4. Effect of Low Slew Rate on RMS Jitter

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Clock Inputs

4.3 Fault Monitoring

four input clocks (IN0, IN1, IN2, IN3) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in Figure 4.5 Fault

All

Monitors on page 25. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the

DSPLLs. Each of the DSPLLs also has a Loss Of Lock (LOL) indicator which is asserted when synchronization is lost with their selected input clock.

Si5347

OSC

LOS

DSPLL A

LOL

LPF

÷M

IN0

IN1

LOS

OOF

Precision

Fast

Precision

Fast

LOL

DSPLL B

LPF

÷M

IN2

IN3

LOS

OOF

Precision

Fast

Precision

Fast

LOL

DSPLL C

LPF

÷M

DSPLL D

LPF

÷M

Figure 4.5. Fault Monitors

4.3.1 Input Loss of Signal (LOS) Detection

The

loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register, when set, always stays asserted until cleared.

Monitor

LOS

Live

LOS

Sticky

Figure 4.6. LOS Status Indicator

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Clock Inputs

4.3.2 XA/XB LOS Detection

LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when

A XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is detected.

Table 4.7. LOS Status Monitor Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

LOS Status Indicators

LOS(3,2,1,0) 000D[3:0] 000D[3:0] LOS status monitor for IN3, IN2, IN1, IN0. Indicates if a

valid clock is detected or if a LOS condition is present.

LOSXAXB 000C[1] 000C[1] LOS status monitor for the XTAL or REFCLK at the

XA/XB pins.

LOS(3,2,1,0)_FLG 0012[3:0] 0012[3:0] LOS status monitor sticky bits for IN3, IN2, IN1, IN0.

Sticky bits will remain asserted when an LOS event occurs until they are cleared. Writing a zero to a sticky bit will clear it.

LOSXAXB_FLG 0011[1] 0011[1] LOS status monitor sticky bits for XAXB. Sticky bits will

remain asserted when an LOS event occurs until cleared. Writing a zero to a sticky bit will clear it.

LOS Fault Monitor Controls and Settings

LOS(3,2,1,0)_EN 002C[3:0] 002C[3:0] LOS monitor enable for IN3, IN2, IN1, IN0. Allows disa-

bling the monitor if unused.

LOS(3,2,1,0)_TRIG_THR 002E[7:0] -

0035[7:0]

LOS(3,2,1,0)_CLR_THR 0036[7:0] -

003D[7:0]

002E[7:0] -

0035[7:0]

0036[7:0] -

003D[7:0]

Sets the LOS trigger threshold and clear sensitivity for IN3, IN2, IN1, IN0. These 16-bit values are determined with the ClockBuilder Pro utility.

LOS(3,2,1,0)_VAL_TIME 002D[7:0] 002D[7:0] LOS clear validation time for IN3, IN2, IN1, IN0. This

sets the time that an input must have a valid clock before the LOS condition is cleared. Settings of 2 ms, 100 ms, 200 ms, and 1 s are available.

4.3.3 OOF Detection

Each

input clock is monitored for frequency accuracy with respect to a OOF reference which it considers as its “0 ppm” reference. This

OOF reference can be selected as either:

• XA/XB pins

• Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in Figure

4.7 OOF Status Indicator on page 26. An option to disable either monitor is also available. The live OOF register always displays the

current OOF state and its sticky register bit stays asserted until cleared.

Sticky

OOF

Monitor

Precision

Fast

Live

LOS

OOF

Figure 4.7. OOF Status Indicator

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Clock Inputs

4.3.3.1 Precision OOF Monitor

precision OOF monitor circuit measures the frequency of all input clocks to within ±0.0625 ppm accuracy with respect to the selec-

The ted OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency range of from ±0.0625 ppm to ±512 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0-IN3) as the 0 ppm OOF reference instead of the XAXB pins is available. These options are all register configurable.

OOF Declared

OOF Cleared

Hysteresis Hysteresis

-6 ppm

(Set)

-4 ppm

(Clear

)

OOF

0 ppm

+4 ppm

(Clear)

+6 ppm

Reference

Figure 4.8. Example of Precise OOF Monitor Assertion and Deassertion Triggers

(Set)

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4.3.3.2 Fast OOF Monitor

Si5347, Si5346 Revision D Reference Manual

Clock Inputs

Because

the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds more quickly and has larger thresholds.

Table 4.8. OOF Status Monitor Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

OOF Status Indicators

OOF(3,2,1,0) 000D[7:4] 000D[7:4] OOF status monitor for IN3, IN2, IN1, IN0. Indicates if a

valid clock is detected or if a OOF condition is detected.

OOF(3,2,1,0)_FLG 0012[7:4] 0012[7:4] OOF status monitor sticky bits for IN3, IN2, IN1, IN0.

Sticky bits will remain asserted when an OOF event occurs until cleared. Writing a zero to a sticky bit will clear it.

OOF(3,2,1,0)_INTR_MSK 0x0018[7:4] 0x0018[7:4] Marks OOF from generating INTRb interrupt for IN3-IN0.

0: Allow OOF interrupt (default)

1: Mask (ignore) OOF for interrupt

OOF Monitor Control and Settings

OOF_REF_SEL 0040[2:0] 0040[2:0] This selects the clock that the OOF monitors use as

their “0 ppm” reference. Selections are: XA/XB, IN0, IN1, IN2, IN3.

OOF(3,2,1,0)_EN 003F[3:0] 003F[3:0] This allows to enable/disable the precision OOF monitor

for IN3, IN2, IN1, IN0.

FAST_OOF(3,2,1,0)_EN 003F[7:4] 003F[7:4] To enable/disable the fast OOF monitor for IN3, IN2,

IN1, IN0.

OOF(3,2,1,0)_SET_THR 0046[7:0] -

0049[7:0]

0046[7:0] -

0049[7:0]

Determines the OOF alarm set threshold for IN3, IN2, IN1, IN0. Range is from ±2 ppm to ±500 ppm in steps of 2 ppm.

OOF(3,2,1,0)_CLR_THR 004A[7:0] -

004D[7:0]

FAST_OOF(3,2,1,0)_SET_THR 0x0051[7:0] -

0x0054[7:0]

FAST_OOF(3,2,1,0)_ CLR_THR

0x0055 [7:0] -

0x0058[7:0]

004A[7:0] -

004D[7:0]

0x0051[7:0] -

0x0054[7:0]

0x0055 [7:0] -

0x0058[7:0]

Determines the OOF alarm clear threshold for INx. Range is from ±2 ppm to ±500 ppm in steps of 2 ppm.

Determines the fast OOF alarm set threshold for IN3, IN2, IN1, IN0.

Determines the fast OOF alarm clear threshold for IN3, IN2, IN1, IN0.

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Clock Inputs

4.3.4 LOL Detection

is a loss of lock (LOL) monitor for each of the DSPLLs. The LOL monitor asserts a LOL register bit when a DSPLL has lost

There synchronization with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs (LOL_A, LOL_B, LOL_C, LOL_D). The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that clears the indicator (LOL Clear).

A block diagram of the LOL monitor is shown in Figure 4.9 LOL Status Indicators on page 29. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor.

Si5347

LOL Monitor

LOL

Clear

LOL

Set

LPF

÷M

DSPLL A

LOS

LOL Status Registers

Live

DSPLL A

Sticky

DSPLL D

DSPLL C

DSPLL B

LOL_D

LOL_C

LOL_B

LOL_A

Figure 4.9. LOL Status Indicators

Each of the LOL frequency monitors has adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. Having two separate

frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration of the LOL set and clear thresholds is shown in Figure 4.10 LOL Set and Clear Thresholds on page 29.

Clear LOL

Threshold

Set LOL

Threshold

Lock Acquisition

LOL

Hysteresis

LOCKED

Lost Lock

10,0000.1 1

Phase Detector Frequency Difference (ppm)

Figure 4.10. LOL Set and Clear Thresholds

An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input

The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The

clock. configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using the ClockBuilder Pro utility.

It is important to know that, in addition to being status bits, LOL optionally enables Fastlock.

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Clock Inputs

Table 4.9. LOL Status Monitor Registers

Setting Name Hex Address [Bit Field] Function

Si5347 Si5346

LOL Status Indicators

LOL_PLL(D,C,B,A) 000E[3:0] 000E[1:0] Status bit that indicates if DSPLL A, B, C, or D is locked

to an input clock.

LOL_FLG_PLL(D,C,B,A) 0013[3:0] 0013[1:0] Sticky bits for LOL_[D,C,B,A]_STATUS register. Writing

a zero to a sticky bit will clear it.

LOL Fault Monitor Controls and Settings

LOL_SET_THR_PLL(D,C,B,A) 009E[7:0] -

009F[7:0]

LOL_CLR_THR_PLL(D,C,B,A) 00A0[7:0] -

00A1[7:0]

LOL_CLR_DELAY_DIV256_PLL(D,C,B,A)

00A4[7:0] -

00B6[7:0]

009E[7:0] Configures the loss of lock set thresholds for DSPLL A,

B, C, D.

00A0[7:0] Configures the loss of lock clear thresholds for DSPLL

A, B, C, D.

00A4[7:0] -

00AC[7:0]

This is a 29-bit register that configures the delay value for the LOL Clear delay. Selectable from 4 ns to over 500 seconds. This value depends on the DSPLL frequency configuration and loop bandwidth. It is calculated using the ClockBuilder Pro utility

LOL_TIMER_EN_PLL(D,C,B,A) 00A2[3:0] 00A2[1:0] Allows bypassing the LOL Clear timer for DSPLL A, B,

C, D. 0- bypassed, 1-enabled

The settings in Table

4.9 LOL Status Monitor Registers on page 30 are handled by ClockBuilder Pro. Manual settings should be avoi-

ded.

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+ 256 hidden pages

Silicon Labs Si5347, Si5346 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

1. Overview

1.1 Work Flow Using ClockBuilder Pro and the Register Map

1.2 Family Product Comparison

2. Functional Description

2.1 DSPLL

2.2 DSPLL Loop Bandwidth

2.2.1 Fastlock

2.3 Dividers Overview

3. Modes of Operation

3.1 Reset and Initialization

3.1.1 Updating Registers during Device Operation

3.1.1.1 Dynamic PLL Changes

3.1.2 NVM Programming

3.2 Free Run Mode

3.3 Lock Acquisition Mode

3.4 Locked Mode

3.5 Holdover Mode

4. Clock Inputs

4.1 Input Source Selection

4.2 Types of Inputs

4.2.1 Hitless Input Switching with Phase Buildout

4.2.2 Ramped Input Switching

4.2.3 Hitless Switching, LOL (loss of lock) and Fastlock

4.2.4 External Clock Switching

4.2.5 Synchronizing to Gapped Input Clocks

4.2.6 Rise Time Considerations

4.3 Fault Monitoring

4.3.1 Input Loss of Signal (LOS) Detection

4.3.2 XA/XB LOS Detection

4.3.3 OOF Detection

4.3.3.1 Precision OOF Monitor

4.3.3.2 Fast OOF Monitor

4.3.4 LOL Detection