Silicon Labs Si5345, Si5344, Si5342 User Manual

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Any-frequency, Any-output Jitter-Attenuators/Clock Multipliers Si5345, Si5344, Si5342 Family Reference Manual

This Family Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the Si5345/44/42 devices in end applications. The official device specifications can be found in the Si5345/44/42 data sheets.

1. Overview

The Si5345/44/42 jitter attenuating clock multipliers combine 4th generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation for applications that require the highest level of jitter performance. These devices are programmable via a serial interface with in-circuit programmable non-volatile memory (NVM) ensuring power up with a known frequency configuration. Freerun, synchronous, and holdover modes of operation are supported offering both automatic and manual input clock switching. The loop filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable providing jitter performance optimization at the application level.

These devices are capable of generating any combination of output frequency from any input frequency within the specified input and output range.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Work Flow Expectations with ClockBuilder Pro™ and the Register Map

2. Work Flow Expectations with ClockBuilder Pro™ and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is that it saves having to understand all the complexities of the device. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

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2.1 Family Product Comparison

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Work Flow Expectations with ClockBuilder Pro™ and the Register Map

Table 2.1 Product Selection Guide on page

7 lists a comparison of the different family members.

Table 2.1. Product Selection Guide

Part Number Number of Inputs Number of MultiSynths Number of Outputs Package Type

Si5342 4 2 2 44-QFN

Si5344 4 4 4 44-QFN

Si5345 4 5 10 64-QFN

IN_SEL[1:0]

IN0

IN1

IN2

IN3/FB_IN

Si5345/44/42

VDDA

VDD

Optional

External

Feedback

25MHz,48-54MHz XTAL

or REFCLK

OSC

DSPLL

LPFPD

XBXA

PXAXB

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CS

INTR

LOL

SPI/

Status

Monitors

RST

NVM

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

FINC

N N

FDEC

÷R

Si5342

VDDO0

OUT0 OUT0

VDDO1

OUT1 OUT1

VDDO2 OUT2 OUT2

VDDO3 OUT3 OUT3

VDDO4

OUT4 OUT4

VDDO5

OUT5 OUT5

VDDO6

OUT6 OUT6

VDDO7

OUT7 OUT7

VDDO8

OUT8 OUT8

VDDO9 OUT9 OUT9

Si5344

Si5345

Figure 2.1. Block Diagram Si5345/44/42

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2.2 Available Software Tools and Support

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Work Flow Expectations with ClockBuilder Pro™ and the Register Map

ClockBuilder Pro is a

software tool that is used for the Si5345/44/42 family and other product families, capable of configuring the timing chip in an intuitive, easy-to-use, step-by-step process. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to a device or written to the EVB and a custom part number can be created. This is all done with one software tool. ClockBuilder Pro integrates all the data sheets, application notes and information that might be helpful in one environment. It is intended that customers will use the software tool for the proper configuration of the device. Register map descriptions given in the document should not be the only source of information for programming the device. The complexity of the algorithms is embedded in the software tool.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

DSPLL and MultiSynth

3. DSPLL and MultiSynth

The DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter reference for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the MultiSynth generated frequencies to any of the outputs. A single MultiSynth output can connect to two or more output drivers. Additional integer division (R) determines the final output frequency as shown in Figure 3.1 Si5342 DSPLL and Multisynth System Flow Diagram on page 9.

25MHz, 48-54MHz XTAL

or REFCLK

XBXA

IN_SEL[1:0]

IN0

IN1

IN2

IN3/FB_IN

OSC

PXAXB

Optional External

Feedback

Multi

Synth

Multi

Synth

Figure 3.1. Si5342 DSPLL and Multisynth System Flow Diagram

DSPLL

LPFPD

÷ 5

÷R

VDDO0

OUT0 OUT0

VDDO1

OUT1 OUT1

The frequency configuration of the DSPLL is programmable through the SPI or I2C serial

interface and can also be stored in non-volatile memory or RAM. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output MultiSynth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

DSPLL and MultiSynth

3.1 Dividers

There are five divider classes within the Si5345/4/2. See Figure 1 for a block diagram that shows all of these dividers.

1. P-dividers: Wide range input dividers P3, P2, P1, P0

• MultiSynth divider: 48 bit numerator, 32 bit denominator, min value is 1

Practical range limited by phase detector and VCO range

•

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

2. Narrow range input divider: Pxaxb

• Only divides by 1, 2, 4, 8

3. Feedback M divider

• MultiSynth divider

• Integer or fractional divide values

• 56 bit numerator, 32-bit denominator

• Practical range limited by phase detector and VCO range

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

4. Output N divider

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

5. Output R divider

• Only even integer divide values

• Min value is 2

•

Maximum value is 225 – 2

3.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection. The DSPLL loop bandwidth is set in registers 0x0508-0x050D and are determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (F

), the more chance that F

pfd

will cause a spur in the

pfd

Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase noise/jitter it is recommended that the normal PLL bandwidth be kept less than F

/160 although ratios of F

pfd

/100 will typically work fine.

pfd

Table 3.1. PLL Bandwidth Registers

BWx_PLL 0x0508[7:0]-0x050D[7:0] Determines the loop BW for the DSPLL. This is set by CBPro. See CBPro for a

correlation of bandwidths and values.

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3.2.1 Fastlock Feature

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

DSPLL and MultiSynth

Selecting a

low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The Fastlock feature allows setting a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process to reduce lock time. Higher Fastlock loop bandwidth settings will enable the DSPLLs to lock faster. Fastlock Bandwidth settings in the range from 100 Hz up to 4 kHz are available for selection. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting. The Fastlock feature can be enabled or disabled independently by register control. If enabled, when LOL is asserted Fastlock will be automatically enabled. When LOL is no longer asserted, Fastlock will be automatically disabled.

Note: This update bit will latch new values for Loop, Fastlock, and Holdover bandwidths simultaneously.

Table 3.2. Fastlock Registers

FASTLOCK_AUTO_EN 0x052B[0] Auto Fastlock Enable/Disable

FASTLOCK_MAN 0x052B[1] 0 for normal operation,

1 to force fast lock

FASTLOCK_BW_PLL 0x050E[7:0]-0x0513[7:0] Fastlock BW selection.

The loss of lock (LOL) feature is a fault monitoring mechanism. Details of the LOL feature can be found in 5.3.3 Loss

of Lock (LOL)

Fault Monitoring.

3.2.2 Holdover Exit Bandwidth

In addition to the operating loop and fastlock bandwidths, there is also a user-selectable bandwidth when exiting holdover and locking or relocking to an input clock, available when ramping is disabled (HOLD_RAMP_BYP = 1). CBPro sets this value equal to the loop bandwidth by default.

Note: The BW_UPDATE bit will latch new values for Loop, Fastlock, and Holodver bandwidths simultaneously.

Table 3.3. DSPLL Holdover Exit Bandwidth Registers

HOLDEXIT_BW 0x059D–0x05A2 Determines the Holdover Exit BW for the DSPLL. Parameters are generated by

ClockBuilder Pro. See CBPro for the generated values and corresponding bandwidths.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

4. Modes of Operation

After initialization the DSPLL will operate in one of the following modes: Free-run, lock-acquisition, locked, or holdover. See Figure

4.1 Modes of Operation on page 12 below for the state diagram showing the modes of operation. The following sections describe

each of these modes in greater detail.

Power-Up

Reset and

Initialization

Is holdover

history valid?

No valid

input clocks

selected

An input is qualified

and available

selection

Holdover

Mode

Yes

Selected input

clock fails

Figure 4.1. Modes of Operation

for

Free-run

Valid input clock

Lock Acquisition

(Fast Lock)

Locked

Mode

selected

Phase lock on selected input

clock is achieved

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4.1 Reset and Initialization

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

Once power

is applied, the device begins an initialization period where it downloads default register values and configuration data from NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until initialization is complete.

There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers are restored to the values stored in NVM, and all circuits, including the serial interface, are restored to their initial state. A hard reset is initiated using the RST pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Table 4.1 Reset Registers on page 13 lists the reset and control registers.

NVM

OTP

RAM

Figure 4.2. Si5345/44/42 Memory Configuration

Table 4.1. Reset Registers

Function dress [Bit Field]

HARD_RST 0x001E[1] Performs the same function as power cycling the device. All registers will be re-

stored to their default values.

SOFT_RST 0x001C[0] Performs a soft reset. Initiates register configuration changes.

Power-Up

NVM download

Initialization

Serial interface

ready

Hard Reset bit asserted

Soft Reset

bit asserted

RST

pin asserted

Figure 4.3. Initialization from Hard Reset and Soft Reset

The Si5345/44/42 is fully configurable using the serial interface (I2C or

SPI). At power up the device downloads its default register values from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8V) and VDDA (3.3 V) pins.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

4.2 Dynamic PLL Changes

possible for a PLL to become unresponsive (i.e., lose lock indefinitely) when it is dynamically reprogrammed or changed via the

It is serial port. Reprogramming/changing the N divider does not affect the PLL. Any change that causes the VCO frequency to change by more than 250 ppm since Power-up, NVM download, or SOFT_RST requires the following special sequence of writes. Changes to the following registers require the this special sequence of writes:

• PXAXB

• MXAXB_NUM

• MXAXB_DEN

• M_NUM

• M_DEN

1. First, write in the preamble

Write 0x0B24 = 0xC0

Write 0x0B25 = 0x00

Write 0x0540 = 0x01 (NOTE: for all new designs it is recommend that this register be written as part of the preamble. In some rare cases, omitting this write may result in a one-time LOL occurrence. However, if this issue has not occurred with your current frequency plan it is not likely to occur)

2. Wait 300 ms.

3. Then perform the desired register modifications

4. Write SOFT_RST 0x001C[0] = 1

5. Write the post-amble

Write 0x0540 = 0x00 (NOTE: for all new designs it is recommend that this register be written as part of the post-amble. In some rare cases, omitting this write may result in a one-time LOL occurrence. However, if this issue has not occurred with your current frequency plan it is not likely to occur)

Write 0x0B24 = 0xC3

Write 0x0B25 = 0x02

Note: This programming sequence applies only to Rev D and later and has changed for revision D and later from what it was in the earlier revisions. The preamble and postamble values for updating certain registers during device operation are different for earlier revisions. Either the new or old values below may be written to revision D or later devices without issue. No system software changes are necessary for legacy systems. When writing old values, note that reading back these registers will not give the written old values, but will reflect the new values. Silicon Labs recommends using the new values for all revision D (described above) and later designs, since the write and read values will match. Please contact Silicon Labs if you need information about an earlier revision. Please always ensure to use the correct sequence for the correct revision of the device. Also check for the latest information online. This information is updated from time to time. The latest information is always posted online.

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4.3 NVM Programming

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

Devices have

two categories of non-volatile memory: user NVM and factory (Silabs) NVM. Each type is segmented into NVM banks. There are three user NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). User NVM can be therefore be burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Active NVM BANK Value (Decimal) Number of User Banks Burned Number of User Banks

Available to Burn

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met in order to ensure that the correct values are written into the NVM:

• VDD and VDDA power must both be stable throughout the process.

No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01.

• DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write all registers as needed. Verify device operation before writing registers to NVM.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register.

4. Poll DEVICE_READY until DEVICE_READY=0x0F.

5. Set NVM_READ_BANK 0x00E4[0]=1. This will load the NVM contents into non-volatile memory.

6. Poll DEVICE_READY until DEVICE_READY=0x0F.

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 4.2. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

Warning: Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt

NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the

the PAGE register.

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4.4 Free Run Mode

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

The DSPLL

will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a low-jitter XAXB source will be needed for lowjitter clock outputs.

4.5 Acquisition Mode

The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO frequency change as it pulls-in to the input clock frequency.

4.6 Locked Mode

Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input clock. At this point any XTAL frequency drift will typically not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is achieved. See 5.3.3 Loss of Lock (LOL) Fault Monitoring for more details on the operation of the loss of lock circuit.

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4.7 Holdover Mode

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

The DSPLL

if programmed for holdover mode will automatically enter Holdover mode when the selected input clock becomes invalid and no other valid input clocks are available for selection. It uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit stores up to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in the figure below. The window size determines the amount of holdover frequency averaging. This delay value allows recent frequency information to be ignored for Holdover in cases where the input clock source frequency changes as it is removed.

Clock Failure

and Entry into

Holdover

Historical Frequency Data Collected

time

120s

Programmable historical data window

used to

determine the final holdover value

1s,10s, 30s, 60s

Programmable delay

30ms, 60ms, 1s,10s, 30s, 60s

Figure 4.4. Programmable Holdover Window

When entering Holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in Holdover, the

output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XAXB pins. If the clock input becomes valid, the DSPLL will automatically exit the Holdover mode and re-acquire lock to the new input clock. This process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is Glitchless and its rate is controlled by the DSPLL bandwidth or the Fastlock bandwidth, if Fastlock is enabled. These options are register programmable.

The recommended mode of exit from holdover is a ramp in frequency. Just before the exit begins, the frequency difference between the output frequency while in holdover and the desired, new output frequency is measured. It is quite possible (even likely) that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the holdover history circuit may have changed the holdover output frequency. The ramp logic calculates the difference in frequency between the holdover frequency and the new, desired output frequency. Using the user selected ramp rate, the correct ramp time is calculated. The output ramp rate is then applied for the correct amount of time so that when the ramp ends, the output frequency will be the desired new frequency. Using the ramp, the transition between the two frequencies is smooth and linear. The ramp rate can be selected to be very slow (0.2 ppm/sec), very fast (40,000 ppm/sec) or any of approximately 40 values that are in between. The loop BW values do not limit or affect the ramp rate selections and vice versa. CBPro defaults to ramped exit from holdover. Ramped exit from holdover is also used for ramped input clock switching. See 5.2.3 Ramped Input Switching for more information.

As shown in Figure 4.1 Modes of Operation on page 12, the Holdover and Freerun modes are closely related. The device will only enter Holdover if a valid clock has been selected long enough for the holdover history to become valid, i.e., HOLD_HIST_VALID = 1. If the clock fails before the combined HOLD_HIST_LEN + HOLD_HIST_DELAY time has been met, HOLD_HIST_VALID = 0 and the device will enter Freerun mode instead. Reducing the HOLD_HIST_LEN and HOLD_HIST_DELAY times will allow Holdover in less time, limited by the source clock failure and wander characteristics. Note that the Holdover history accumulation is suspended when the input clock is removed and resumes accumulating when a valid input clock is again presented to the DSPLL.

Table 4.3. Holdover Mode Control Registers

Function

[Bit Field]

Holdover Status

HOLD 0x000E[5] DSPLL Holdover status indicator.

0: Normal Operation

1: In Holdover/Freerun Mode:

HOLD_HIST_VALID = 0 ? Freerun Mode

HOLD_HIST_VALID = 1 ? Holdover Mode

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Modes of Operation

Function

[Bit Field]

HOLD_FLG 0x0013[5] Holdover indicator sticky flag bit. Remains asserted after the indicator bit

shows a fault until cleared by the user. Writing a 0 to the flag bit will clear it if the indicator bit is no longer asserted.

HOLD_INTR_MSK 0x0019[5] Masks Holdover/Freerun from generating INTR interrupt.

0: Allow Holdover/Freerun interrupt (default)

1: Mask (ignore) Holdover/Freerun for interrupt

HOLD_HIST_VALID 0x053F[1] Holdover historical frequency data valid.

0: Incomplete Holdover history, Freerun mode available

1: Valid Holdover history, Holdover mode available

Holdover Control and Settings

HOLD_HIST_LEN 0x052E[4:0] Window Length time for historical average frequency used in Holdover mode.

Window Length in seconds (s):

Window Length = ((2

LEN

) – 1) x 268 ns

HOLD_HIST_DELAY 0x052F[4:0] Delay Time to ignore data for historical average frequency in Holdover mode.

Delay Time in seconds (s):

Delay Time (s) = (2

DELAY

) x 268 ns

FORCE_HOLD 0x0535[0] Force the device into Holdover mode. Used to hold the device output clocks

while retraining an upstream input clock.

0: Normal Operation

1: Force Holdover/Freerun Mode:

HOLD_HIST_VALID = 0 ? Freerun Mode

HOLD_HIST_VALID = 1 ? Holdover Mode

Holdover Exit Control

HOLD_RAMP_BYP 0x052C[3] Holdover Exit Ramp Bypass

0: Use Ramp when exiting from Holdover (default)

1: Use Holdover/Fastlock/Loop bandwidth when exiting from Holdover

HOLDEXIT_BW_SEL0 0x059B[6] Select the exit bandwidth from Holdover when ramped exit is not selected

(HOLD_RAMP_BYP = 1).

00: Use Fastlock bandwidth on Holdover exit

01: Use Holdover Exit bandwidth on Holdover exit (default)

10, 11: Use Normal Loop bandwidth on Holdover exit

HOLDEXIT_BW_SEL1 0x052C[4] Select the exit bandwidth from Holdover when ramped exit is not selected

(HOLD_RAMP_BYP = 1).

00: Use Fastlock bandwidth on Holdover exit

01: Use Holdover Exit bandwidth on Holdover exit (default)

10, 11: Use Normal Loop bandwidth on Holdover exit

RAMP_STEP_INTERVAL 0x052C[7:5] Time Interval of the frequency ramp steps when ramping between inputs or

exiting holdover.

RAMP_STEP_SIZE 0x05A6[2:0] Size of the frequency ramp steps when ramping between inputs or exiting

holdover.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

5. Clock Inputs

The Si5342/44/45 support 4 inputs that can be used to synchronize to the internal DSPLL.

5.1 Inputs (IN0, IN1, IN2, IN3)

The inputs accept both standard format inputs and low-duty-cycle pulsed CMOS clocks. Input selection from CLK_SWITCH_MODE can be manual (pin or register controlled) or automatic with user definable priorities. Register 0x052A is used to select pin or register control, and to configure the input as shown below in Table 5.1 Input Selection Configuration on page 19.

Table 5.1. Input Selection Configuration

[Bit Field]

CLK_SWITCH_MODE 0x0536[1:0] Selects manual or automatic switching modes. Automatic mode can be revertive or

non-revertive. Selections are the following:

00 Manual,01 Automatic non-revertive

02 Automatic revertive, 03 Reserved

IN_SEL_REGCTRL 0x052A [0] 0 for pin controlled clock selection

1 for register controlled clock selection

IN_SEL 0x052A [2:1] 0 for IN0, 1 for IN1,

2 for IN2, 3 for IN3 (or FB_IN)

5.1.1 Manual Input Switching

In manual mode, CLK_SWITCH_MODE=0x00.

Input switching 0 of register 0x052A determines if the input selection is pin selectable or register selectable. The default is pin selectable. The following table describes the input selection on the pins. Note that when Zero Delay Mode is enabled, the FB_IN pins will become the feedback input and IN3 therefore is not available as a clock input. Also, in Zero Delay Mode, ZDM_EN must be set and register based input clock selection must be done with ZDM_IN_SEL. If there is no clock signal on the selected input, the device will automatically enter free-run or holdover mode.

can be done manually using the IN_SEL[1:0] device pins from the package or through register 0x052A IN_SEL[2:1]. Bit

Function

Table 5.2. Manual Input Selection using IN_SEL[1:0] Pins

IN_SEL[1:0] DEVICE PINS Zero Delay Mode Disabled Zero Delay Mode Enabled

00 IN0 IN0

01 IN1 IN1

10 IN2 IN2

11 IN3 Reserved

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5.1.2 Automatic Input Selection

In automatic mode CLK_SWITCH_MODE = 0x01 (non-revertive) or 0x02 (revertive)

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

An automatic

input selection is available in addition to the above mentioned manual switching option described in 5.1.1 Manual Input

Switching. In automatic mode, the selection criteria is based on input clock qualification, input priority and the revertive option. The

IN_SEL[1:0] pins or IN_SEL[2:1] register bits are not used in automatic input selection. Also, only input clocks that are valid (i.e., with no active alarms) can be selected by the automatic clock selection. If there are no valid input clocks available the DSPLL will enter the holdover mode. With revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority becomes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated.

Table 5.3. Registers for Automatic Input Selection

CLK_SWITCH_MOD

Hex Address [Bit

Field]

0x0536[1:0]

Function

Selects manual or automatic switching modes. Automatic mode can be revertive or nonrevertive. Selections are the following: 00 Manual,01 Automatic non-revertive 02 Automatic revertive, 03 Reserved

0: disable zero delay mode

ZDM_EN 0x0487[0]

1: enable zero delay mode

ZDM_IN_SEL 0x0487[2:1]

Selects the input when in manual register controlled mode when zero delay mode is enabled. Selections are IN0, IN1, IN2. A register value of 3 is not allowed.

0: automatic switching disabled for zero-delay mode

ZDM_AUTOSW_EN 0x0487[4]

1: automatic input switching enabled and input clock selection governed by automatic input switching engine

IN0_PRIORITY 0x0538[2:0]

IN1_PRIORITY 0x0538[6:4]

IN2_PRIORITY 0x0539[2:0]

IN0, IN1, IN2, IN3 priority select for the automatic selection state machine. Priority selections are 1,2,3,4, or zero for no priority.

IN3_PRIORITY 0x0539[6:4]

Determines the LOS status for IN3,2,1,0 and is used in determining a valid clock for au-

IN_LOS_MSK 0x0537[3:0]

tomatic input selection

0 to use LOS in clock selection logic, 1 to mask LOS from the clock selection logic

Determines the OOF status for IN3,2,1,0 and is used in determining a valid clock for the automatic input selection

IN_OOF_MSK 0x0537[7:4]

0 to use OOF in the clock selection logic, 1 to mask the OOF from the clock selection logic

When in zero delay mode (ZDM_EN (0x0487[0]) the phase difference between the output, which is connected to the selected input, will be nulled to zero. However the IO delay variation will substantially increase in ZDM mode if the Fpfd is below 128 kHz. When in zero delay mode, the DSPLL must have the phase buildout turned off for input switching or else the IO delay can change on each input switch. Manual control of the input clock selection is by either pin or register and also depends upon the device being in zero delay mode or not. See Table 5.4 Register 0x0949 Clock Input Control and Configuration on page 22.

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5.2 Types of Inputs

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

Each of

the four different inputs IN0–IN3 can be configured as standard LVDS, LVPECL, HCL, CML, and single-ended LVCMOS formats, or as a low duty cycle pulsed CMOS format. The standard format inputs have a nominal 50% duty cycle, must be ac-coupled and use the “Standard” Input Buffer selection as these pins are internally dc-biased to approximately 0.83 V. The pulsed CMOS input format allows pulse-based inputs, such as frame-sync and other synchronization signals, having a duty cycle much less than 50%. These pulsed CMOS signals are dc-coupled and use the “Pulsed CMOS” Input Buffer selection. In all cases, the inputs should be terminated near the device input pins as shown in Figure 5.1 Input Termination for Standard and Pulsed CMOS Inputs on page 21. The resistor divider values given below will work with up to 1 MHz pulsed inputs.

Standard AC-Coupled Differential (IN0-IN3)

0.1uF *

100

VDS, LVPECL, CML

* These caps should have < ~5 ohms capacitive reactance at the

0.1uF *

lock inpu

INxb

t frequency.

INx

Standard

Pulsed CMOS

Standard AC-Coupled Single-Ended (IN0-IN3)

3.3/2.5/1.8V LVCMOS

RS matches the CMOS driver to a 50 ohm

transmission line (if used)

0.1uF *

0.1uF

INx

INxb

Standard

Pulsed CMOS

Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267

ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf

may improve the output jitter due to faster input slew rate at INx. If

attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm and omit C1,

R2 and the capacitor below R2. C1, R1, and R2 should be physically placed

as close as practicle to the device input pins. *This cap should have less than

~20 ohms of capacitive reactance at the clock input frequency

DC-Coupled Pulsed CMOS only for Frequencies

< 1MHz (IN0-IN3)

RS matches the CMOS driver to a 50 ohm

3.3V, 2.5V, 1.8V

line (if used)

transmission

LVCMOS

Note: See Datasheet for input clock specifications

INx

INxb

Standard

Pulsed CMOS

Figure 5.1. Input Termination for Standard and Pulsed CMOS Inputs

Note: Floating clock inputs are noise sensitive. Add a cap to non-CMOS unused clock inputs.

Input clock buffers are enabled by setting the IN_EN 0x0949[3:0] bits appropriately for IN3 through IN0. Unused clock inputs may be powered down and left unconnected at the system level. For standard mode inputs, both input pins must be properly connected as shown in Figure 5.1 Input Termination for Standard and Pulsed CMOS Inputs on page 21 above, including the “Standard AC Coupled Single Ended” case. In Pulsed CMOS mode, it is not necessary to connect the inverting INx input pin. To place the input buffer into Pulsed CMOS mode, the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949[7:4] for IN3 through IN0.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Table 5.4. Register 0x0949 Clock Input Control and Configuration

Clock Inputs

Function

[Bit Field]

IN_EN 0x0949[3:0] Enables for the four inputs clocks, IN0 through IN3.

1 to enable.

IN_PULSED_CMOS_EN 0x0949[7:4] Selects CMOS or differential receiver for IN3, IN2, IN1, IN0. Defaults to dif-

ferential input.

Differential = 0, CMOS = 1

5.2.1 Unused Inputs

Unused inputs

can be disabled and left unconnected when not in use. Register 0x0949[3:0] defaults the input clocks to being enabled.

Clearing the unused input bits will disable them.

5.2.2 Hitless Input Switching with Phase Buildout

Phase buildout, also referred to as hitless switching, prevents a phase change from propagating to the output when switching between two clock inputs with the exact same frequency and a fixed phase relationship (i.e., they are phase/frequency locked, but with a nonzero phase difference). When phase buildout is enabled, the DSPLL absorbs the phase difference between the two input clocks during a clock switch. When phase buildout is disabled, the phase difference between the two inputs is propagated to the output at a rate determined by the DSPLL loop bandwidth. It supports a minimum input frequency of 8 kHz, but if a fractional P input divider is used, the input frequency must be 300 MHz or higher in order to ensure proper operation. Note that hitless switching is not available in zero delay mode.

Table 5.5. Hitless Switching Enable Bit

Function dress [Bit Field]

HSW_EN 0x0536[2] Hitless switching is enabled = 1, or disabled = 0.

5.2.3 Ramped Input Switching

If switching

between input clocks that are not exactly the same frequency (i.e. are plesiochronous), ramped switching should be enabled to ensure a smooth transition between the two inputs. In this situation, it is also advisable to enable phase buildout to minimize the input-to-output clock skew after the clock switch ramp has completed.

When ramped clock switching is enabled, the Si5345/44/42 will very briefly go into holdover and then immediately exit from holdover. This means that ramped switching will behave the same as an exit from holdover. This is particularly important when switching between two input clocks that are not the same frequency because the transition between the two frequencies will be smooth and linear. Ramped switching should be turned off when switching between input clocks that are always frequency-locked (i.e., are the same exact frequency). Because ramped switching avoids frequency transients and overshoot when switching between clocks that are not the same frequency, CBPro defaults to ramped clock switching. The same ramp rate settings are used for both exit from holdover and clock switching. For more information on ramped exit from holdover including the ramp rate, see 4.7 Holdover Mode.

Table 5.6. Ramped Input Switching Control Registers

Setting Name Hex Address [Bit Field] Function

RAMP_SWITCH_EN 0x05A6[3] Enable frequency ramping on an input switch.

HSW_MODE 0x053A[1:0] Input switching mode select.

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5.2.4 Hitless Switching, LOL (loss of lock) and Fastlock

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

When doing

a clock switch between clock inputs that are frequency locked, LOL might momentarily be asserted. If so programmed, the assertion of LOL with invoke Fastlock. Because Fastlock temporarily increases the loop BW by asynchronously inserting new filter parameters into the DSPLL’s closed loop, there may be transients at the clock outputs when Fastlock is either entered or exited. For this reason, it is suggested that automatic entry into Fastlock be disabled by writing a zero to FASTLOCK_AUTO_EN at 0x52B[0] whenever a clock switch might occur. For more details on hitless switching please refer to AN1057: Hitless Switching using Si534x/8x Devices.

5.2.5 Glitchless Input Switching

The DSPLL has the ability to switch between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the new frequency at a rate determined by the DSPLL loop bandwidth. The DSPLL loop bandwidth is set using registers 0x0508–0x050D. Note that if “Fastlock” is enabled then the DSPLL will pull-in to the new frequency using the Fastlock Loop Bandwidth. Depending on the LOL configuration settings, the loss of lock (LOL) indicator may assert while the DSPLL is pulling-in to the new clock frequency. There will never be output runt pulses generated at the output during the transition.

5.2.6 External Clock Switching

External clock switches should be avoided because the Si5342/4/5 has no way of knowing when a clock switch will or has occurred. Because of this, neither the phase buildout engine or the ramp logic can be used. If expansion beyond the four clock inputs is an important issue, please see AN1111: Si534x/8x Input Clock Expander which describes how an external FPGA can be used for this purpose.

5.2.7 Synchronizing to Gapped Input Clocks

The DSPLL supports locking to an input clock that has missing clock periods. This is also referred to as a gapped clock. The purpose of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely increases its jitter so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter, truly periodic clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For example, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of 2 missing cycles out of every 8.

When properly configured, locking to a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transient, when the switch occurs during a gap in either input clocks. Figure 5.2 Generating an Averaged Non Gapped Output Frequency from a Gapped Input on page 23 shows a 100 MHz clock with one cycle removed every 10 cycles, which results in a 90 MHz periodic non-gapped output clock.

Gapped Input Clock Periodic Output Clock

100 MHz clock

1 missing period

100 ns 100 ns

every

90 MHz non-gapped clock

DSPLL

1 2 3 4 5 6 7 8 9 10

10 ns

Period Removed

Figure 5.2. Generating an Averaged Non Gapped Output Frequency from a Gapped Input

1 2 3 4 5 6 7 8 9

11.11111... ns

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

5.2.8 Rise Time Considerations

well known that slow rise time signals with low slew rates are a cause of increased jitter. In spite of the fact that the low loop BW of

It is the Si5342/44/45 will attenuate a good portion of the jitter that is associated with a slow rise time clock input, if the slew rate is low enough, the output jitter will increase. The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input. The figure shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values.

IN_X Slew Rate in Differential Mode

4.5

3.5

2.5

Relateive Jitter

1.5

TYP

0.5

0 100 200 300 400 500 600

Input Slew (V/us)

Figure 5.3. Effect of Low Slew Rate on RMS Jitter

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5.3 Fault Monitoring

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

The four at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. There is also a Loss of Lock (LOL) indicator asserted when the DSPLL loses synchronization within the feedback loop. Figure 5.4 Si5342/44/45 Fault Monitors on

page 25 shows the fault monitors for each input path going into the DSPLL, which includes the crystal input as well as IN0-3.

clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF). Note that the reference

Si5345/44/42

OSC

IN0

IN1

IN2

IN3/FB_IN

÷P

LOS

OOF

Precision

Fast

Precision

Fast

Precision

Fast

Precision

Fast

LOL

÷M

LOS

DSPLL

LPFPD

÷5

Figure 5.4. Si5342/44/45 Fault Monitors

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5.3.1 Input Loss of Signal (LOS) Fault Detection

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

The loss

of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status register. The live LOS register always displays the current LOS state and a sticky register when set, always stays asserted until cleared by the user.

Monitor

LOS

Live

LOS

Sticky

Figure 5.5. LOS Status Indicators

A LOS monitor is also available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when LOSXAXB is detected. This feature can be disabled such that the device will continue to produce output clocks even when LOSXAXB is detected. Single-ended inputs must be connected to the XA input pin with the XB pin terminated properly for LOSXAXB to function correctly. The table below lists the loss of signal status indicators and fault monitoring control registers.

Table 5.7. Loss of Signal Status Monitoring and Control Registers

Function

[Bit Field]

LOS 0x000D[3:0] LOS status monitor for IN3 (bit3), IN2 (bit2), IN1(bit1), IN0 (bit0) indicates if a valid

clock is detected. A set bit indicates the input is LOS.

SYSINCAL 0x000C[0] Asserted when in calibration

LOSXAXB 0x000C[1] LOS status monitor for the STAL or REFCLK at the XA/XB pins

LOS_FLG 0x0012[3:0] LOS status monitor sticky bits for IN3, IN2, IN1, IN0. Sticky bits will remain asserted

when a LOS event occurs until manually cleared. Writing zero to the bit will clear it.

SYSINCAL_FLG 0x0011[0] SYSINCAL sticky bit. Sticky bits will remain asserted until written with a zero to clear.

LOSXAXB_FLG 0x0011[1] LOS status monitor sticky bits for XAXB. Sticky bits will remain asserted when a LOS

event occurs until cleared. Writing zero to the bit will clear it.

LOS_EN 0x002C[3:0] LOS monitor enable for IN3, IN2, IN1, IN0. Allows disabling the monitor if unused.

0: Disable LOS Detection

1: Enable LOS Detection (default)

LOSXAXB_DIS 0x002C[4] Enable LOS detection on the XAXB inputs.

0: Enable LOS Detection (default)

1: Disable LOS Detection

LOS_TRIG_THR 0x002E[7:0]-0

x0035[7:0]

Sets the LOS trigger threshold and clear sensitivity for IN3, IN2, IN1, IN0. These 16- bit values are determined by ClockBuilder Pro

LOS_CLR_THR 0x0036[7:0]-0

x003D[7:0]

LOS_VAL_TIME 0x002D[7:0] LOS clear validation time for IN3, IN2, IN1, IN0. This sets the time that an input must

have a valid clock before the LOS condition is cleared. Settings of 2ms, 100ms, 200ms, and 1 s are available.

LOS_INTR_MSK 0x0018[3:0] This is the LOS interrupt mask, which can be cleared to trigger an interrupt on the

INTR pin if an LOS occurs for IN0-3.

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5.3.2 Out of Frequency (OOF) Fault Detection

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

Each input

clock is monitored for frequency accuracy with respect to an OOF reference which it considers as its 0 ppm reference. This

OOF reference can be selected as either:

XA/XB pins

Any input clock (IN0, IN1, IN2, IN3)

The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in Figure 9. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cleared.

Sticky

OOF

Monitor

Precision

LOS

OOF

Fast

Figure 5.6. OOF Status Indicator

The Precision OOF monitor circuit measures the frequency of all input clocks to within up to ±0.0625 ppm accuracy with respect to the selected OOF frequency reference. A valid input clock frequency is one that remains within the register-programmable OOF frequency range of from ±0.0625 ppm to ±512 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of the XAXB pins is available. These options are all register configurable.

Live

OOF Declared

Hysteresis Hysteresis

OOF Cleared

-6 ppm

(Set)

-4 ppm

(Clear)

0 ppm

OOF

+4 ppm

(Clear)

+6 ppm

(Set)

Reference

Figure 5.7. Example of Precise OOF Monitor Assertion and De-assertion Triggers

Table 5.8 Out-of-Frequency Status Monitoring and Control Registers on page 27 lists

the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds more quickly and has larger thresholds.

Table 5.8. Out-of-Frequency Status Monitoring and Control Registers

Function

[Bit Field]

OOF 0x000D[7:4] OOF status monitor for IN3, IN2, IN1, IN0. Indicates if a valid clock is detec-

ted or if a OOF condition is detected.

OOF_FLG 0x0012[7:4] OOF status monitor sticky bits for IN3, IN2, IN1, IN0. Stick bits will remain as-

serted when an OOF event occurs until cleared. Writing zero to the bit will clear it.

OOF_INTR_MSK 0x0018[7:4] Masks OOF from generating INTR interrupt for IN3 – IN0.

0: Allow OOF interrupt (default)

1: Mask (ignore) OOF for interrupt

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

Function

[Bit Field]

OOF_REF_SEL 0x0040[2:0] This selects the clock that the OOF monitors use as the 0 ppm reference. Se-

lections are XA/XB, IN0, IN1, IN2, IN3. Default is XAXB.

OOF_EN 0x003F[3:0] This allows to enable/disable the precision OOF monitor for IN3, IN2, IN1, IN0

FAST_OOF_EN 0x003F[7:4] This allows to enable/disable the fast OOF monitor for IN3, IN2, IN1, IN0

OOF_SET_THR 0x0046[7:0]-0x0

OOF Set threshold. Range is up to ±500 ppm in steps of 1/16 ppm

049[7:0]

OOF_CLR_THR 0x004A[7:0]-0x0

OOF Clear threshold. Range is up to ±500 ppm in steps of 1/16 ppm

04D[7:0]

FAST_OOF_SET_THR 0x0051[7:0]-0x0

Determines the fast OOF alarm set threshold for IN3, IN2, IN1, IN0.

054[7:0]

FAST_OOF_CLR_THR 0x0055[7:0]-0x0

Determines the fast OOF alarm clear threshold for IN3, IN2, IN1, IN0.

058[7:0]

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5.3.3 Loss of Lock (LOL) Fault Monitoring

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

The Loss is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency difference between the input and feedback clocks at the phase detector. There are four parameters that control the LOL monitor. First, there is an assert threshold which sets the LOL assertion threshold. The user sets this threshold in ppm in CBPro. Then, there is a fast assert threshold. CBPro sets this to ~100 times the assert threshold. Then there is a de-assert threshold to clear the LOL, which is set in ppm in CBPro. Then, there is a clear delay, which CBPro sets based upon the project plan.

Note: A very large ppm error in a short time will assert LOL.

A block diagram of the LOL monitor is shown in Figure 5.8 LOL Status Indicators on page 29. The live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects the current state of the LOL monitor.

of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock. There

LOL Monitor

LOL

Clear

Timer

LOS

LOL

Sticky

LOL

Set

Live

LOL

DSPLL

LPFPD

Feedback

Clock

÷M

÷5

Si5345/44/42

Figure 5.8. LOL Status Indicators

The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10000 ppm. CBPro provides a wide range of set and clear thresholds for the LOL function. Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration of the LOL set and clear thresholds is shown in Figure 5.9 LOL Set and

Clear Thresholds on page 29.

LOL

LOCKED

Clear LOL

Threshold

Hysteresis

0.1 1

Phase Detector Frequency Difference (ppm)

Set LOL

Threshold

Lock Acquisition

Lost Lock

10,000

Figure 5.9. LOL Set and Clear Thresholds

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Table 5.9. Loss of Lock Status Monitor and Control Registers

Clock Inputs

Function

[Bit Field]

LOL 0x000E[1] Status bit that indicates if the DSPLL is locked to an input clock

LOL_FLG 0x0013[1] Sticky bits for LOL register. Writing 0 to a sticky bit will clear it.

LOL_SET_THR 0x009E[7:4] Configures the loss of lock set threshold in ppm.

LOL_CLR_THR 0x00A0[7:4] Configures the loss of lock clear threshold in ppm.

LOL_TIMER_EN 0x00A2[1] Allows bypassing the LOL clear delay timer.

0-bypassed, 1-enabled. Set by CBPro.

LOL_NOSIG_TIME 0x02B7[3:2] Sets 417 μs as time without an input to assert LOL. Set by CBPro.

LOL_CLR_DELAY_DIV256 [ 0x00AC[4:0]

0x00AB[7:0]

This 29 bit timer sets the delay value for the LOL clear delay timer.

Set by CBPro. 0x00AA[7:0] 0x00A9[7:0] ]

FASTLOCK_EXTEND_EN 0x00E5[5] Enables FASTLOCK_EXTEND.

FASTLOCK_EXTEND [ 0x00ED[4:0]

0x00EC[7:0]

Set by CBPro to minimize phase transients when switching the PLL

bandwidth. 0x00EB[7:0] 0x00EA[7:0] ]

FASTLOCK_EXTEND_SCL 0x0294[7:4] Set by CBPro.

LOL_SLW_VALWIN_SELX 0x0296[1] Set by CBPro.

FASTLOCK_DLY_ONSW_EN 0x0297[1] Set by CBPro.

FASTLOCK_DLY_ONSW 0x02A9[19:0] Set by CBPro.

FASTLOCK_DLY_ONLOL_EN 0x0299[1] Set by CBPro.

FASTLOCK_DLY_ONLOL 0x029D[19:0] Set by CBPro.

The settings in Table 5.9

Loss of Lock Status Monitor and Control Registers on page 30 are handled by ClockBuilder Pro. Manual set-

tings should be avoided.

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5.4 Interrupt (INTR) Monitoring

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Clock Inputs

There is

an interrupt pin available on the device which is used to indicate a change in state of one or several of the status indicators. Any of the status indicators are maskable to prevent assertion of the interrupt pin. The state of the INTR pin is reset by clearing the status register that caused the interrupt. If an interrupt occurs the various status registers from the unmasked flags must be checked and then cleared.

mask

0x0012[0]

0x0012[4]

0x0012[1]

0x0012[5]

0x0012[2]

0x0012[6]

0x0012[3]

0x0012[7]

0x0013[1]

0x0013[5]

0x0011[1]

IN0_LOS_FLG

IN0_OOF_FLG

IN1_LOS_FLG

IN1_OOF_FLG

IN2_LOS_FLG

IN2_OOF_FLG

IN3_LOS_FLG

IN3_OOF_FLG

LOL_FLG

HOLD_FLG

XAXB_LOS_FLG

mask

IN0

IN1

IN2

INTR

IN3

Figure 5.10. Interrupt Pin Source Masking Options

The _FLG bits are “sticky” versions of the alarm bits and will stay high until cleared. An _FLG bit can be cleared by writing a zero to the _FLG bit. When an _FLG bit is high and its corresponding alarm bit is low, the _FLG bit can be cleared.

During run time, the source of an interrupt can be determined by reading the _FLG register values and logically ANDing them with the corresponding _MSK register bits (after inverting the _MSK bit values). If the result is a logic one, then the _FLG bit will cause an interrupt.

For example, if LOS_FLG[0] is high and LOS_INTR_MSK[0] is low, then the INTR pin will be active (low) and cause an interrupt. If LOS[0] is zero and LOS_MSK[0] is one, writing a zero to LOS_MSK[0] will clear the interrupt (assuming that there are no other interrupt sources). If LOS[0] is high, then LOS_FLG[0] and the interrupt cannot be cleared.

silabs.com | Building a more connected world. Rev. 1.3 | 31

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

6. Output Clocks

Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3, 2.5, or 1.8 V) providing up to 20 single-ended outputs or any combination of differential and single-ended outputs.

silabs.com | Building a more connected world. Rev. 1.3 | 32

6.1 Output Crosspoint Switch

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

A crosspoint

switch allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 6.1 MultiSynth to Output

Driver Crosspoint on page 33. The crosspoint configuration is programmable and can be stored in NVM so that the desired output

configuration is ready at power up. Any MultiSynth output can connect to multiple output drivers.

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

N N

÷R

VDDO0

OUT0 OUT0

VDDO1

OUT1 OUT1

VDDO2

OUT2 OUT2

VDDO3

OUT3 OUT3

VDDO4

OUT4 OUT4

VDDO5

OUT5 OUT5

VDDO6

OUT6 OUT6

VDDO7

OUT7 OUT7

VDDO8

OUT8 OUT8

VDDO9 OUT9 OUT9

Figure 6.1. MultiSynth to Output Driver Crosspoint

Table 6.1 Output Driver Crosspoint Configuration Registers on page 33 is used to set up the routing from the MultiSynth frequency

selection to the output.

Table 6.1. Output Driver Crosspoint Configuration Registers

Si5345 Si5344 Si5342

OUT0_MUX_SEL 0x010B[2:0] 0x0115[2:0] 0x0115[2:0] Connects the output drivers to one of the N dividers.

OUT1_MUX_SEL 0x0110[2:0] 0x011A[2:0] 0x011A[2:0]

Selections are N0, N1, N2, N3, N4 for each output divider.

OUT2_MUX_SEL 0x0115[2:0] 0x0129[2:0] —

OUT3_MUX_SEL 0x011A[2:0] 0x012E[2:0] —

OUT4_MUX_SEL 0x011F[2:0] — —

OUT5_MUX_SEL 0x0124[2:0] — —

OUT6_MUX_SEL 0x0129[2:0] — —

OUT7_MUX_SEL 0x012E[2:0] — —

OUT8_MUX_SEL 0x0133[2:0] — —

OUT9_MUX_SEL 0x013D[2:0] — —

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6.2 Performance Guidelines for Outputs

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

Whenever a

number of high frequency, fast rise time, large amplitude signals are all close to one another, there will be some amount of crosstalk. The jitter of the Si5342/44/45 is so low that crosstalk can become a significant portion of the final measured output jitter. Some of the source of the crosstalk will be the Si5342/44/45 and some will be introduced by the PCB. It is difficult (and possibly irrelevant) to allocate the jitter portions between these two sources because the jitter can only be measured when a Si5342/44/45 is mounted on a PCB.

For extra fine tuning and optimization in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying the arrangements of different output clocks. For example, consider the following lineup of output clocks in Table 6.2 Example of Output

Clock Frequency Sequencing Choice on page 34.

Table 6.2. Example of Output Clock Frequency Sequencing Choice

Output Not Recommended (Frequency MHz) Recommended (Frequency MHz)

0 155.52 155.52

1 156.25 155.52

2 155.52 622.08

3 156.25 Not used

4 200 156.25

5 100 156.25

6 622.08 625

7 625 Not used

8 Not used 200

9 Not used 100

Using this example, a few guidelines are illustrated:

Avoid adjacent

frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock. If the jitter integration

bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart.

Adjacent frequency values that are integer multiples of one another are acceptable, and these outputs should be grouped accordingly. Noting that because 155.52 x 4 = 622.08 and 156.25 x 4 = 625, it is permissible to place these frequency values close to one another.

Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. In this case, see OUT3 and OUT7.

If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible to crosstalk. These guidelines typically only need to be followed by those applications that wish to achieve the highest possible levels of jitter performance. Because CMOS outputs have large pk-pk swings, are single ended, and do not present a balanced load to the VDDO supplies, CMOS outputs generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided whenever possible. When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines. For more information on these issues, see AN862 “Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.”

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6.3 Output Signal Format

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

The differential

output swing and common mode voltage are both fully programmable covering a wide variety of signal formats including LVDS, LVPECL, HCSL. For CML applications, see 18. Setting the Differential Output Driver to Non-Standard Amplitudes. The differential formats can be either normal or low power. Low power format uses less power for the same amplitude but has the drawback of slower rise/fall times. The source impedance in low power format is much higher than 100 Ω. See 18. Setting the Differential Output

Driver to Non-Standard Amplitudes for register settings to implement variable amplitude differential outputs. In addition to supporting

differential signals, any of the outputs can be configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins. See “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for additional information.

Table 6.3. Output Signal Format Control Registers

Si5345 Si5344 Si5342

OUT0_FORMAT 0x0109[2:0] 0x0113[2:0] 0x0113[2:0] Selects the output signal format as differential or

OUT1_ FORMAT 0x010E[2:0] 0x0118[2:0] 0x0118[2:0]

LVCMOS mode.

OUT2_ FORMAT 0x0113[2:0] 0x0127[2:0] —

OUT3_ FORMAT 0x0118[2:0] 0x012C[2:0] —

OUT4_ FORMAT 0x011D[2:0] — —

OUT5_ FORMAT 0x0122[2:0] — —

OUT6_ FORMAT 0x0127[2:0] — —

OUT7_ FORMAT 0x012C[2:0] — —

OUT8_ FORMAT 0x0131[2:0] — —

OUT9_ FORMAT 0x013B[2:0] — —

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6.3.1 Differential Output Terminations

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

The differential

output drivers support both ac and dc-coupled terminations as shown in Figure 6.2 Supported Differential Output Termi-

nations on page 36.

LVDS: V

DDO

LVPECL: V

*All caps should have < 5 ohms capacitive reactance at the clock output frequency

= 3.3V, 2.5V, 1.8V

DDO

OUTx

OUTxb

AC Coupled LVDS/LVPECL

= 3.3V

, 2.5V

, 1.8V

= 3.3V, 2.5V

DDO

OUTx

OUTxb

AC Coupled CMLDC Coupled LVDS

= 3.3V

, 2.5V

DDO

100

OUTx

OUTxb

VDD – 1.3V

5050

0.1uF*

AC Coupled HCSL

VDD

= 3.3V, 2.5V. 1.8V

DDO

0.1uF*

100

0.1uF*

Internally self-biased

For V

VDD

3.3 V

2.5 V

1.8 V

0.1uF*

OUTx

OUTxb

0.1uF*

= 0.35 V

R1 Ω R2 Ω

442

332

243

56.2

59.0

63.4

Standard

HCSL

Receiver

Figure 6.2. Supported Differential Output Terminations

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6.3.2 Differential Output Swing Modes

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

There are unique mode.

Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific reason to do otherwise. When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. Table 6.4 Differential Output Voltage Swing Control Registers on

page 37 lists the registers that control the output voltage swing. The output impedance in the Normal Swing Mode is 100 Ω differen-

tial. Any of the terminations shown in Figure 6.2 Supported Differential Output Terminations on page 36 are supported in this mode.

Differential High Swing Mode—When an output driver is configured in high swing mode, its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 Ω PCB traces. Any of the terminations shown in Figure 6.2 Supported Differential Output Terminations on page 36 are supported. The use of High Swing mode will result in larger pk-pk output swings that draw less power. The trade off will be slower rise and fall times.

Vpp_diff is 2 x Vpp_se as shown in Figure 6.3 Vpp_se and Vpp_diff on page 37.

two selectable differential output swing modes: Normal and High (also called low power mode). Each output can support a

OUTx

Vcm

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTx

Figure 6.3. Vpp_se and Vpp_diff

Table 6.4. Differential Output Voltage Swing Control Registers

Si5345 Si5344 Si5342

OUT0_AMPL 0x010A[6:4] 0x0114[6:4] 0x0114[6:4] Sets the voltage swing

OUT1_ AMPL 0x010F[6:4] 0x0119[6:4] 0x0119[6:4]

OUT2_ AMPL 0x0114[6:4] 0x0128[6:4] —

OUT3_ AMPL 0x0119[6:4] 0x012D[6:4] —

OUT4_ AMPL 0x011E[6:4] — —

OUT5_ AMPL 0x0123[6:4] — —

OUT6_ AMPL 0x0128[6:4] — —

OUT7_ AMPL 0x012D[6:4] — —

OUT8_ AMPL 0x0132[6:4] — —

OUT9_ AMPL 0x013C[6:4] — —

for the differential output drivers for both normal and high swing modes.

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6.3.3 Programmable Common Mode Voltage for Differential Outputs

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

The common to 2.3 V depending on the voltage available at the output's VDDO pin. Setting the common mode voltage is useful when dc coupling the output drivers. High swing mode may also cause an increase in the rise/fall time.

OUT0_CM 0x010A[3:0] 0x0114[3:0] 0x0114[3:0] Sets the common mode voltage for the dif-

OUT1_ CM 0x010F[3:0] 0x0119[3:0] 0x0119[3:0]

OUT2_ CM 0x0114[3:0] 0x0128[3:0] —

OUT3_ CM 0x0119[3:0] 0x012D[3:0] —

OUT4_ CM 0x011E[3:0] — —

OUT5_ CM 0x0123[3:0] — —

OUT6_ CM 0x0128[3:0] — —

OUT7_ CM 0x012D[3:0] — —

OUT8_ CM 0x0132[3:0] — —

OUT9_ CM 0x013C[3:0] — —

mode voltage (VCM) for the differential Normal and High Swing modes is programmable in 100 mV increments from 0.7

Table 6.5. Differential Output Common Mode Voltage Control Registers

Si5345 Si5344 Si5342

ferential output driver.

6.3.4 LVCMOS Output Terminations

LVCMOS outputs are dc-coupled as shown in Figure 6.4 LVCMOS Output Terminations on page 38.

DC Coupled LVCMOS

3.3V, 2.5V, 1.8V

DDO

= 3.3V

OUTx

, 1.8V

, 2.5V

OUTx

Figure 6.4. LVCMOS Output Terminations

LVCMOS

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6.3.5 LVCMOS Output Impedance and Drive Strength Selection

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

Each LVCMOS

driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programmable output impedance selections for each VDDO option as shown in Table 6.6 Output Impedance and Drive Strength Selections on

page 39. The value for the OUTx_CMOS_DRIVE bits are given.

Table 6.6. Output Impedance and Drive Strength Selections

VDDO OUTx_CMOS_DRV Source Impedance (Rs) Drive Strength (Iol/Ioh)

3.3 V 0x01 38 Ω 10 mA

0x02 30 Ω 12 mA

0x03* 22 Ω 17 mA

2.5 V 0x01 43 Ω 6 mA

0x02 35 Ω 8 mA

0x03* 24 Ω 11 mA

1.8 V 0x03* 31 Ω 5 mA

Note: Use of the lowest impedance setting is recommended for all supply voltages.

Table 6.7. LVCMOS Drive Strength Control Registers

Si5345 Si5344 Si5342

OUT0_CMOS_DRV 0x0109[7:6] 0x0113[7:6] 0x0113[7:6] LVCMOS output impe-

OUT1_ CMOS_DRV 0x010E[7:6] 0x0118[7:6] 0x0118[7:6]

dance.

OUT2_ CMOS_DRV 0x0113[7:6] 0x0127[7:6] —

OUT3_ CMOS_DRV 0x0118[7:6] 0x012C[7:6] —

OUT4_ CMOS_DRV 0x011D[7:6] — —

OUT5_ CMOS_DRV 0x0122[7:6] — —

OUT6_ CMOS_DRV 0x0127[7:6] — —

OUT7_ CMOS_DRV 0x012C[7:6] — —

OUT8_ CMOS_DRV 0x0131[7:6] — —

OUT9_ CMOS_DRV 0x0136[7:6] — —

6.3.6 LVCMOS Output Signal Swing

The signal

swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

silabs.com | Building a more connected world. Rev. 1.3 | 39

6.3.7 LVCMOS Output Polarity

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

When a

driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock on the OUTx pin is generated with the same polarity (in phase) with the clock on the OUTxb pin. The polarity of these clocks is configurable enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.

Table 6.8. LVCMOS Output Polarity Control Registers

Hex Address [Bit Field]

Function

Si5345 Si5344 Si5342

OUT0_INV 0x010B[7:6] 0x0115[7:6] 0x0115 [7:6]

OUT1_ INV 0x0110[7:6] 0x011A[7:6] 0x011A [7:6]

OUT2_ INV 0x0115[7:6] 0x0129[7:6] —

OUT3_ INV 0x011A[7:6] 0x012E[7:6] —

OUT4_ INV 0x011F[7:6] — —

Controls the output polarity of the OUTx and OUTxb pins when in LVCMOS mode. Selections are below in Table 6.9 Output

OUT5_ INV 0x0124[7:6] — —

OUT6_ INV 0x0129[7:6] — —

Polarity of OUTx and OUTxb Pins in LVCMOS Mode on page 40

OUT7_ INV 0x012E[7:6] — —

OUT8_ INV 0x0133[7:6] — —

OUT9_ INV 0x013D[7:6] — —

OUTx_INV

00 CLK CLK Both in phase (default)

01 CLK CLK OUTxb inverted

10 CLK CLK OUTx and OUTxb inverted

11 CLK CLK OUTx inverted

Table 6.9. Output Polarity of OUTx and OUTxb Pins in LVCMOS Mode

OUTx OUTxb Comment

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

6.3.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

Each differential output has four settings for control:

• Normal or Low Power Format

Amplitude (sometimes called Swing)

•

• Common Mode Voltage

• Stop High or Stop Low

The normal Format setting has a 100 Ω internal resistor between the plus and minus output pins. The Low Power Format setting removes this 100 Ω internal resistor and then the differential output resistance will be > 500 Ω. However as long as the termination impedance matches the differential impedance of the pcb traces the signal integrity across the termination impedance will be good. For the same output amplitude the Low Power Format will use less power than the Normal Format. The Low Power Format also has a lower rise/fall time than the Normal Format. See the Si5345/44/42 data sheet for the rise/fall time specifications. For LVPECL and LVDS standards, ClockBuilder Pro does not support the Low Power Differential Format. Stop High means that when the output driver is disabled the plus output will be high and the minus output will be low. Stop Low means that when the output driver is disabled the plus output will be low and the minus output will be high.

The Format, Amplitude and Common Mode settings for the various supported standards are shown in Table 6.10 Settings for LVDS,

LVPECL, and HCSL on page 41.

Table 6.10. Settings for LVDS, LVPECL, and HCSL

OUTx_FORMAT

Standard VDDO Volts OUTx_CM (Deci-

mal)

OUTx_AMPL

(Decimal)

001 = Normal Differential LVPECL 3.3 11 6

001 = Normal Differential LVPECL 2.5 11 6

002 = Low Power Differential LVPECL 3.3 11 3

002 = Low Power Differential LVPECL 2.5 11 3

001 = Normal Differential LVDS 3.3 3 3

001 = Normal Differential LVDS 2.5 11 3

001 = Normal Differential

Sub-LVDS

1.8 13 3

002 = Low Power Differential LVDS 3.3 3 1

002 = Low Power Differential LVDS 2.5 11 1

002 = Low Power Differential

Sub-LVDS

HCSL

1.8 13 1

3.3 11 3

2.5 11 3

1.8 13 3

Note:

The low-power format will cause the rise/fall time to increase by approximately a factor of two. See the Si5345/44/42 data sheet for more information.

The common-mode voltage produced is not compliant with LVDS standards; therefore ac coupling the driver to an LVDS receiver is highly recommended.

3. Creates HCSL compatible signal. See Figure 5.4 Si5342/44/45 Fault Monitors on page 25.

The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes. See 18. Setting the Differ-

ential Output Driver to Non-Standard Amplitudes for additional information.

silabs.com | Building a more connected world. Rev. 1.3 | 41

6.4 Output Enable/Disable

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

The OE

pin provides a convenient method of disabling or enabling the output drivers. When the OE pin is held high all outputs will be disabled. When the pin is not driven, the device defaults to all outputs on. Outputs in the enabled state can be individually disabled through register control. If the pin is high register control is disabled and all outputs will be disabled.

Table 6.11. Output Enable/Disable Control Registers

Si5345 Si5344 Si5342

OUTALL_

DISABLE_LOW

0x0102[0] 0x0102[0] 0x0102[0] Disables all output drivers: 0 - all outputs disa-

bled, 1 – all outputs enabled. This bit essentially has the same function as the OE pin if the OE pin is held low. If the OE pin is held high, then all outputs will be disabled regardless of the state of this register bit.

OUT0_OE 0x0108[1] 0x0112[1] 0x0112[1] Allows enabling/disabling individual output

OUT1_ OE 0x010D[1] 0x0117[1] 0x0117[1]

drivers. Note that the OE pin must be held low in order to enable an output.

OUT2_ OE 0x0112[1] 0x0126[1] —

OUT3_ OE 0x0117[1] 0x012B[1] —

OUT4_ OE 0x011C[1] — —

OUT5_ OE 0x0121[1] — —

OUT6_ OE 0x0126[1] — —

OUT7_ OE 0x012B[1] — —

OUT8_ OE 0x0130[1] — —

OUT9_ OE 0x013A[1] — —

6.4.1 Output Driver State When Disabled

The disabled state of an output driver is configurable as disable low or disable high.

Table 6.12. Output Driver State Control Registers

Si5345 Si5344 Si5342

OUT0_DIS_STATE 0x0109[5:4] 0x0113[5:4] 0x0113[5:4] Determines the state of an output driver

OUT1_ DIS_STATE 0x010E[5:4] 0x0118[5:4] 0x0118[5:4]

OUT2_ DIS_STATE 0x0113[5:4] 0x0127[5:4] —

OUT3_ DIS_STATE 0x0118[5:4] 0x012C[5:4] —

OUT4_ DIS_STATE 0x011D[5:4] — —

OUT5_ DIS_STATE 0x0122[5:4] — —

when disabled.

Selectable as:

Disable logic low

Disable logic high

OUT6_ DIS_STATE 0x0127[5:4] — —

OUT7_ DIS_STATE 0x012C[5:4] — —

OUT8_ DIS_STATE 0x0131[5:4] — —

OUT9_ DIS_STATE 0x013B[5:4] — —

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6.4.2 Synchronous Output Disable Feature

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Output Clocks

The output

drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the period to complete. The default state is for the synchronous output disable to be turned off.

Table 6.13. Synchronous Disable Control Registers

Si5345 Si5344 Si5342

OUT0_SYNC_EN 0x0109[3] 0x0113[3] 0x0113[3] Synchronous output disable. When this

OUT1_ SYNC_EN 0x010E[3] 0x0118[3] 0x0118[3]

OUT2_ SYNC_EN 0x0113[3] 0x0127[3] —

OUT3_ SYNC_EN 0x0118[3] 0x012C[3] —

OUT4_ SYNC_EN 0x011D[3] — —

feature is enabled, the output clock will always finish a complete period before disabling. When this feature is disabled, the output clock will disable immediately without waiting for the period to complete.

This feature is disabled by default.

OUT5_ SYNC_EN 0x0122[3] — —

OUT6_ SYNC_EN 0x0127[3] — —

OUT7_ SYNC_EN 0x012C[3] — —

OUT8_ SYNC_EN 0x0131[3] — —

OUT9_ SYNC_EN 0x013B[3] — —

6.5 Output Buffer Supply Voltage Selection

These power supply settings must match the actual VDDOx voltage so that the output driver operates properly.

Table 6.14. OUTx VDD Settings

Setting Name Description

OUTx_VDD_SEL_EN These bits are set to 1 and should not be changed

OUTx_VDD_SEL These bits are set by CBPro to match the expected VDDOx voltage. 0: 3.3 V; 1:

1.8 V; 2: 2.5 V; 3: Reserved

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Zero Delay Mode

7. Zero Delay Mode

A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in Figure 7.1 Si5345 Zero Delay Mode Set-up on page 44. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection in the Si5345. OUT3 and FB_IN pins are recommended for the external feedback in the Si5344. OUT1 or OUT2 are recommended with FB_IN in the Si5342. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for best performance. For this reason, customers should avoid using CMOS outputs for driving the external feedback path. Zero Delay Mode performance will degrade with low values of phase detector frequency (Fpfd). For this reason, ClockBuilder Pro will not enable Zero Delay Mode with an Fpfd of less than 128 kHz.

When the DSPLL is set for Zero-Delay Mode (ZDM), a hard reset request from either the RSTb pin or RST_REG register bit will have a delay of ~750 ms before executing. Any subsequent register writes to the device should be made after this time expires or they will be overwritten with the NVM values. Please contact Silicon Labs technical support for information on reducing this ZDM hard reset time.

IN0

IN1

IN2

IN3/FB_IN

100

IN3/FB_IN

÷P

Si5345/44/42

DSPLL

÷N

÷M

15GHz

LPFPD

÷5

÷R

VDDO0

OUT0 OUT0

VDDO1

OUT1 OUT1

VDDO2

OUT2 OUT2

VDDO7

OUT7 OUT7

VDDO8

OUT8 OUT8

VDDO9

OUT9 OUT9

External Feedback Path

Figure 7.1. Si5345 Zero Delay Mode Set-up

The following table lists the registers used for the Zero Delay mode.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Table 7.1. Zero Delay Mode Registers

Zero Delay Mode

Function

[Bit Field]

ZDM_EN 0x0487[0] 0: Disable zero delay mode.

1: Enable zero delay mode.

ZDM_IN_SEL 0x0487[2:1] Selects (normal feedback IN0-IN3) by creating an external feedback through

FB_IN (zero delay mode).

ZDM_AUTOSW_EN 0x0487[4] 0: Automatic switching disabled for zero-delay mode

1: Automatic input switching enabled and input clock selection governed by automatic input switching engine

Table 7.2. Input Clock Selection in Zero Delay Mode

ZDM_AUTO_SW_EN ZDM_EN IN_SEL_REGCTRL Input Clock Selection Governed by

0 0 0 IN_SEL[1:0] Pins

0 0 1 IN_SEL Register

0 1 0 IN_SEL[1:0] Pins

0 1 1 ZDM_IN_SEL Register

1 X X Input clock selection governed by automatic input

switching engine (see 5.1.2

Automatic Input Selection)

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Digitally-Controlled Oscillator (DCO) Mode

8. Digitally-Controlled Oscillator (DCO) Mode

An output that is controlled as a DCO is useful for simple tasks, such as frequency margining, CPU speed control, or just changing the output frequency. The output can also be used for more sophisticated tasks, such as FIFO management, by adjusting the frequency of the read or write clock to the FIFO or using the output as a variable Local Oscillator in a radio application.

The N dividers can be digitally controlled so that all outputs connected to the N divider change frequency in real time without any transition glitches. There are two ways to control the N divider :

Use the Frequency Increment/Decrement Pins or register bits.

Write directly to the numerator or denominator of the N divider.

The output N divider can be changed from its minimum value to its maximum value in very small fractional increments or in a single large increment. Each N divider has a value of Nx_NUM/Nx_DEN. Nx_NUM is a 44-bit word, and Nx_DEN is a 32-bit word. Clockbuilder Pro left-shifts these values as far as possible before writing them to the actual Nx_NUM and Nx_DEN registers. For example, an integer Nx divider of 30/1, when left shifted, becomes Nx_NUM=64424509440 (decimal) and Nx_DEN=2147483648 (decimal). By adjusting the size of the Nx_NUM and Nx_DEN but keeping the ratio the same, the resolution of the LSbit of numerator or denominator can be controlled.

When changing the N divider(s) to fractional values, the setting name, N_PIBYP[4:0], must be a 0 for the N divider that is being changed. This applies when using FINC/FDEC or when directly writing to the N divider. After changing N_PIBYP a soft reset must occur to update the part.

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8.1 DCO with Frequency Increment/Decrement Pins/Bits

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Digitally-Controlled Oscillator (DCO) Mode

The Nx_FSTEPW

(Frequency STEP Word) is a 44-bit word that is used to change the value of the Nx_NUM word. Whenever an FINC or FDEC is asserted, the Nx_FSTEPW will automatically add or subtract from the Nx_NUM word so that the output frequency will, respectively, increment (FINC) or decrement (FDEC).

Each of the N dividers can be independently stepped up or down in numerical, predefined steps with a maximum resolution that varies from ~ 0.05 ppb to a ~0.004 ppb depending upon the frequency plan. One or more N dividers can be controlled by FINC/FDEC at the same time by use of the N_FSTEP_MSK bits. Any N divider that is masked by its corresponding bit in the N_FSTEP_MSK field will not change when FINC or FDEC is asserted. The magnitude of the frequency change caused by FINC or FDEC is determined by the value of the Nx_FSTEPW word and the magnitude of the word in Nx_NUM. For a specific frequency step size, it may be necessary to adjust the Nx_NUM value while keeping the ratio of Nx_NUM/Nx_DEN the same. When the FINC or FDEC pin or register bit is asserted, the selected N dividers will have their numerator changed by the addition or subtraction of the Nx_FSTEPW so that an FINC will increase the output frequency, and an FDEC will decrease the output frequency. A FINC or FDEC can be followed by another FINC or FDEC in 1 μs minimum.

Because the output frequency = FVCO*Nx_DEN/(Rx*Nx_NUM), subsequent changes to Nx_NUM by the Nx_FSTEPW will not produce exactly the same output frequency change. The amount of error in the frequency step is extremely small and, in a vast number of applications, will not cause a problem. When consecutive frequency steps must be exactly the same, it is possible to set FINC and FDEC to change the Nx_DEN instead of Nx_NUM, and then, consecutive FINCs or FDECs will be exactly the same frequency change. However, there are some special setups that are necessary to achieve this. For more information, contact Silicon Labs at https://www.silabs.com/

support/pages/contacttechnicalsupport.aspx.

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Si5345

N0_FSTEP_MASK

0x0339

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Digitally-Controlled Oscillator (DCO) Mode

Multi

Synth

Frequency

Step Word

0x033B – 0x0340

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CS

SPI/

FINC

FDEC

0x001D

N1_FSTEP_MASK

N2_FSTEP_MASK

N3_FSTEP_MASK

N4_FSTEP_MASK

0x0339

Multi

Synth

Frequency

Step Word

0x0341 – 0x0346

Multi

Synth

Frequency

Step Word

0x0347 – 0x034C

Multi

Synth

Frequency

Step Word

0x034D – 0x0352

Multi

Synth

Frequency

Step Word

0x0353 – 0x0358

N N

FINC

FDEC

Figure 8.1. DCO with FINC/FDEC Pins or Bits

Table 8.1. Frequency Increment/Decrement Control Registers

Si5345 Si5344 Si5342

FINC 0x001D[0] 0x001D[0] 0x001D[0] Asserting this bit will increase the DSPLL output

frequency by the frequency step word.

FDEC 0x001D[1] 0x001D[1] 0x001D[1] Asserting this bit will decrease the DSPLL out-

put frequency by the frequency step word.

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Digitally-Controlled Oscillator (DCO) Mode

N0_FSTEPW 0x033B[7:0]-

0x033B[7:0]-

This is a 44-bit frequency step word for each of the Multi-

0x0340[7:0]

N1_FSTEPW 0x0341[7:0]-

0x0346[7:0]

N2_FSTEPW 0x0347[7:0]-

0x0340[7:0]

0x0341[7:0]-

0x0346[7:0]

0x0347[7:0]-

0x0340[7:0]

0x0341[7:0]-

0x0346[7:0]

—

Synths. The Nx_FSTEPW will be added or subtracted to the output frequency during assertion of the FINC/FDEC bits or pins. The Nx_FSTEPW is calculated based on the frequency configuration and is easily determined using the ClockBuilder Pro

0x034C[7:0]

N3_FSTEPW 0x034D[7:0]-

0x0352[7:0]

N4_FSTEPW 0x0353[7:0]-

0x034C[7:0]

0x034D[7:0]-

—

0x0352[7:0]

— —

0x0358[7:0]

N_FSTEP_MSK 0x0339[4:0] 0x0339[3:0] 0x0339[1:0] This mask bit determines if a FINC or FDEC af-

fects N0, N1, N2, N3, N4. 0 = FINC/FDEC will Increment/decrement

the Nx_FSTEPW to the selected MultiSynth(s), 1 = Ignores FINC/FDEC.

8.2 DCO with Direct Register Writes

When an

N divider numerator (Nx_NUM) and its corresponding update bit (Nx_UPDATE) are written, the new numerator value will take effect, and the output frequency will change without any glitches. The N divider numerator and denominator terms (Nx_NUM and Nx_DEN) can be left- and right-shifted so that the least significant bit of the numerator word represents the exact step resolution that is needed for your application. Each N divider has an update bit (Nx_UPDATE) that must be written to cause the written values to take effect. All N dividers can be updated at the same time by writing the N_UPDATE_ALL bit. Writing this bit will NOT cause any output glitching on an N divider that did not have its numerator or denominator changed.

When changing the N divider denominator (Nx_DEN), it is remotely possible that a small phase shift may occur at the exact time of the frequency change. However, with the proper setup, it is possible to change Nx_DEN and never have a phase shift. If your application requires changing an N divider denominator, contact Silicon Labs at https://www.silabs.com/support/pages/contacttechnicalsup-

port.aspx for support.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

9. Serial interface

Configuration and operation of the Si5345/44/42 is controlled by reading and writing registers using the I2C or SPI interface. Both of these serial interfaces are based on 8-bit addressing, which means that the page byte must be written every time you need to access a

different page in the register map. See the PAGE byte at register 0x0001 for more information. The I2C_SEL pin selects I2C or SPI operation. The Si5345/44/42 supports communication with a 3.3 or 1.8 V host by setting the IO_VDD_SEL (0x0943[0]) configuration bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit.

Host = 1.8V

Host = 3.3V

I2C_SEL pin = High

1.8V

SDA

HOST

SCLK

IO_VDD_SEL = 1

3.3V

SDA

HOST

SCLK

SPI 4-Wire SPI 3-Wire

I2C_SEL pin = Low

SPI_3WIRE = 0

IO_VDD_SEL = 0

(Default) (Default)

1.8V

VDDA

Si5345/44/42

1.8V3.3V

VDD

SPI

HOST

SDO

SDI

SCLK

1.8V

SDA

SCLK

IO_VDD_SEL = 1 IO_VDD_SEL = 1

3.3V

VDDA

Si5345/44/42

1.8V3.3V

VDD

SPI

HOST

SDO

SDI

SCLK

3.3V

SDA

SCLK

I2C_SEL pin = Low

SPI_3WIRE

= 1

IO_VDD_SEL = 0

(Default)

1.8V3.3V

VDD

VDDA

SDI

SDO

SCLK

Si5345/44/42 Si5345/44/42

1.8V3.3V

VDD

VDDA

SDI

SDO

SCLK

Si5345/44/42

SPI

HOST

SPI

HOST

1.8V

3.3V

SDIO

SCLK

SDIO

SCLK

VDDA

SDIO SCLK

VDDA

SDIO SCLK

Si5345/44/42

1.8V3.3V

VDD

1.8V3.3V

VDD

Figure 9.1. I2C/SPI Device Connectivity Configurations

Table 9.1 I2C/SPI Register Settings

on page 50 lists register settings of interest for the I2C/SPI.

Table 9.1. I2C/SPI Register Settings

Function

[Bit Field]

IO_VDD_SEL 0x0943[0] The IO_VDD_SEL bit determines whether the VDD or VDDA supply voltage is used for

the serial port, control pins, and status pins voltage references. See the register map description of this bit for additional details.

SPI_3WIRE 0x002B[3] The SPI_3WIRE configuration bit selects the option of 4-wire or 3-wire SPI communica-

tion. By default, the SPI_3WIRE configuration bit is set to the 4-wire option. In this mode, the Si5345/44/42 will accept write commands from a 4-wire or 3- wire SPI host allowing configuration of device registers. For full bidirectional communication in 3-wire mode, the host must write the SPI_3WIRE configuration bit to “1”.

If neither serial interface is used, leave pins I2C_SEL, A1/SDO, and A0/CS disconnected, and tie SDA/SDIO and SCLK low.

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9.1 I2C Interface

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

When in Fast-Mode (400 kbps) and supports burst data transfer with auto address increments. The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 9.4 I2C Write Operation on page 51. Both the SDA and SCL pins must be connected to a supply via an external pull-up (4.7 kΩ) as recommended by the I2C specification as shown in Figure 9.2 I2C Configu-

ration on page 51. Two address select bits (A0, A1) are provided allowing up to four Si5345/44/42 devices to communicate on the

same bus. This also allows four choices in the I2C address for systems that may have other overlapping addresses for other I2C devices.

I2C mode, the serial interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or

VDDI2C

VDD

I2C_SEL

To I

or Host

C Bus

LSBs of I

Address

Figure 9.2. I2C Configuration

SDA

SCLK

Si5345/44/42

The 7-bit slave device address of the Si5345/44/42 consists of a 5-bit fixed address plus 2 pins which are selectable for the last two bits, as shown in Figure 9.3 7-bit I2C Slave Address Bit-Configuration on page 51.

0123456

Slave Address

Figure 9.3. 7-bit I2C Slave Address Bit-Configuration

Data is transferred MSB first in 8-bit words as specified by the I2C specification. address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9.6 SPI Interface Connections on page 53. A write burst operation is also shown where subsequent data words are written using to an auto-incremented address.

1 1 0 1 0 A0

A write command consists of a 7-bit device (slave)

Write Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] PA

Write Operation - Burst (Auto Address Increment)

S 0 A Reg Addr [7:0]Slv Addr [6:0] A Data [7:0] A Data [7:0] PA

Reg Addr +1

Host

Si5345/44/42

1 – Read 0 – Write A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition

Figure 9.4. I2C Write Operation

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in Figure 9.5 I2C Read Operation

on page 52.

Read Operation – Single Byte

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

S 1 ASlv Addr [6:0] Data [7:0] PN

Read Operation - Burst (Auto Address Increment)

S 0 A Reg Addr [7:0]Slv Addr [6:0] A P

S 1 ASlv Addr [6:0] Data [7:0] A PNData [7:0]

Reg Addr +1

Host

Si5345/44/42

1 – Read 0 – Write

Host

Si5345/44/42

A – Acknowledge (SDA LOW) N – Not Acknowledge (SDA HIGH) S – START condition P – STOP condition

Figure 9.5. I2C Read Operation

The SMBUS interface requires a timeout. The error flags are found in the registers listed in Table 9.2 SMBus Timeout Error Bit Indica-

tors on page 52.

Table 9.2. SMBus Timeout Error Bit Indicators

[Bit Field]

SMBUS_TIMEOUT 0x000C[5] 1 if there is a SMBus timeout error.

SMBUS_TIMEOUT_FLG 0x0011[5] 1 if there is a SMBus timeout error.

Function

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9.2 SPI Interface

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

When in wire interface consists of a clock input (SCLK), a chip select input (CS), serial data input (SDI), and serial data output (SDO). The 3wire interface combines the SDI and SDO signals into a single bidirectional data pin (SDIO). Both 4-wire and 3-wire interface connections are shown in Figure 9.6 SPI Interface Connections on page 53.

SPI mode, the serial interface operates in 4-wire or 3-wire depending on the state of the SPI_3WIRE configuration bit. The 4-

SPI 3-Wire

SPI_3WIRE = 1

I2C_SEL

SPI 4-Wire

SPI_3WIRE = 0

I2C_SEL

To SPI

Host

SDI

SDO

To SPI

Host

SDIO

SCLK

Si5345/44/42

Figure 9.6. SPI Interface Connections

Table 9.3. SPI Command Format

Si5345/44/42

Instruction

Set Address 000x xxxx 8-bit Address — —

Write Data 010x xxxx 8-bit Data — —

Read Data 100x xxxx 8-bit Data — —

Write Data + Address Increment 011x xxxx 8-bit Data — —

Read Data + Address Increment 101x xxxx 8-bit Data — —

Burst Write Data 1110 0000 8-bit Address 8-bit Data 8-bit Data

1. X = don’t care (1 or 0)

The Burst Write Command is terminated by de-asserting /CS (/CS = high)

There is no limit to the number of data bytes that follow the Burst Write Command, but the address will wrap around to zero in the byte after address 255 is written.

Writing or reading data consist of sending a “Set Address” command followed by a “Write Data” or “Read Data” command. The 'Write Data + Address Increment' or “Read Data + Address Increment” commands are available for cases where multiple byte operations in sequential address locations is necessary. The “Burst Write Data” instruction provides a compact command format for writing data since it uses a single instruction to define starting address and subsequent data bytes. Figure 9.7 Example Writing Three Data Bytes

Using the Write Commands on page 54 shows an example of writing three bytes of data using the write commands. This demon-

strates that the “Write Burst Data” command is the most efficient method for writing data to sequential address locations. Figure

9.8 Example of Reading Three Data Bytes Using the Read Commands on page 54 provides a similar comparison for reading data

with the read commands. Note that there is no burst read, only read increment.

Ist Byte

2nd Byte 3rd Byte Nth Byte

2,3

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

‘Set Address’ and ‘Write Data’

‘Set Addr’ Addr [7:0] ‘Write Data’ Data [7:0]

‘Set Address’ and ‘Write Data + Address Increment’

‘Set Addr’ Addr [7:0] ‘Write Data + Addr Inc’ Data [7:0]

‘Write Data + Addr Inc’ Data [7:0]

‘Burst Write Data’

Serial interface

‘Burst Write Data’ Addr [7:0] Data [7:0] Data [7:0] Data [7:0]

Si5345/44/42Host

Figure 9.7. Example Writing Three Data Bytes Using the Write Commands

Si5345/44/42Host

‘Set Address’ and ‘Read Data’

‘Set Addr’ Addr [7:0] ‘Read Data’ Data [7:0]

‘Set Address’ and ‘Read Data + Address Increment’

‘Set Addr’ Addr [7:0] ‘Read Data + Addr Inc’ Data [7:0]

‘Read Data + Addr Inc’ Data [7:0]

Si5345/44/42Host

Figure 9.8. Example of Reading Three Data Bytes Using the Read Commands

The timing diagrams for the SPI commands are shown in Figures Figure

9.10 SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing on page 56, Figure 9.11 SPI “Read Data” and “Read Data + Address Increment” Instruction Timing on page 57, and Figure 9.12 SPI “Burst Data Write” Instruction Timing on page 57.

silabs.com | Building a more connected world. Rev. 1.3 | 54

Si5345/44/42Host

9.9

SPI “Set Address” Command Timing on page 55, Figure

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Set Address’ Command

> 2

SCLK

Periods

Set Address Instruction Base Address

01234567

> 2.0

SCLK

Periods

0123456

Command

Si5345/44/42Host

Figure 9.9. SPI “Set Address” Command Timing

Si5345/44/42Host

Don’t Care

High Impedance

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Write Data’ or ‘Write Data + Address Increment’

Command

> 2

SCLK

Periods

Write Data instruction

Data byte @ base address + 1

01234567

> 2.0

SCLK

Periods

01234567

Command

Si5345/44/42Host

Figure 9.10. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing

Si5345/44/42Host

Don’t Care

High Impedance

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Serial interface

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

‘Read Data’ or ‘Read Data + Address Increment’

Command

> 2.0

SCLK

Periods

Read Data instruction

Read byte @ base address + 1

01234567

> 2.0

SCLK

Periods

01234567

Command

SCLK

4-Wire

SDI

SDO

3-Wire

SDIO

Si5345/44/42Host

Don’t Care

High Impedance

Figure 9.11. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing

‘Burst Data Write’ Command

Burst Write Instruction Base address

Si5345/44/42Host

01234567

7 7 7

Si5345/44/42Host

Don’t Care

data byte @ base address

0123456 0123456 01234567

0123456 0123456 0123456

High Impedance

data byte @ base address +n

Command

Figure 9.12. SPI “Burst Data Write” Instruction Timing

Note that for all SPI communication the chip select (CS) must be high for the minimum time period between commands. When chip select goes

high it indicates the termination of the command. The SCLK can be turned off between commands, particularly if there are

very long delays between commands.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Field Programming

10. Field Programming

To simplify design and software development of systems using the Si5345/44/42, a field programmer is available. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB), as well as “in-socket” programming of Si5345/44/42 sample devices. Refer to www.silabs.com/CBProgrammer for information about this kit.

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

XA/XB External References

11. XA/XB External References

11.1 Performance of External References

An external standard non-pullable crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 11.1 Crystal Resonator and External Reference Clock Connection Options on page 59. The device includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Although the device includes built-in XTAL load capacitors (CL) of 8 pF, crystals with load capacitances up to 18 pF can also be accommodated. See AN905: Si534x External References; Optimizing Performance for more information on the performance of various XO's with these devices. The recommended crystal suppliers are listed in the Si534x/8x Jitter Attenuators Recommended Crystal,

TCXO and OCXOs Reference Manual.

25-54 MHz

XTAL

XB XA

2xC

OSC

Crystal Resonator

Connection

25-54 MHz

XO/Clock LVCMOS

0.1 uf

XB XA

2xC

OSC

LVCMOS XO/Clock

Connection

0.1 uf

2xC

C1 is recommended to

increase the slew rate at

nc nc

÷ P

REF

Note: See Pin

Descriptions for

X1/X2 connections

2xC

÷ P

REF

25-54 MHz

XO/Clock

0.1 uf

2xC

Note: See Datasheet for input clock specifications

0.1 uf

XB XA

2xC

OSC

Differential XO/Clock

Connection

nc nc

÷ P

REF

Figure 11.1. Crystal Resonator and External Reference Clock Connection Options

3.3V* These settings should be done if there CMOS level is up to 4 V pp to limit the input at Xa to less than 2V ppse

The Si5345/44/42 accepts a clipped sine wave, CMOS, or differential reference clock on the XA/XB interface. Most clipped sine wave and CMOS

TCXOs have insufficient drive strength to drive a 100 Ω or 50 Ω load. For this reason, place the TCXO as close to the Si5345/44/42 as possible to minimize PCB trace length. In addition, ensure that both the Si5345/44/42 and the TCXO are both connected directly to the ground plane. Figure 11.2 Clipped Sine Wave TCXO Output on page 60 shows the recommended method of connecting a clipped sine wave TCXO to the Si5345/44/42. Because the Si5345/44/42 provides dc bias at the XA and XB pins, the ~800 mV peak-peak swing can be input directly into the XA interface of the Si5345/44/42 once it has been ac-coupled. Because the signal is single-ended, the XB input is ac-coupled to ground. Note that when using a single-ended XO, the XO signal must be driven on XA. If XA is not driven, the device will report an LOSXAXB alarm. Figure 11.3 CMOS TCXO Output on page 60 illustrates the recommended method of connecting a CMOS rail-to-rail output to the XA/XB inputs of the Si5345/44/42. The resistor network attenuates the rail-to-rail output swing to ensure that the maximum input voltage swing at the XA pin is less than 1.6 V pk-pk. The signal is ac-coupled before connecting it to the Si5345/44/42 XA input.

If an external oscillator is used as the XA/XB reference, it is important to use a very low phase noise external oscillator because there is essentially no jitter attenuation (up to 1 MHz) from the XA/XB pins to the outputs. Before selecting an external oscillator at XA/XB, it is important to first test the output jitter to determine if the output jitter degradation from the use of the external oscillator is acceptable.

To achieve the lowest output jitter the best approach is usually to use a crystal in the range of 48–54 MHz at XA/XB.

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V3P3

Si5345, Si5344, Si5342 Rev. D Family Reference Manual

XA/XB External References

TCXO

VDD

100 nF

TCXO

GND

OUT

100 nF

Figure 11.2. Clipped Sine Wave TCXO Output

V3P3

VDD

OUT

453

GND

100 nF

453

Si5345/44/42

100 nF

Figure 11.3. CMOS TCXO Output

The Si5345/44/42 can also accommodate an external reference clock (REFCLK) instead of a crystal. Selection between the external XTAL or REFCLK is controlled by XAXB_EXTCLK_EN, the LSB of register 0x090E. The internal crystal loading capacitors (CL) are disabled when an external clock source is selected. A PXAXB prescale divider is available to accommodate external clock frequencies higher than 125 MHz as shown in 11.2 Recommended Crystals and External Oscillators. For best jitter performance, keep the REFCLK frequency above 40 MHz. To minimize jitter at the XA/XB pins, the rise time of the XA/XB signals should be as fast as possible. Though clipped sine wave TCXOs can be used, they are not recommended because the output jitter will increase compared to a TCXO with a CMOS output.

For applications with loop BW values less than 10 Hz that require low wander output clocks, using a TCXO as the XA/XB reference source should be considered to avoid the wander of a crystal. For more infomation on recommended crystals, TCXOs and guidance for their use, see "AN1093: Achieving Low Jitter Using an Oscillator Reference with the Si5342-47 Jitter Attenuators", "AN905: Si534x Ex-

ternal References; Optimizing Performance” and “Si534x-8x Jitter Attenuators, Recommended Crystal, TCXO and OCXOs Reference Manual".

11.2 Recommended Crystals and External Oscillators

See Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual for more information.

11.3 Register Settings to Control External XTAL Reference

The following registers can be used to control and make adjustments for the external reference source used.

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11.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register

Table 11.1. XA/XB External Clock Selection Register

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Function

[Bit Field]

XAXB_EXTCLK_EN 090E[0] This bit selects between the XTAL or external REFCLK on the XA/XB pins. The de-

fault is XTAL = 0

This bit selects between XTAL or external REFCLK on the XA/XB pins. Set this bit to use the external REFCLK.

11.3.2 PXAXB Pre-scale Divide Ratio for Reference Clock Register

Table 11.2. Pre-Scale Divide Ratio Register

Function

[Bit Field]

PXAXB 0206[1:0] This is a two bit value that sets the divider value.

Table 11.3 Pre-Scale Divide Values on page 61 lists the input values for the two-bit field and the corresponding divider values.

Table 11.3. Pre-Scale Divide Values

Value (Decimal) PXAXB Divider Value

0 1

1 2

2 4

3 8

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Crystal and Device Circuit Layout Recommendations

12. Crystal and Device Circuit Layout Recommendations

The main layout issues that should be carefully considered include the following:

•

Number and size of the ground vias for the Epad

• Output clock trace routing

• Input clock trace routing

• Control and Status signals to input or output clock trace coupling

• Xtal signal coupling

• Xtal layout (See 12.1.2 Si5345 Crystal Guidelines and 12.2.2 Si5342/44 Crystal Guidelines for important crystal layout guidelines.)

If the application uses a crystal for the XAXB inputs a shield should be placed underneath the crystal connected to the X1 and X2 pins to provide the best possible performance. The shield should not be connected to the ground plane and the planes underneath should have as little under the shield as possible. It may be difficult to do this for all the layers, but it is important to do this for the layers that are closest to the shield.

12.1 64-Pin QFN Si5345 Layout Recommendations

This section details the recommended guidelines for the crystal layout of the 64-pin Si5345 device using an example 8-layer PCB. The following are the descriptions of each of the eight layers.

Layer 1: device layer, with low speed CMOS control/status signals, ground flooded

Layer 2: crystal shield

Layer 3: ground plane

Layer 4: power distribution, ground flooded

Layer 5: power routing layer

Layer 6: ground input clocks, ground flooded

Layer 7: output clocks layer

Layer 8: ground layer

Figure 12.1 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1) on page 63 is the top layer layout of the Si5345

device mounted on the top PCB layer. This particular layout was designed to implement either a crystal or an external oscillator as the XA/XB reference. The crystal/ oscillator area is outlined with the white box around it. In this case, the top layer is flooded with ground. Note that this layout has a resistor in series with each pin of the crystal. In typical applications, these resistors should be removed.

12.1.1 Si5345 Applications without a Crystal

For applications that do not use a crystal, leave X1 and X2 pins as “no connect”. Do not tie to ground. There is no need for a crystal shield or the voids underneath the shield. The XA/XB connection should be treated as a high speed critical path that is ac-coupled and terminated at the end of the etch run. The layout should minimize the stray capacitance from the XA pin to the XB pin. Jitter is very critical at the XAXB pins and therefore split termination and differential signaling should be used whenever possible.

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12.1.2 Si5345 Crystal Guidelines

The following are five recommended crystal guidelines:

1. Place the crystal as close as possible to the XA/XB pins.

2. DO NOT connect the crystal's GND pins to PCB gnd.

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3. Connect

the crystal's GND pins to the DUT's X1 and X2 pins via a local crystal GND shield placed around and under the crystal. See

Figure 12.1 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1) on page 63 at the bottom left for an illustration of

how to create a crystal GND shield by placing vias connecting the top layer traces to the shield layer underneath. Note that a zoom view of the crystal shield layer on the next layer down is shown in Figure 12.2 Zoom View Crystal Shield Layer, Below the Top Layer

(Layer 2) on page 64.

4. Minimize traces adjacent to the crystal/oscillator area especially if they are clocks or frequently toggling digital signals.

5. In general do not route GND, power planes/traces, or locate components on the other side, below the crystal GND shield. As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing, then place the next reference plane in the stack-up at least two layers away or at least 0.05 inches away. The Si5345 should have all layers underneath the ground shield removed if possible.

Figure 12.1. 64-pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1)

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Figure 12.2. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2)

Figure 12.2

Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) on page 64 shows the layer that implements the shield

underneath the crystal. The shield extends underneath the entire crystal and the X1 and X2 pins. This layer also has the clock input pins. The clock input pins go to layer 2 using vias to avoid crosstalk. As soon as the clock inputs are on layer 2, they have a ground shield above, below, and on the sides for protection.

Figure 12.3 Crystal Ground Plane (Layer 3) on page 65 is the ground plane and shows a void underneath the crystal shield. Figure

12.4 Power Plane (Layer 4) on page 66 is a power plane and shows the clock output power supply traces. The void underneath the

crystal shield is continued.

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Figure 12.3. Crystal Ground Plane (Layer 3)

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Figure 12.4. Power Plane (Layer 4)

Figure 12.5 Layer 5 Power Routing on Power Plane (Layer 5) on page 67 shows layer 5, which is the power plane with the power

routed to the clock output power pins.

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Figure 12.5. Layer 5 Power Routing on Power Plane (Layer 5)

Figure 12.6 Ground Plane (Layer 6)

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on page 68 is another ground plane similar to layer 3.

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Figure 12.6. Ground Plane (Layer 6)

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12.1.3 Output Clocks

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Figure 12.7

Output Clock Layer (Layer 7) on page 69 shows the output clocks. Similar to the input clocks the output clocks have vias

that immediately go to a buried layer with a ground plane above them and a ground flooded bottom layer. There is a ground flooding between the clock output pairs to avoid crosstalk. There should be a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6.

Figure 12.7. Output Clock Layer (Layer 7)

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Figure 12.8. Bottom Layer Ground Flooded (Layer 8)

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12.2 44-Pin QFN Si5344/42 Layout Recommendations

This section details the layout recommendations for the 44-pin Si5344 and Si5342 devices using an example 6-layer PCB.

The following guidelines details images of a six layer board with the following stack:

Layer 1: device layer, with low speed CMOS control/status signals, ground flooded

Layer 2: crystal shield, output clocks, ground flooded

Layer 3: ground plane

Layer 4: power distribution, ground flooded

Layer 5: input clocks, ground flooded

Layer 6: low-speed CMOS control/status signals, ground flooded

This layout

was designed to implement either a crystal or an external oscillator as the XAXB reference. The top layer is flooded with ground. The clock output pins go to layer 2 using vias to avoid crosstalk during transit. When the clock output signals are on layer 2 there is a ground shield above, below and on all sides for protection. Output clocks should always be routed on an internal layer with ground reference planes directly above and below. The plane that has the routing for the output clocks should have ground flooded near the clock traces to further isolate the clocks from noise and other signals.

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12.2.1 Si5342/44 Applications without a Crystal

application does not use a crystal, then the X1 and X2 pins should be left as “no connect” and should not be tied to ground. In

If the addition, there is no need for a crystal shield or the voids underneath the shield. If there is a differential external clock input on XAXB there should be a termination circuit near the XA and XB pins. This termination circuit should be two 50 Ω resistors and one 0.1 μF cap connected in the same manner as on the other clock inputs (IN0, IN1 and IN2). The clock input on XA/XB must be ac-coupled. Care should be taken to keep all clock inputs well isolated from each other as well as any other dynamic signal.

Figure 12.9. Device Layer (Layer 1)

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12.2.2 Si5342/44 Crystal Guidelines

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Figure 12.10

Crystal Shield Layer 2 on page 73 is the second layer. The second layer implements the shield underneath the crystal.

The shield extends underneath the entire crystal and the X1 and X2 pins. There should be no less than 12 vias to connect the X1 and X2 planes on layers 1 and 2. These vias are not shown in any other figures. All traces with signals that are not static must be kept well away from the crystal and the X1 and X2 plane.

Figure 12.10. Crystal Shield Layer 2

The following figure is the ground plane and shows a void underneath the crystal shield.

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Figure 12.11. Ground Plane (Layer 3)

The following figure is a power plane showing the clock output power supply traces. The void underneath the crystal shield is continued.

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Figure 12.12. Power Plane and Clock Output Power Supply Traces (Layer 4)

The following

figure shows layer 5 and the clock input traces. Similar to the clock output traces, they are routed to an inner layer and

surrounded by ground to avoid crosstalk.

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Figure 12.13. Clock Input Traces (Layer 5)

The following

figure shows the bottom layer, which continues the void underneath the shield. Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue. PCB ground can be placed under the XTAL Ground shield (X1/X2) as long as the PCB ground is at least 0.05 inches below it.

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Figure 12.14. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer)

For any

high-speed, low-jitter application, the clock signal runs should be impedance-controlled to 100 Ω differential or 50 Ω singleended. Differential signaling is preferred because of its increased immunity to common-mode noise. All clock I/O runs should be properly terminated.

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Power Management

13. Power Management

13.1 Power Management Features

Several unused functions can be powered down to minimize power consumption. The registers listed in Table 13.1 Power-Down Regis-

ters on page 78 are used for powering down different features.

Table 13.1. Power-Down Registers

Si5345 Si5344 Si5342

PDN 0x001E[0] 0x001E[0] 0x001E[0] This bit allows the device to be powered down.

The serial interface remains powered.

OUT0_PDN 0x0108[0] 0x0112[0] 0x0112[0] Powers down all unused clock outputs.

OUT1_PDN 0x010D[0] 0x0117[0] 0x0117[0]

OUT2_PDN 0x0112[0] 0x0126[0]

OUT3_PDN 0x0117[0] 0x012B[0]

OUT4_PDN 0x011C[0]

OUT5_PDN 0x0121[0]

OUT6_PDN 0x0126[0]

OUT7_PDN 0x012B[0]

OUT8_PDN 0x0130[0]

OUT9_PDN 0x0135[0]

OUT_PDN_ALL 0x0145[0] 0x0145[0] 0x0145[0] Power down all outputs

XAXB_EXTCLK_EN 0x090E[1] 0 to use a crystal at the XAXB pins, 1 to use an

external clock source at the XAXB pins

13.2 Power Supply Recommendations

The power chip regulation to minimize the impact of board level noise on clock jitter. Following conventional power supply filtering and layout techniques will further minimize signal degradation from the power supply.

It is recommended to use a 0402 1 μF ceramic capacitor on each power supply pin for optimal performance. If the supply voltage is extremely noisy, it might be necessary to use a ferrite bead in series between the supply voltage and the power supply pin.

supply filtering generally is important for optimal timing performance. The Si5345/44/42 devices have multiple stages of on-

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13.3 Power Supply Sequencing

Four classes of supply voltages exist on the Si5345/44/42:

VDD = 1.8 V ± 5% (Core digital supply)

VDDA = 3.3 V ± 5% (Analog supply)

VDDOx = 1.8/2.5/3.3 V ± 5% (Clock output supply)

VDDS = 1.8/3.3 V ± 5% (Digital I/O supply)

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Power Management

There is

no requirement for power supply sequencing unless the output clocks are required to be phase aligned with each other. In this case, the VDDO of each clock which needs to be aligned must be powered up before VDD and VDDA. VDDS has no effect on output clock alignment.

If output-to-output alignment is required for applications where it is not possible to properly sequence the power supplies, then the output clocks can be aligned by asserting the SOFT_RST 0x001C[0] or Hard Reset 0x001E[1] register bits or driving the RSTB pin. Note that using a hard reset will reload the register with the contents of the NVM and any unsaved changes will be lost.

Note: One may observe that when powering up the VDD = 1.8 V rail first, that the VDDA = 3.3 V rail will initially follow the 1.8 V rail. Likewise, if the VDDA rail is powered down first then it will not drop far below VDD until VDD itself is powered down. This is due to the pad I/O circuits which have large MOSFET switches to select the local supply from either the VDD or VDDA rails. These devices are relatively large and yield a parasitic diode between VDD and VDDA. Please allow for both VDD and VDDA to power-up and powerdown before measuring their respective voltages.

13.4 Grounding Vias

The pad on the bottom of the device functions as both the sole electrical ground and primary heat transfer path. Hence it is important to minimize the inductance and maximize the heat transfer from this pad to the internal ground plane of the PCB. Use no fewer than 25 vias from the center pad to a ground plane under the device. In general, more vias will perform better. Having the ground plane near the top layer will also help to minimize the via inductance from the device to ground and maximize the heat transfer away from the device.

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Si5345 Register Map

14. Si5345 Register Map

14.1 Base vs. Factory Preprogrammed Devices

The Si5345/44/42 devices can be ordered as “base” or “factory-preprogrammed” (also known as “custom OPN”) versions.

14.1.1 “Base” Devices (a.k.a. “Blank” Devices)

Example “base” orderable part numbers (OPNs) are of the form “Si5345A-D-GM” or “Si5344B-D-GM”.

Base devices are available for applications where volatile reads and writes are used to program and configure the device for a particular application.

Base devices do not power up in a usable state (all output clocks are disabled).

Base devices are, however, configured by default to use a 48 MHz crystal on the XA/XB reference and a 1.8 V compatible I/O voltage setting for the host I2C/SPI interface.

Additional programming of a base device is mandatory to achieve a usable configuration.

See the on-line lookup utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clockbuilder-lookup.aspx to access the default configuration plan and register settings for any base OPN.

14.1.2 “Factory Preprogrammed” (Custom OPN) Devices

Factory preprogammed devices use a “custom OPN”, such as Si5345A-D-xxxxx-GM, where xxxxx is a sequence of characters assigned by Silicon Labs for each customer-specific configuration. These characters are referred to as the “OPN ID”. Customers must initiate custom OPN creation using the ClockBuilder Pro software.

Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the XAXB reference frequency/type, the clock input frequencies, the clock output frequencies, as well as the other options, such as automatic clock selection, loop BW, etc. The ClockBuilder software is required to select among all of these options and to produce a project file which Silicon Labs uses to preprogram all devices with custom orderable part number (“custom OPN”).

Custom OPN devices contain all of the initialization information in their non-volatile memory (NVM) so that it powers up fully configured and ready to go.

Because preprogrammed device applications are inherently quite different from one another, the default power up values of the register settings can be determined using the custom OPN utility at: www.silabs.com/products/clocksoscillators/clock-generator/Pages/clock-

builder-lookup.aspx.

Custom OPN devices include a device top mark which includes the unique OPN ID. Refer to the device data sheet's Ordering Guide and Top Mark sections for more details.

Both “base” and “factory preprogrammed” devices can have their operating configurations changed at any time using volatile reads and writes to the registers. Both types of devices can also have their current register configuration written to the NVM by executing an NVM bank burn sequence (see 4.3 NVM Programming.)

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14.2 Register Map Pages and Default Settings Values

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Si5345 Register Map

The Si5345/44/42

family has a large register map and is divided into separate pages. Each page contains a total of 256 registers, although all 256 registers are not used. Register 1 on each page is reserved to indicate the page and register 0x00FE is reserved for the device ready status. The following is a summary of the content that can be found on each of the pages. Note any page that is not listed is not used for the device. Do not attempt to write to registers that have not been described in this document, even if they are accessible. Note that the default value will depend on the values loaded into NVM, which is determined by the part number.

Where not provided in the register map information below, you can get the default values of the register map settings by accessing the Silicon Labs part number lookup utility. Register map settings values are listed in the datasheet addendum, which can also be accessed by using the link above.The register maps are broken out for the Si5345, Si5344, and Si5342 separately.

Table 14.1. Register Map Paging Descriptions

Page Start Address (Hex) Start Address (Dec-

Contents

imal)

Page 0 0000h 0 Alarms, interrupts, reset, other configuration

Page 1 0100h 256 Clock output configuration

Page 2 0200h 512 P,R dividers, scratch area

Page 3 0300h 768 Output N dividers, N divider Finc/Fdec

Page 4 0400h 1024 ZD mode configuration

Page 5 0500h 1280 M divider, BW, holdover, input switch, FINC/DEC

Page 9 0900h 2304 Control IO configuration

R = Read Only

R/W = Read Write

S = Self Clearing

Registers that are sticky are cleared by writing “0” to the bits that have been set in hardware. A self-clearing bit will clear on its own when the state has changed.

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Si5345 Register Definitions

15. Si5345 Register Definitions

15.1 Page 0 Registers Si5345

Table 15.1. 0x0001 Page

Reg Address Bit Field Type Name Description

0x0001 7:0 R/W PAGE Selects one of 256 possible pages.

On every page, there is a “Page Register” located at address 0x01. When read, it indicates the current page. When written, it changes the page to the value entered. There are page registers at addresses 0x0001, 0x0101, 0x0201, 0x0301, … etc.

Table 15.2. 0x0002–0x0003 Base Part Number

Reg Address Bit Field Type Name Value Description

0x0002 7:0 R PN_BASE 0x45 Four-digit “base” part number, one nibble per digit.

0x0003 15:8 R PN_BASE 0x53

Example: Si5345A-D-GM. The base part number (OPN) is 5345, which is stored in this register.

Refer to the device data sheet Ordering Guide section for more information about device grades.

Table 15.3. 0x0004 Device Grade

Reg Address Bit Field Type Name Description

0x0004 7:0 R GRADE One ASCII character indicating the device speed/synthesis mode.

0 = A

1 = B

2 = C

3 = D

Table 15.4. 0x0005 Device Revision

Reg Address Bit Field Type Name Description

0x0005 7:0 R DEVICE_REV One ASCII character indicating the device revision level.

0 = A; 1 = B, etc.

Example Si5345C-D12345-GM, the device revision is "D" and stored as 3.

Table 15.5. 0x0006–0x0008 TOOL_VERSION

Reg Address Bit Field Type

Name

Description

0x0006 3:0 R/W TOOL_VERSION[3:0] Special

0x0006 7:4 R/W TOOL_VERSION[7:4] Revision

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Reg Address Bit Field Type

Name

Description

0x0007 7:0 R/W TOOL_VERSION[15:8] Minor[7:0]

0x0008 0 R/W TOOL_VERSION[15:8] Minor[8]

0x0008 4:1 R/W TOOL_VERSION[16] Major

0x0008 7:5 R/W TOOL_VERSION[13:17] Tool. 0 for ClockBuilder Pro

Note:

The software tool version that creates the register values downloaded at power up is represented by TOOL_VERSION.

Table 15.6. 0x0009 Temperature Grade

Reg Address Bit Field Type Name Description

0x0009 7:0 R/W TEMP_GRADE Device temperature grading

0 = Industrial (–40° C to 85° C) ambient conditions

Table 15.7. 0x000A Package ID

Reg Address Bit Field Type Name Description

0x000A 7:0 R/W PKG_ID Package ID

0 = 9x9 mm 64 QFN

Part numbers are of the form:

Si<Part Num Base><Grade>-<Device Revision><OPN ID>-<Temp Grade><Package ID>

Examples

Si5345C-D12345-GM.

Applies to

a “base” or “blank” OPN (Ordering Part Number) device. These devices are factory pre-programmed with the frequency plan

and all other operating characteristics defined by the user’s ClockBuilder Pro project file.

Si5345C-D-GM.

Applies to a “base” or “non-custom” OPN device. Base devices are factory pre-programmed to a specific base part type (e.g., Si5345 but exclude any user-defined frequency plan or other user-defined operating characteristics selected in ClockBuilder Pro.

Table 15.8. 0x000B I2C Address

Reg Address Bit Field Type Setting Name Description

0x000B 6:0 R/W I2C_ADDR

The upper five bits of the 7-bit I2C address.

The lower two bits are controlled by the A1 and A0 pins. Note: This register is not bank burnable.

Table 15.9. 0x000C Internal Status Bits

Reg Address Bit Field Type Name Description

0x000C 0 R SYSINCAL 1 if the device is calibrating.

0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins.

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Reg Address Bit Field Type Name Description

0x000C 3 R XAXB_ERR 1 if there is a problem locking to the XAXB input

signal.

0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout error.

Bit 1 is the LOS status monitor for the XTAL or REFCLK at the XA/XB pins.

Table 15.10. 0x000D Out-of-Frequency (OOF) and Loss-of Signal (LOS) Alarms

Reg Address Bit Field Type Name Description

0x000D 3:0 R LOS 1 if the clock input is currently LOS

0x000D 7:4 R OOF 1 if the clock input is currently OOF

Note that each bit corresponds to the input. The LOS and OOF bits are not sticky.

Input 0 (IN0) corresponds to LOS 0x000D [0], OOF 0x000D [4]

Input 1 (IN1) corresponds to LOS 0x000D [1], OOF 0x000D [5]

Input 2 (IN2) corresponds to LOS 0x000D [2], OOF 0x000D [6]

Input 3 (IN3) corresponds to LOS 0x000D [3], OOF 0x000D [7]

Table 15.11. 0x000E Holdover and LOL Status

Reg Address Bit Field Type Name Description

0x000E 1 R LOL 1 if the DSPLL is out of lock

0x000E 5 R HOLD 1 if the DSPLL is in holdover (or free run)

These status bits indicate if the DSPLL is in holdover and if it is in Loss of Lock. These bits are not sticky.

Table 15.12. 0x000F Calibration Status

Reg Address Bit Field Type Name Description

0x000F 5 R CAL_PLL 1 if the DSPLL internal calibration is busy

This status bit indicates if a DSPLL is currently busy with calibration. This bit is not sticky.

Table 15.13. 0x0011 Internal Error Flags

Reg Address Bit Field Type Name Description

0x0011 0 R/W SYSINCAL_FLG Sticky version of SYSINCAL. Write a 0 to this bit

to clear.

0x0011 1 R/W LOSXAXB_FLG Sticky version of LOSXAXB. Write a 0 to this bit

to clear.

0x0011 3 R/W XAXB_ERR_FLG Sticky version of XAXB_ERR.Write a 0 to this

bit to clear.

0x0011 5 R/W SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT. Write a 0

to this bit to clear.

If any of these six bits are high, there is an internal fault. Please contact Silicon Labs. These are sticky flag bits. They are cleared by writing zero to the bit that has been set.

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Table 15.14. 0x0012 Sticky OOF and LOS Flags

Reg Address Bit Field Type Name Description

0x0012 3:0 R/W LOS_FLG 1 if the clock input is LOS for the given input

0x0012 7:4 R/W OOF_FLG 1 if the clock input is OOF for the given input

These are the sticky flag versions of register 0x000D. These bits are cleared by writing 0 to the bits that have been set.

Input 0 (IN0) corresponds to LOS_FLG 0x0012 [0], OOF_FLG 0x0012 [4]

Input 1 (IN1) corresponds to LOS_FLG 0x0012 [1], OOF_FLG 0x0012 [5]

Input 2 (IN2) corresponds to LOS_FLG 0x0012 [2], OOF_FLG 0x0012 [6]

Input 3 (IN3) corresponds to LOS_FLG 0x0012 [3], OOF_FLG 0x0012 [7]

Table 15.15. 0x0013 Sticky Holdover and LOL Flags

Reg Address Bit Field Type Name Description

0x0013 1 R/W LOL_FLG 1 if the DSPLL was unlocked

0x0013 5 R/W HOLD_FLG 1 if the DSPLL was in holdover or free run

These are the sticky flag versions of register 0x000E. These bits are cleared by writing 0 to the bits that have been set.

Table 15.16. 0x0014 Sticky PLL In Calibration Flag

Reg Address Bit Field Type Name Description

0x0014 5 R/W CAL_PLL_FLG 1 if the internal calibration was busy

This bit is the sticky flag version of 0x000F. This bit is cleared by writing 0 to bit 5.

Table 15.17. 0x0016

Reg Address Bit Field Type Name Description

0x0016 1 R/W LOL_ON_HOLD Set by CBPro.

Table 15.18. 0x0017 Status Flag Masks

Reg Address Bit Field Type Name Description

0x0017 0 R/W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an in-

terrupt

0x0017 1 R/W LOSXAXB_INTR_MSK 1 to mask the LOSXAXB_FLG from causing an

interrupt

0x0017 5 R/W SMBUS_TIMEOUT_FLG_MSK 1 to mask SMBUS_TIMEOUT_FLG from the in-

terrupt

0x0017 6 R/W RESERVED Factory set to 1 to mask reserved bit from caus-

ing an interrupt. Do not clear this bit.

0x0017 7 R/W RESERVED Factory set to 1 to mask reserved bit from caus-

ing an interrupt. Do not clear this bit.

These are the interrupt mask bits for the fault flags in register 0x0011. If a mask bit is set, the alarm will be blocked from causing an interrupt.

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Note: Bit 1 corresponds to XAXB LOS from asserting the interrupt (INTR) pin.

Table 15.19. 0x0018 OOF and LOS Masks

Reg Address Bit Field Type Name Description

0x0018 3:0 R/W LOS_INTR_MSK 1 to mask the clock input LOS flag

0x0018 7:4 R/W OOF_INTR_MSK 1 to mask the clock input OOF flag

These are the interrupt mask bits for the OOF and LOS flags in register 0x0012.

Input 0 (IN0) corresponds to LOS_INTR_MSK 0x0018 [0], OOF_INTR_MSK 0x0018 [4]

Input 1 (IN1) corresponds to LOS_INTR_MSK 0x0018 [1], OOF_INTR_MSK 0x0018 [5]

Input 2 (IN2) corresponds to LOS_INTR_MSK 0x0018 [2], OOF_INTR_MSK 0x0018 [6]

Input 3 (IN3) corresponds to LOS_INTR_MSK 0x0018 [3], OOF_INTR_MSK 0x0018 [7]

Table 15.20. 0x0019 Holdover and LOL Masks

Reg Address Bit Field Type Name Description

0x0019 1 R/W LOL_INTR_MSK 1 to mask the clock input LOL flag

0x0019 5 R/W HOLD_INTR_MSK 1 to mask the holdover flag

These are the interrupt mask bits for the LOL and HOLD flags in register 0x0013. If a mask bit is set the alarm will be blocked from causing an interrupt.

Table 15.21. 0x001A PLL In Calibration Interrupt Mask

Reg Address Bit Field Type Name Description

0x001A 5 R/W CAL_INTR_MSK 1 to mask the DSPLL internal calibration busy flag

The interrupt mask for this bit flag bit corresponds to register 0x0014.

Table 15.22. 0x001C Soft Reset and Calibration

Reg Address Bit Field Type Name Description

0x001C 0 S SOFT_RST_ALL 1 Initialize and calibrates the entire device

0 No effect

0x001C 2 S SOFT_RST 1 Initialize outer loop

0 No effect

These bits are of type “S”, which is self-clearing.

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Table 15.23. 0x001D FINC, FDEC

Reg Address Bit Field Type Name Description

0x001D 0 S FINC 1 a rising edge will cause the selected MultiSynth to in-

crement the output frequency by the Nx_FSTEPW parameter. See registers 0x0339–0x0358

0x001D 1 S FDEC 1 a rising edge will cause the selected MultiSynth to

decrement the output frequency by the Nx_FSTEPW parameter. See registers 0x0339–0x0358

Figure 15.1 FINC, FDEC Logic Diagram on page 87 shows the logic for the FINC, FDEC bits.

FINC, 1Dh[0] (self clear)

FINC pin, pos

edge trig

FDEC is the same as FINC

N_FSTEP_MSKx, 339h[4:0]

NxFINC

Figure 15.1. FINC, FDEC Logic Diagram

Table 15.24. 0x001E Power Down and Hard Reset

Reg Address Bit Field Type Name Description

0x001E 0 R/W PDN 1 to put the device into low power mode

0x001E 1 R/W HARD_RST 1 causes hard reset. The same as power up except that

the serial port access is not held at reset.

0 No reset

0x001E 2 S SYNC 1 to reset all output R dividers to the same state.

Table 15.25. 0x002B SPI 3 vs 4 Wire

Reg Address Bit Field Type Name Description

0x002B 3 R/W SPI_3WIRE 0 for 4-wire SPI, 1 for 3-wire SPI

0x002B 5 R/W AUTO_NDIV_UPDATE Set by CBPro.

Table 15.26. 0x002C LOS Enable

Reg Address Bit Field Type Name Description

0x002C 3:0 R/W LOS_EN 1 to enable LOS for a clock input;

0 for disable

0x002C 4 R/W LOSXAXB_DIS Enable LOS detection on the XAXB inputs.

0: Enable LOS Detection (default)

1: Disable LOS Detection

Input 0 (IN0): LOS_EN[0]

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Input 1 (IN1): LOS_EN[1]

Input 2 (IN2): LOS_EN[2]

Input 3 (IN3): LOS_EN[3]

Table 15.27. 0x002D Loss of Signal Requalification Value

Reg Address Bit Field Type Name Description

0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0

0 for 2 msec

1 for 100 msec

2 for 200 msec

3 for one second

0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above

0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above

0x002D 7:6 R/W LOS3_VAL_TIME Clock Input 3, same as above

When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME.

Table 15.28. 0x002E–0x002F LOS0 Trigger Threshold

Reg Address Bit Field Type Name Description

0x002E 7:0 R/W LOS0_TRG_THR 16-bit Threshold Value

0x002F 15:8 R/W LOS0_TRG_THR

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 0, given a particular frequency plan.

Table 15.29. 0x0030–0x0031 LOS1 Trigger Threshold

Reg Address Bit Field Type Name Description

0x0030 7:0 R/W LOS1_TRG_THR 16-bit Threshold Value

0x0031 15:8 R/W LOS1_TRG_THR

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1, given a particular frequency plan.

Table 15.30. 0x0032–0x0033 LOS2 Trigger Threshold

Reg Address Bit Field Type Name Description

0x0032 7:0 R/W LOS2_TRG_THR 16-bit Threshold Value

0x0033 15:8 R/W LOS2_TRG_THR

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 2, given a particular frequency plan.

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Table 15.31. 0x0034-0x0035 LOS3 Trigger Threshold

Reg Address Bit Field Type Name Description

0x0034 7:0 R/W LOS3_TRG_THR 16-bit Threshold Value

0x0035 15:8 R/W LOS3_TRG_THR

ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 3, given a particular frequency plan.

Table 15.32. 0x0036–0x0037 LOS0 Clear Threshold

Reg Address Bit Field Type Name Description

0x0036 7:0 R/W LOS0_CLR_THR 16-bit Threshold Value

0x0037 15:8 R/W LOS0_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0, given a particular frequency plan.

Table 15.33. 0x0038-0x0039 LOS1 Clear Threshold

Reg Address Bit Field Type Name Description

0x0038 7:0 R/W LOS1_CLR_THR 16-bit Threshold Value

0x0039 15:8 R/W LOS1_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 1, given a particular frequency plan.

Table 15.34. 0x003A-0x003B LOS2 Clear Threshold

Reg Address Bit Field Type Name Description

0x003A 7:0 R/W LOS2_CLR_THR 16-bit Threshold Value

0x003B 15:8 R/W LOS2_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan.

Table 15.35. 0x003C–0x003D LOS3 Clear Threshold

Reg Address Bit Field Type Name Description

0x003C 7:0 R/W LOS3_CLR_THR 16-bit Threshold Value

0x003D 15:8 R/W LOS3_CLR_THR

ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan.

Table 15.36. 0x003F OOF Enable

Reg Address Bit Field Type Name Description

0x003F 3:0 R/W OOF_EN 1 to enable, 0 to disable

0x003F 7:4 R/W FAST_OOF_EN 1 to enable, 0 to disable

Input 0 corresponds to OOF_EN [0], FAST_OOF_EN [4]

Input 1 corresponds to OOF_EN [1], FAST_OOF_EN [5]

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Input 2 corresponds to OOF_EN [2], FAST_OOF_EN [6]

Input 3 corresponds to OOF_EN [3], FAST_OOF_EN [7]

Table 15.37. 0x0040 OOF Reference Select

Reg Address Bit Field Type Name Description

0x0040 2:0 R/W OOF_REF_SEL 0 for CLKIN0

1 for CLKIN1

2 for CLKIN2

3 for CLKIN3

4 for XAXB

Table 15.38. 0x0041–0x0045 OOF Divider Select

Reg Address Bit Field Type Name Description

0x0041 4:0 R/W OOF0_DIV_SEL Sets a divider for the OOF circuitry for each input clock

0x0042 4:0 R/W OOF1_DIV_SEL

0,1,2,3. The divider value is 2 these dividers.

OOFx_DIV_SEL

. CBPro sets

0x0043 4:0 R/W OOF2_DIV_SEL

0x0044 4:0 R/W OOF3_DIV_SEL

0x0045 4:0 R/W OOFXO_DIV_SEL

Table 15.39. 0x0046–0x0049 Out of Frequency Set Threshold

Reg Address Bit Field Type Name Description

0x0046 7:0 R/W OOF0_SET_THR OOF Set threshold. Range is up to ±500 ppm in steps of

1/16 ppm.

0x0047 7:0 R/W OOF1_SET_THR OOF Set threshold. Range is up to ±500 ppm in steps of

1/16 ppm.

0x0048 7:0 R/W OOF2_SET_THR OOF Set threshold. Range is up to ±500 ppm in steps of

1/16 ppm.

0x0049 7:0 R/W OOF3_SET_THR OOF Set threshold. Range is up to ±500 ppm in steps of

1/16 ppm.

Table 15.40. 0x004A–0x004D Out of Frequency Clear Threshold

Reg Address Bit Field Type Name Description

0x004A 7:0 R/W OOF0_CLR_THR OOF Clear threshold. Range is up to ±500 ppm in steps

of 1/16 ppm.

0x004B 7:0 R/W OOF1_CLR_THR OOF Clear threshold. Range is up to ±500 ppm in steps

of 1/16 ppm.

0x004C 7:0 R/W OOF2_CLR_THR OOF Clear threshold. Range is up to ±500 ppm in steps

of 1/16 ppm.

0x004D 7:0 R/W OOF3_CLR_THR OOF Clear threshold. Range is up to ±500 ppm in steps

of 1/16 ppm.

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Table 15.41. 0x004E–0x04F OOF Detection Windows

Reg Address Bit Field Type Setting Name Description

0x004E 2:0 R/W OOF0_DETWIN_SEL Values calculated by CBPro.

0x004E 6:4 R/W OOF1_DETWIN_SEL Values calculated by CBPro.

0x004F 2:0 R/W OOF2_DETWIN_SEL Values calculated by CBPro.

0x004F 6:4 R/W OOF3_DETWIN_SEL Values calculated by CBPro.

Table 15.42. 0x0050 OOF_ON_LOS

Reg Address Bit Field Type Setting Name Description

0x0050 3:0 R/W OOF_ON_LOS Values set by CBPro

Table 15.43. 0x0051–0x0054 Fast Out of Frequency Set Threshold

Reg Address Bit Field Type Name Description

0x0051 3:0 R/W FAST_OOF0_SET_THR (1+ value) x 1000 ppm

0x0052 3:0 R/W FAST_OOF1_SET_THR (1+ value) x 1000 ppm

0x0053 3:0 R/W FAST_OOF2_SET_THR (1+ value) x 1000 ppm

0x0054 3:0 R/W FAST_OOF3_SET_THR (1+ value) x 1000 ppm

These registers determine the OOF alarm set threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers.

Table 15.44. 0x0055–0x0058 Fast Out of Frequency Clear Threshold

Reg Address Bit Field Type Name Description

0x0055 3:0 R/W FAST_OOF0_CLR_THR (1+ value) x 1000 ppm

0x0056 3:0 R/W FAST_OOF1_CLR_THR (1+ value) x 1000 ppm

0x0057 3:0 R/W FAST_OOF2_CLR_THR (1+ value) x 1000 ppm

0x0058 3:0 R/W FAST_OOF3_CLR_THR (1+ value) x 1000 ppm

These registers determine the OOF alarm clear threshold for IN3, IN2, IN1 and IN0 when the fast control is enabled. The value in each of the register is (1+ value) x 1000 ppm. ClockBuilder Pro is used to determine the values for these registers.

OOF needs a frequency reference. ClockBuilder Pro provides the OOF register values for a particular frequency plan.

Table 15.45. 0x0059 Fast OOF Detection Window

Reg Address Bit Field Type Name Description

0x0059 1:0 R/W FAST_OOF0_DETWIN_SEL Values calculated by CBPro.

0x0059 3:2 R/W FAST_OOF1_DETWIN_SEL Values calculated by CBPro.

0x0059 5:4 R/W FAST_OOF2_DETWIN_SEL Values calculated by CBPro.

0x0059 7:6 R/W FAST_OOF3_DETWIN_SEL Values calculated by CBPro.

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Table 15.46. 0x005A–0x005D OOF0 Ratio for Reference

Reg Address Bit Field Type Name Description

0x005A 7:0 R/W OOF0_RATIO_REF Values calculated by CBPro.

0x005B 15:8 R/W OOF0_RATIO_REF Values calculated by CBPro.

0x005C 23:16 R/W OOF0_RATIO_REF Values calculated by CBPro.

0x005D 25:24 R/W OOF0_RATIO_REF Values calculated by CBPro.

Table 15.47. 0x005E–0x0061 OOF1 Ratio for Reference

Reg Address Bit Field Type Name Description

0x005E 7:0 R/W OOF1_RATIO_REF Values calculated by CBPro.

0x005F 15:8 R/W OOF1_RATIO_REF Values calculated by CBPro.

0x0060 23:16 R/W OOF1_RATIO_REF Values calculated by CBPro.

0x0061 25:24 R/W OOF1_RATIO_REF Values calculated by CBPro.

Table 15.48. 0x0062–0x0065 OOF2 Ratio for Reference

Reg Address Bit Field Type Name Description

0x0062 7:0 R/W OOF2_RATIO_REF Values calculated by CBPro.

0x0063 15:8 R/W OOF2_RATIO_REF Values calculated by CBPro.

0x0064 23:16 R/W OOF2_RATIO_REF Values calculated by CBPro.

0x0065 25:24 R/W OOF2_RATIO_REF Values calculated by CBPro.

Table 15.49. 0x0066-0x0069 OOF3 Ratio for Reference

Reg Address Bit Field Type Name Description

0x0066 7:0 R/W OOF3_RATIO_REF Values calculated by CBPro

0x0067 15:8 R/W OOF3_RATIO_REF

0x0068 23:16 R/W OOF3_RATIO_REF

0x0069 25:24 R/W OOF3_RATIO_REF

Table 15.50. 0x0092 Fast LOL Enable

Reg Address Bit Field Type Name Description

0x0092 1 R/W LOL_FST_EN Enables fast detection of LOL. A large input frequency

error will quickly assert LOL when this is enabled.

Table 15.51. 0x0093 Fast LOL Detection Window

Reg Address Bit Field Type Name Description

0x0093 7:4 R/W LOL_FST_DETWIN_SEL Values calculated by CBPro

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Table 15.52. 0x0095 Fast LOL Detection Value

Reg Address Bit Field Type Name Description

0x0095 3:2 R/W LOL_FST_VALWIN_SEL Values calculated by CBPro.

Table 15.53. 0x0096 Fast LOL Set Threshold

Reg Address Bit Field Type Name Description

0x0096 7:4 R/W LOL_FST_SET_THR_SEL Values calculated by CBPro

Table 15.54. 0x0098 Fast LOL Clear Threshold

Reg Address Bit Field Type Name Description

0x0098 7:4 R/W LOL_FST_CLR_THR_SEL Values calculated by CBPro.

Table 15.55. 0x009A LOL Enable

Reg Address Bit Field Type Name Description

0x009A 1 R/W LOL_SLOW_EN_PLL 1 to enable LOL; 0 to disable LOL.

ClockBuilder Pro provides the LOL register values for a particular frequency plan.

Table 15.56. 0x009B Slow LOL Detection Window

Reg Address Bit Field Type Name Description

0x009B 7:4 R/W LOL_SLW_DETWIN_SEL Values calculated by CBPro.

Table 15.57. 0x009D Slow LOL Detection Value

Reg Address Bit Field Type Setting Name Description

0x009D 3:2 R/W LOL_SLW_VALWIN_SEL Values calculated by CBPro.

Table 15.58. 0x009E LOL Set Threshold

Reg Address Bit Field Type Name Description

0x009E 7:4 R/W LOL_SLW_SET_

THR

Configures the loss of lock set thresholds. Selectable as

0.1, 0.3, 1, 3, 10, 30, 100, 300, 1000, 3000, 10000. Values are in ppm.

The following are the thresholds for the value that is placed in the top four bits of register 0x009E.

0 = 0.1 ppm

1 = 0.3 ppm

2 = 1 ppm

3 = 3 ppm

4 = 10 ppm

5 = 30 ppm

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6 = 100 ppm

7 = 300 ppm

8 = 1000 ppm

9 = 3000 ppm

10 = 10000 ppm

Table 15.59. 0x00A0 LOL Clear Threshold

Reg Address Bit Field Type Name Description

0x00A0 7:4 R/W LOL_SLW_CLR_THR Configures the loss of lock set thresholds. Selectable

as 0.1, 0.3, 1, 3, 10, 30, 100, 300, 1000, 3000, 10000. Values are in ppm.

The following are the thresholds for the value that is placed in the top four bits of register 0x00A0. ClockBuilder Pro™ sets these values.

0 = 0.1 ppm

1 = 0.3 ppm

2 = 1 ppm

3 = 3 ppm

4 = 10 ppm

5 = 30 ppm

6 = 100 ppm

7 = 300 ppm

8 = 1000 ppm

9 = 3000 ppm

10 = 10000 ppm

Table 15.60. 0x00A2 LOL Timer Enable

Reg Address Bit Field Type Name Description

0x00A2 1 R/W LOL_TIMER_EN 0 to disable

1 to enable

Table 15.61. 0x00A9–0x00AC LOL_CLR_DELAY_DIV256

Reg Address Bit Field Type Name Description

0x00A9 7:0 R/W LOL_CLR_DELAY_DIV256 Set by CBPro.

0x00AA 15:8 R/W LOL_CLR_DELAY_DIV256 Set by CBPro.

0x00AB 23:16 R/W LOL_CLR_DELAY_DIV256 Set by CBPro.

0x00AC 28:24 R/W LOL_CLR_DELAY_DIV256 Set by CBPro.

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Table 15.62. 0x00E2

Reg Address Bit Field Type Name Description

0x00E2 7:0 R ACTIVE_NVM_BANK Read-only field indicating number of user bank

writes carried out so far.

Value Description

0 zero

3 one

15 two

63 three

Table 15.63. 0x00E3

Reg Address Bit Field Type Setting Name Description

0x00E3 7:0 R/W NVM_WRITE Write 0xC7 to initiate an NVM bank burn.

Table 15.64. 0x00E4

Reg Address Bit Field Type Setting Name Description

0x00E4 0 S NVM_READ_BANK When set, this bit will read the NVM down into

the volatile memory.

Table 15.65. 0x00E5 Fastlock Extend Enable

Reg Address Bit Field Type Name Description

0x00E5 5 R/W FASTLOCK_EXTEND_EN Extend Fastlock bandwidth period past LOL

Clear

0: Do not extend Fastlock period

1: Extend Fastlock period (default)

Table 15.66. 0x00EA–0x00ED FASTLOCK_EXTEND

Reg Address Bit Field Type Name Description

0x00EA 7:0 R/W FASTLOCK_EXTEND 29-bit value. Set by CBPro to minimize the phase transi-

ents when switching the PLL bandwidth. See FASTLOCK_EXTEND_SCL.

0x00EB 15:8 R/W FASTLOCK_EXTEND 29-bit value. Set by CBPro to minimize the phase transi-

ents when switching the PLL bandwidth. See FASTLOCK_EXTEND_SCL.

0x00EC 23:16 R/W FASTLOCK_EXTEND 29-bit value. Set by CBPro to minimize the phase transi-

ents when switching the PLL bandwidth. See FASTLOCK_EXTEND_SCL.

0x00ED 28:24 R/W FASTLOCK_EXTEND 29-bit value. Set by CBPro to minimize the phase transi-

ents when switching the PLL bandwidth. See FASTLOCK_EXTEND_SCL.

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Table 15.67. 0x00F6

Reg Address Bit Field Type Name Description

0x00F6 0 R REG_0xF7_INTR Set by CBPro.

0x00F6 1 R REG_0xF8_INTR Set by CBPro.

0x00F6 2 R REG_0xF9_INTR Set by CBPro.

Table 15.68. 0x00F7

Reg Address Bit Field Type Name Description

0x00F7 0 R SYSINCAL_INTR Set by CBPro.

0x00F7 1 R LOSXAXB_INTR Set by CBPro.

0x00F7 2 R LOSREF_INTR Set by CBPro.

0x00F7 4 R LOSVCO_INTR Set by CBPro.

0x00F7 5 R SMBUS_TIME_O

Set by CBPro.

UT_INTR

Table 15.69. 0x00F8

Reg Address Bit Field Type Name Description

0x00F8 3:0 R LOS_INTR Set by CBPro.

0x00F8 7:4 R OOF_INTR Set by CBPro.

Table 15.70. 0x00F9

Reg Address Bit Field Type Name Description

0x00F9 1 R LOL_INTR Set by CBPro.

0x00F9 5 R HOLD_INTR Set by CBPro.

Table 15.71. 0x00FE Device Ready

Reg Address Bit Field Type Name Description

0x00FE 7:0 R DEVICE_READY Ready Only byte to indicate device is ready. When read

data is 0x0F one can safely read/write registers. This register is repeated on every page therefore a page write is not ever required to read the DEVICE_READY status.

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15.2 Page 1 Registers Si5345

Table 15.72. 0x0102 Global OE Gating for All Clock Output Drivers

Reg Address Bit Field Type Name Description

0x0102 0 R/W OUTALL_DISABLE_LOW 1 Pass through the output enables, 0 disables

all output drivers

Table 15.73. 0x0108 Clock Output Driver 0 and R-Divider 0 Configuration

Reg Address Bit Field Type Name Description

0x0108 0 R/W OUT0_PDN Output driver 0: 0 to power up the regulator, 1 to power

down the regulator. Clock outputs will be weakly pulledlow.

0x0108 1 R/W OUT0_OE Output driver 0: 0 to disable the output, 1 to enable the

output

0x0108 2 R/W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG

1 R0 divider value is forced into divide by 2

Table 15.74. 0x0109 Output 0 Format

Reg Address Bit Field Type Name Description

0x0109 2:0 R/W OUT0_FORMAT 0 Reserved

1 swing mode (normal swing) differential

2 swing mode (high swing) differential

3 Reserved

4 LVCMOS single ended

5 LVCMOS (+pin only)

6 LVCMOS (–pin only

7 Reserved

0x0109 3 R/W OUT0_SYNC_EN 0 disable

1 enable

enable/disable synchronized (glitchless) operation. When enabled, the power down and output enables are synchronized to the output clock.

0x0109 5:4 R/W OUT0_DIS_STATE Determines the state of an output driver when disa-

bled, selectable as

00 Disable low

01 Disable high

10 Reserved

11 Reserved

0x0109 7:6 R/W OUT0_CMOS_DRV LVCMOS output impedance. Selectable as

CMOS1,CMOS2, CMOS3.

See 6.2 Performance Guidelines for Outputs.

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Table 15.75. 0x010A Output 0 Swing and Amplitude

Reg Address Bit Field Type Name Description

0x010A 3:0 R/W OUT0_CM This field only applies when OUT0_FORMAT=1 or 2.

See Table 6.10

on page to Non-Standard Amplitudes for details of the settings.

0x010A 6:4 R/W OUT0_AMPL This field only applies when OUT0_FORMAT=1, 2, or 3.

See Table 5.5 Hitless Switching Enable Bit on page 22 and

18. Setting the Differential Output Driver to Non-

Standard Amplitudes for details of the settings.

Settings for LVDS, LVPECL, and HCSL

41 and 18. Setting the Differential Output Driver

See the settings and values from Table 6.10 Settings for LVDS, LVPECL, and HCSL

on page 41 for details of the settings. ClockBuilder

Pro is used to select the correct settings for this register.

Table 15.76. 0x010B R-Divider 0 Mux Selection

Reg Address Bit Field Type Name Description

0x010B 2:0 R/W OUT0_MUX_SEL Output driver 0 input mux select.This selects the

source of the multisynth.

0: N0

1: N1

2: N2

3: N3

4: N4

5: reserved

6: reserved

7: reserved

0x010B 3 R/W OUT0_VDD_SEL_EN 1 = Enable OUT0_VDD_SEL

0x010B 5:4 R/W OUT0_VDD_SEL Must be set to the VDD0 voltage.

0: 3.3 V

1: 1.8 V

2: 2.5 V

3: Reserved

0x010B 7:6 R/W OUT0_INV CLK and CLK not inverted

CLK inverted

CLK and CLK inverted

CLK inverted

Each output can be configured to use Multisynth N0-N4 divider. The frequency for each N-divider is set in registers 0x0302–0x0337 for N0 to N4. Five different frequencies can be set in the N-dividers (N0–N4) and each of the 10 outputs can be configured to any of the five different frequencies.

The 10 output drivers are all identical. The single set of descriptions above for output driver 0 applies to the other 9 output drivers.

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Table 15.77. Registers that Follow the Same Definitions Above

0x010D Clock Output Driver 1 Config 0x0108

0x010E Clock Output Driver 1 Format, Sync 0x0109

0x010F Clock Output Driver 1 Ampl, CM 0x010A

0x0110 OUT1_MUX_SEL, OUT1_VDD_SEL_EN, OUT1_VDD_SEL,

0x010B

OUT1_INV

0x0112 Clock Output Driver 2 Config 0x0108

0x0113 Clock Output Driver 2 Format, Sync 0x0109

0x0114 Clock Output Driver 2 Ampl, CM 0x010A

0x0115 OUT2_MUX_SEL, OUT2_VDD_SEL_EN, OUT2_VDD_SEL,

0x010B

OUT2_INV

0x0117 Clock Output Driver 3 Config 0x0108

0x0118 Clock Output Driver 3 Format, Sync 0x0109

0x0119 Clock Output Driver 3 Ampl, CM 0x010A

0x011A OUT3_MUX_SEL, OUT3_VDD_SEL_EN, OUT3_VDD_SEL,

0x010B

OUT3_INV

0x011C Clock Output Driver 4 Config 0x0108

0x011D Clock Output Driver 4 Format, Sync 0x0109

0x011E Clock Output Driver 4 Ampl, CM 0x010A

0x011F OUT4_MUX_SEL, OUT4_VDD_SEL_EN, OUT4_VDD_SEL,

0x010B

OUT4_INV

0x0121 Clock Output Driver 5 Config 0x0108

0x0122 Clock Output Driver 5 Format, Sync 0x0109

0x0123 Clock Output Driver 5 Ampl, CM 0x010A

0x0124 OUT5_MUX_SEL, OUT5_VDD_SEL_EN, OUT5_VDD_SEL,

0x010B

OUT5_INV

0x0126 Clock Output Driver 6 Config 0x0108

0x0127 Clock Output Driver 6 Format, Sync 0x0109

0x0128 Clock Output Driver 6 Ampl, CM 0x010A

0x0129 OUT6_MUX_SEL, OUT6_VDD_SEL_EN, OUT6_VDD_SEL,

0x010B

OUT6_INV

0x012B Clock Output Driver 7 Config 0x0108

0x012C Clock Output Driver 7 Format, Sync 0x0109

0x012D Clock Output Driver 7 Ampl, CM 0x010A

0x012E OUT7_MUX_SEL, OUT7_VDD_SEL_EN, OUT7_VDD_SEL,

0x010B

OUT7_INV

0x0130 Clock Output Driver 8 Config 0x0108

0x0131 Clock Output Driver 8 Format, Sync 0x0109

0x0132 Clock Output Driver 8 Ampl, CM 0x010A

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Si5345, Si5344, Si5342 Rev. D Family Reference Manual

Si5345 Register Definitions

0x0133 OUT8_MUX_SEL, OUT8_VDD_SEL_EN, OUT8_VDD_SEL,

0x010B

OUT8_INV

0x013A Clock Output Driver 9 Config 0x0108

0x013B Clock Output Driver 9 Format, Sync 0x0109

0x013C Clock Output Driver 9 Ampl, CM 0x010A

0x013D OUT9_MUX_SEL, OUT9_VDD_SEL_EN, OUT9_VDD_SEL,

0x010B

OUT9_INV

Table 15.78. 0x013F–0x0140

Reg Address Bit Field Type Setting Name Description

0x013F 7:0 R/W OUTX_ALWAYS_ON This setting is managed by CBPro during

0x0140 11:8 R/W OUTX_ALWAYS_ON

zero delay mode.

Table 15.79. 0x0141 Output Disable Mask for LOS XAXB

Reg Address Bit Field Type Setting Name Description

0x0141 1 R/W OUT_DIS_MSK Set by CBPro.

0x0141 5 R/W OUT_DIS_LOL_MSK Set by CBPro.

0x0141 6 R/W OUT_DIS_LOSXAXB_MSK Determines if outputs are disabled

during an LOSXAXB condition.

0: All outputs disabled on LOSXAXB

1: All outputs remain enabled during LOSXAXB condition

0x0141 7 R/W OUT_DIS_MSK_LOS_PFD Set by CBPro.

Table 15.80. 0x0142 Output Disable Loss of Lock PLL

Reg Address Bit Field Type Setting Name Description

0x0142 1 R/W OUT_DIS_MSK_LOL 0: LOL will disable all connected out-

puts

1: LOL does not disable any outputs

0x0142 5 R/W OUT_DIS_MSK_HOLD Set by CBPro.

Table 15.81. 0x0145 Power Down All

Reg Address Bit Field Type Name Description

0x0145 0 R/W OUT_PDN_ALL 0- no effect

1- all drivers powered down

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Silicon Labs Si5345, Si5344, Si5342 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

1. Overview

2. Work Flow Expectations with ClockBuilder Pro™ and the Register Map

2.1 Family Product Comparison

2.2 Available Software Tools and Support

3. DSPLL and MultiSynth

3.1 Dividers

3.2 DSPLL Loop Bandwidth

3.2.1 Fastlock Feature

3.2.2 Holdover Exit Bandwidth

4. Modes of Operation

4.1 Reset and Initialization

4.2 Dynamic PLL Changes

4.3 NVM Programming

4.4 Free Run Mode

4.5 Acquisition Mode

4.6 Locked Mode

4.7 Holdover Mode

5. Clock Inputs

5.1 Inputs (IN0, IN1, IN2, IN3)

5.1.1 Manual Input Switching

5.1.2 Automatic Input Selection

5.2 Types of Inputs

5.2.1 Unused Inputs

5.2.2 Hitless Input Switching with Phase Buildout

5.2.3 Ramped Input Switching

5.2.4 Hitless Switching, LOL (loss of lock) and Fastlock

5.2.5 Glitchless Input Switching

5.2.6 External Clock Switching

5.2.7 Synchronizing to Gapped Input Clocks

5.2.8 Rise Time Considerations

5.3 Fault Monitoring

5.3.1 Input Loss of Signal (LOS) Fault Detection

5.3.2 Out of Frequency (OOF) Fault Detection

5.3.3 Loss of Lock (LOL) Fault Monitoring

5.4 Interrupt (INTR) Monitoring

6. Output Clocks

6.1 Output Crosspoint Switch

6.2 Performance Guidelines for Outputs

6.3 Output Signal Format

6.3.1 Differential Output Terminations

6.3.2 Differential Output Swing Modes

6.3.3 Programmable Common Mode Voltage for Differential Outputs

6.3.4 LVCMOS Output Terminations

6.3.5 LVCMOS Output Impedance and Drive Strength Selection

6.3.6 LVCMOS Output Signal Swing

6.3.7 LVCMOS Output Polarity

6.3.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

6.4 Output Enable/Disable

6.4.1 Output Driver State When Disabled

6.4.2 Synchronous Output Disable Feature

6.5 Output Buffer Supply Voltage Selection

7. Zero Delay Mode

8. Digitally-Controlled Oscillator (DCO) Mode

8.1 DCO with Frequency Increment/Decrement Pins/Bits

8.2 DCO with Direct Register Writes

9. Serial interface

9.1 I2C Interface

9.2 SPI Interface

10. Field Programming

11. XA/XB External References

11.1 Performance of External References

11.2 Recommended Crystals and External Oscillators

11.3 Register Settings to Control External XTAL Reference

11.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register

11.3.2 PXAXB Pre-scale Divide Ratio for Reference Clock Register

12. Crystal and Device Circuit Layout Recommendations

12.1 64-Pin QFN Si5345 Layout Recommendations

12.1.1 Si5345 Applications without a Crystal

12.1.2 Si5345 Crystal Guidelines

12.1.3 Output Clocks

12.2 44-Pin QFN Si5344/42 Layout Recommendations

12.2.1 Si5342/44 Applications without a Crystal

12.2.2 Si5342/44 Crystal Guidelines

13. Power Management

13.1 Power Management Features