Silicon Labs Si5341, Si5340 Reference Manual

Si5341, Si5340 Rev D Family Reference Manual

Ultra Low Jitter, Any-Frequency, Any Output Clock Generator: Si5341, Si5340 Rev D Family Reference Manual

1. Overview

Using patented MultiSynth™ technology, the Si5341/40 generates up to 10 unique clock frequencies, each with 0 ppm frequency synthesis error. Each output clock has an independent VDDO reference and selectable signal format, simplifying format/level translation. The loop filter is fully integrated on-chip eliminating the risk of potential noise coupling associated with discrete solutions.The Si5341/40 is ideally suited for simplifying clock tree design by minimizing the number of timing components required. The Si5341/40 supports factory or in-circuit programmable non-volatile memory, enabling the device to power up in a user-specified configuration. The default configuration may be overwritten at any time by reprogramming the device via I2C/SPI.

1.1 Work Flow Expectations with ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other operating settings are supported by the devices. However, describing all the possible changes are not a primary purpose of this document. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to implement the most common, real-time frequency plan changes.

The primary purpose of the software is that it saves having to understand all the complexities of the device. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing the settings in the register map described in this document.

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1.2 Family Product Comparison

The following table lists a comparison of the different family members.

Table 1.1. Product Selection Guide

Si5341, Si5340 Rev D Family Reference Manual

Overview

Part Number Number of Inputs

Number of

Fractional Dividers

Number of Outputs Package Type

Si5341 4 5 10 64-pin QFN

Si5340 4 4 4 44-pin QFN

Si5341/40

IN_SEL[1:0]

IN0

XTAL

IN1

IN2

OSC

FB_IN

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

Multi

Synth

PLL

OUT0

OUT1

OUT2

OUT3

OUT4

Si5340

OUT5

NVM

I2C/ SPI

Control/

Status

OUT6

OUT7

OUT8

OUT9

Si5341

Figure 1.1. Block Diagram Si5341/40

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1.3 Available Software Tools and Support

Si5341, Si5340 Rev D Family Reference Manual

Overview

ClockBuilder

Pro is a software tool that is used for the Si5341/40 family and other product families, capable of configuring the timing chip in an intuitive friendly step by step process. The software abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and configure for the end application. The software walks the user through each step, with explanations about each configuration step in the process to explain the different options available. The software will restrict the user from entering an invalid combination of selections. The final configuration settings can be saved, written to a device or written to the EVB and a custom part number can be created. ClockBuilder Pro integrates all the datasheets, application notes and information that might be helpful in one environment. It is intended that customers will use the software tool for the proper configuration of the device. Register map descriptions are given in the document should not be the only source of information for programming the device. The complexity of the algorithms is embedded in the software tool.

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Si5341, Si5340 Rev D Family Reference Manual

Functional Description

2. Functional Description

The Si5341/40 uses next generation MultiSynth™ technology to offer the industry’s most frequency-flexible, high performance clock generator. The PLL locks to either an external crystal (XA/XB) or to an external input on XAXB, IN0, IN1 or IN2. The input frequency (crystal or external input) is multiplied by the DSPLL and divided by the MultiSynth™ stage (N divider) and R divider to any frequency in the range of 100 Hz to 712.5 MHz per output. The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to the selected input and provide a common reference to all the output MultiSynth highperformance fractional dividers (N). The high-resolution fractional MultiSynth™ dividers enables true any-frequency input to any-frequency on any of the outputs. A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers (R) provide further frequency division if required. The frequency configuration of the device is programmed by setting the input dividers (P), the DSPLL feedback fractional divider (M_NUM/M_DEN), the MultiSynth fractional dividers (N_NUM/ N_DEN), and the output integer dividers (R). Silicon Labs’ Clockbuilder Pro configuration utility determines the optimum divider values for any desired input and output frequency plan.

The output drivers offer flexible output formats which are independently configurable on each of the outputs. This clock generator is fully configurable via its serial interface (I2C/SPI) and includes in-circuit programmable non-volatile memory. The block diagram for the

Si5341 is shown in Figure 2.1 Si5341 Detailed Block Diagram on page 10, and the block diagram for the Si5340 is shown in Figure

2.2 Si5340 Detailed Block Diagram on page 11.

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Si5341, Si5340 Rev D Family Reference Manual

Functional Description

2.1 Dividers

are five divider classes within the Si5341/40. See Figure 2.2 Si5340 Detailed Block Diagram on page 11 for a block diagram

There that shows all of these dividers.

• 1. Wide range input dividers Pfb, P2, P1, P0

• Only integer divider values

• Range is from 1 to 216 – 1

• Since the input to the phase detector needs to be

Each divider has an update bit that must be written to cause a newly written divider value to take effect.

•

2. Narrow range input divider Pxaxb

• Only divides by 1, 2, 4, 8

3. Feedback M divider

• Ultra low jitter in fractional and integer modes

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Practical range limited by phase detector range of 10–120 MHz and VCO range of 13500–14256 MHz

• This divider has an update bit that must be written to cause a newly written divider value to take effect.

4. Output N dividers

• Ultra low jitter in fractional and integer modes

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Min value is 10

• Maximum value is 212 – 1

• Each N divider has an update bit that must be written to cause a newly written divider value to take effect. In addition there is a global update bit that when written updates all N dividers.

5. Output R divider

• Only even integer divide values

• Min value is 2

• Maximum value is 225 – 2

> 10 MHz, the practical range is limited to ~75 on the high side.

Additionally, FSTEPW can be used to adjust the nominal output frequency in DCO mode. See Section 6. Digitally Controlled Oscilla-

tor (DCO) Modes for more information and block diagrams on DCO mode.

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Si5341, Si5340 Rev D Family Reference Manual

Functional Description

VDDA

VDD

IN_SEL[1:0]

IN0

IN1

IN2

25MHz, 48-

54MHz

XTAL

FB_IN

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

A0/CS

OSC

SPI/

Zero Delay

Mode

÷P

NVM

÷P

÷Pxaxb

Status

Monitors

Si5341

Clock

Generator

PLL

LPF

MultiSynth

Frequency

Control

Dividers/

Drivers

VDDO0

÷R

OUT0 OUT0

VDDO1

OUT1 OUT1

VDDO2

OUT2 OUT2

VDDO3

OUT3 OUT3

VDDO4

OUT4 OUT4

VDDO5

OUT5 OUT5

VDDO6

OUT6 OUT6

VDDO7

OUT7 OUT7

VDDO8

OUT8

VDDO9

OUT9 OUT9

RST

LOL

INTR

FINC

FDEC

SYNC

Figure 2.1. Si5341 Detailed Block Diagram

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25MHz, 48-

54MHz

IN0

IN1

IN2

IN_SEL[1:0]

Si5341, Si5340 Rev D Family Reference Manual

Functional Description

Si5340

OSC

Zero Delay

Mode

÷Pxaxb

÷P

Clock

Generator

PLL

LPF

MultiSynth

N N

Dividers/

Drivers

÷R

VDDO0 OUT0 OUT0

VDDO1 OUT1 OUT1

VDDO2 OUT2 OUT2

VDDO3 OUT3 OUT3

FB_IN

÷P

Status

Monitors

RST

VDD

VDDA

LOL

INTR

LOSXAB

SPI/

I2C_SEL

SDA/SDIO

A1/SDO

SCLK

NVM

A0/CS

Figure 2.2. Si5340 Detailed Block Diagram

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3. Powerup and Initialization

The following figure shows the powerup and initialization sequence.

Si5341, Si5340 Rev D Family Reference Manual

Powerup and Initialization

Power-Up

Hard Reset bit asserted

RST

pin asserted

NVM download

Soft Reset

bit asserted

Initialization

Serial interface

ready

Figure 3.1. Power-Up and Initialization

3.1 Reset and Initialization

power is applied, the device begins an initialization period where it downloads default register values and configuration data from

Once NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initialization period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.

Table 3.1. Reset Registers

HARD_RST 001E[1] 001E[1]

SOFT_RST 001C[0] 001C[0]

The Si541/40 is fully configurable using the serial interface (I2C from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power supply voltages applied to its VDD (1.8 V) and VDDA (3.3 V) pins.

3.1.1 Power Supply Sequencing

If the output clocks do not need to have a specific phase/delay relationship between them the timing of the power supplies coming up to full voltage is irrelevant. However, if the phase/delay of any output clock to any other output clock is important, then the VDDO of the relevant clock output must come up to full voltage before VDD and VDDA voltages are applied. See . Voltage can always be applied to the VDDS pin regardless of any output clock alignment.

Hex Address [Bit Field]

Function

Si5341 Si5340

Performs the same function as power cycling the device. All registers will be restored to their default values.

Performs a soft reset. Resets the device while it does not redownload the register configuration from NVM.

or SPI). At power up the device downloads its default register values

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3.2 NVM Programming

Si5341, Si5340 Rev D Family Reference Manual

Powerup and Initialization

Devices

have two categories of non-volatile memory: user NVM and Factory (Silabs) NVM. Each type is segmented into NVM banks. There are three NVM banks, one of which is used for factory programming (whether a base part or an Orderable Part Number). Two user NVM banks remain; therefore, the device NVM can be re-burned in the field up to two times. Factory NVM cannot be modified, and contains fixed configuration information for the device.

The ACTIVE_NVM_BANK device setting can be used to determine which user NVM bank is currently being used and therefore how many banks, if any, are available to burn. The following table describes possible values:

Table 3.2. NVM Bank Burning Values

Active NVM BANK Value (Deci-

Number of User Banks Burned Number of User Banks Available to Burn

mal)

3 (factory state) 1 2

15 2 1

63 3 0

Note: While polling DEVICE_READY during the procedure below, the following conditions must be met to ensure the correct values are written into the NVM:

VDD and VDDA power must both be stable throughout the process.

•

• No additional registers may be written or read during DEVICE_READY polling. This includes the PAGE register at address 0x01. DEVICE_READY is available on every register page, so no page change is needed to read it.

• Only the DEVICE_READY register (0xFE) should be read during this time.

The procedure for writing registers into NVM is as follows:

1. Write registers as needed for desired device operation. Verify device operation to ensure the device is configured correctly before preceeding. Do not skip this important step.

2. You may write to the user scratch space (Registers 0x026B to 0x0272 DESIGN_ID0-DESIGN_ID7) to identify the contents of the NVM bank.

3. Write 0xC7 to NVM_WRITE register. This starts the internal NVM burn sequence, writing NVM from the internal registers. Do not access ANY other registers than DEVICE_READY during the NVM burn process. Doing so may corrupt the NVM burn in progress.

4. Poll DEVICE_READY until DEVICE_READY=0x0F (waiting for completion of NVM burn sequence).

5. Set NVM_READ_BANK 0x00E4[0]=1. This will download the NVM contents back into non-volatile memory (registers).

6. Poll DEVICE_READY until DEVICE_READY=0x0F (waiting for NVM download to complete).

7. Read ACTIVE_NVM_BANK and verify that the value is the next highest value in the table above. For example, from the factory it will be a 3. After NVM_WRITE, the value will be 15.

Alternatively, steps 5 and 6 can be replaced with a Hard Reset, either by RSTb pin, HARD_RST register bit, or power cycling the device to generate a POR. All of these actions will load the new NVM contents back into the device registers.

The ClockBuilder Pro Field Programmer kit is a USB attached device to program supported devices either in-system (wired to your PCB) or in-socket (by purchasing the appropriate field programmer socket). ClockBuilder Pro software is then used to burn a device configuration (project file). Learn more at https://www.silabs.com/products/development-tools/timing/cbprogrammer.

Table 3.3. NVM Programming Registers

Function

[Bit Field]

ACTIVE_NVM_BANK 0x00E2[7:0] Identifies the active NVM bank.

NVM_WRITE 0x00E3[7:0] Initiates an NVM write when written with value 0xC7.

NVM_READ_BANK 0x00E4[0] Download register values with content stored in NVM.

DEVICE_READY 0x00FE[7:0] Indicates that the device is ready to accept commands when

value = 0x0F.

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Si5341, Si5340 Rev D Family Reference Manual

Powerup and Initialization

Warning:

Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming and may corrupt the register contents, as they are read from NVM. Note that this includes accesses to the PAGE register.

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4. Clock Inputs

The PLL in the Si5341/40 requires a clock at the XAXB or IN2, 1, 0 input pins or a clock from a crystal connected across the XAXB pins.

4.1 Inputs on XA/XB

4.1.1 Crystal on XA/XB

An external standard crystal (XTAL) is connected to XA/XB when this input is configured as a crystal oscillator. A crystal frequency of 25 MHz can be used although crystals in the frequency range of 48 MHz to 54 MHz are recommended for the best jitter performance. Recommended crystals are listed below. The Si5341/40 includes a built-in XTAL load capacitance (CL) of 8 pF, but crystals with CL

specifications as high as 18 pF can also be used. When using crystals with CL specs higher than 8 pf it is not generally recommended to use external capacitors from XA/XB to ground to increase the crystal load capacitance. Rather the frequency offset due to CL mis-

match can be adjusted using the XAXB_FREQ_OFFSET word which allows frequency adjustments of up to ±1000 ppm. See 11. Crys-

tal and Device Circuit Layout Recommendations for the PCB layout guidelines.

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4.1.2 Clock Input on XA/XB

external clock can also be input on the XA/XB pins. Selection between the external crystal or clock is controlled by register configu-

An ration. The internal crystal load capacitors (CL) are disabled in external clock mode. Because the input buffer at XA/XB is a lower noise

buffer than the buffers on IN2,1,0, a very clean input clock at XA/XB, such as a very high quality TCXO or XO, will, in some cases, produce lower output clock jitter than the same input at IN2,1,0. If the XAXB input is unused and powered down then the XA and XB inputs can be left floating. Note that ClockBuilder Pro will power down the XAXB input if it is selected as “unused”. If XAXB is powered up but no input is applied then the XA input should be left floating and the XB input must be connected directly to ground. Both a singleended or a differential clock can be connected to the XA/XB pins as shown in the following figure:

Differential Connection

0.1 µf

Note: 2.5 Vpp diff max

CMOS/XO

Output

XO VDD R1 R2

3.3 V 523 Ohms

475 Ohms

2.5 V

1.8 V

158 Ohms

422 Ohms

649 Ohms

866 Ohms

2xC

OSC

2xC

Single-ended Connection

Note: 2.0 Vpp_se max

0.1 µf

Si5341/40

2xC

OSC

Single-ended XO Connection

Note: 2.0 Vpp_se max

XO with Clipped Sine

Wave Output

Si5341/40

2xC

0.1 µf

2xC

Crystal Connection

XTA

2xCL

2xC

OSC

Si5341/40

Figure 4.1. Crystal Resonator and External Reference Clock Connection Options

In addition to crystal operations, a clipped sine wave, CMOS, or differential reference clock is also accepted on the XA/XB interface.

clipped sine wave and CMOS TCXOs have insufficient drive strength to drive a 100 Ω or 50 Ω load. For this reason, place the

Most TCXO as close to the Si5340/41 as possible to minimize PCB trace length. In addition, ensure that both the Si5340/41 and the TCXO are both connected directly to the ground plane. The above figure includes the recommended method of connecting a clipped sine wave TCXO to the Si5340/41. Because the Si5340/41 provides DC bias at the XA and XB pins, the ~800 mV peak-peak swing can be input directly into the XA interface of the Si5340/41 once it has been ac-coupled.

The above figure also illustrates the recommended method of connecting a CMOS rail-to-rail output to the XA/XB inputs. Because the signal is single-ended, the XB input is ac-coupled to ground. The resistor network attenuates the rail-to-rail output swing to ensure that the maximum input voltage swing at the XA pin is less than the data sheet specification. The signal is ac-coupled before connecting it to the Si5340/41 XA input. Again, since the signal is single-ended, the XB input should be ac-coupled to ground.

If an external oscillator is used as the XAXB reference, it is important to use a low jitter source because there is effectively no jitter attenuation from the XAXB pins to the outputs. To minimize jitter at the XA/XB pins, the rise time of the XA/XB signals should be as fast as possible.

For best jitter performance, use a XAXB frequency above 40 MHz. Also, for XAXB frequencies higher than 125 MHz, the PXAXB control must be used to divide the input frequency down below 125 MHz.

In most applications, using the internal OSC with an external crystal provides the best phase noise performance. See AN905: External

References; Optimizing Performance for more information on the performance of various XO's with these devices.

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

The recommended crystal and oscillator suppliers are listed in the Si534x/8x

XOs Reference Manual.

4.2 Clock Inputs on IN2, IN1, IN0

A single ended or differential clock may be input to the IN2, 1, 0 inputs as shown below. All input signals must be ac-coupled. When INx (x = 0, 1, 2) is unused and powered down the plus and minus input can be left floating. ClockBuilder Pro will power down any INx input that is selected as “unused.” If any INx is powered up but does not have any input signal then the plus input should be left floating and the minus input should be directly connected to ground. If the plus input is left floating and the minus input is connected to ground with a

4.7 kΩ or smaller resistor, then the INx can be powered up or down when it does not have an input. The recommended input termination schemes are shown in the figure below. Unused inputs can be disabled by register configuration.

Jitter Attenuators Recommended Crystal, TCXO and OC-

Standard AC-Coupled Differential

0.1uF *

INx

100

Standard

INxb

LVDS, LVPECL, CML

0.1uF *

* These caps should have < ~5 ohms capacitive reactance at the clock input frequency.

Clock IC

Standard AC-Coupled Single-Ended

3.3V, 2.5V, 1.8V LVCMOS

RS matches the CMOS driver to a

50 ohm transmission

line (if used)

0.1uF

INx

INxb

Standard

0.1uF *

*This cap should have less than ~20 ohms of capacitive reactance at the clock input frequency. ** Only when 3.3V LVCMOS driver is present, use R2 = 845 ohm and R1 = 267 ohm if needed to keep the signal at INx < 3.6 Vpp_se. Including C1 = 6 pf may improve the output jitter due to faster input slew rate at INx. If attenuation is not needed for Inx<3.6Vppse, make R1 = 0 ohm and omit C1, R2 and the capacitor below R2. C1, R1, and R2 should be physically placed as close as practicle to the device input pins.

Figure 4.2. Terminations for Differential and Single-Ended Inputs

Clock IC

4.3 Unused Inputs

Unused used input bits will disable them. Enabled inputs not actively being driven by a clock may benefit from pull up or pull down resistors to avoid them responding to system noise.

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inputs can be disabled and left unconnected. Register 0x0949[3:0] defaults the input clocks to being enabled. Clearing the un-

Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4.4 Reference Input Selection (IN0, IN1, IN2, XA/XB)

active clock input is selected using the IN_SEL1,0 pins or by register control. The register bit IN_SEL_REGCTRL determines input

The selection as pin or register selectable. If the selected input does not have a clock, all output clocks will be shut off.

Table 4.1. Manual Input Selection Using IN_SEL[1:0] Pins

IN_SEL[1:0] Selected Input

0 0 IN0

0 1 IN1

1 0 IN2

1 1 XA/XB

Table 4.2. Input Control Registers

Function

Si5341 Si5340

Adjusts for crystal load capacitance mismatch causing oscillation frequency errors up to ±1000 ppm. This word is in 2s complement

Hex Address [Bit Field]

XAXB_FREQ_OFFSET 0202[7:0]–0205[7:0]

format. The XAXB_FREQ_OFFSET word is added to the M divider numerator.

Selects between the XTAL or external reference clock on the

XAXB_EXTCLK_EN 090E[0]

XA/XB pins. Default is 0, XTAL. Set to 1 to use an external reference oscillator

IN_SEL_REGCTRL 0021[0] Determines pin or register clock input selection.

IN_SEL 0021[2:1] Selects the input when in register input selection mode.

IN_EN 0949[3:0]

Allows enabling/disabling IN0, IN1, IN2 and FB_IN when not in use.

Table 4.3. XAXB Pre-Scale Divide Ratio Register

Setting Name Hex Address [Bit Field] Function

PXAXB 0x0206[1:0] Sets the XAXB input divider value according to the table be-

low.

The following table lists the values, along with the corresponding divider ratio.

Table 4.4. XAXB Pre-Scale Divide Values

Value (Decimal) PXAXB Divider Value

0 1

1 2

2 4

3 8

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4.5 Fault Monitoring

Si5341/40 provides fault indicators which monitor loss of signal (LOS) of the inputs (IN0, IN1, IN2, XA/XB, FB_IN) and loss of lock

The (LOL) for the PLL. This is shown in the following figure.

IN0

IN1

IN2

FB_IN

OSC

÷P

LOS0

LOL

LOS1

Si5341/40

PLL

LPFPD

÷P

÷Pxaxb

LOS2

LOSXAXB

LOS0

LOSFB

LOS1

LOS2

LOSXAB

LOL

INTR

Figure 4.3. LOS and LOL Fault Monitors

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4.5.1 Status Indicators

state of the status monitors are accessible by reading registers through the serial interface or with dedicated pin (LOLb). Each of

The the status indicator register bits has a corresponding sticky bit (_FLG) in a separate register location. Once a status bit is asserted its corresponding _FLG bit will remain asserted until cleared. Writing a logic zero to a _FLG register bit clears its state.

Table 4.5. Status Monitor Bits (Si5341 and Si5340)

Setting Name Hex Address [Bit Field] Function

Status Register Bits

SYSINCAL 0x000C[0] Asserted when in calibration.

LOSXAXB 0x000C[1]

Loss of Signal at the XA input.

The XB input does not have an LOS detector.

LOSREF 0x000C[2] Loss of Signal for the input that has been selected.

LOL 0x000C[3] Loss of Lock for the PLL.

SMBUS_TIMEOUT 0x000C[5] The SMB bus has a timeout.

LOSIN[3:0] 0x000D[3:0] Loss of Signal for the FB_IN, IN2, IN1, IN0 inputs.

Sticky Status Register Bits

SYSINCAL_FLG 0x0011[0] Sticky bit for SYSINCAL

LOSXAXB_FLG 0x0011[1] Sticky bit for LOSXAXB

LOSREF_FLG 0x0011[2] Sticky bit for LOSREF

LOL_FLG 0x0011[3] Sticky bit for LOL

SMBUS_TIMEOUT_FLG 0x0011[5] Sticky bit for SMBUS_TIMEOUT

LOSIN_FLG 0x0012[3:0] Sticky bit for FB_IN, IN2, IN1, IN0

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Si5341, Si5340 Rev D Family Reference Manual

Clock Inputs

4.5.2 Interrupt Pin (INTRb)

interrupt pin (INTRb) is asserted (low) whenever any of the unmasked _FLG bits are asserted. All _FLG bits are maskable to pre-

An vent assertion of the interrupt pin. The state of the INTRb pin is reset by writing zeros to all _FLG bits that are set or by writing a 1 to mask all _FLG bits that are set.

Table 4.6. Interrupt Mask Bits

Setting Name

Function

Si5341 and Si5342

SYSINCAL_INTR_MSK 0x0017[0] 1 = SYSINCAL_FLG is prevented from asserting the INTR pin

LOSXAXB_INTR_MSK 0x0017[1] 1 = LOSXAXB_FLG is prevented from asserting the INTR pin

LOSREF_INTR_MSK 0x0017[2] 1 = LOSREF_FLG is prevented from asserting the INTR pin

LOL_INTR_MSK 0x0017[3] 1 = LOL_FLG is prevented from asserting the INTR pin

SMB_TMOUT_INTR_MSK 0x0017[5] 1 = SMBUS_TIMEOUT_FLG is prevented from asserting the INTR pin

LOSIN _INTR_MSK[3:0] 0x0018[3:0] 1 = LOS_FLG is prevented from asserting the INTR pin

mask

LOSIN_FLG[0]

mask

LOSIN_FLG[1]

mask

LOSIN_FLG[2]

Hex Address [Bit Field]

mask

LOSIN_FLG[3]

INTRb

LOSXAXB_FLG

LOL_FLG

mask

Figure 4.4. Interrupt Flags and Masks

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Output Clocks

5. Output Clocks

5.1 Outputs

The Si5341 supports ten differential output drivers which can be independently configured as differential or LVCMOS. The Si5340 supports four output drivers independently configurable as differential or LVCMOS.

5.2 Performance Guidelines for Outputs

Whenever a number of high-frequency, fast-rise-time, large amplitude signals are all close to one another, the laws of physics dictate that there will be some amount of crosstalk. The jitter of the Si5341/40 is so low that crosstalk can become a significant portion of the final measured output jitter. Some of the source of the crosstalk will be the Si5341/40, and some will be introduced by the PCB. It is difficult (and possibly irrelevant) to allocate the jitter portions between these two sources because the jitter can only be measured when an Si5341/40 is mounted on a PCB.

For extra fine tuning and optimization, in addition to following the usual PCB layout guidelines, crosstalk can be minimized by modifying the arrangements of different output clocks. For example, consider the following lineup of output clocks in the table below.

Table 5.1. Example of Output Clock Frequency Sequencing Choice

Output

0 155.52 155.52

1 156.25 155.52

2 155.52 622.08

3 156.25 Not used

4 200 156.25

5 100 156.25

6 622.08 625

7 625 Not used

8 Not used 200

9 Not used 100

Using this example, a few guidelines are illustrated:

1. Avoid

2. Adjacent frequency values that are integer multiples of one another are okay and these outputs should be grouped accordingly.

3. Unused outputs can be used to separate clock outputs that might otherwise interfere with one another. In this case, see OUT3 and

adjacent frequency values that are close. A 155.52 MHz clock should not be next to a 156.25 MHz clock. If the jitter integra-

tion bandwidth goes up to 20 MHz, then keep adjacent frequencies at least 20 MHz apart.

Noting that, because 155.52 x 4 = 622.08 and 156.25 x 4 = 625, it is acceptable to place 155.52 MHz close to 622.08 MHz and

156.25 MHz close to 625 MHz.

OUT7.

Not Recommended

(Frequency MHz)

Recommended

(Frequency MHz)

If some outputs have tight jitter requirements while others are relatively loose, rearrange the clock outputs so that the critical outputs are the least susceptible to crosstalk. These guidelines typically only need to be followed by those applications that wish to achieve the highest possible levels of jitter performance. Because CMOS outputs have large pk-pk swings and do not present a balanced load to the VDDO supplies, CMOS outputs generate much more crosstalk than differential outputs. For this reason, CMOS outputs should be avoided whenever possible. When CMOS is unavoidable, even greater care must be taken with respect to the above guidelines. It is highly recommended that you consult AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems.

The ClockBuilder Pro Clock Placement Wizard is an easy way to reduce crosstalk for a given frequency plan. This feature can be accessed on the “Define Output Clocks” page of ClockBuilder Pro in the lower left hand corner of the page. It is recommended to use this tool after each project frequency plan change.

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Output Clocks

5.3 Output Signal Format

differential amplitude is fully programmable covering a wide variety of signal formats including LVDS, LVPECL, HCSL. For CML or

The non-standard amplitude applications, see XREF Appendix A. The common-mode voltage must be set as required for LVDS or LVPECL or CML/non-standard amplitude levels. The differential formats can be either normal or low power. Low power format uses less power for the same amplitude but has the drawback of slower rise/fall times. The source impedance in low power format is much higher than 100 ohms. See XREF Appendix A for register settings to implement variable amplitude differential outputs. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS (3.3, 2.5, or 1.8 V) drivers providing up to 20 single-ended outputs, or any combination of differential and single-ended outputs. Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins. See AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems for additional information.

Table 5.2. Output Signal Format Control Registers

Setting Name

OUT0_FORMAT

OUT1_FORMAT

OUT2_FORMAT

OUT3_FORMAT

OUT4_FORMAT

OUT5_FORMAT

OUT6_FORMAT

OUT7_FORMAT

OUT8_FORMAT

OUT9_FORMAT

Hex Address [Bit Field]

Si5341 Si5340

0109[2:0]

010E[2:0]

0113[2:0]

0118[2:0]

011D[2:0]

0122[2:0]

0127[2:0]

012C[2:0]

0131[2:0]

013B[2:0]

0113[2:0]

0118[2:0]

0127[2:0]

012C[2:0]

—

Function

Selects the output signal format as normal differential, low power differential, in phase CMOS, or complementary CMOS.

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5.3.1 Differential Output Terminations

The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.

AC Coupled CMLDC Coupled LVDS

LVDS: V

= 3.3V, 2.5V, 1.8V

DDO

OUTx

OUTxb

= 3.3V

, 2.5V

DDO

100

OUTx

OUTxb

VDD – 1.3V

0.1uF*

Output Clocks

5050

AC Coupled LVDS/LVPECL

= 3.3V

DDO

, 2.5V, 1.8V

= 3.3V, 2.5V

DDO

OUTx

OUTxb

0.1uF*

100

0.1uF*

Internally self-biased

LVDS: V

LVPECL: V

*All caps should have < 5 ohms capacitive reactance at the clock output frequency

= 3.3V, 2.5V. 1.8V

DDO

VDD

3.3 V

2.5 V

1.8 V

For V

AC Coupled HCSL

0.1uF*

OUTx

OUTxb

0.1uF*

= 0.35 V

R1 R2

442

332

243

56.2

59.0

63.4

VDD

Standard

HCSL

Receiver

Figure 5.1. Supported Differential Output Terminations

5.3.2 Differential Amplitude Controls

differential amplitude of each output can be controlled with the following registers. See XREF Appendix A for register settings for

The non-standard amplitudes.

Table 5.3. Differential Output Voltage Swing (Amplitude) Control Registers

Setting Name

Function

Si5341 Si5340

Hex Address [Bit Field]

OUT0_AMPL

OUT1_AMPL

OUT2_AMPL

OUT3_AMPL

OUT4_AMPL

OUT5_AMPL

OUT6_AMPL

OUT7_AMPL

OUT8_AMPL

OUT9_AMPL

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010A[6:4]

010F[6:4]

0114[6:4]

0119[6:4]

011E[6:4]

0123[6:4]

0128[6:4]

012D[6:4]

0132[6:4]

013C[6:4]

0114[6:4]

0119[6:4]

0128[6:4]

012D[6:4]

—

Sets the voltage swing (amplitude) for the differential output drivers when in Normal differential format and Low Power differential format (Table 5.4 Settings for LVDS, LVPECL, and HCSL on page

25).

Si5341, Si5340 Rev D Family Reference Manual

Output Clocks

5.3.3 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

Each differential output has four settings for control:

Normal or Low Power Format

2. Amplitude (sometimes called Swing)

3. Common Mode Voltage

4. Stop High or Stop Low

The normal Format setting has a 100 Ω internal resistor between the plus and minus output pins. The Low Power Format setting removes this 100 Ω internal resistor and then the differential output resistance will be > 500 Ω. However, as long as the termination impedance matches the differential impedance of the PCB traces, the signal integrity across the termination impedance will be good. For the same output amplitude, the Low Power Format will use less power than the Normal Format. The Low Power Format also has a lower rise/fall time than the Normal Format. See the Si5341/40 data sheet for the rise/fall time specifications. For LVPECL and LVDS standards, ClockBuilder Pro does not support the Low Power Differential Format. Stop High means that when the output driver is disabled, the plus output will be high, and the minus output will be low. Stop Low means that when the output driver is disabled, the plus output will be low, and the minus output will be high.

Differential Normal Swing Mode—This is the usual selection for differential outputs and should be used, unless there is a specific reason to do otherwise. When an output driver is configured in normal swing mode, its output swing is selectable as one of 7 settings ranging from 200 mVpp_se to 800 mVpp_se in increments of 100 mV. The output impedance in the Normal Swing Mode is 100 Ω differential.

Differential High Swing Mode—When an output driver is configured in high swing mode, its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV. The output driver is in high impedance mode and supports standard 50 Ω PCB traces The use of High Swing mode will result in larger pk-pk output swings that draw less power. The trade off will be slower rise and fall times.

Vpp_diff is 2 x Vpp_se as shown below:

OUTx

Vcm

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

OUTx

Figure 5.2. Vpp_se and Vpp_diff

The Format, Amplitude, and Common Mode settings for the various supported standards are shown in the following table.

Table 5.4. Settings for LVDS, LVPECL, and HCSL

OUTx_FORMAT Standard VDDO Volts

OUTx_CM (Deci-

mal)

001 = Normal Differential LVPECL 3.3 11 6

001 = Normal Differential LVPECL 2.5 11 6

002 = Low Power Differential LVPECL 3.3 11 3

002 = Low Power Differential LVPECL 2.5 11 3

001 = Normal Differential LVDS 3.3 3 3

001 = Normal Differential LVDS 2.5 11 3

001 = Normal Differential

Sub-LVDS

1.8 13 3

OUTx_AMPL

(Decimal)

002 = Low Power Differential LVDS 3.3 3 1

002 = Low Power Differential LVDS 2.5 11 1

002 = Low Power Differential

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Sub-LVDS

HCSL

1.8 13 1

3.3 11 3

2.5 11 3

Si5341, Si5340 Rev D Family Reference Manual

Output Clocks

OUTx_FORMAT Standard VDDO Volts

002 = Low Power Differential

Note:

The common mode voltage produced is not compliant with LVDS standards, therefore ac coupling the driver to an LVDS receiver is highly recommended.

2. Creates HCSL compatible signal. See Figure 5.1 Supported Differential Output Terminations on page 24.

3. The low-power format will cause the rise/fall time to increase by approximately a factor of two. See the Si5341/40 data sheet for more information.

The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes. See XREF Appendix A for additional information.

5.3.4 LVCMOS Output Terminations

LVCMOS outputs are dc coupled as shown in the figure below.

HCSL

1.8 13 3

OUTx_CM (Deci-

mal)

OUTx_AMPL

(Decimal)

DC Coupled LVCMOS

3.3 V, 2.5 V, 1.8 V

DDO

= 3.

3 V, 2.5 V, 1.8 V

OUTx

LVCMOS

Si5341/40

OUTx

Figure 5.3. LVCMOS Output Terminations

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Output Clocks

5.3.5 LVCMOS Output Impedance and Drive Strength Selection

LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source

Each termination resistor (Rs) is highly recommended to help match the selected output impedance to the trace impedance (i.e. Rs ~= Trace Impedance – Zs). For the best signal integrity, Silicon Labs strongly recommends using the setting that produces the lowest source impedance and then choosing the proper external source resistor to produce the best signal shape at the end of the signal trace.

VDDO

OUTx_CMOS_DRV

Value Setting

0x01 38 Ω

Source Impedance (ZS)

3.3 V

2.5 V

1.8 V

Note:

This setting is strongly recommended.

Setting Name

Si5341 Si5340

OUT0_CMOS_DRV

OUT1_CMOS_DRV

0109[7:6]

010E[7:6]

0x02 30 Ω

0x03

0x01 43 Ω

0x02 35 Ω

0x03

0x02 46 Ω

0x03

Table 5.5. LVCMOS Drive Strength Control Registers

Hex Address [Bit Field]

0113[7:6]

0118[7:6]

22 Ω

24 Ω

31 Ω

Function

OUT2_CMOS_DRV

OUT3_CMOS_DRV

OUT4_CMOS_DRV

0113[7:6]

0118[7:6]

011D[7:6]

0127[7:6]

012C[7:6]

—

LVCMOS output impedance. See previous table.

OUT5_CMOS_DRV

OUT6_CMOS_DRV

OUT7_CMOS_DRV

OUT8_CMOS_DRV

OUT9_CMOS_DRV

0122[7:6]

0127[7:6]

012C[7:6]

0131[7:6]

013B[7:6]

—

5.3.6 LVCMOS Output Signal Swing

The

signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

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Si5341, Si5340 Rev D Family Reference Manual

Output Clocks

5.3.7 LVCMOS Output Polarity

a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on

When the OUTxb pin is generated with the opposite polarity (complementary) with the clock on the OUTx pin. The polarity of these clocks is configurable enabling in-phase clock generation and/or inverted polarity with respect to other output drivers.

Table 5.6. LVCMOS Output Polarity Control Registers

Setting Name Hex Address [Bit Field] Function

Si5341 Si5340

OUT0_INV

OUT1_INV

OUT2_INV

OUT3_INV

OUT4_INV

OUT5_INV

OUT6_INV

OUT7_INV

OUT8_INV

OUT9_INV

010B[7:6]

0110[7:6]

0115[7:6]

011A[7:6]

011F[7:6]

0124[7:6]

0129[7:6]

012E[7:6]

0133[7:6]

0138[7:6]

0115[7:6]

011A[7:6]

0129[7:6]

012E[7:6]

—

Controls output polarity of the OUTx and OUTxb pins when in LVCMOS mode. Selections are as follows:

OUTx_INV OUTx OUTxb Comment

0 0 CLK CLK

Both in phase

(default)

0 1 CLK CLKb OUTxb inverted

1 0 CLKb CLKb

OUTx and OUTxb

inverted

1 1 CLKb CLK OUTx inverted

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5.3.8 Output Enable/Disable

Clock outputs are disabled by four signals within Si5341/40 and the OEB pin:

OUTALL_DISABLE_LOW

•

• SYSINCAL

• OUTx_OE

• LOL

• OEB pin

The following figure shows the logic of how these disable/enables occur.

1 instance of this is used per output driver

LOL

OUTALL_DISABLE_LOW

OEB Pin

OUTX_OE

SYSINCAL

Si5341, Si5340 Rev D Family Reference Manual

Output Clocks

Enable to Individual Output Drivers

OUTX_OE are the individual Output Driver enables as shown in the table below

Table 5.7. Output Enable/Disable Control Registers

Hex Address [Bit Field]

Setting Name

Si5341 Si5340

OUTALL_DISABLE_LOW 0102[0]

OUT0_OE

OUT1_OE

OUT2_OE

OUT3_OE

OUT4_OE

OUT5_OE

OUT6_OE

0108[1]

010D[1]

0112[1]

0117[1]

011C[1]

0121[1]

0126[1]

Figure 5.4. Output Enable

0 = Disables all outputs.

1 = All outputs are not disabled by this signal but may be disabled by other signals or the OEB pin. See figure above.

0112[1]

0117[1]

0126[1]

012B[1]

0 = Specific output disabled.

—

1 = Specific output is not disabled. The OEB pin or other signals

—

within the device may be causing an output disable. See figure above.

—

Function

OUT7_OE

OUT8_OE

OUT9_OE

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012B[1]

0130[1]

013A[1]

—

Si5341, Si5340 Rev D Family Reference Manual

Output Clocks

5.3.9 Output Driver State When Disabled

disabled state of an output driver is configurable as: disable low, disable high, or disable mid. When set for disable mid, the output

The common mode voltage will stay nearly the same when disabled as when enabled. The output common mode voltage is maintained while the driver is disabled, reducing enable/disable transients. By contrast, powering down the driver rather than disabling it increases output impedance and shuts off the output common mode voltage. For all output drivers connected in the system, it is recommended to use Disable rather than Powerdown to reduce enable/disable common mode transients. Unused outputs may be left unconnected, powered down to reduce current draw, and, with the corresponding VDDOx, left unconnected.

Table 5.8. Output Driver Disable State Control Registers

Setting Name

Function

Si5341 Si5340

Hex Address [Bit Field]

OUT0_DIS_STATE

OUT1_DIS_STATE

OUT2_DIS_STATE

OUT3_DIS_STATE

0109[5:4]

010E[5:4]

0113[5:4]

0118[5:4]

0113[5:4]

0118[5:4]

0127[5:4]

012C[5:4]

Determines the state of an output driver when disabled. Selecta-

OUT4_DIS_STATE

OUT5_DIS_STATE

011D[5:4]

0122[5:4]

—

ble as:

Disable logic low.

•

• Disable logic high

OUT6_DIS_STATE

OUT7_DIS_STATE

OUT8_DIS_STATE

OUT9_DIS_STATE

0127[5:4]

012C[5:4]

0131[5:4]

013B[5:4]

—

5.3.10 Synchronous/Asynchronous Output Disable Feature

Outputs

can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In asynchronous disable mode the output clock will disable immediately without waiting for the period to complete.

Setting Name

OUT0_SYNC_EN

OUT1_SYNC_EN

OUT2_SYNC_EN

OUT3_SYNC_EN

OUT4_SYNC_EN

OUT5_SYNC_EN

OUT6_SYNC_EN

OUT7_SYNC_EN

OUT8_SYNC_EN

OUT9_SYNC_EN

Table 5.9. Synchronous Disable Control Registers

Hex Address [Bit Field]

Si5341 Si5340

0109[3]

010E[3]

0113[3]

0118[3]

011D[3]

0113[3]

0118[3]

0127[3]

012C[3]

—

When this bit is high, the output will turn on/off (enable/disable) without generating runt pulses or glitches. The default for this bit is high. When this bit is low, the outputs will turn on/off asynchro-

0122[3]

0127[3]

012C[3]

0131[3]

013B[3]

—

nously. In this case, there may be glitches on the output when it turns on/off.

Function

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+ 81 hidden pages

Silicon Labs Si5341, Si5340 Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

1. Overview

1.1 Work Flow Expectations with ClockBuilder Pro and the Register Map

1.2 Family Product Comparison

1.3 Available Software Tools and Support

2. Functional Description

2.1 Dividers

3. Powerup and Initialization

3.1 Reset and Initialization

3.1.1 Power Supply Sequencing

3.2 NVM Programming

4. Clock Inputs

4.1 Inputs on XA/XB

4.1.1 Crystal on XA/XB

4.1.2 Clock Input on XA/XB

4.2 Clock Inputs on IN2, IN1, IN0

4.3 Unused Inputs

4.4 Reference Input Selection (IN0, IN1, IN2, XA/XB)

4.5 Fault Monitoring

4.5.1 Status Indicators

4.5.2 Interrupt Pin (INTRb)

5. Output Clocks

5.1 Outputs

5.2 Performance Guidelines for Outputs

5.3 Output Signal Format

5.3.1 Differential Output Terminations

5.3.2 Differential Amplitude Controls

5.3.3 Output Driver Settings for LVPECL, LVDS, HCSL, and CML

5.3.4 LVCMOS Output Terminations

5.3.5 LVCMOS Output Impedance and Drive Strength Selection

5.3.6 LVCMOS Output Signal Swing

5.3.7 LVCMOS Output Polarity

5.3.8 Output Enable/Disable

5.3.9 Output Driver State When Disabled

5.3.10 Synchronous/Asynchronous Output Disable Feature