Silicon Labs Si53258, Si53254 User Manual

Si53258/Si53254 数据表

8/4 输出 PCIe Gen1/2/3/4/5 时钟缓冲器

Si53258/54 是业界性能高、功耗低的汽车级 PCI Express 扇出缓冲器，适用于 PCIe Gen 1/2/3/4/5

公共时钟和/或 SRIS 应用。Si53258 和 Si53254 分别提供 8 路和 4 路 100 MHz PCIe 差分时钟输
出。所有时钟输出均符合 PCIe Gen 1/2/3/4/5 公共时钟和单独参考时钟体系结构规格。

硬件控制引脚可用于使能和禁用输出，以及为具有双输入功能的设备进行输入选择。

要详细了解 PCI Express、Silicon Labs 的完整 PCIe 产品组合、应用说明和设计工具，包括符合
PCI Express 标准的 Silicon Labs PCIe 时钟抖动工具，请访问 Silicon Labs PCI Express 学习中心。

应用：

• 信息娱乐

ADAS ECU

•

• 雷达传感器

• LiDar 传感器

主要特点

• 8/4 输出，带内部终端

• 符合 PCIe Gen 1/2/3/4/5 标准

• 汽车级 2：-40 至 +105 °C

• 内部 100 Ω 或 85 Ω 线匹配

• 出色的附加抖动性能

• 0.05 ps RMS (Gen3/4)

• 0.025 ps RMS (Gen5)

• 支持扩频，以对输入时钟进行扩频直通，实
现 EMI 降低

• 独立硬件控制引脚，用于输出使能

• 可选双输入功能，带 MUX

• 1.8–3.3 V 电源

• 无铅、符合 RoHS-6

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Table of Contents

1. Features List ...............................

3

2. Ordering Guide ..............................4

3. Functional Description............................5

3.1 Functional Block Diagrams ..........................5

3.1.1 Si53258A-D01AM Functional Block Diagram ..................5

3.1.2 Si53254A-D01AM Functional Block Diagram ..................5

3.1.3 Si53258A-D02AM Functional Block Diagram ..................6

3.1.4 Si53254A-D02AM Functional Block Diagram ..................6

3.2 HCSL Differential Output Terminations ......................7

3.3 Output Enable/Disable ...........................7

3.4 Loss of Signal (LOS) ............................7

4. Power Supply Filtering Recommendations ....................8

5. Electrical Specifications ...........................9

6. Pin Descriptions .............................14

6.1 Si53258A-D01AM Pin Descriptions (40-QFN) ...................14

6.2 Si53258A-D02AM Pin Descriptions (40-QFN) ...................18

6.3 Si53254A-D01AM Pin Descriptions (32-QFN) ...................22

6.4 Si53254A-D02AM Pin Descriptions (40-QFN) ...................25

7. Package Outline .............................29

7.1 6x6 mm 40-QFN Package Diagram .......................29

7.2 5x5 mm 32-QFN Package Diagram .......................31

8. PCB Land Pattern ............................33

8.1 40-QFN Land Pattern............................33

8.2 32-QFN Land Pattern............................35

9. Top Marking ............................... 37

10. Revision History............................. 38

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1. 功能列表

• 8/4-HCSL 输出，带内部终端

• 符合 PCIe Gen1/2/3/4/5 标准

• 汽车级 2：-40 至 +105 °C

• 内部 100 Ω 或 85 Ω 线匹配

• 出色的附加抖动性能

•

0.05 ps RMS (Gen3/4)

•

0.025 ps RMS (Gen5)

• 支持扩频，以对输入时钟进行扩频直通，实现 EMI 降低

• 信号丢失 (LOS) 输出引脚

• 独立硬件控制引脚，用于输出使能

• 可选双输入功能，带 MUX

• 1.8–3.3 V 电源

• 无铅、符合 RoHS-6

Si53258/Si53254 数据表

功能列表

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2. Ordering Guide

Si53258/Si53254 Data Sheet

Ordering Guide

Number of

Outputs

8

4

Number of

Inputs

1

2

1

2

Part Number Package Type Temperature

Si53258A-D01AM 40-QFN

Si53258A-D01AMR 40-QFN, Tape and Reel

Si53258A-D02AM 40-QFN

Si53258A-D02AMR 40-QFN, Tape and Reel

Automotive, –40 to 105 °C

Si53254A-D01AM 32-QFN

Si53254A-D01AMR 32-QFN, Tape and Reel

Si53254A-D02AM 40-QFN

Si53254A-D02AMR 40-QFN, Tape and Reel

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3. Functional Description

3.1 Functional Block Diagrams

3.1.1 Si53258A-D01AM Functional Block Diagram

Si53258/Si53254 Data Sheet

Functional Description

OE1:0

OUT0

OUT1

OE2

OUT2

CLKIN

IMP_SEL

LOS

Figure 3.1. Si53258A-D01AM Functional Block Diagram

3.1.2 Si53254A-D01AM Functional Block Diagram

Control

OE3

OUT3

OE4

OUT4

OE5

OUT5

OE6

OUT6

OE7

OUT7

OE1:0

OUT0

OUT1

CLKIN

OE2

OUT2

IMP_SEL

LOS

Control

OE3

OUT3

Figure 3.2. SSi53254A-D01AM Functional Block Diagram

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3.1.3 Si53258A-D02AM Functional Block Diagram

Si53258/Si53254 Data Sheet

Functional Description

OE1:0

OUT0

OUT1

OE3:2

CLKIN1

CLKIN2

SEL

IMP_SEL

Control

LOS

Figure 3.3. Si53258A-D02AM Functional Block Diagram

3.1.4 Si53254A-D02AM Functional Block Diagram

OUT2

OUT3

OE5:4

OUT4

OUT5

OE7:6

OUT6

OUT7

OE0

OUT0

CLKIN1

CLKIN2

CLK_SEL

IMP_SEL

Control

LOS

Figure 3.4. Si53254A-D02AM Functional Block Diagram

OE1

OUT1

OE2

OUT2

OE3

OUT3

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3.2 HCSL Differential Output Terminations

Termination for HCSL Outputs

Si53258/Si53254 Data Sheet

Functional Description

The Si52254/8
ports both 100 Ω and 85 Ω transmission line options, and can be selected using the IMP_SEL hardware input pin.

HCSL driver features integrated termination resistors to simplify interfacing to an HCSL receiver. The HCSL driver sup-

1.71 V to 3.465 V
Zo = 42.5 Ω or 50 Ω

OUTx

HCSL Output

Driv

er

HCSL

Receiver

Zo = 42.5 Ω or 50 Ω

OUTxb

Figure 3.5. HCSL Internal Termination Mode

3.3 Output Enable/Disable

An output
all designated outputs will be disabled. When held low, the designated outputs will be enabled.

3.4 Loss of Signal (LOS)

The LOS indicator is used to check for the presence of an input reference source (crystal or clock). LOS will assert when the reference
source frequency drops below approximately 10 MHz.

enable pin provides a convenient method of disabling or enabling the output drivers. When the output enable pin is held high,

The LOS pin must be checked prior to selecting the clock input or should be polled to check for the presence of the currently selected
input clock. In the event that a reference source is not present, the associated LOS pin will assume a logic low (LOS = 0) state. When a
reference source is present at the associated input clock pin, the LOS pin will assume a logic high (LOS = 1) state.

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Si53258/Si53254 Data Sheet

Power Supply Filtering Recommendations

4. Power Supply Filtering Recommendations

The Si53258/4 features internal LDOs on each power supply pin, providing excellent power supply noise rejection. As a guideline, each
power supply pin should use a parallel combination of a 1 μf and a 0.1 μF bypass capacitor placed as close to the supply pin as possi­ble.

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5. Electrical Specifications

Si53258/Si53254 Data Sheet

Electrical Specifications

Table 5.1. Recommended Operating Conditions

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 105 °C)

DDO

Parameter Symbol Test Condition Min Typ Max Units

DDA

TJ

, V

T

A

MAX

DD_DIG

V

DDO

, V

DD

–40 25 105 °C

— — 125 °C

1.71 — 3.46 V

1.42

2

— 3.46 V

Ambient Temperature

Junction Temperature

Core Supply Voltage

Output Driver Supply Voltage

V

Note:

All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-

1.
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

2.

LVCMOS outputs only.

Table 5.2. DC Characteristics

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 105 °C)

DDO

Parameter Symbol Test Condition Min Typ Max Units

Core Supply Current

Output Buffer Supply Cur­rent

I

DD

I

DDOx

HCSL Output1 @ 100 MHz

— 11 18 mA

— 20 22 mA

Total Power Dissipation

P

d

32-pin — 145 215 mW

Notes:

40-pin 530 670 mW

Differential outputs terminated into a 100

1.

Ω load at 3.3 V.

Table 5.3. Clock Input Specifications

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 105 °C)

DDO

Parameter Symbol Test Condition Min Typ Max Units

Input Clock (AC-coupled Differential Input Clock on CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#)

Frequency F

Voltage Swing

V

PP_DIFF

IN

3

Differential — 100 — MHz

0.5 — 1.8 V

PP_diff

Slew Rate SR/SF 20-80% 0.75 — — V/ns

Duty Cycle DC 40 — 60 %

Input Impedance R

Input Capacitance C

IN

IN

10 — — kΩ

2 3.5 6 pF

Notes:

1.

Imposed for jitter performance.

Rise and fall times can be estimated using the following simplified equation: tr/tf

2.

3. V

PP_DIFF

= 2 x V

PP_SINGLE-ENDED

= ((0.8 - 0.2) * V

80-20

IN_Vpp_se

) / SR.

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Table 5.4. Differential Clock Output Specifications

Si53258/Si53254 Data Sheet

Electrical Specifications

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 105 °C)

DDO

Parameter Symbol Test Condition Min Typ Max Units

Output Frequency

f

OUT

100 MHz

Duty Cycle DC With 50% duty cycle input. 48 — 52 %

V

V

T

SK

SEPP

CM

— — 80 ps

HCSL 0.7 0.8 0.9

V

HCSL 0.35 0.4 0.45 V

Output-Output Skew

Output Voltage Swing

Common Mode Voltage

HCSL Edge Rate Edgr Notes 1, 2, 3 1 — 4.5 V/ns

HCSL Delta Tr

HCSL Delta Tf

HCSL Vcross Abs

HCSL Delta Vcross

HCSL Vovs

HCSL Vuds

HCSL Vrng

D

tr

D

tf

V

xa

D

vcrs

V

ovs

V

uds

V

rng

Notes 2, 4, 8 — — 140 mV

Notes 2, 4, 9 — —

Notes 2, 4, 10 — —

Notes 2, 4

Notes 2, 4, 5 — — 155 ps

Notes 2, 4, 5 — — 155 ps

Notes 6, 7, 2, 4 250 — 550 mV

V

V

HIGH

-200

—

V

V

HIGH

LOW

LOW

+300

-300

+200

mV

mV

mV

PP

Rise and Fall Times
(20% to 80%)

tR/t

F

HCSL — — 420 ps

Notes:

Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV to +150

1.
mV on the differential waveform . Scope is set to average because the scope sample clock is making most of the dynamic wig­gles along the clock edge Only valid for Rising clock and Falling Clock#. Signal must be monotonic through the Vol to Voh region
for Trise and Tfall.

Applies to a 2 pf load with both internal or external 50 Ω or 42.5 Ω Rp.

2.

3. Measurement taken from differential waveform.

4. Measurement taken from Single Ended waveform.

5. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

OUTx

Vcm

Vcm

OUTx

Vpp_se

Vpp_se

Vcm

Vpp_diff = 2*Vpp_se

6. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.

7. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.

ΔVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum

8.
allowed variance in Vcross for any particular system.

9. Overshoot is defined as the absolute value of the maximum voltage.

10. Undershoot is defined as the absolute value of the minimum voltage.

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Table 5.5. Performance Characteristics

Si53258/Si53254 Data Sheet

Electrical Specifications

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 105 °C)

DDO

Parameter Symbol Test Condition Min Typ Max Units

Power Ramp

Clock Stabilization from Power-up

t

VDD

t

STABLE

0 V to V

DDmin

Time for clock outputs to

appear after POR

0.1 — 10 ms

— 15 25 ms

Table 5.6. PCI-Express Clock Output Additive Phase Jitter (100 MHz)

(VDD = V

DDA

= V

= 1.8 V to 3.3 V +5%/-5%, V

DD_DIG

= 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

DDO

Parameter Test Condition Typ Max Units

Includes PLL BW 1.5–22 MHz,

PCIe Gen 1.1

Peaking = 3 dB, Td = 10 ns,

Ftrk = 1.5 MHz with BER = 1E-12

1

11 19 ps RMS

Includes PLL BW 5MHz and 8–16 MHz,

Jitter Peaking = 0.01–1 dB and 3 dB,

0.02 0.026 ps RMS

Td=12ns, Low Band, F < 1.5 MHz

PCIe Gen 2.1

Includes PLL BW 5 MHz and 8–16 MHz,

Jitter Peaking = 0.01–1 dB and 3 dB,

Td = 12 ns, High Band, 1.5 MHz < F < Nyquist

1

0.2 0.31 ps RMS

Includes PLL BW 2–4 MHz and 5 MHz, Peaking = 0.01–2 dB and

PCIe Gen 3.0

1 dB,

Td = 12 ns, CDR = 10 MHz

1, 2

0.06 0.1 ps RMS

Includes PLL BW 2–4 MHz and 5 MHz, Peaking = 0.01–2 dB and

PCIe Gen 4.0

Td = 12 ns, CDR = 10 MHz

1dB,

0.05 0.1 ps RMS

1

,

2

PCIe Gen5.0 0.025 0.04 ps RMS

Note:

1.

All output clocks 100 MHz HCSL format. Jitter data taken from Clock Jitter Tool v.1.3.

2. Excludes oscilloscope sampling noise.

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Table 5.7. Thermal Characteristics

Si53258/Si53254 Data Sheet

Electrical Specifications

Parameter Symbol

40 QFN

Thermal Resistance, Junction to Ambient

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Board

32 QFN

Thermal Resistance, Junction to Ambient

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Board

Note:

Based on JEDEC standard 4-layer PCB.

1.

Test Condition

1

Value Units

Still Air 23.1

θ

JA

Air Flow 1 m/s 17.5

Air Flow 2 m/s 16.5

θ

JC

θ

JB

ψ

JB

13.4

8.7

8.4

°C/W

Still Air 28.4

θ

JA

Air Flow 1 m/s 24

Air Flow 2 m/s 23

θ

JC

θ

JB

ψ

JB

15.9

11.5

11.2

°C/W

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