Silicon Labs EFM32JGxx, EFM32JPGxx User Manual
AN0918.0: MCU Series 0 to EFM32JGxx/
PGxx Compatibility and Migration Guide
This porting guide is targeted at migrating an existing design from
MCU Series
0 to EFM32JGxx/PGxx or Wireless SoC Series 1.
Both hardware and software migration needs to be considered.
The core and peripherals of EFM32JGxx/PGxx or Wireless SoC Series 1 devices are
based on the existing MCU Series 0 with better performance and lower current consumption.
This document will describe which aspects are enhanced in the peripherals common
between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1. Details for all
of the new peripherals of EFM32JGxx/PGxx and Wireless SoC Series 1 can be found
in the reference manual, and it is recommended to review the available example code
for assistance and recommendations.
All peripherals in the MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
devices are described in general terms. Not all modules are present in all devices, and
the feature set for each device might vary. Such differences, including pinout, are covered in the device-specific data sheets.
KEY POINTS
• EFM32JGxx/PGxx and Wireless SoC
Series 1 have commonalities and
enhancements from
peripherals.
• Software and hardware migration must
both be considered when porting from an
MCU Series 0 device to EFM32JGxx/
PGxx or Wireless SoC Series 1 device.
• The EFM32JGxx/PGxx and Wireless SoC
Series 1 devices are software compatible
with the existing MCU Series 0 devices, so
only minor changes are required for
common peripherals.
• Refer to the example code for specific
recommendations and assistance.
MCU Series 0
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
1. Device Compatibility
This application note supports multiple device families, and some functionality is different depending on the device.
MCU Series 0 consists of:
• EFM32 Gecko (EFM32G)
• EFM32 Giant Gecko (EFM32GG)
• EFM32 Wonder Gecko (EFM32WG)
• EFM32 Leopard Gecko (EFM32LG)
• EFM32 Tiny Gecko (EFM32TG)
• EFM32 Zero Gecko (EFM32ZG)
• EFM32 Happy Gecko (EFM32HG)
Wireless MCU Series 0 consists of:
• EZR32 Wonder Gecko (EZR32WG)
• EZR32 Leopard Gecko (EZR32LG)
• EZR32 Happy Gecko (EZR32HG)
MCU Series 1 consists of:
• EFM32 Jade Gecko (EFM32JG1/EFM32JG12) (Collectively referred to in this document as EFM32JGxx)
• EFM32 Pearl Gecko (EFM32PG1/EFM32PG12) (Collectively referred to in this document as EFM32PGxx)
Device Compatibility
Wireless SoC Series 1 consists of:
• EFR32 Blue Gecko (EFR32BG1/EFR32BG12/EFR32BG13)
• EFR32 Flex Gecko (EFR32FG1/EFR32FG12/EFR32FG13)
• EFR32 Mighty Gecko (EFR32MG1/EFR32MG12/EFR32MG13)
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Compatibility Overview
2. Compatibility Overview
Four factors must be considered when porting a design from MCU Series 0 to EFM32JGxx/PGxx or Wireless SoC Series 1: pin compatibility, hardware compatibility, software compatibility, and peripheral compatibility.
2.1 Pins and Hardware
EFM32JGxx/PGxx and Wireless SoC Series 1 devices are not footprint compatible with MCU Series 0 devices.
More information on footprint and hardware compatibility between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1 can
be found in 6. Hardware Migration.
2.2 Software and Peripherals
Software compatibility between MCU Series 0 is maintained using emlib and emdrv, which are software libraries built upon the CMSIS
(Cortex Microcontroller Software Interface Standard) layer defined by ARM. These devices are not binary compatible, meaning code
compiled for an MCU Series 0 should not work after being downloaded to an EFM32JGxx/PGxx. However, if the software is written
using the emlib or emdrv modules, then the application code should not need to change in most cases when recompiling for the new
EFM32JGxx/PGxx target.
Note: There are some small exceptions to full software compatibility across MCU Series 0 and EFM32JGxx/PGxx. For example, wakeup pins and GPIO drive strength are implemented slightly differently on these parts, so the emlib functions have changed slightly to
accommodate these differences. Wherever possible, these details have been abstracted away by the emlib and emdrv modules. See
5.1 Peripheral Support Library (emlib) and energyAware Drivers (emdrv) for more information on compatibility between MCU Series 0
and EFM32JGxx/PGxx. Consult the [Gecko SDK Suite] under [Documentation] in Simplicity Studio for more information on the emlib
and emdrv modules.
The emlib and emdrv modules provide abstraction layers that make peripheral initialization and usage simple and easy. Version 5.1.2
or above of the emlib and emdrv modules support the following peripherals across MCU Series 0 and EFM32JGxx/PGxx:
Table 2.1. The emlib and emdrv Support for MCU Series 0 and EFM32JGxx/PGxx
Peripherals Supported by emlib
ACMP ADC
AES
1
BURTC CMU CORE CRYOTIMER
CRYPTO
1
CSEN DAC DBG DMA EBI EMU GPCRC GPIO
I2C IDAC INT LCD LDMA LESENSE LETIMER LEUART
MPU MSC OPAMP PCNT PRS RMU RTC RTCC
SYSTEM TIMER USART VCMP VDAC WDOG — —
Note:
1.
For AES and CRYPTO, use the mbedTLS library.
The emdrv Modules
DMADRV EZRADIODRV GPIOINTERR-
NVM RTCDRV SLEEP SPIDRV TEMPDRV
PUT
UARTDRV USTIMER — — — — — —
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Compatibility Overview
Since the emlib and emdrv modules are common across MCU Series 0 and EFM32JGxx/PGxx, the look and feel of the software development experience
struct software and use peripherals on the EFM32JGxx/PGxx products. In addition, existing MCU Series 0 designs can be quickly ported to new products to take advantage of new capabilities available on the EFM32JGxx/PGxx by utilizing the common code base between the families.
For systems that have software written without the use of emdrv, there are two methods to migrate a design from MCU Series 0 to
EFM32JGxx/PGxx:
1. Elevate the code to the level of emdrv to take advantage of the hardware abstraction provided by this layer.
2. Use the information in this document to migrate the code to the peripherals featured on the EFM32JGxx/PGxx products.
More information on software migration can be found in 5. Software Migration, and more information on the peripheral commonalities
and differences can be found in 4. Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1.
Wireless SoC Series 1 devices are configurable through the Silicon Labs software stacks, which are a layer on top of the emdrv modules. Systems migrating from MCU Series 0 to a Wireless SoC Series 1 platform should use the tools available in Simplicity Studio to
migrate their code.
is familiar. In other words, developers experienced with the MCU Series 0 products will already know how to con-
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
3. System Overview
3.1 Core and Memory
This section compares the core and memory of MCU Series 0 with EFM32JGxx/PGxx and Wireless SoC Series 1.
Table 3.1. Core and Memory
System Overview
MCU Series 0 EFM32JGxx/PGxx and Wire-
less SoC Series 1
Core
ARM Cortex M0+, M3 and M4
with FPU
Debug Interface
The 2-pin serial-wire debug
(SWD) interface.
DMA Controller (DMA)
ARM µDMA Controller Linked DMA Controller (LDMA) LDMA is completely a new design, it is more flexible and higher
EFM32JGxx:
ARM Cortex M3
EFM32PGxx and Wireless SoC
Series 1:
ARM Cortex M4 with FPU
The 2-pin serial-wire debug
(SWD) interface or a 4-pin Joint
Test Action Group (JTAG) interface.
Notes
—
Debug interface (SWD, JTAG, and ETM) for each device might
vary, such differences are covered in the device-specific data
sheets.
performance.
Number of DMA channels for each device might vary, such differences are covered in the device-specific data sheets. The dmadrv
module can also be used to assist with family differences.
Flash Program Memory
4 - 1024 KB 128 - 1024 KB Flash program memory for each device might vary, such differen-
ces are covered in the device-specific data sheets.
RAM Memory
2 - 128 KB EFM32JGxx/PGxx:
32 - 256 KB
Wireless SoC Series 1
16 - 256 KB
:
RAM memory for each device might vary, such differences are
covered in the device-specific data sheets.
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3.2 Peripherals in MCU Series 0 only
AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
System Overview
This section descibes the peripherals of MCU Series 0 that are not available in
EFM32JGxx/PGxx and Wireless SoC Series 1.
Refer to 5.1 Peripheral Support Library (emlib) and energyAware Drivers (emdrv) and 6.4 Peripherals Only on MCU Series 0 on how to
migrate these MCU Series 0 peripherals to EFM32JGxx/PGxx or Wireless SoC Series 1.
Table 3.2. Peripherals in MCU Series 0 only
MCU Series 0
Analog Interfaces
LCD Controller (LCD)
Energy Management
Voltage Comparator (VCMP)
Back-up Power Domain
I/O Ports
External Bus Interface (EBI)
Security
Advanced Encryption Standard Accelerator (AES)
Serial Interfaces
UART
USB
Timers and Triggers
Backup Real Time Counter (BURTC)
Real Time Counter (RTC)
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
3.3 New Peripherals in EFM32JGxx/PGxx and Wireless SoC Series 1
System Overview
This section
describes the new peripherals that are available in EFM32JGxx/PGxx and Wireless SoC Series 1. The RF portions of
Wireless SoC Series 1 are not included in this comparison.
Table 3.3. New Peripherals in EFM32JGxx/PGxx and Wireless SoC Series 1
EFM32JGxx/PGxx and Wireless SoC Series 1
Analog Interfaces
Analog Port (APORT)
Capacitive Sense Module (CSEN)
1
Clock Management
High Frequency RC Oscillator (HFRCO) with Digital Phase-Locked Loop (DPLL)
Energy Management
DC-DC Converter
Voltage/Temp Monitor
Security
Crypto Accelerator (CRYPTO)
General Purpose Cyclic Redundancy Check (GPCRC)
Security Management Unit (SMU)
True Random Number Generator (TRNG)
1
1
2
Timers and Triggers
Ultra Low Energy Timer/Counter (CRYOTIMER)
Real Time Counter and Calendar (RTCC)
32 bit General Purpose Timer (WTIMER)
1
Note:
1.
Peripherals are only available on
EFM32JG1x/PG1x and EFR32xG12/xG13 devices.
2. Peripherals are only available on EFM32JG1x/PG1x devices.
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
4. Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
4.1 Core and Memory
4.1.1 Debug (DBG)
The major changes are JTAG support and AAP lock.
Table 4.1. DBG
MCU Series 0 EFM32JGxx/PGxx and Wire-
less SoC Series 1
Enhancements
Hardware Debug support
through a 2-pin serial-wire debug (SWD) interface.
Debug Lock only. Debug Lock (DLW in lockbits
New Features
— The system bus can be stalled
— The CRCREQ command
Limitations
— — —
Hardware debug support
through a 2-pin serial-wire debug (SWD) interface or a 4-pin
Joint Test Action Group (JTAG)
interface.
page) and AAP Lock (ALW in
lockbits page).
by AAP_CTRL register.
(AAP_CRCCMD register) initiates a CRC calculation on a
given Flash Page.
Notes
The debug pins can be enabled and disabled through
GPIO_ROUTE_PEN.
If enabling the JTAG pins, the part must be power cycled to enable a SWD debug session.
The AAP_CMD register is locked by AAP Lock and this process is
irreversible. The user can no longer access the AAP_CMD register to issue a mass erase to the FLASH in order to gain entry to
the system via the debugger.
Use the SYSBUSSTALL bit in AAP_CTRL register.
The CRC is only available on the Main, User Data, and Lock Bit
pages.
It is highly recommended that the system bus is stalled before any
CRCREQ commands are issued.
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
4.1.2 Memory and Bus System
The major changes are the RAM segments and single-cycle bit access for peripherals.
Table 4.2. Memory and Bus System
MCU Series 0 EFM32JGxx/PGxx and Wire-
Notes
less SoC Series 1
Enhancements
Single RAM segment. The SRAM memory is split into
different AHB slaves, each having an individual bus connec-
This enables simultaneous access to different RAM segments,
e.g. if the core is accessing one RAM segment, the DMA can access another RAM segment without any bus contention.
tion.
New Features
— Peripheral Bit Set and Clear –
Dedicate inline function in em_bus.h.
single cycle bit set and clear to
peripherals' registers.
__STATIC_INLINE void BUS_RegBitWrite(volatile
uint32_t* const addr, uint32_t bit, uint32_t val)
Peripherals that do not support Bit Set and Bit Clear are EMU,
RMU, CRYOTIMER and TRNG0.
Limitations
— — —
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
4.1.3 Memory System Controller (MSC)
The major change is the addition of a dedicated page for the bootloader and AAP lock.
Table 4.3. MSC
MCU Series 0 EFM32JGxx/PGxx and Wire-
Notes
less SoC Series 1
Enhancements
Configure MSC_TIMEBASE
register for falsh erase and write
opeations.
Bus fault only on access to unmapped code and system
Timing configuration is not re-
—
quired for flash erase and write
operations.
Bus fault on different scenarios. The different bus fault responses are enabled by fields in
MSC_CTRL register.
space.
New Features on All EFM32JGxx/PGxx and Wireless SoC Series 1 Devices
Bootloader is placed on Main
Page.
Bootloader can be placed on
dedicated page at address
The system is configured to boot from bootloader at address
0x0FE10000 automatically after system reset.
0x0FE10000 (10 KB or 32 KB).
User can bypass the bootloader by clear bit 1 in Config Lock
Word 0 (CLW0) in word 122 of lockbit (LB) page.
— An additional atomic Read-clear
operation for IFC register.
— Authentication Access Port
It can be enabled by setting IFCREADCLEAR in the MSC_CTRL
register.
Word 124 of lockbit (LB) page is the AAP lock word (ALW).
(AAP) lock bits for AAP lock.
New Features Only on EFM32JG1x/PG1x and EFR32xG12/xG13 Devices
— The SWITCHINGBANK comm-
This command is only available on devices with dual-bank flash.
nad (MSC_CMD) initiates a
bank swithcing to swap between
two flash instances.
This feature can be disabled by Config Lock Word 1 (CLW1) in
word 123 of lockbit (LB) page.
— Low voltage flash read when
scaling down supply voltage to
reduce current consumption.
The system clock frequency and flash wait states should be pro-
grammed accordingly since it takes a longer time to read from
flash with a lower voltage supply.
Flash write/erase is not supported in low voltage mode.
— Bootloader software reads and
writes enable.
Reading and writing of bootloader area may be enabled with the
MSC_BOOTLOADERCTRL register.
The BOOTLOADERCTRL register is write-once, so after writing
the register, a reset of the system is required in order to change
permissions again.
— Advance cache control. Through MSC_CACHECONFIG0 and MSC_RAMCTRL registers.
Limitations
Flash wait states:
•
HFCLK > 16 MHz 1WS
•
HFCLK > 32 MHz 2WS
Flash wait states:
•
HFCLK > 26 MHz 1WS
Flash wait states (MODE field in MSC_READCTRL register) at
voltage scaling level 0 on EFM32JG1x/PG1x and EFR32xG12/
xG13 devices:
• 7 MHz < HFCLK <= 14 MHz 1WS
• 14 MHz < HFCLK <= 21 MHz 2WS
No Flash Startup time on transitions from EM2/3 to EM0
Flash Startup time on transitions
from EM2/3 to EM0 depends on
The related parameters are stored in MSC_STARTUP register.
the current operating conditions.
Minimum 20000 erase cycles
endurance.
Minimum 10000 erase cycles
endurance.
—
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
4.2 Clock Management
4.2.1 Clock Management Unit (CMU)
The major changes are the new HFXO automatic start features and Digital Phased-Locked Loop (DPLL).
Table 4.4. CMU
MCU Series 0 EFM32JGxx/PGxx and Wireless
Notes
SoC Series 1
Enhancements on All EFM32JGxx/PGxx and Wireless SoC Series 1 Devices
1.2 MHz – 28 MHz HFRCO
(1.2, 6.6, 11, 14, 21 and 28
MHz), HFRCO is 14 MHz after
reset.
1.2 MHz – 28 MHz AUXHFRCO
(1.2, 6.6, 11, 14, 21 and 28
MHz), AUXHFRCO is 14 MHz
after reset.
LFRCO and LFXO ready interrupt are available in EM0 - EM1
energy modes.
Startup time setup for LFXO
and HFXO.
1 MHz – 38 MHz HFRCO (1, 2, 4,
7, 13, 16, 19, 26, 32 and 38
MHz), HFRCO is 19 MHz after
reset.
1 MHz – 38 MHz AUXHFRCO (1,
2, 4, 7, 13, 16, 19, 26, 32 and 38
MHz), AUXHFRCO is 19 MHz after reset.
LFRCO and LFXO ready interrupt
are available in EM0 - EM2 energy modes.
Startup time setup for LFRCO,
LFXO, and HFXO.
Additional FINETUNING and FINETUNINGEN fields in
MSC_HFRCOCTRL register for HFRCO frequency tuning.
Additional FINETUNING and FINETUNINGEN fields in
MSC_AUXHFRCOCTRL register for AUXHFRCO frequency tuning.
The LFRCORDY and LFXORDY fields are in CMU_IEN register.
The HFXO has a second time-out counter which can be used to
achieve deterministic startup time based on timing from the
LFXO, ULFRCO, or LFRCO.
Only TUNING field in
CMU_LFRCOCTRL register.
More fields in
CMU_LFRCOCTRL register to
—
configure LFRCO.
— More settings for HFXO startup
with on-chip tunable capacitance.
Add CMU_HFXOCTRL, CMU_HFXOSTARTUPCTRL,
CMU_HFXOSTEADYSTATECTRL and CMU_HFXOTIMEOUTCTRL registers.
— More settings for LFXO startup
Add CMU_LFXOCTRL register.
with on-chip tunable capacitance.
— Clock output to PRS. Selected by a PRS consumer as CMUCLKOUT0 or CMUCLK-
OUT1.
— Calibration input from PRS. Selected by PRSUPSEL and PRSDOWNSEL fields in
CMU_CALCTRL register.
Enhancements Only on EFM32JG1x/PG1x and EFR32xG12/xG13 Devices
The Watchdog (WDOG) can be
clocked by LFRCO, LFXO, and
ULFRCO.
The SYSTICK can be clocked
by HFCORECLK.
The Watchdog (WDOG) can be
clocked by HFCORECLK,
LFRCO, LFXO, and ULFRCO.
The SYSTICK can be clocked by
HFCORECLK or LFBCLK.
—
The LFBCLK can be HFCLKLE, LFXO, LFRCO, or ULFRCO.
New Features on All EFM32JGxx/PGxx and Wireless SoC Series 1 Devices
— Add LFECLK for RTCC. LFECLK is available down to EM4H.
— Add HFEXPCLK for HFCLK out-
Prescaled version of HFCLK to CMU_OUT0 or CMU_OUT1.
put.
— Add HFBUSCLK without prescal-
er, separate it from HFCOR-
The LE, CRYPTOn, GPIO, PRS, LDMA and GPCRC are clocked
by HFBUSCLK if enable.
ECLK.
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AN0918.0: MCU Series 0 to EFM32JGxx/PGxx Compatibility and Migration Guide
Peripherals Common Between MCU Series 0, EFM32JGxx/PGxx, and Wireless SoC Series 1
MCU Series 0 EFM32JGxx/PGxx and Wireless
Notes
SoC Series 1
— AUXHFRCO can clock ADC in
Selected by ADC0CLKSEL field in CMU_ADCCTRL register.
EM2/3.
— Automatic HFXO Start. The enabling of the HFXO and its selection as HFCLK source
can be performed automatically by hardware.
New Features Only on EFM32JG1x/PG1x and EFR32xG12/xG13 Devices
— New clock sources, HFRCODIV2
and CLKIN0, for HFCLK.
— The Digital Phase-Locked Loop
The HFROCDIV2 is HFRCO divided by 2 and CLKIN0 is the external clock source from the dedicate CLKIN0 pin.
The reference clock source can be HFXO, LFXO, or CLKIN0.
(DPLL) generates a digitally controlled oscillator (DCO), which is
HFRCO, as a ratio of a reference
The DPLL is disabled automatically when entering EM2, EM3,
EM4H or EM4S.
clock source.
Limitations
HFXO range is 4 – 48 MHz. HFXO range is 38 – 40 MHz. —
HFCORECLKLE > 24 or 32
MHz
•
Set HFLE if available
Set HFCORECLKLEDIV to
•
HFBUSCLKLE > 32 MHz
• Set WSHFLE
• Set HFCLKLEPRESC to DIV4
The WSHFLE is in CMU_CTRL register and HFCLKLEPRESC is
in CMU_HFPRESC register.
DIV4
HFXTAL_P and HFXTAL_N
pins can use as GPIO.
HFXTAL_P and HFXTAL_N pins
cannot use as GPIO.
— LFACLK cannot select
HFBUSCLKLE as clock source.
—
The LESENSE and LETIMER are clocked by LFACLK.
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