Silicon Labs EFM32, EFR32 User Manual

AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

This application note provides an overview of the CMU module for EFM32 and EFR32 Wireless Gecko Series 1 devices with explanations on how to choose clock sources, prescaling, and clock calibration.

It also contains information about how to handle oscillators on wake up, external clock sources, and RC oscillator calibration.

KEY POINTS

• The CMU has several internal clock sources available.

• The CMU can also use external high frequency and low frequency clock sources.

• Selecting the right clock source is key for creating low energy applications.

• This application note includes:

• This PDF document

• Source files

• Example C-code

• Multiple IDE projects

Oscillators

CMU

WDOG clock

LETIMER clock

LCD clock

Peripheral A clock

Peripheral B clock

Peripheral C clock

Peripheral D clock

CPU clock

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

1. Device Compatibility

This application note supports multiple device families, and some functionality is different depending on the device.

EFM32 Series 1 consists of:

• EFM32 Jade Gecko (EFM32JG1/EFM32JG12)

• EFM32 Pearl Gecko (EFM32PG1/EFM32PG12)

• EFM32 Giant Gecko (EFM32GG11)

EFR32 Wireless Gecko Series 1 consists of:

• EFR32 Blue Gecko (EFR32BG1/EFR32BG12/EFR32BG13)

• EFR32 Flex Gecko (EFR32FG1/EFR32FG12/EFR32FG13)

• EFR32 Mighty Gecko (EFR32MG1/EFR32MG12/EFR32MG13)

Device Compatibility

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

2. Functional Description

The Clock Management Unit (CMU) controls the oscillators and clocks. It can enable or disable the clock to the different peripherals individually, as well as enable, disable, or configure the available oscillators. This allows for minimizing energy consumption by disabling the clock for unused peripherals or having them run at lower frequencies.

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

2.1 Clock Branches

The CMU main and sub clock branches are described in the tables below. Some peripherals have dedicated prescalers, such as the Low Energy peripherals. Other peripheral clocks must be prescaled at the source such that the same prescaled clock is driven to all peripherals using that same source.

A detailed clock tree diagram can be found in the CMU chapter at the beginning of the Functional Description section of a given device's reference manual.

Table 2.1. Blue, Flex, Jade, Mighty, and Pearl Gecko Clock Branches

Main Clock Branch

Clock Source

HFCLK HFSRCCLK

• HFRCO

• HFXO

• LFRCO

• LFXO

• HFRCODIV2

• CLKIN0

Sub-clock Branch 1

HFPERCLK

Sub-clock Branch 2

• ACMP0, ACMP1

• ADC0

• CRYOTIMER

• CSEN

• IDAC0

• I2C0, I2C1

• TIMER0, TIMER1

• TRNG0

• USART0, USART1, USART2, USART3

• WTIMER0, WTIMER1

• VDAC0

HFCORECLK CORTEX (Core)

HFEXPCLK —

HFBUSCLK • CRYPTO0, CRYPTO1

• GPCRC

• GPIO

• LDMA

• LE

• PRS

DBGCLK —

HFRADIOCLK • AGC

• BUFC

• CRC

• FRC

• MODEM

• PROTIMER

• RAC

• RFSENSE

• SYNTH

Radio Transceiver HFXO — —

(DPLL) • HFXO

ref

— —

• CLKIN0

• LFXO

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

Main Clock Branch

Clock Source

Sub-clock Branch 1

Sub-clock Branch 2

AUXCLK AUXHFRCO ADC_CLK —

DBGCLK

LESENSE —

MSC —

LFACLK • LFRCO

• LFXO

• ULFRCO

LFBCLK • HFCLKLE (HFBUSCLKLE/2

or /4)

• LFRCO

• LESENSE

• LETIMER0

• PCNT

• CSEN

• LEUART0

• SYSTICK

—

• LFXO

• ULFRCO

LFECLK • LFRCO

RTCC —

• LFXO

• ULFRCO

WDOGCLK • HFRCORECLK

CORETEX

WDOG —

• LFRCO

• LFXO

• ULFRCO

CRYOCLK • LFRCO

CRYOTIMER —

• LFXO

• ULFRCO

RFSENSECLK • RF Detector Clock

RFSENSE —

• LFRCO

• LFXO

• ULFRCO

Note:

1. Not all main and sub clock branches are available on a given device. Refer to the device reference manual and data sheet for details

2. Not all clock sources for main clock branches are available on a given device. Refer to the device reference manual and data sheet for details.

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Table 2.2. Giant Gecko Series 1 Clock Branches

Functional Description

Main Clock Branch

Clock Source

HFCLK HFSRCCLK

• HFRCO

• HFXO

• LFRCO

• LFXO

• HFRCODIV2

• USHFRCO

• CLKIN0

Sub-clock Branch 1

Sub-clock Branch 2

HFPERCLK • ADC0

• CAN0, CAN1

• TIMER1, TIMER2, TIMER3 TIMER4, TIMER5, TIMER6

• TRNG0

• UART0, UART1

• USART0, USART1, USART3, USART4, USART5

• WTIMER0, WTIMER1, WTIMER2, WTIMER3

HFPERBCLK • TIMER0

• USART2

HFPERCCLK • ACMP0, ACMP1, ACMP2,

ACMP3

• ADC0, ADC1

• CRYOTIMER

• CSEN

• IDAC0

• I2C0, I2C1, I2C2

• VDAC0

(DPLL) • HFXO

ref

• LFXO

• USHFRCO

• CLKIN0

HFCORECLK CORTEX (Core)

HFEXPCLK —

HFBUSCLK

• CRYPTO0

• EBI

• ETH

• GPCRC

• GPIO

• LDMA

• LE

• PRS

• QSPI0

• SDIO

• USB

DBGCLK —

— —

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

Main Clock Branch

Clock Source

Sub-clock Branch 1

Sub-clock Branch 2

AUXCLK AUXHFRCO ADC0_CLK —

ADC1_CLK —

DBGCLK

LESENSE —

MSC —

QSPI0_CLK —

SDIO_CLK —

LFACLK • LFRCO

• LFXO

• ULFRCO

• LCD

• LESENSE

• LETIMER0, LETIMER1

—

• PCNT

• RTC

LFBCLK • HFCLKLE (HFBUSCLKLE/2

or /4)

• LFRCO

• CSEN

• LEUART0, LEUART1

• SYSTICK

—

• LFXO

• ULFRCO

LFCCLK • LFRCO

USB —

• LFXO

• ULFRCO

LFECLK • LFRCO

RTCC —

• LFXO

• ULFRCO

WDOGnCLK • HFRCORECLK

CORETEX

WDOGn —

• LFRCO

• LFXO

• ULFRCO

CRYOCLK • LFRCO

CRYOTIMER —

• LFXO

• ULFRCO

Note:

1. Not all main and sub clock branches are available on a given device. Refer to the device reference manual and data sheet for details

2. Not all clock sources for main clock branches are available on a given device. Refer to the device reference manual and data sheet for details.

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

2.2 Clock Sources

There are a maximum of eight oscillators that can be used as clock sources for different purposes. The HFCLK is usually clocked by the HFXO or HFRCO, whereas low energy peripherals are usually clocked by the LFXO, LFRCO, or ULFRCO. The AUXHFRCO is typically used for the LESENSE, ADC asynchronous mode, flash programming, and the SWO debug output. The USHFRCO is intended primarily for the USB controller on Giant Gecko Series 1 but can also drive the HFCLK, if needed.

Table 2.3. Clock Sources

Oscillator Frequency Range

HFXO

HFRCO

AUXHFRCO

USHFRCO

38 – 40 MHz1 or 4 to 50 MHz

1 – 38 MHz1 or 72 MHz

1 – 381 MHz or 1 – 50 MHz

1 – 50 MHz

LFXO 32768 Hz

LFRCO 32768 Hz

ULFRCO 1000 Hz

Note:

1. EFM32xG1 and EFR32xG1/xG12/xG13

2. Giant Gecko Series 1 only

To select the clock source for a branch (e.g. HFCLK, LFA, or LFB), the chosen oscillator must be enabled before it is selected as the clock source. If this is not done, the modules that are running from that clock branch will stop. In the case of selecting a disabled oscillator for the HFCLK branch, the CPU will stop and can only be recovered after a reset.

After a reset, the HFCLK branch is clocked by the HFRCO at the default 19 MHz frequency band, and all low frequency branches are disabled.

Emlib has functions to enable or disable an oscillator and select it as a clock source.

Table 2.4. emlib Functions for Oscillator Enable, Disable and Selection

emlib Function Usage Example

CMU_OscillatorEnable(CMU_Osc_ TypeDef osc, bool enable, bool wait)

Select which oscillator to enable or disable and if it should wait for the oscillator to stabilize before returning.

Enable HFXO and wait for it to stabilize:

CMU_OscillatorEnable (cmuOsc_HFXO, true, true);

Disable HFRCO:

CMU_OscillatorEnable (cmuOsc_HFRCO, false, false);

CMU_ClockSelectSet(CMU_Clock_ TypeDef clock, CMU_Select_TypeDef ref)

• Enables the chosen clock source in case it has not been enabled yet.

• The clock parameter is one of the main clock branches, and the ref parameter is one of the clock sources for the selected clock branch.

Select HFXO as the source of HFCLK:

CMU_ClockSelectSet (cmuClock_HF, cmuSelect_HFXO);

Select LFXO as the source of LFACLK:

CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

2.2.1 Clock Input from a Pin

It is possible to configure the CMU to use an external clock input on the CLKIN0 pin. This clock can be selected as the HFSRCCLK and as the DPLL reference using the CMU_HFCLKSEL and CMU_DPLLCTRL registers, respectively. The input pin must be enabled in the CMU_ROUTEPEN register, and the pin location is selected by the CLKIN0LOC bit field in the CMU_ROUTELOC1 register.

Note: This feature is not available on EFM32xG1 and EFR32xG1 devices.

2.3 Oscillator Configuration

2.3.1 HFXO

The High Frequency Crystal Oscillator (HFXO) is configured to ensure safe startup and operation for most common crystals by default. In order to optimize startup time and power consumption for a given crystal, it is possible to adjust certain oscillator parameters. For more information, refer to application note, AN0016: Oscillator Design Considerations.

The HFXO (38 MHz - 40 MHz) needs to be configured to ensure safe startup for the given crystal. The HFXO includes on-chip tunable capacitance, which can replace external load capacitors.

Upon enabling the HFXO, a hardware state machine sequentially applies the configurable startup state and steady state control settings from the CMU_HFXOSTARTUPCTRL and CMU_HFXOSTEADYSTATECTRL registers. Please refer to the device reference manual for the detailed CMU HFXO control state machine flow.

Both the startup state and the steady state of the HFXO require configuration. After reaching the steady operating state, the HFXO configuration can optionally be further tuned to minimize noise and current consumption.

Optimization for noise can be performed using an automatic Peak Detection Algorithm (PDA). Optimization for current can be performed after running the PDA by an automatic Shunt Current Optimization algorithm (SCO). HFXO operation is possible without running PDA and SCO at the cost of higher noise and current consumption than is necessary.

Fixed frequency clock sources (e.g. the HFXO or CLKIN) must be disabled if voltage scaling is used (not availble on EFM32xG1 and EFR32xG1 devices) and the frequency of such sources exceeds the maximum supported system frequency.

Table 2.5. HFXO Configuration

Configuration and Optimization Bit Field and Register

Configurable startup state Bit fields in CMU_HFXOSTARTUPCTRL

Configurable Steady State Bit fields in CMU_HFXOSTEADYSTATECTRL

Optimization for Noise (PDA)

Optimization for Current (SCO)

PEAKDETSHUNTOPTMODE bit field in CMU_HFXOCTRL

Note:

1. The manual PDA and SCO modes are not recommended for general use. PDA should not be used with an external clock source.

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

2.3.1.1 Using emlib for HFXO Configuration

Emlib has structures and functions that simplify configuration of the HFXO for efficient operation. Use of emlib is strongly recommended for this reason and also in order to avoid or workaround errata related to the HFXO.

Initialization of the HFXO depends on the structure of type CMU_HFXOInit_TypeDef:

typedef struct { #if defined( _CMU_HFXOCTRL_MASK ) bool lowPowerMode; /**< Enable low-power mode */ bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ uint8_t regIshSteadyState; /**< Shunt steady-state current */ uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ uint8_t thresholdPeakDetect; /**< Peak detection threshold */ uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ uint8_t timeoutSteady; /**< Timeout - steady-state */ uint8_t timeoutStartup; /**< Timeout - startup */ #else uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ uint8_t timeout; /**< Startup delay */ bool glitchDetector; /**< Enable/disable glitch detector */ #endif CMU_OscMode_TypeDef mode; /**< Oscillator mode */ } CMU_HFXOInit_TypeDef;

Structure members can be set by the user, otherwise the default structures CMU_HFXOINIT_DEFAULT and

CMU_HFXOINIT_EXTERNAL_CLOCK can be used as templates for HFXO initialization.

#if defined( _EFR_DEVICE ) #define CMU_HFXOINIT_DEFAULT \ { \ false, /* Low-noise mode for EFR32 */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ 0x20, /* Matching errata fix in CHIP_Init() */ \ 0x7, /* Recommended steady-state XO core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ 0xA, /* Recommended peak detection timeout */ \ 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ cmuOscMode_Crystal, \ } #else /* EFM32 device */ #define CMU_HFXOINIT_DEFAULT \ { \ true, /* Low-power mode for EFM32 */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ 0x20, /* Matching errata fix in CHIP_Init() */ \ 0x7, /* Recommended steady-state osc core bias current */ \ 0x6, /* Recommended peak detection threshold */ \ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ 0xA, /* Recommended peak detection timeout */ \ 0x4, /* Recommended steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

cmuOscMode_Crystal, \ } #endif /* _EFR_DEVICE */ #define CMU_HFXOINIT_EXTERNAL_CLOCK \ { \ true, /* Low-power mode */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ false, /* @deprecated no longer in use */ \ 0, /* Startup CTUNE=0 recommended for external clock */ \ 0, /* Steady CTUNE=0 recommended for external clock */ \ _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \ 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ 0x6, /* Recommended peak detection threshold */ \ _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \ 0x0, /* Peak-detect not recommended for external clock usage */ \ _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ cmuOscMode_External, \ }

The HFXO initialization structure is used as an argument when calling the CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) function, which writes the HFXO initialization parameters to the relevant CMU registers. After calling this function call, the HFXO can be enabled and selected as the source of HFCLK as shown below.

/* Initialize HFXO with specific parameters */ CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; CMU_HFXOInit(&hfxoInit);

/* Enable and set HFXO for HFCLK */ CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);

2.3.2 LFXO

The Low Frequency Crystal Oscillator (LFXO) is configured to ensure safe startup and operation for most common crystals by default. In order to optimize startup time and power consumption for a given crystal, it is possible to adjust certain oscillator parameters. For more information, refer to application note, AN0016: Oscillator Design Considerations.

The LFXO includes on-chip tunable capacitance, which can replace external load capacitors. The LFXO is configured by bit fields in the CMU_LFXOCTRL register. Note that these bit fields should set only during initialization and are not be changed while the LFXO is enabled.

Table 2.6. CMU_LFXOCTRL Register for LFXO Configuration

Bit Field Usage

GAIN Adjusts the oscillator startup gain .

TUNING Tunes the internal load capacitance connected between LFXTAL_P and ground and LFXTAL_N and ground

symmetrically.

HIGHAMPL Setting this bit drives the crystal with a higher amplitude waveform, which in turn provides safer operation,

somewhat improves duty cycle, and lowers sensitivity to noise at the cost of increased current consumption.

AGC Setting this bit enables Automatic Gain Control, which limits the amplitude of the driving waveform in order to

reduce current draw. When AGC is disabled, the LFXO runs at the startup current, and the crystal will oscillate rail to rail, providing safer operation, improved duty cycle, and lower sensitivity to noise at the cost of increased current consumption.

BUFCUR The default value is intended to cover all use cases and reprogramming is not recommended.

CUR The default value is intended to cover all use cases and reprogramming is not recommended.

2.3.2.1 Using emlib for LFXO Configuration

Emlib has structures and functions that simplify configuration of the LFXO for efficient operation. Use of emlib is strongly recommended for this reason and also in order to avoid or workaround errata related to the LFXO.

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AN0004.1: EFM32 Series 1 and EFR32 Wireless MCU Clock Management Unit (CMU)

Functional Description

Initialization of the LFXO depends on the structure of type CMU_LFXOInit_TypeDef:

typedef struct { #if defined( _CMU_LFXOCTRL_MASK ) uint8_t ctune; /**< CTUNE (load capacitance) value */ uint8_t gain; /**< Gain / max startup margin */ #else CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ #endif uint8_t timeout; /**< Startup delay */ CMU_OscMode_TypeDef mode; /**< Oscillator mode */ } CMU_LFXOInit_TypeDef;

Structure members can be set by the user, otherwise the default structures CMU_LFXOINIT_DEFAULT and

CMU_LFXOINIT_EXTERNAL_CLOCK below can be used as templates for LFXO initialization.

#define CMU_LFXOINIT_DEFAULT \ { \ _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32k cycles */ \ cmuOscMode_Crystal, /* Crystal oscillator */ \ } #define CMU_LFXOINIT_EXTERNAL_CLOCK \ { \ 0, /* No CTUNE value needed */ \ 0, /* No LFXO startup gain */ \ _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ cmuOscMode_External, /* External digital clock */ \ }

The LFXO initialization structure is used as an argument when calling the CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) function, which writes the LFXO initialization parameters to the relevant CMU registers. After calling this function, the LFXO can be enabled and selected as the clock source for low energy peripherals.

/* Initialize LFXO with specific parameters */ CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; CMU_LFXOInit(&lfxoInit);

/* Enable and set LFXO for LFACLK */ CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);

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+ 27 hidden pages

Silicon Labs EFM32, EFR32 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Device Compatibility

2. Functional Description

2.1 Clock Branches

2.2 Clock Sources

2.2.1 Clock Input from a Pin

2.3 Oscillator Configuration

2.3.1 HFXO

2.3.1.1 Using emlib for HFXO Configuration

2.3.2 LFXO

2.3.2.1 Using emlib for LFXO Configuration