Silicon Labs AN0002.2, EFM32, EFR32 User Manual
AN0002.2: EFM32 and EFR32 Wireless
Gecko Series 2 Hardware Design
Considerations
This application note details hardware design considerations for
EFM32 and EFR32 Wireless Gecko Series 2 devices. For hardware design considerations for EFM32 and EZR32 Wireless
MCU Series 0 and EFM32 and EFR32 Wireless Gecko Series 1
devices, refer to AN0002.0: EFM32 and EZR32 Wireless MCU
Series 0 Hardware Design Considerations and AN0002.1:
EFM32 and EFR32 Wireless MCU Series 1 Hardware Design
Considerations, respectively.
Topics specifically covered are supported power supply configurations, supply filtering
considerations, debug interface connections, and external clock sources.
For more information on hardware design considerations for the radio portion of EFM32
and EFR32 Wireless Gecko Series 2 devices, see AN930.2: EFR32 Series 2 2.4 GHz
Matching Guide, AN933.2: EFR32 Series 2 2.4 GHz Minimal BOM and AN928.2:
EFR32 Series 2 Layout Design Guide.
KEY POINTS
• Decoupling capacitors are crucial to
ensuring the integrity of the device's power
supplies.
• The debug interface consists of two
communication pins (SWCLK and
SWDIO).
• External clock sources must be connected
to the device correctly for proper
operation.
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AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
1. Device Compatibility
This application note supports multiple device families, and some functionality is different depending on the device.
EFR32 Wireless Gecko Series 2 consists of:
• EFR32BG21
• EFR32MG21
• EFR32BG22
• EFR32FG22
• EFR32MG22
EFM32 Series 2 consists of:
• EFM32PG22
Device Compatibility
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AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
Power Supply Overview
2. Power Supply Overview
2.1 Introduction
Although the EFM32 and EFR32 Wireless Gecko Series 2 devices have very low average current consumption, proper decoupling is
crucial. As for all digital circuits, current is drawn in short pulses corresponding to the clock edges. Particularly when several I/O lines
are switching simultaneously, transient current pulses on the power supply can be in the order of several hundred mA for a few nanoseconds, even though the average current consumption is quite small.
These kinds of transient currents cannot be properly delivered over high impedance power supply lines without introducing considerable noise in the supply voltage. To reduce this noise, decoupling capacitors are employed to supplement the current during these short
transients.
2.2 Decoupling Capacitors
Decoupling capacitors make the current loop between supply, MCU, and ground as short as possible for high frequency transients.
Therefore, all decoupling capacitors should be placed as close as possible to each of their respective power supply pins, ground pins,
and PCB (Printed Circuit Board) ground planes.
All external decoupling capacitors should have a temperature range reflecting the environment in which the application will be used. For
example, a suitable choice might be X5R ceramic capacitors with a change in capacitance of ±15% over the temperature range -55 to
+85 °C (standard temperature range devices) or -55 to +125 °C (extended temperature range devices).
For regulator output capacitors (DECOUPLE, VREGSW, and VREGO, if available), the system designer should pay particular attention
to the characteristics of the capacitor over temperature and bias voltage. Some capacitors (particularly those in smaller packages or
using cheaper dielectrics) can experience a dramatic reduction in capacitance value across temperature or as the DC bias voltage increases. Any change pushing the regulator output capacitance outside the data sheet specified limits may result in output instability on
that supply.
2.3 Power Supply Requirements
An important consideration for all devices is the voltage requirements and dependencies between the power supply pins. The system
designer needs to ensure that these power supply requirements are met, regardless of power configuration or topology. These internal
relationships between the external voltages applied to the various EFM32 and EFR32 supply pins are defined below. Failure to observe
the below constraints can result in damage to the device and/or increased current draw. Refer to the device data sheet for absolute
maximum ratings and additional details regarding relative system voltage constraints.
EFM32 Series 2 Power Supply Requirements
• AVDD and IOVDD — No dependency on each other or any other supply pin
• VREGVDD ≥ DVDD
• DVDD ≥ DECOUPLE
EFR32 Wireless Gecko Series 2 Power Supply Requirements
• AVDD and IOVDD — No dependency on each other or any other supply pin
• VREGVDD ≥ DVDD
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD
Note: To use EFR32 Wireless Gecko Series 2 for MCU only application, connect the radio related pins as follows:
• PAVDD = RFVDD = DVDD
• RF2G4_IO P/N = NC
Note:
• VREGVDD Power Supply Pin is not available on EFR32xG21 devices.
• On the devices having VREGVDD Power Supply Pin, VREGVDD connections are depend on whether or not the DCDC is used. See
the 2.7 DC-DC section for more information on VREGVDD connections.
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AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
Power Supply Overview
Power Supply Pin Overview
Note that not all supply pins exist on all devices. The table below provides an overview of the available power supply pins.
Table 2.1. Power Supply Pin Overview
Pin Name Product Family Description
AVDD All devices Supply to analog peripherals
DECOUPLE All devices Output of the internal digital LDO and digital logic supply input
IOVDD All devices GPIO supply voltage
VREGVDD All DC-DC-enabled devices Input to the DC-DC converter
VREGSW All DC-DC-enabled devices DC-DC powertrain switching node
VREGVSS All DC-DC-enabled devices DC-DC ground
DVDD All devices Input to the internal digital LDO
RFVDD EFR32 Wireless Gecko Series 2 only Supply to radio analog and HFXO
PAVDD EFR32 Wireless Gecko Series 2 only Supply to radio power amplifier
2.4 DVDD and DECOUPLE
All EFM32 and EFR32 Wireless Gecko Series 2 devices include an internal linear regulator that powers the core and digital logic. The
DECOUPLE pin is the output of the digital LDO, and requires a 1 µF capacitor. For better high frequency noise suppression a 0.1 µF
capacitor can be placed in parallel with the 1 µF capacitor on the DECOUPLE pin.
As mentioned in section 2.2 Decoupling Capacitors, care should be taken in the selection of decoupling capacitors for regulator output,
such as DECOUPLE, to ensure that changes in system temperature and bias voltage do not cause capacitance changes that fall outside of the data sheet specified limits, which could destabilize the regulator output.
EFM32 and EFR32 Wireless Gecko Series 2 DVDD Pin
On EFM32 and EFR32 Wireless Gecko Series 2 devices, the input supply to the digital LDO is the DVDD pin and the DECOUPLE pin
is the output of the LDO. Decoupling of DVDD should include a bulk capacitor of C
and this bulk capacitor should be at least
DVDD
2.2 µF for EFR32xG21 and 2.7 µF for EFM32PG22 and EFR32xG22. For better high frequency noise suppression a 0.1 µF capacitor
(C
with C
) can be placed in parallel with the C
DVDD1
DECOUPLE
to further improve high frequency noise suppression.
capacitor on the DVDD pin. A similar 0.1 μF capacitor may also be added in parallel
DVDD
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AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
Power Supply Overview
V
Main
Supply
DD
+
–
C
DVDD
C
DVDD1
0.1 µF
DVDD
Digital
LDO
DECOUPLE
C
DEC
1 µF
Digital
Logic
Figure 2.1. DVDD and DECOUPLE on EFM32 and EFR32 Wireless Gecko Series 2 Devices
Note:
• The DECOUPLE pin should not be used to power any external circuitry. Although DECOUPLE is connected to the output of the
internal digital LDO, it is provided solely for the purposes of decoupling this supply and is not intended to power anything other than
the internal digital logic of the device.
• On EFR32xG22 and EFM32PG22, if DVDD is directly connected to the DCDC, then proper decoupling of DVDD should include a
bulk capacitor of 4.7 µF as shown in 3.4 EFM32 and EFR32 Wireless Gecko Series 2 — DCDC Example. This capacitor should be
placed closer to the L
inductor and the VREGSW pin.
DCDC
2.5 IOVDD
The IOVDD pin(s) provide decoupling for all of the GPIO pins on the device. For proper decoupling when powering IOVDD from the
main supply, include a 0.1 µF capacitor per IOVDD pin, along with a 1 µF bulk capacitor. Increase the bulk capacitor value in applications using GPIO to drive heavy and dynamic loads.
V
Main
Supply
DD
+
–
C
IOVDD_n
0.1 µF
IOVDD_n
. . .
IOVDD_0
C
IOVDD
1 µF
Figure 2.2. IOVDD Decoupling from Main Supply
IOVDD can optionally be driven by the output of the DC-DC converter when present on a device. This is primarily used when connecting to external devices with different operating voltages than the microcontroller. When powering IOVDD from the output of the DC-DC
converter, the bulk 1 µF capacitor is not required, and the DC-DC output should be decoupled by a bulk 4.7 µF capacitor.
Note: When powering IOVDD from the output of the DC-DC converter, the debug interface must connect the V
not the main supply. See the 4. Debug Interface and External Reset Pin section for information on the V
C
IOVDD_0
0.1 µF
target
pin.
pin to IOVDD, and
target
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AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
Power Supply Overview
2.6 AVDD
The analog peripheral performance of the device is impacted by the quality of the AVDD power supply. For applications with less demanding analog performance, a simpler decoupling scheme for AVDD may be acceptable. For applications requiring the highest quality
analog performance, more robust decoupling and filtering is required.
Note that the number of AVDD analog power pins may vary by device and package.
2.6.1 AVDD Standard Decoupling
The figure below illustrates a standard approach for decoupling the AVDD pin(s). In general, one 1 µF bulk capacitor (C
as one 10 nF capacitor for each AVDD pin (C
Main
Supply
AVDD_0
through C
V
DD
+
–
), must be provided.
AVDD_n
C
10 nF
AVDD_n
AVDD_n
. . .
AVDD
), as well
AVDD_0
C
AVDD
1 µF
Figure 2.3. AVDD Standard Decoupling
2.6.2 AVDD Improved Decoupling
The figure below illustrates an improved approach for decoupling and filtering the AVDD pin(s). In general, one 1 µF bulk capacitor
(C
), as well as one 10 nF capacitor for each AVDD pin (C
AVDD
and series 1 Ω resistor provide additional power supply filtering and isolation and is preferred when higher ADC accuracy is required.
AVDD_0
C
AVDD_0
10 nF
through C
), must be provided. In addition, a ferrite bead
AVDD_n
Main
Supply
V
DD
+
–
FB
VDD
R
AVDD
1 Ω
C
AVDD_n
10 nF
AVDD_n
. . .
AVDD_0
C
AVDD
1 µF
Figure 2.4. AVDD Improved Decoupling
Note: AVDD can be driven by the output of the DC-DC converter when present on a device, so long as analog peripheral inputs are
limited to the lower of AVDD and IOVDD. For example, in a system with 3.3 V digital I/O, the current draw of analog peripherals, such
as the IADC, can be reduced by allowing the DC-DC converter to supply AVDD with and limiting the analog inputs to 1.8 V.
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C
AVDD_0
10 nF
AN0002.2: EFM32 and EFR32 Wireless Gecko Series 2 Hardware Design Considerations
The table below lists some recommended ferrite bead part numbers suitable for AVDD filtering.
Table 2.2. Recommended Ferrite Beads
Power Supply Overview
Manufacturer Part Number Impedance I
(mA) DCR (Ω) Operating Tempera-
MAX
Package
ture (°C)
Würth Elec-
74279266 1 kΩ @ 100 MHz 200 0.600 -55 to +125 0603/1608
tronics
Würth Elec-
742692004 240 Ω@ 100 MHz 200 0.750 -55 to +125 0201/0603
tronics
Murata BLM21BD102SN1D 1 kΩ @ 100 MHz 200 0.400 -55 to +125 0805/2012
2.7 DC-DC
Some EFM32 and EFR32 Wireless Gecko Series 2 devices provide an on-chip DC-DC converter that can be used for improved power
efficiency. However, the additional switching noise present on the DC-DC converter output (V
), necessitates the use of specific
DCDC
filtering components.
2.7.1 DC-DC — Unused
When the DC-DC converter is not used, the DVDD pin should be shorted to the VREGVDD pin. VREGSW must be left floating, and
VREGVSS should be grounded.
Bypass
Switch
Main
Supply
V
DD
+
–
C
VDD
10 µF
C
VDD1
0.1 µF
VREGVDD
VREGSW
DC-DC
Driver
VREGVSS
DC-DC
DVDD
C
DVDD
C
DVDD1
0.1 µF
Figure 2.5. Configuration when the DC-DC converter is unused
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