Silicon Laboratories WGM160P Hardware Design User Manual
UG384: WGM160P Hardware Design
User’s Guide
The purpose of this guide is to help users design WiFi applications using the WGM160P.
This guide includes information for schematics and layout. Some options available with
WGM160P hardware are not available with all software architectures, so the pin features
versus software are detailed.
KEY FEATURES
• Schematic guidelines
•
Package information
• Layout guidelines
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Table of Contents
WGM160P Pinout ..............................3
1.
2. WGM160P Pin Description ..........................4
2.1 Pin Table ................................4
2.2 Power Pin ...............................5
2.3 RESETn Pin ...............................5
2.4 RF Pins ................................5
2.5 Clocks .................................6
2.6 PTA Pins ................................7
2.7 Multifunction Pins .............................7
2.7.1 Software Architecture Considerations .....................7
3. Application Schematic Recommendations ...................10
3.1 Power Supply ..............................10
3.2 RF Part ................................10
4. Typical Application Schematics .......................11
5. Layout Recommendations .........................12
5.1 Generic RF Layout Considerations .......................12
5.2 RF-Pads Including the Diversity Port and External Antennas ..............13
5.3 Module Chip Antenna............................14
6. Recommendations for Certification ......................20
7. Package Outline .............................21
8. Recommended PCB Land Pattern ......................22
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1. WGM160P Pinout
WGM160P is a 23.8 mm x 14.2 mm x 2.3 mm PCB module.
The diagram below describes pinout (top view)
UG384: WGM160P Hardware Design User’s Guide
WGM160P Pinout
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Figure 1.1. WGM160P Device Pinout
UG384: WGM160P Hardware Design User’s Guide
2. WGM160P Pin Description
2.1 Pin Table
Table 2.1. WGM160P Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
WGM160P Pin Description
1
ANT_GND
GND
PTA_TX_CO
NF
PTA_FREQ 12
PE14 14 GPIO
PA0 16 GPIO PA1 17 GPIO
2
Antenna ground.
54
55
4
8
9
10
11
Ground. Connect all ground pins to
23
ground plane.
27
30
33
43
52
PTA TX_CONF pin. These pins can be
6
used to manage co-existence with another 2.4 GHz radio.
PTA FREQ pin. These pins can be
used to manage co-existence with another 2.4 GHz radio.
RF2 3
VBAT 5 Module power supply
PTA_RF_AC
T
PTA_STA-
TUS
PE15 15 GPIO
7
13
External antenna connection for diversity antenna. Terminate to ground with
47-51 Ohms if not connected to an antenna.
PTA RF_ACT pin. These pins can be
used to manage co-existence with another 2.4 GHz radio.
PTA STATUS pin. These pins can be
used to manage co-existence with another 2.4 GHz radio.
PA2 18 GPIO PA3 19 GPIO
PA4 20 GPIO
PB3 22 GPIO PB4 24 GPIO
PB5 25 GPIO PB6 26 GPIO
PB13 28 GPIO PB14 29 GPIO
PB11 31 GPIO
Reset input, active low. This pin is internally pulled up to VBAT. To apply an
RESETn 34
PD8 36 GPIO PF2 37 GPIO
PF5 38 GPIO
VBUS 40
PF11 42 GPIO (5V) PF0 44 GPIO (5V)
PF1 45 GPIO (5V) PE7 46 GPIO
external reset source to this pin, it is required to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
USB VBUS signal and auxiliary input to
5 V regulator. May be left disconnected
if USB is unused.
PA5 21 GPIO
PB12 32 GPIO
PD6 35 GPIO
PC5 39 GPIO
PF10 41 GPIO (5V)
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UG384: WGM160P Hardware Design User’s Guide
Pin Name Pin(s) Description Pin Name Pin(s) Description
WGM160P Pin Description
PE6 47 GPIO
PE5 48 GPIO
PC4 49 GPIO PA6 50 GPIO
External antenna connection on
PA15 51 GPIO RF1 53
WGM160P22N. Not connected on
WGM160P22A.
Note:
1.
GPIO with 5V tolerance are indicated by (5V).
2.2 Power Pin
The
WGM160P module is supplied through the VBAT pin. There is no need for external bypass capacitors as the ICs decoupling is
performed within the module. Note that, although the VBAT supply is variable, the maximum TX output power can be achieved only
when the supply is set to 3.3 V or higher.
Note that pin VBUS cannot be used to supply the module.
2.3 RESETn Pin
The WGM160P module is reset by driving the RESETn pin low. A weak internal pull-up resistor holds the RESETn pin high allowing it
to be left unconnected if no external reset source is required.
Note that when WGM160P is not powered, RESETn must not be connected to an active supply through an external pull-up resistor as
this could damage the device.
Note also that the WGM160P features Power On Reset to keep WGM160P in reset mode until VBAT is high enough. For more details,
refer to the MCU EFM32GG11 reference manual.
2.4 RF Pins
The WGM160P module is available with two RF configurations.
Table 2.2. WGM160P RF Configuration
Part Numbers RF1 RF2
WGM160PX22KGA2
Internal antenna.
RF port
WGM160P022KGA2
Pin RF1 is not connected.
WGM160PX22KGN2
RF port RF port
WGM160P022KGN2
RF ports are internally matched to 50 Ω.
It is recommended to connect any unused RF port to ground through a 50 Ω resistor. Any of
the RF ports can be used in a similar way. However, performance obtained on RF1 is slightly better, so it is preferable to use this one.
Only one RF port is active at a given time, but the module can also achieve antenna diversity if the application requires it. Port selection
and antenna diversity enablement are achieved through software configuration.
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2.5 Clocks
The WGM160P module is available with two clock configurations.
Table 2.3. WGM160P Low Power Clock Configuration
Part Numbers Low Frequency Crystal
UG384: WGM160P Hardware Design User’s Guide
WGM160P Pin Description
WGM160PX22KGA2
Internal 32.768 kHz crystal
WGM160PX22KGN2
WGM160P022KGA2
No crystal
WGM160P022KGN2
A 32.768 kHz clock source is required to enable the lowest power operation in WiFi power save modes. 32.768 kHz can be generated
either an internal Low Frequency RC oscillator or an internal crystal. As the frequency tolerance of this clock affects wake-up
using
scheduling, power consumption in DTIM modes is optimized when using the WGM160P with an integrated 32.768 kHz crystal.
For WGM160P applications requiring Ethernet, a 50 MHz reference clock is required. This can be achieved either by connecting a 50
MHz external clock to module pin PB14 or by connecting a 50 MHz crystal oscillator between pins PB13 (HFXTAL_P) and PB14
(HFXTAL_N). For more details, refer to the MCU EFM32GG11 reference manual.
Table 2.4. WGM160P 50 MHz High-Frequency Crystal Oscillator
Parameter Symbol Test Condition Min Typ Max Unit
No clock doubling 4 — 50 MHz
Crystal frequency
f
HFXO
Clock doubler enabled 4 — 25 MHz
50 MHz crystal — — 50 Ω
Supported crystal equivalent ser-
ies resistance (ESR)
ESR
HFXO
24 MHz crystal — — 150 Ω
4 MHz crystal — — 180 Ω
Nominal on-chip tuning cap
1
range
On-chip tuning capacitance step
Startup time
Current consumption after startup
C
HFXO_T
SS
HFXO
t
HFXO
I
HFXO
Note:
1.
The effective load capacitance seen by the crystal will be C
two caps will be seen in series by the crystal.
On each of HFXTAL_N and
HFXTAL_P pins
50 MHz crystal, ESR = 50 Ω,
CL = 8 pF
24 MHz crystal, ESR = 150 Ω,
CL = 6 pF
4 MHz crystal, ESR = 180 Ω,
CL = 18 pF
50 MHz crystal — 880 — µA
24 MHz crystal — 420 — µA
4 MHz crystal — 80 — µA
/2. This is because each XTAL pin has a tuning cap and the
HFXO_T
8.7 — 51.7 pF
— 0.084 — pF
— 350 — µs
— 700 — µs
— 3 — ms
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UG384: WGM160P Hardware Design User’s Guide
WGM160P Pin Description
2.6 PTA Pins
an RF transceiver using the same 2.4 GHz band (e.g. Bluetooth) is located next to WGM160P, a Packet Transfer Arbitration (PTA)
If
interface can be used to avoid mutual interference. In this case, the PTA pins are connected to the other transceiver. The PTA interface
is highly programmable and can use 1, 2, 3, or 4 pins upon configuration. PTA signal names can vary by manufacturer, so the table
below shows their alternative names.
Table 2.5. WGM160P PTA Configuration
WGM160P Pin # WGM160P Pin Name Alternative Name
6 PTA_TX_CONF GRANT
7 PTA_RF_ACT REQUEST
13 PTA_STATUS PRIORITY
12 PTA_FREQ RHO
PTA interface configuration is achieved through software configuration. PTA operation will be detailed in an upcoming application note.
2.7 Multifunction Pins
The multifunction pins refer to the WGM160P pins directly connected to the embedded MCU, EFM32GG11.
2.7.1 Software Architecture Considerations
As
described in the data sheet, the WGM160P module has considerable flexibility regarding the configuration of MCU pins, but not all
software architectures support all functions.
2.7.1.1 Bootloader
All devices come preprogrammed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More
information about the bootloader protocol and usage can be found in AN0003: UART Bootloader. Application notes can be found on the
Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.
WGM160P pin 44 (GG11 PF0) and pin 45 (GG11 PF1) provide the bootloader with TX and RX access, respectively.
2.7.1.2 Implementation with GG11 Open Software
Full flexibility can be achieved when using the source software based on the Full MAC driver provided by Silicon Labs. The configuration of multifunction pins is accomplished within Simplicity Studio similar to the software development for the EFM32GG11. For more
details regarding these pins, refer to tables 6.2 and 6.3 of the WGM160P data sheet.
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UG384: WGM160P Hardware Design User’s Guide
WGM160P Pin Description
2.7.1.3 Implementation with Gecko OS
following table provides details on the various multifunction pin features supported through Gecko OS 4.0. Features such as SPI
The
slave and USB will be supported in future releases of the Gecko OS.
Table 2.6. WGM160P Multifunction Pin Configuration With GeckoOS
WGM160P
Pin
GG11
Port
Default
Function
1
GPIO
(GOS_
GPIO_x)
2
UART
(GOS_
UART_x)
3
SPI
(GOS_
SPI_x)
I2C
(GOS_
I2C_x)
ADC
(GOS_
ADC_x)
PWM
(GOS_
PWM_x)
14 PE14 GPIO 0 0 0 TXD1
15 PE15 GPIO 1 - 1 TXD0
16 PA0
17 PA1
18 PA2
SPI Master
MOSI
SPI Master
MISO
SPI Master
CLK
2 SPI0 MOSI 6 2 TXEN
3 SPI0 MISO - 3 RXD1
4 SPI0 CLK 10 4 RXD0
19 PA3 GPIO 5 - 5 REFCLK
20 PA4 GPIO 6 11 6 CRSDV
21 PA5 GPIO 7 - 7 RXER
Bulk sflash
22 PB3
MOSI or
4
8 UART1 TX SPI1 MOSI - 8
UART TX
(logging)
Ethernet
(RMII)
Bulk sflash
MISO or 4
24 PB4
9 UART1 RX SPI1 MISO 12 9
UART RX
(logging)
25 PB5
26 PB6
UART RTS
(Com-
mands)
UART CTS
(Com-
mands)
10
11
UART0
RTS
UART0
CTS
- 10
1 11
28 PB13 GPIO 12 - -
29 PB14 GPIO 13 2 -
31 PB11
32 PB12
I2C Master
SDA
I2C Master
SCL
14 I2C0 SDA - 12
15 I2C0 SCL 3 13
Factory Re-
35 PD6
set
5
16
UART1
CTS
4 14
GPIO
36 PD8 GPIO 17
UART1
RTS
- 15
37 PF2 GPIO 18 5 16
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