Silicon Laboratories SiM3L1xx User Manual

SiM3L1xx

High-Performance, Low-Power, 32-Bit Precision32™

MCU Family with up to 256 kB of Flash

32-bit ARM Cortex-M3 CPU

- 50 MHz maximum frequency

- Single-cycle multiplication, hardware division support

- Nested vectored interrupt control (NVIC) with 8 priority levels

Memory

- 32–256 kB flash, in-system programmable

- 8–32 kB SRAM with configurable low power retention

Clock Sources

- Internal oscillator with PLL: 23–50 MHz

- Low power internal oscillator: 20 MHz

- Low frequency internal oscillator (LFO): 16.4 kHz

- External real-time clock (RTC) crystal oscillator

- External oscillator: Crystal, RC, C, CMOS clock

Power Management

- Three adjustable low drop-out (LDO) regulators

- Power-on reset circuit and brownout detectors

- DC-DC buck converter allows dynamic voltage scaling for

maximum efficiency (250 mW output)

- Multiple power modes supported for low power optimization

Low Power Features

- 75 nA typical current in Power Mode 8

- Low-current RTC (180 nA from LFO, 300 nA from crystal)

- 4 μs wakeup, register state retention and no reset required from

lowest power mode

- 175 μA/MHz at 3.6 V executing from flash

- 140 μA/MHz at 3.6 V executing from SRAM

- Specialized on-chip charge pump reduces power consumption

- Process/Voltage/Temperature (PVT) Monitor

5 V Tolerant Flexible I/O

- Up to 62 contiguous 5 V tolerant GPIO with one priority cross-

bar providing flexibility in pin assignments

Temperature Range: –40 to +85 °C
Supply Voltage: 1.8 to 3.8 V

Analog Peripherals

- 12-Bit Analog-to-Digital Converter: Up to 250 ksps 12-bit mode

or 1

Msps 10-bit mode

- 10-Bit Current-mode Digital-to-Analog Converter

- 2 x Low-current comparators

Digital and Communication Peripherals

- 1 x USART with IrDA and ISO7816 Smartcard support

- 1 x UART that operates in low power mode

- 2 x SPIs, 1 x I2C, 16/32-bit CRC

- 128/192/256-bit Hardware AES Encryption

- Encoder/Decoder: Manchester and Three-out-of-Six

- Integrated LCD Controller: up to 160 segments (40x4), auto-

contrast and low power operation

Timers/Counters

- 3 x 32-bit or 6 x 16-bit timers with capture/compare

- 16-bit, 6-channel counter with capture/compare/PWM and

dead-time controller with differential outputs

- 16-bit low power timer/advanced capture counter operational in

the lowest power mode

- 32-bit real time clock (RTC) with multiple alarms

- Watchdog timer

- Low power mode advanced capture counter (ACCTR)

Data Transfer Peripherals

- 10-Channel DMA Controller

- 3 Channel Data Transfer Manager manages complex DMA

transfers without core intervention

On-Chip Debugging

- Serial wire debug (SWD) with serial wire viewer (SWV) or JTAG

(no boundary scan) allow debug and programming

- Cortex-M3 embedded trace macrocell (ETM)

Package Options

- QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)

- TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)

Rev 1.1 11/14 Copyright © 2013 by Silicon Laboratories SiM3L1xx

2 Rev 1.1

SiM3L1xx

Table of Contents

1. Related Documents and Conventions...............................................................................5

1.1. Related Documents........................................................................................................5

1.1.1. SiM3L1xx Reference Manual.................................................................................5

1.1.2. Hardware Access Layer (HAL) API Description ....................................................5

1.1.3. ARM Cortex-M3 Reference Manual.......................................................................5

1.2. Conventions ...................................................................................................................5

2. Typical Connection Diagrams ............................................................................................6

2.1. Power .............................................................................................................................6

3. Electrical Specifications......................................................................................................8

3.1. Electrical Characteristics ................................................................................................8

3.2. Thermal Conditions ......................................................................................................30

3.3. Absolute Maximum Ratings..........................................................................................31

4. Precision32™ SiM3L1xx System Overview.....................................................................32

4.1. Power ...........................................................................................................................34

4.1.1. DC-DC Buck Converter (DCDC0)........................................................................34

4.1.2. Three Low Dropout LDO Regulators (LDO0) ......................................................35

4.1.3. Voltage Supply Monitor (VMON0) .......................................................................35

4.1.4. Power Management Unit (PMU)..........................................................................35

4.1.5. Device Power Modes...........................................................................................35

4.1.6. Process/Voltage/Temperature Monitor (TIMER2 and PVTOSC0).......................38

4.2. I/O.................................................................................................................................39

4.2.1. General Features.................................................................................................39

4.2.2. Crossbar ..............................................................................................................39

4.3. Clocking........................................................................................................................40

4.3.1. PLL (PLL0)...........................................................................................................41

4.3.2. Low Power Oscillator (LPOSC0) .........................................................................41

4.3.3. Low Frequency Oscillator (LFOSC0)...................................................................41

4.3.4. External Oscillators (EXTOSC0)..........................................................................41

4.4. Integrated LCD Controller (LCD0)................................................................................42

4.5. Data Peripherals...........................................................................................................43

4.5.1. 10-Channel DMA Controller.................................................................................43

4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2) .................................................43

4.5.3. 128/192/256-bit Hardware AES Encryption (AES0) ............................................43

4.5.4. 16/32-bit Enhanced CRC (ECRC0) .....................................................................44

4.5.5. Encoder / Decoder (ENCDEC0) ..........................................................................44

4.6. Counters/Timers...........................................................................................................45

4.6.1. 32-bit Timer (TIMER0, TIMER1, TIMER2)...........................................................45

4.6.2. Enhanced Programmable Counter Array (EPCA0) .............................................45

4.6.3. Real-Time Clock (RTC0) .....................................................................................46

4.6.4. Low Power Timer (LPTIMER0)............................................................................46

4.6.5. Watchdog Timer (WDTIMER0)............................................................................46

4.6.6. Low Power Mode Advanced Capture Counter (ACCTR0)...................................47

4.7. Communications Peripherals .......................................................................................48

4.7.1. USART (USART0) ............................................................................................... 48

Rev 1.1 3

SiM3L1xx

4.7.2. UART (UART0)....................................................................................................48

4.7.3. SPI (SPI0, SPI1) .................................................................................................. 49

4.7.4. I2C (I2C0) ............................................................................................................49

4.8. Analog ..........................................................................................................................50

4.8.1. 12-Bit Analog-to-Digital Converter (SARADC0)...................................................50

4.8.2. 10-Bit Digital-to-Analog Converter (IDAC0) ......................................................... 50

4.8.3. Low Current Comparators (CMP0, CMP1) .......................................................... 50

4.9. Reset Sources..............................................................................................................51

4.10.Security ........................................................................................................................ 52

4.11.On-Chip Debugging .....................................................................................................52

5. Ordering Information.........................................................................................................53

6. Pin Definitions....................................................................................................................55

6.1. SiM3L1x7 Pin Definitions .............................................................................................55

6.2. SiM3L1x6 Pin Definitions .............................................................................................62

6.3. SiM3L1x4 Pin Definitions .............................................................................................69

6.4. TQFP-80 Package Specifications ................................................................................74

6.4.1. TQFP-80 Solder Mask Design.............................................................................77

6.4.2. TQFP-80 Stencil Design ...................................................................................... 77

6.4.3. TQFP-80 Card Assembly.....................................................................................77

6.5. QFN-64 Package Specifications ..................................................................................78

6.5.1. QFN-64 Solder Mask Design...............................................................................80

6.5.2. QFN-64 Stencil Design ........................................................................................ 80

6.5.3. QFN-64 Card Assembly.......................................................................................80

6.6. TQFP-64 Package Specifications ................................................................................81

6.6.1. TQFP-64 Solder Mask Design.............................................................................84

6.6.2. TQFP-64 Stencil Design ...................................................................................... 84

6.6.3. TQFP-64 Card Assembly.....................................................................................84

6.7. QFN-40 Package Specifications ..................................................................................85

6.7.1. QFN-40 Solder Mask Design...............................................................................87

6.7.2. QFN-40 Stencil Design ........................................................................................ 87

6.7.3. QFN-40 Card Assembly.......................................................................................87

7. Revision Specific Behavior...............................................................................................88

7.1. Revision Identification ..................................................................................................88

Document Change List...........................................................................................................90

Contact Information................................................................................................................91

4 Rev 1.1

SiM3L1xx

1. Related Documents and Conventions

1.1. Related Documents

This data sheet accompanies several documents to provide the complete description of the SiM3L1xx devices.

1.1.1. SiM3L1xx Reference Manual

The Silicon Laboratories SiM3L1xx Reference Manual provides the detailed description for each peripheral on the
SiM3L1xx devices.

1.1.2. Hardware Access Layer (HAL) API Description

The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3L1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.

1.1.3. ARM Cortex-M3 Reference Manual

The ARM-specific features like the Nested Vectored Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:

http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.

1.2. Conventions

The block diagrams in this document use the following formatting conventions:

Figure 1.1. Block Diagram Conventions

Rev 1.1 5

SiM3L1xx

2. Typical Connection Diagrams

This section provides typical connection diagrams for SiM3L1xx devices.

2.1. Power

Figure 2.1 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck
converter is not used.

Figure 2.1. Connection Diagram with DC-DC Converter Unused

Figure 2.2 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the internal dc-dc
buck converter is in use and I/O are powered directly from the battery.

Figure 2.2. Connection Diagram with DC-DC Converter Used and I/O Powered from Battery

Figure 2.3 shows a typical connection diagram for the power pins of the SiM3L1xx devices when used with an
external radio device like the Silicon Labs EZRadio® or EZRadioPRO® devices.

6 Rev 1.1

SiM3L1xx

Figure 2.3. Connection Diagram with External Radio Device

Figure 2.4 shows a typical connection diagram for the power pins of the SiM3L1xx devices when the dc-dc buck
converter is used and the I/O are powered separately.

Figure 2.4. Connection Diagram with DC-DC Converter Used and I/O Powered Separately

Rev 1.1 7

SiM3L1xx

3. Electrical Specifications

3.1. Electrical Characteristics

All electrical parameters in all Tables are specified under the conditions listed in Table 3.1, unless stated otherwise.

Table 3.1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating Supply Voltage on
VBAT/VBATDC

Operating Supply Voltage on VDC V

Operating Supply Voltage on VDRV V

Operating Supply Voltage on VIO V

Operation Supply Voltage on VIORF V

Operation Supply Voltage on VLCD V

System Clock Frequency (AHB) f

Peripheral Clock Frequency (APB) f

Operating Ambient Temperature T

Operating Junction Temperature T

Note: All voltages with respect to V

SS

.

V

BAT

DC

DRV

IO

IORF

LCD

AHB

APB

A

J

1.8 — 3.8 V

1.25 — 3.8 V

1.25 — 3.8 V

1.8 — V

1.8 — V

1.8 — 3.8 V

0 — 50 MHz

0 — 50 MHz

–40 — +85 °C

–40 — 105 °C

BAT

BAT

V

V

8 Rev 1.1

Table 3.2. Power Consumption

Parameter Symbol Test Condition Min Typ Max Unit

Digital Core Supply Current

Normal Mode
with code executing from flash,
peripheral clocks ON

Normal Mode
with code executing from flash,
peripheral clocks OFF

Normal Mode
with code executing from flash,
LDOs powered by dc-dc at 1.9 V,
peripheral clocks OFF

Notes:

1. Currents are additive. For example, where I

functions increases supply current by the specified amount.

2. Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

1,2,3,4

—Full speed

1,2,3,4

—Full speed

1,2,3,4

—Full speed

I

BAT

I

BAT

I

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

V

= 3.3 V

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

V

= 3.8 V

BAT

F

= 20 MHz,

AHB

F

= 10 MHz

APB

V

= 3.3 V

BAT

F

= 20 MHz,

AHB

F

= 10 MHz

APB

V

= 3.8 V

BAT

is specified and the mode is not mutually exclusive, enabling the

BAT

SiM3L1xx

— 17.5 18.9 mA

— 6.7 7.2 mA

— 1.15 1.4 mA

— 13.3 14.5 mA

— 5.4 5.9 mA

— 980 1.2 μA

— 9.7 — mA

— 8.65 — mA

— 4.15 — mA

— 3.9 — mA

is included in all I

VIO

BAT

PM8

Rev 1.1 9

SiM3L1xx

Table 3.2. Power Consumption (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Power Mode 1
with code executing from RAM,
peripheral clocks ON

Power Mode 1
with code executing from RAM,
peripheral clocks OFF

Power Mode 1
with code executing from RAM,
LDOs powered by dc-dc at 1.9 V,
peripheral clocks OFF

Power Mode 2
with peripheral clocks ON

Notes:

1. Currents are additive. For example, where

functions increases supply current by the specified amount.

2.

Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4,5

—Full speed

—Full speed

—Full speed

—Core halted

I

BAT

I

BAT

I

BAT

I

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

V

= 3.3 V

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

V

= 3.8 V

BAT

F

= 20 MHz,

AHB

F

= 10 MHz

APB

V

= 3.3 V

BAT

F

= 20 MHz,

AHB

F

= 10 MHz

APB

V

= 3.8 V

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

I

is specified and the mode is not mutually exclusive, enabling the

BAT

<20 MHz) supply current.

— 13.4 16.6 mA

— 4.7 — mA

— 810 — μA

— 9.4 12.5 mA

— 3.3 — mA

— 630 — μA

— 7.05 — mA

— 6.3 — mA

— 2.75 — mA

— 2.6 — mA

— 7.6 11.3 mA

— 2.75 — mA

— 575 — μA

is included in all I

VIO

BAT

PM8

10 Rev 1.1

Table 3.2. Power Consumption (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Power Mode 2
with only Port I/O clocks on (wake
from pin).

Power Mode 3
Mode (PM3CLKEN = 1)

Power Mode 4
speed with code executing from
flash, peripheral clocks ON

Power Mode 5
speed with code executing from
RAM, peripheral clocks ON

Power Mode 6
with peripheral clocks ON

Power Mode 8
Sleep, powered through VBAT,
VIO, and VIORF at 2.4 V, 32kB of
retention RAM

1,2,3,4,5

—Core halted

1,2,6

—Fast-Wake

1,2,4,6

—Slower clock

1,2,4,6

—Slower clock

1,2,4,6

—Core halted

1,2

—Low Power

I

BAT

I

BAT

I

BAT

I

BAT

I

BAT

I

BAT

F

= 49 MHz,

AHB

F

= 24.5 MHz

APB

F

= 20 MHz,

AHB

F

= 10 MHz

APB

F

= 2.5 MHz,

AHB

F

= 1.25 MHz

APB

V

= 3.8 V — 320 530 μA

BAT

V

= 1.8 V — 225 — μA

BAT

F

= F

AHB

V

F

= F

AHB

V

F

= F

AHB

V

F

= F

AHB

V

F

= F

AHB

V

F

= F

AHB

V

RTC Disabled,

APB

BAT

APB

BAT

APB

BAT

APB

BAT

APB

BAT

APB

BAT

= 16 kHz,

= 3.8 V

= 16 kHz,

= 1.8 V

= 16 kHz,

= 3.8 V

= 16 kHz,

= 1.8 V

= 16 kHz,

= 3.8 V

= 16 kHz,

= 1.8 V

TA = 25 °C

RTC w/ 16.4 kHz LFO,

TA = 25 °C

SiM3L1xx

— 4 7.2 mA

— 1.47 — mA

— 430 — μA

— 385 640 μA

— 330 — μA

— 320 490 μA

— 275 — μA

— 315 490 μA

— 270 — μA

— 75 400 nA

— 360 — nA

RTC w/ 32.768 kHz Crystal,

TA = 25 °C

Notes:

1. Currents are additive. For example, where

functions increases supply current by the specified amount.

2.

Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

I

is specified and the mode is not mutually exclusive, enabling the

BAT

<20 MHz) supply current.

Rev 1.1 11

— 670 — nA

is included in all I

VIO

BAT

PM8

SiM3L1xx

Table 3.2. Power Consumption (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Power Mode 8
Sleep, powered by the low power
mode charge pump, 32kB of reten­tion RAM

Unloaded VIO and V

Power Mode 8 Peripheral Currents

1,2

—Low Power

IORF

Current

10

I

BAT

I

VIO

RTC w/ 16.4 kHz LFO,

V

= 2.4 V, TA = 25 °C

BAT

RTC w/ 32.768 kHz Crystal,

V

= 2.4 V, TA = 25 °C

BAT

RTC w/ 16.4 kHz LFO,

V

= 3.8 V, TA = 25 °C

BAT

RTC w/ 32.768 kHz Crystal,

V

= 3.8 V, TA = 25 °C

BAT

— 180 — nA

— 300 — nA

— 245 — nA

— 390 — nA

— 2 — nA

UART0 I

LCD07, No segments active I

LCD07, All (4 x 40) segments active I

Advanced Capture Counter
(ACCTR0), LC Single-Ended
Mode, Relative to Sampling Fre­quency

Notes:

9

1. Currents are additive. For example, where

functions increases supply current by the specified amount.

2.

Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

UART0

LCD0

LCD0

I

ACCTR

V

= 3.8 V, TA = 25 °C — 195 600 nA

BAT

V

= 2.4 V, TA = 25 °C — 120 — nA

BAT

V

= 3.8 V, TA = 25 °C — 495 660 nA

BAT

V

= 2.4 V, TA = 25 °C — 395 — nA

BAT

V

= 3.8 V, TA = 25 °C — 800 — nA

BAT

V

= 2.4 V, TA = 25 °C — 580 — nA

BAT

V

= 2.4 V, TA = 25 °C,

BAT

CPMD = 01

V

= 3.8 V, TA = 25 °C,

BAT

V

BAT

V

BAT

V

BAT

V

BAT

I

is specified and the mode is not mutually exclusive, enabling the

BAT

CPMD = 01

= 2.4 V, TA = 25 °C,

CPMD = 10

= 3.8 V, TA = 25 °C,

CPMD = 10

= 2.4 V, TA = 25 °C,

CPMD = 11

= 3.8 V, TA = 25 °C,

CPMD = 11

<20 MHz) supply current.

— 1.11 — nA/Hz

— 1.44 — nA/Hz

— 1.45 — nA/Hz

— 1.82 — nA/Hz

— 2.15 — nA/Hz

— 2.54 — nA/Hz

is included in all I

VIO

BAT

PM8

12 Rev 1.1

Table 3.2. Power Consumption (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

SiM3L1xx

Advanced Capture Counter
(ACCTR0), LC Dual or Quadrature
Mode, Relative to Sampling Fre­quency

Analog Peripheral Supply Currents

PLL0 Oscillator (PLL0OSC) I

Low-Power Oscillator (LPOSC0) I

Low-Frequency Oscillator
(LFOSC0)

External Oscillator (EXTOSC0) I

9

I

ACCTR

PLLOSC

LPOSC

I

LFOSC

EXTOSC

V

= 2.4 V, TA = 25 °C,

BAT

CPMD = 01

V

= 3.8 V, TA = 25 °C,

BAT

CPMD = 01

V

= 2.4 V, TA = 25 °C,

BAT

CPMD = 10

V

= 3.8 V, TA = 25 °C,

BAT

CPMD = 10

V

= 2.4 V, TA = 25 °C,

BAT

CPMD = 11

V

= 3.8 V, TA = 25 °C,

BAT

CPMD = 11

Operating at 49 MHz — 1.4 1.6 mA

Operating at 20 MHz — 25 — μA

Operating at 2.5 MHz — 25 — μA

Operating at 16.4 kHz — 190 310 nA

FREQCN = 111 — 3.8 4.5 mA

FREQCN = 110 — 840 960 μA

FREQCN = 101 — 185 230 μA

— 1.39 — nA/Hz

— 1.89 — nA/Hz

— 2.08 — nA/Hz

— 2.59 — nA/Hz

— 3.47 — nA/Hz

— 4.03 — nA/Hz

FREQCN = 100 — 65 80 μA

FREQCN = 011 — 25 30 μA

FREQCN = 010 — 10 13 μA

FREQCN = 001 — 5 7 μA

FREQCN = 000 — 3 5 μA

Notes:

1. Currents are additive. For example, where

functions increases supply current by the specified amount.

2.

Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

I

is specified and the mode is not mutually exclusive, enabling the

BAT

<20 MHz) supply current.

is included in all I

VIO

BAT

PM8

Rev 1.1 13

SiM3L1xx

Table 3.2. Power Consumption (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

SARADC0 I

Temperature Sensor I

Internal SAR Reference I

VREF0 I

Comparator 0 (CMP0),
Comparator 1 (CMP1)

8

IDAC0

Voltage Supply Monitor (VMON0) I

Flash Current on VBAT

Write Operation I

Erase Operation I

Notes:

1. Currents are additive. For example, where

functions increases supply current by the specified amount.

2.

Includes all peripherals that cannot have clocks gated in the Clock Control module.

3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (

4. Internal Digital and Memory LDOs scaled to optimal output voltage.

5. Flash AHB clock turned off.

6. Running from internal LFO, Includes LFO supply current.

7. LCD0 current does not include switching currents for external load.

8. IDAC output current not included.

9. Does not include LC tank circuit.

10. Does not include digital drive current or pullup current for active port I/O. Unloaded I

production test measurements.

SARADC

TSENSE

REFFS

REFP

I

CMP

I

IDAC

VMON

FLASH-W

FLASH-E

Sampling at 1 Msps, Internal

VREF used

Sampling at 250 ksps, lowest

power mode settings.

Normal Power Mode — 680 — μA

Normal Power Mode — 160 — μA

CMPMD = 11 — 0.5 2 μA

CMPMD = 10 — 3 8 μA

CMPMD = 01 — 10 16 μA

CMPMD = 00 — 25 42 μA

I

is specified and the mode is not mutually exclusive, enabling the

BAT

<20 MHz) supply current.

— 1.2 1.6 mA

— 390 540 μA

— 75 110 μA

— 80 — μA

— 70 100 μA

— 10 22 μA

— — 8 mA

— — 15 mA

is included in all I

VIO

BAT

PM8

14 Rev 1.1

Table 3.3. Power Mode Wake Up Times

Parameter Symbol Test Condition Min Typ Max Unit

SiM3L1xx

Power Mode 2 or 6 Wake Time t

Power Mode 3 Fast Wake Time
(using LFO as clock source)

Power Mode 8 Wake Time t

Notes:

1. W

ake times are specified as the time from the wake source to the execution phase of the first instruction following WFI.

This includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0).

Table 3.4. Reset and Supply Monitor

Parameter Symbol Test Condition Min Typ Max Unit

V

High Supply Monitor Threshold

BAT

(VBATHITHEN = 1)

V

Low Supply Monitor Threshold

BAT

(VBATHITHEN = 0)

Power-On Reset (POR) Threshold V

V

Ramp Time t

BAT

Reset Delay from POR t

Reset Delay from non-POR source t

V

V

PM2

t

PM3FW

PM8

VBATMH

VBATML

POR

RMP

POR

RST

4 — 5 clocks

— 425 — μs

— 3.8 — μs

Early Warning — 2.20 — V

Reset 1.95 2.05 2.1 V

Early Warning — 1.85 — V

Reset 1.70 1.75 1.77 V

Rising Voltage on

V

BAT

Falling Voltage on

V

BAT

Time to V

Time between release

of reset source and

> 1.8 V 10 — 3000 μs

BAT

Relative to V

V

POR

code execution

BAT

>

— 1.4 — V

0.8 1 1.3 V

3 — 100 ms

— 10 — μs

RESET Low Time to Generate Reset t

Missing Clock Detector Response
Time (final rising edge to reset)

Missing Clock Detector Trigger
Frequency

V

Supply Monitor Turn-On Time t

BAT

RSTL

t

MCD

F

MCD

MON

50 — — ns

F

> 1 MHz — 0.5 1.5 ms

AHB

— 2.5 10 kHz

— 2 — μs

Rev 1.1 15

SiM3L1xx

Table 3.5. On-Chip Regulators

Parameter Symbol Test Condition Min Typ Max Unit

DC-DC Buck Converter

Input Voltage Range V

Input Supply to Output Voltage Differ­ential (for regulation)

Output Voltage Range V

Output Voltage Accuracy V

Output Current I

Inductor Value

Inductor Current Rating I

Output Capacitor Value C

Input Capacitor Value

Load Regulation R

Maximum DC Load Current During
Startup

Switching Clock Frequency F

Local Oscillator Frequency F

LDO Regulators

Input Voltage Range

Output Voltage Range

LDO Output Voltage Accuracy V

Output Settings in PM8 (All LDOs) V

Notes:

1. See reference manual for recommended inductors.

2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10

m (@ frequency > 1 MHz).

3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure

that the LDO output voltage will remain at a valid level as long as

4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both

LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO.
When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO.

5. Output range represents the programmable output range, and does not reflect the minimum voltage under all

conditions. Dropout when the input supply is close to the output setting is normal, and accounted for.

6. Analog peripheral specifications assume a 1.8 V output on the analog LDO.

1

2

3

4

DCIN

V

DCREG

DCOUT

DCACC

DCOUT

L

DC

LDC

DCOUT

C

DCIN

load

I

DCMAX

DCCLK

DCOSC

V

LDOIN

V

LDO

LDOACC

LDO

I

< 50 mA 450 — — mA

load

I

> 50 mA 550 — — mA

load

Sourced from VBAT 1.8 — 3.8 V

Sourced from VDC 1.9 — 3.8 V

1.8 V < V

1.95 V < V

2.0 V < V

< 2.9 V 1.5 V

BAT

< 3.5 V 1.8 V

BAT

< 3.8 V 1.9 V

BAT

V

LDOIN

1.8 — 3.8 V

0.45 — — V

1.25 — 3.8 V

— ±25 — mV

— — 90 mA

0.47 0.56 0.68 μH

1 2.2 10 μF

— 4.7 — μF

— 0.03 — mV/mA

— — 5 mA

1.9 2.9 3.8 MHz

2.4 2.9 3.4 MHz

0.8 — 1.9 V

— ±25 — mV

is at or above the specified minimum.

16 Rev 1.1

Table 3.5. On-Chip Regulators (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Memory LDO Output Setting

5

V

LDOMEM

SiM3L1xx

During Programming 1.8 — 1.9 V

During Normal

Operation

1.5 — 1.9 V

Digital LDO Output Setting V

Analog LDO Output Setting During

Normal Operation

Notes:

1. See reference manual for recommended inductors.

2. Recommended: X7R or X5R ceramic capacitors with low ESR. Example: Murata GRM21BR71C225K with ESR < 10

m (@ frequency > 1 MHz).

3. Input voltage specification accounts for the internal LDO dropout voltage under the maximum load condition to ensure

that the LDO output voltage will remain at a valid level as long as

4. The memory LDO output should always be set equal to or lower than the output of the analog LDO. When lowering both

LDOs (for example to go into PM8 under low supply conditions), first adjust the memory LDO and then the analog LDO.
When raising the output of both LDOs, adjust the analog LDO before adjusting the memory LDO.

5. Output range represents the programmable output range, and does not reflect the minimum voltage under all

conditions. Dropout when the input supply is close to the output setting is normal, and accounted for.

6. Analog peripheral specifications assume a 1.8 V output on the analog LDO.

6

LDODIG

V

LDOANA

F

< 20 MHz 1.0 — 1.9 V

AHB

F

> 20 MHz 1.2 — 1.9 V

AHB

1.8 V

V

is at or above the specified minimum.

LDOIN

Rev 1.1 17

SiM3L1xx

Table 3.6. Flash Memory

Parameter Symbol Test Condition Min Typ Max Unit

Write Time

Erase Time

Endurance (Write/Erase Cycles) N

Retention

Notes:

1. Does not include sequencing time before and after the write/erase operation, which may take up to 35 μs. During

2. Additional Data Retention Information is published in the Quarterly Quality and Reliability Report.

1

1

2

sequential write operations, this extra time is only taken prior to the first write and after the last write.

t

WRITE

t

ERASE

t

ERALL

WE

t

RET

One 16-bit Half Word 20 21 22 μs

One Page 20 21 22 ms

Full Device 20 21 22 ms

20k 100k — Cycles

TA = 25 °C, 1k Cycles 10 100 — Years

18 Rev 1.1

Table 3.7. Internal Oscillators

Parameter Symbol Test Condition Min Typ Max Unit

Phase-Locked Loop (PLL0OSC)

SiM3L1xx

Calibrated Output Frequency
(Free-running output mode,

RANGE = 2)

Power Supply Sensitivity
(Free-running output mode,

RANGE = 2)

Temperature Sensitivity
(Free-running output mode,

RANGE = 2)

Adjustable Output Frequency
Range

Lock Time t

PSS

f

PLL0OSC

PLL0OSC

TS

PLL0OSC

f

PLL0OSC

PLL0LOCK

Full Temperature and

Supply Range

TA = 25 °C,

Fout = 49 MHz

V

= 3.3 V,

BAT

Fout = 49 MHz

f

= 20 MHz,

REF

f

PLL0OSC

f

REF

f

PLL0OSC

M=19, N=399,

f

REF

f

PLL0OSC

M=0, N=1524,

= 50 MHz
M=39, N=99,
LOCKTH = 0

= 2.5 MHz,

= 50 MHz

LOCKTH = 0

= 32.768 kHz,

= 50 MHz

LOCKTH = 0

48.3 49 49.7 MHz

— 300 — ppm/V

— 50 — ppm/°C

23 — 50 MHz

— 2.75 — μs

— 9.45 — μs

— 92 — μs

Low Power Oscillator (LPOSC0)

Oscillator Frequency f

Divided Oscillator Frequency f

Power Supply Sensitivity PSS

Temperature Sensitivity TS

Low Frequency Oscillator (LFOSC0)

Oscillator Frequency f

Power Supply Sensitivity PSS

Temperature Sensitivity TS

LPOSCD

LPOSC

LPOSC

LPOSC

LFOSC

LFOSC

LFOSC

Full Temperature and

Supply Range

Full Temperature and

Supply Range

TA = 25 °C — 0.5 — %/V

V

= 3.3 V — 55 — ppm/°C

BAT

Full Temperature and

Supply Range

TA = 25 °C,

V

= 3.3 V

BAT

TA = 25 °C — 2.4 — %/V

V

= 3.3 V — 0.2 — %/°C

BAT

Rev 1.1 19

19 20 21 MHz

2.375 2.5 2.625 MHz

13.4 16.4 19.7 kHz

15.8 16.4 17.3 kHz

SiM3L1xx

Table 3.7. Internal Oscillators (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

RTC0 Oscillator (RTC0OSC)

Missing Clock Detector Trigger
Frequency

RTC External Input CMOS Clock
Frequency

RTC Robust Duty Cycle Range DC

Table 3.8. External Oscillator

Parameter

External Input CMOS Clock
Frequency

External Crystal Frequency f

External Input CMOS Clock High Time t

External Input CMOS Clock Low Time t

Low Power Mode Charge Pump
Supply Range (input from V

*Note: Minimum of 10 kHz when debugging.

BAT

)

f

RTCMCD

f

RTCEXTCLK

RTC

Symbol

f

CMOS

XTAL

CMOSH

CMOSL

V

BAT

Test Condition

— 8 15 kHz

0 — 40 kHz

25 — 55 %

Min Typ Max Unit

0* — 50 MHz

0.01 — 25 MHz

9 — — ns

9 — — ns

2.4 — 3.8 V

20 Rev 1.1

Table 3.9. SAR ADC

Parameter Symbol Test Condition Min Typ Max Unit

SiM3L1xx

Resolution N

Supply Voltage Requirements
(VBAT)

Throughput Rate
(High Speed Mode)

Throughput Rate
(Low Power Mode)

Tracking Time t

SAR Clock Frequency f

Conversion Time t

Sample/Hold Capacitor C

Input Pin Capacitance C

V

bits

ADC

f

S

f

S

TRK

SAR

CNV

SAR

IN

12 Bit Mode 12 Bits

10 Bit Mode 10 Bits

High Speed Mode 2.2 — 3.8 V

Low Power Mode 1.8 — 3.8 V

12 Bit Mode — — 250 ksps

10 Bit Mode — — 1 Msps

12 Bit Mode — — 62.5 ksps

10 Bit Mode — — 250 ksps

High Speed Mode 230 — — ns

Low Power Mode 450 — — ns

High Speed Mode — — 16.24 MHz

Low Power Mode — — 4 MHz

10-Bit Conversion,

SAR Clock = 16 MHz,

APB Clock = 40 MHz

Gain = 1 — 5 — pF

Gain = 0.5 — 2.5 — pF

High Quality Inputs — 18 — pF

Normal Inputs — 20 — pF

762.5 ns

Input Mux Impedance R

Voltage Reference Range V

Input Voltage Range* V

Power Supply Rejection Ratio PSRR

DC Performance

Integral Nonlinearity INL 12 Bit Mode — ±1 ±1.9 LSB

Differential Nonlinearity
(Guaranteed Monotonic)

Offset Error (using VREFGND) E

MUX

REF

IN

ADC

DNL 12 Bit Mode –1 ±0.7 1.8 LSB

OFF

High Quality Inputs — 300 — 

Normal Inputs — 550 — 

1 — V

Gain = 1 0 — V

Gain = 0.5 0 — 2xV

— 70 — dB

10 Bit Mode — ±0.2 ±0.5 LSB

10 Bit Mode — ±0.2 ±0.5 LSB

12 Bit Mode, VREF = 2.4 V –2 0 2 LSB

10 Bit Mode, VREF = 2.4 V –1 0 1 LSB

Rev 1.1 21

BAT

REF

REF

V

V

V

SiM3L1xx

Table 3.9. SAR ADC (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Offset Temperature Coefficient TC

Slope Error E

Dynamic Performance (10 kHz Sine Wave Input 1dB below full scale, Max throughput)

Signal-to-Noise SNR 12 Bit Mode 62 66 — dB

Signal-to-Noise Plus Distortion SNDR 12 Bit Mode 62 66 — dB

Total Harmonic Distortion (Up to
5th Harmonic)

Spurious-Free Dynamic Range SFDR 12 Bit Mode — –79 — dB

*Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO.

OFF

M

10 Bit Mode 58 60 — dB

10 Bit Mode 58 60 — dB

THD 12 Bit Mode — 78 — dB

10 Bit Mode — 77 — dB

10 Bit Mode — –74 — dB

— 0.004 — LSB/°C

–0.07 –0.02 0.02 %

22 Rev 1.1

Table 3.10. IDAC

Parameter Symbol Test Condition Min Typ Max Unit

Static Performance

SiM3L1xx

Resolution N

Integral Nonlinearity INL — ±0.5 ±2 LSB

Differential Nonlinearity (Guaranteed
Monotonic)

Output Compliance Range V

Full Scale Output Current I

Offset Error E

Full Scale Error Tempco TC

VBAT Power Supply Rejection Ratio 2 mA Range — –220 — ppm/V

Test Load Impedance (to VSS) R

Dynamic Performance

bits

DNL — ±0.5 ±1 LSB

OCR

OUT

OFF

FS

TEST

2 mA Range,

T

= 25 °C

A

1 mA Range,

TA = 25 °C

0.5 mA Range,
TA = 25 °C

2 mA Range — 100 — ppm/°C

— — V

1.98 2.046 2.1 mA

0.99 1.023 1.05 mA

491 511.5 525 μA

— 250 — nA

— 1 — k

10 Bits

BAT

1.0

–

V

Output Settling Time to 1/2 LSB min output to max

output

— 1.2 — μs

Startup Time — 3 — μs

Rev 1.1 23

SiM3L1xx

Table 3.11. ACCTR (Advanced Capture Counter)

Parameter Symbol Test Condition Min Typ Max Unit

LC Comparator Response Time,
CMPMD = 11
(Highest Speed)

LC Comparator Response Time,
CMPMD = 00
(Lowest Power)

LC Comparator Positive Hysteresis
Mode 0 (CPMD = 11)

LC Comparator Negative Hysteresis
Mode 0 (CPMD = 11)

LC Comparator Positive Hysteresis
Mode 1 (CPMD = 10)

t

RESP0

t

RESP3

HYS

HYS

HYS

CP+

CP-

CP+

+100 mV Differential — 100 — ns

–100 mV Differential — 150 — ns

+100 mV Differential — 1.4 — μs

–100 mV Differential — 3.5 — μs

CMPHYP = 00 — 0.37 — mV

CMPHYP = 01 — 7.9 — mV

CMPHYP = 10 — 16.7 — mV

CMPHYP = 11 — 32.8 — mV

CMPHYN = 00 — 0.37 — mV

CMPHYN = 01 — –7.9 — mV

CMPHYN = 10 — –16.1 — mV

CMPHYN = 11 — –32.7 — mV

CMPHYP = 00 — 0.47 — mV

CMPHYP = 01 — 5.85 — mV

CMPHYP = 10 — 12 — mV

LC Comparator Negative Hysteresis
Mode 1 (CPMD = 10)

LC Comparator Positive Hysteresis
Mode 2 (CPMD = 01)

LC Comparator Negative Hysteresis
Mode 2 (CPMD = 01)

HYS

HYS

HYS

CP-

CP+

CP-

CMPHYP = 11 — 24.4 — mV

CMPHYN = 00 — 0.47 — mV

CMPHYN = 01 — –6.0 — mV

CMPHYN = 10 — –12.1 — mV

CMPHYN = 11 — –24.6 — mV

CMPHYP = 00 — 0.66 — mV

CMPHYP = 01 — 4.55 — mV

CMPHYP = 10 — 9.3 — mV

CMPHYP = 11 — 19 — mV

CMPHYN = 00 — 0.6 — mV

CMPHYN = 01 — –4.5 — mV

CMPHYN = 10 — –9.5 — mV

CMPHYN = 11 — –19 — mV

24 Rev 1.1

Table 3.11. ACCTR (Advanced Capture Counter) (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

SiM3L1xx

LC Comparator Positive Hysteresis
Mode 3 (CPMD = 00)

LC Comparator Negative Hysteresis
Mode 3 (CPMD = 00)

LC Comparator Input Range
(ACCTR0_LCIN pin)

LC Comparator Common-Mode
Rejection Ratio

LC Comparator Power Supply Rejec­tion Ratio

LC Comparator Input Offset Voltage V

LC Comparator Input Offset Tempco TC

Reference DAC Offset Error DAC

Reference DAC Full Scale Output DAC

Reference DAC Step Size DAC

HYS

HYS

V

CMRR

PSRR

OFF

CP+

CP-

IN

CP

CP

OFF

EOFF

FS

LSB

CMPHYP = 00 — 1.37 — mV

CMPHYP = 01 — 3.8 — mV

CMPHYP = 10 — 7.8 — mV

CMPHYP = 11 — 15.6 — mV

CMPHYN = 00 — 1.37 — mV

CMPHYN = 01 — –3.9 — mV

CMPHYN = 10 — –7.9 — mV

CMPHYN = 11 — –16 — mV

–0.25 — V

— 75 — dB

— 72 — dB

TA = 25 °C –10 0 10 mV

— 3.5 — μV/°C

–1 — 1 LSB

Low Range — VIO/8 — V

BAT

0.25

+

High Range — V

Low Range (48 steps) — VIO/384 — V

High Range (64 steps) — VIO/64 — V

IO

— V

V

LC Oscillator Period T

LC Bias Output Impedance R

LC Bias Drive Strength I

Pull-Up Resistor Tolerance R

LCBIAS

LCOSC

LCBIAS

TOL

— 25 — ns

10 μA Load — 1 — k

— — 2 mA

PUVAL[4:2] = 0 to 6 -15 — 15 %

PUVAL[4:2] = 7 -10 — 10 %

Rev 1.1 25

SiM3L1xx

Table 3.12. Voltage Reference Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Internal Fast Settling Reference

Output Voltage V

Temperature Coefficient TC

Turn-on Time t

Power Supply Rejection PSRR

Internal Precision Reference

Valid Supply Range

Output Voltage

Short-Circuit Current I

Temperature Coefficient TC

Load Regulation

Load Capacitor

Turn-on Time

Power Supply Rejection PSRR

External Reference

Input Current

REFFS

REFFS

V

V

LR

C

VREFP

t

VREFPON

I

EXTREF

REFFS

REFFS

BAT

REFP

SC

VREFP

VREFP

VREFP

–40 to +85 °C,

V

= 1.8–3.8 V

BAT

VREF2X = 0 1.8 — 3.8 V

VREF2X = 1 2.7 — 3.8 V

25 °C ambient,

VREF2X = 0

25 °C ambient,

VREF2X = 1

Load = 0 to 200 μA to

VREFGND

Load = 0 to 200 μA to

VREFGND

4.7 μF tantalum, 0.1 μF
ceramic bypass

0.1 μF ceramic bypass — 200 — μs

VREF2X = 0 — 320 — ppm/V

VREF2X = 1 — 560 — ppm/V

Sample Rate = 250 ksps;

VREF = 3.0 V

1.6 1.65 1.7 V

— 50 — ppm/°C

— — 1.5 μs

— 400 — ppm/V

1.17 1.2 1.23 V

2.35 2.4 2.45 V

— — 10 mA

— 35 — ppm/°C

— 4.5 — ppm/μA

0.1 — — μF

— 3.8 — ms

— 5.25 — μA

Table 3.13. Temperature Sensor

Parameter Symbol Test Condition Min Typ Max Unit

Offset V

Offset Error* E

Slope M — 2.77 — mV/°C

Slope Error* E

Linearity — 1 — °C

Turn-on Time — 1.8 — μs

*Note: Absolute input pin voltage is limited by the lower of the supply at VBAT and VIO.

26 Rev 1.1

OFF

OFF

M

TA = 0 °C — 760 — mV

TA = 0 °C — ±14 — mV

— ±25 — μV/°C

Table 3.14. Comparator

SiM3L1xx

Parameter Symbol Test Condition Min Typ Max Unit

Response Time, CMPMD = 00
(Highest Speed)

Response Time, CMPMD = 11
(Lowest Power)

Positive Hysteresis
Mode 0 (CPMD = 00)

Negative Hysteresis
Mode 0 (CPMD = 00)

Positive Hysteresis
Mode 1 (CPMD = 01)

Negative Hysteresis
Mode 1 (CPMD = 01)

t

RESP0

t

RESP3

HYS

HYS

HYS

HYS

+100 mV Differential — 100 — ns

–100 mV Differential — 150 — ns

+100 mV Differential — 1.4 — μs

–100 mV Differential — 3.5 — μs

CP+

CP-

CP+

CP-

CMPHYP = 00 — 0.37 — mV

CMPHYP = 01 — 7.9 — mV

CMPHYP = 10 — 16.7 — mV

CMPHYP = 11 — 32.8 — mV

CMPHYN = 00 — 0.37 — mV

CMPHYN = 01 — –7.9 — mV

CMPHYN = 10 — –16.1 — mV

CMPHYN = 11 — –32.7 — mV

CMPHYP = 00 — 0.47 — mV

CMPHYP = 01 — 5.85 — mV

CMPHYP = 10 — 12 — mV

CMPHYP = 11 — 24.4 — mV

CMPHYN = 00 — 0.47 — mV

CMPHYN = 01 — –6.0 — mV

Positive Hysteresis
Mode 2 (CPMD = 10)

Negative Hysteresis
Mode 2 (CPMD = 10)

HYS

HYS

CP+

CP-

CMPHYN = 10 — –12.1 — mV

CMPHYN = 11 — –24.6 — mV

CMPHYP = 00 — 0.66 — mV

CMPHYP = 01 — 4.55 — mV

CMPHYP = 10 — 9.3 — mV

CMPHYP = 11 — 19 — mV

CMPHYN = 00 — 0.6 — mV

CMPHYN = 01 — –4.5 — mV

CMPHYN = 10 — –9.5 — mV

CMPHYN = 11 — –19 — mV

Rev 1.1 27

SiM3L1xx

Table 3.14. Comparator (Continued)

Parameter Symbol Test Condition Min Typ Max Unit

Positive Hysteresis
Mode 3 (CPMD = 11 )

Negative Hysteresis
Mode 3 (CPMD = 11 )

Input Range (CP+ or CP–) V

Input Pin Capacitance C

Common-Mode Rejection Ratio CMRR

Power Supply Rejection Ratio PSRR

Input Offset Voltage V

Input Offset Tempco TC

Reference DAC Resolution N

HYS

HYS

IN

CP

OFF

OFF

Bits

CP+

CP-

CP

CP

CMPHYP = 00 — 1.37 — mV

CMPHYP = 01 — 3.8 — mV

CMPHYP = 10 — 7.8 — mV

CMPHYP = 11 — 15.6 — mV

CMPHYN = 00 — 1.37 — mV

CMPHYN = 01 — –3.9 — mV

CMPHYN = 10 — –7.9 — mV

CMPHYN = 11 — –16 — mV

–0.25 — V

— 7.5 — pF

— 75 — dB

— 72 — dB

TA = 25 °C –10 0 10 mV

— 3.5 — μV/°C

6 bits

BAT

0.25

+

V

Table 3.15. LCD0

Parameter Symbol Test Condition Min Typ Max Unit

Charge Pump Output Voltage Error V

LCD Clock Frequency F

CPERR

LCD

— ±50 — mV

16 — 33 kHz

28 Rev 1.1