Silicon Laboratories Si8451, Si8450, Si8452, Si8455 User Manual
Si8450/51/52/55
LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR
Features
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Ultra-low-power (typical)
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Applications
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Safety Regulatory Approvals
UL 1577 recognized
Up to 2500 V
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced
Description
for 1 minute
RMS
insulation)
Not Recommended
Up to 2500 V
60-year life at rated working
voltage
Precise timing (typica l)
<10 ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-16 narrow body
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
RMS
isolation
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
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Ordering Information:
See page 28.
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Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrowbody SOIC package.
Rev. 1.6 4/18 Copyright © 2018 by Silicon Laboratories Si8450/51/52/55
Si8450/51/52/55
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . .25
3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .25
3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
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Not Recommended
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Rev. 1.6 2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Si8450/51/52/55
Ambient Operating Temperature* T
Supply Voltage V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Unit
Storage Temperature
Ambient Temperature Under Bias T
Supply Voltage (Revision A)
Supply Voltage (Revision B)
Input Voltage V
Output Voltage V
Output Current Drive Channel I
Lead Solder Temperature (10 s) — — 260 °C
2
3
3
V
1
DD1
DD2
150 Mbps, 15 pF, 5 V –40 25 125 °C
A
2.70 — 5.5 V
2.70 — 5.5 V
V
V
T
DD1
DD1
STG
A
, V
, V
I
O
O
DD2
DD2
–65 — 150 °C
–40 — 125 °C
–0.5 — 5.75 V
–0.5 — 6.0 V
g
–0.5 — VDD + 0.5 V
s
n
si
–0.5 — VDD + 0.5 V
e
——10mA
D
Maximum Isolation Voltage (1 s) — — 3600 V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "6. Ordering Guide" on page 28 for more information.
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Not Recommended
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Rev. 1.6 3
Si8450/51/52/55
Table 3. Electrical Characteristics
(V
=5V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage V
Low Level Input Volt age V
High Level Output Voltage V
Low Level Output Voltage V
Input Leakage Current I
Output Impedance
Enable Input High Current I
Enable Input Low Current I
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET . When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t
PSK(P-P)
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
is the magnitude of the difference in propagation delay times measured between different units operating at
=5V±10%, TA= –40 to 125 °C)
DD2
IH
IL
OH
OL
1
L
Z
O
ENH
ENL
DC Supply Current (All inputs 0 V or at Supply)
loh = –4 mA V
lol = 4 mA — 0.2 0.4 V
V
ENx=VIH
V
ENx=VIL
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
2.0 — — V
——0.8V
DD1,VDD2
–0.4 4.8 — V
——±10µA
—85—
—2.0—µA
—2.0—µA
—
—
—
—
1.6
s
2.9
7.0
n
3.1
2.4
4.4
10.5
4.7
g
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
si
—
—
e
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
D
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
w
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
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—
—
4.3
3.5
6.5
5.3
Not Recommended
o
f
—
—
—
—
4.1
4.0
4.1
4.0
6.2
6.0
6.2
6.0
mA
mA
mA
mA
mA
mA
4 Rev. 1.6
Si8450/51/52/55
Table 3. Electrical Characteristics (Continued)
(V
=5V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
DD1
V
DD2
Si8451Bx
V
DD1
V
DD2
Si8452Bx
V
DD1
V
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
DD1
V
DD2
Si8451Bx
V
DD1
V
DD2
Si8452Bx
V
DD1
V
DD2
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay t
Pulse Width Distortion
|t
PLH - tPHL
Propagation Delay Skew
Channel-Channel Skew t
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
2. t
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
|
the value of the on-chip series termination resistor and channel resistance of the output driver FET . When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
PSK(P-P)
the same supply voltages, load, and ambient temperature.
is the magnitude of the difference in propagation delay times measured between different units operating at
=5V±10%, TA= –40 to 125 °C)
DD2
—
—
—
—
—
—
—
—
4.3
4.8
4.4
5.0
4.6
4.8
4.6
24
s
6.5
6.7
6.2
7.0
6.4
6.7
6.9
30
mA
mA
mA
mA
n
Timing Characteristics
—
—
si
—
—
e
g
8.6
20.4
12.6
16.5
10.8
25.5
15.8
20.6
mA
mA
D
w
, t
PHL
PLH
PWD See Figure 2 — — 25 ns
2
Not Recommended
t
PSK(P-P)
PSK
See Figure 2 — — 35 ns
e
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— — 40 ns
— — 35 ns
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Rev. 1.6 5
Si8450/51/52/55
Table 3. Electrical Characteristics (Continued)
(V
=5V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay t
Pulse Width Distortion
|t
PLH - tPHL
Propagation Delay Skew
Channel-Channel Skew t
All Models
Output Rise Time t
Output Fall Time t
Common Mode Transient
Immunity
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
2. t
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
|
3,4
the value of the on-chip series termination resistor and channel resistance of the output driver FET . When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
PSK(P-P)
the same supply voltages, load, and ambient temperature.
is the magnitude of the difference in propagation delay times measured between different units operating at
=5V±10%, TA= –40 to 125 °C)
DD2
, t
PHL
PLH
PWD See Figure 2 — 1.5 2.5 ns
2
3
3
t
PSK(P-P)
PSK
r
f
CMTI V
t
en1
t
en2
t
SU
See Figure 2 3.0 6.0 9.5 ns
—2.03.0ns
—0.51.8ns
CL=15pF
See Figure 2
CL=15pF
See Figure 2
I=VDD
See Figure 1 — 5.0 8.0 ns
See Figure 1 — 7.0 9.2 ns
or 0 V — 25 — kV/µs
—3.85.0ns
—2.83.7ns
s
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g
si
—1540µs
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6 Rev. 1.6
Figure 1. ENABLE Timing Diagram
ENABLE
OUTPUTS
t
en1
t
en2
Typical
Input
t
PLH
t
PHL
Typical
Output
t
r
t
f
90%
10%
90%
10%
1.4 V
1.4 V
Si8450/51/52/55
s
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D
Figure 2. Propagation Delay Timing
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Not Recommended
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Rev. 1.6 7
Si8450/51/52/55
Table 4. Electrical Characteristics
(V
= 3.3 V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
Low Level Output Voltage V
Input Leakage Current I
Output Impedance
Enable Input High Current I
Enable Input Low Current I
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. t
PSK(P-P)
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
is the magnitude of the difference in propagation delay times measured between different units operating at
= 3.3 V±10%, TA= –40 to 125 °C)
DD2
IH
IL
OH
OL
1
DC Supply Current (All inputs 0 V or at supply)
L
Z
O
ENH
ENL
loh = –4 mA V
lol = 4 mA — 0.2 0.4 V
V
= V
ENx
V
ENx
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
= V
IH
IL
2.0 — — V
——0.8V
DD1,VDD2
–0.4 3.1 — V
——±10µA
—85—
—2.0—µA
—2.0—µA
—
—
—
—
1.6
s
2.9
7.0
n
3.1
2.4
4.4
10.5
4.7
g
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
si
—
—
e
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
D
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
w
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
e
r N
—
—
4.3
3.5
6.5
5.3
Not Recommended
o
f
—
—
—
—
4.1
4.0
4.1
4.0
6.2
6.0
6.2
6.0
mA
mA
mA
mA
mA
mA
8 Rev. 1.6
Si8450/51/52/55
Table 4. Electrical Characteristics (Continued)
(V
= 3.3 V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
DD1
V
DD2
Si8451Bx
V
DD1
V
DD2
Si8452Bx
V
DD1
V
DD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
V
DD1
V
DD2
Si8451Bx
V
DD1
V
DD2
Si8452Bx
V
DD1
V
DD2
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay t
Pulse Width Distortion
|t
PLH - tPHL
Propagation Delay Skew
Channel-Channel Skew t
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
2. t
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
|
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
PSK(P-P)
the same supply voltages, load, and ambient temperature.
is the magnitude of the difference in propagation delay times measured between different units operating at
= 3.3 V±10%, TA= –40 to 125 °C)
DD2
—
—
—
—
—
—
—
—
4.3
4.8
4.4
5.0
4.6
4.8
4.4
16.8
s
6.5
6.7
6.2
7.0
6.4
6.7
6.6
21
mA
mA
mA
mA
n
Timing Characteristics
—
—
si
—
—
e
g
6.9
14.5
9.5
12
8.6
18.1
11.9
15
mA
mA
D
w
See Figure 2 — — 35 ns
PHL,tPLH
PWD See Figure 2 — — 25 ns
2
Not Recommended
t
PSK(P-P)
r N
PSK
e
— — 40 ns
— — 35 ns
o
f
Rev. 1.6 9
Si8450/51/52/55
Table 4. Electrical Characteristics (Continued)
(V
= 3.3 V±10%, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay t
Pulse Width Distortion
|t
PLH - tPHL
Propagation Delay Skew
Channel-Channel Skew t
All Models
Output Rise Time t
Output Fall Time t
Common Mode Transient
Immunity
Enable to Data Valid
Enable to Data Tri-State
Start-up Time
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
2. t
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.
|
3,4
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
PSK(P-P)
the same supply voltages, load, and ambient temperature.
is the magnitude of the difference in propagation delay times measured between different units operating at
= 3.3 V±10%, TA= –40 to 125 °C)
DD2
, t
PHL
PLH
PWD See Figure 2 — 1.5 2.5 ns
2
3
3
t
PSK(P-P)
PSK
r
f
CMTI V
t
en1
t
en2
t
SU
See Figure 2 3.0 6.0 9.5 ns
—2.03.0ns
—0.51.8ns
CL=15pF
See Figure 2
CL=15pF
See Figure 2
I=VDD
See Figure 1 — 5.0 8.0 ns
See Figure 1 — 7.0 9.2 ns
or 0 V — 25 — kV/µs
—4.36.1ns
—3.04.3ns
s
n
g
si
—1540µs
e
D
w
e
Not Recommended
r N
o
f
10 Rev. 1.6
Si8450/51/52/55
Table 5. Electrical Characteristics
(V
= 2.70 V, V
DD1
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
Low Level Output Voltage V
Input Leakage Current I
Output Impedance
Enable Input High Current I
Enable Input Low Current I
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
V
DD1
V
DD2
Si8450Ax, Bx, Si8455Bx
V
DD1
V
DD2
Si8451Ax, Bx
V
DD1
V
DD2
Si8452Ax, Bx
V
DD1
V
DD2
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to T
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. t
PSK(P-P)
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.
= 2.70 V, TA= –40 to 125°C)
DD2
2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Not Recommended
= 0 to 85 °C.
A
is the magnitude of the difference in propagation delay times measured between different units operating at the
1
IH
IL
OH
OL
L
Z
O
ENH
ENL
DC Supply Current (All inputs 0 V or at supply)
lOH= –4mA V
IOL=4mA — 0.2 0.4 V
V
ENx=VIH
V
ENx=VIL
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
w
D
2.0 — — V
——0.8V
DD1,VDD2
——±10µA
—85—
—2.0—µA
—2.0—µA
—
—
—
—
—
—
si
—
e
—
—
—
—
—
e
—
r N
o
f
—
—
—
—
—
–0.4 2.3 — V
1.6
2.9
s
7.0
n
3.1
2.4
4.4
10.5
4.7
g
2.0
3.0
6.0
4.1
2.3
2.7
5.4
4.7
4.3
3.5
4.1
4.0
4.1
4.0
3.0
4.5
9.0
6.2
3.5
4.1
8.1
7.1
6.5
5.3
6.2
6.0
6.2
6.0
mA
mA
mA
mA
mA
mA
Rev. 1.6 11
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