Silicon Laboratories Si8284-EVB, Si8284CD-IS User Manual
UG168: Si8284-EVB User's Guide
This document describes the operation of the Si8284-EVB.
The Si8284 Evaluation Kit contains the following items:
• Si8284-EVB
Si8284CD-IS installed on the evaluation board.
•
KEY POINTS
• Discusses hardware overview and setup,
including:
• Si8284 low voltage side connections.
•
DC-DC operation.
• Si8284 isolated gate drive connections.
• Offers alternative configurations.
• Demonstrates driver functionality.
• Shows Si8284-EVB schematics and
silkscreen/copper layout.
• Includes the bill of materials and ordering
guide.
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UG168: Si8284-EVB User's Guide
Overview and Setup
1. Overview and Setup
1.1 Hardware
Si8284-EVB can be used to demonstrate the isolated gate drive capabilities of the installed Si8284CD-IS. The Si8284 includes a DCDC converter used to supply isolated power to the gate driver.
Si8284 Low Voltage Side Connections
Supply power to the input side of Si8284 by applying 12 to 24 VDC to VDDP at terminal block J1. LED D6 above terminal block J1
illuminates to show power applied. For interfacing to the low voltage side of Si8284, VDDA supply must be between 3.0 and 5.5 VDC.
Either a separate supply can be connected to VDDA terminal on J1 or 5 VDC can be derived from VDDP through the regulator circuit
and directed to VDDA through a jumper at JP4. LED D5 below terminal block J1 illuminates to show VDDA power applied.
J6-J11 single pin headers provide access to the IN+, IN-, RSTb, and SH inputs and FLTb and RDY outputs of the Si8284. These signals can be brought out to an external microcontroller using a ribbon cable (not supplied). FLTb is an open drain output and has a pullup resistor to VDDA. The open drain output allows multiple gate drivers FLTb outputs to share the same microcontroller input.
Driver functionality can be exercised without microcontroller by applying a GNDA referenced PWM signal from a function generator to
the IN+ and IN- inputs. Maximum input voltage is VDDA.
DC-DC Operation
The isolated DC-DC converter is set to generate (with respect to VMID) 15 V for VDDB and -9 V for VSSB. LED D8 and D7 illuminates
when VDDB and VSSB are powered respectively. DC-DC operation can be turned off by pulling terminal J11 to VDDA.
Si8284 Isolated Gate Drive Connections
There is a provision for a MOSFET or an IGBT in a TO-247 package (not supplied) at Q1.
From top to bottom, the through holes for the transistor leads are Source, Drain, and Gate. Load transistors are biased by applying
voltage across VPWR and VMID terminals of J2. This voltage should not exceed the rated VDS of the transistor or 300 V, whichever is
lower. Supply voltage constraints are summarized in the table below.
Note: Si8284 can drive the gate of either high-side or low-side MOSFET or IGBT in a bridge configuration. VMID is the same net as the
load when driving the gate of a high side MOSFET or IGBT. For a gate drive for a low side MOSFET or IGBT, VMID is the return for the
load.
Table 1.1. Supply Voltage Constraints
3.0 V ≤ VDDA – GNDA ≤ 5.5 V
12 V ≤ VDDP ≤ 24 V
VSSB ≤ VMID < VDDB
UVLO + 1 < VDDB - VSSB < 30 V
VPWR < VDS (Q)
Note:
1. UVLO+ for the Si8284CD-IS is 12.3 V.
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VPWR < 300 V
|GNDA – VSSB| < 5 kV
1.2 Alternative Configurations
Positive Voltage Gate Drive Only
UG168: Si8284-EVB User's Guide
Overview and Setup
The standard
configuration for the gate driver to apply positive voltage, VDDB-VMID, to the gate during the high drive portion of the
PWM cycle and negative voltage, VSSB-VMID, during the low drive portion of the PWM cycle. Alternatively, if only positive drive voltage
is desired, remove R13 and install a 0 Ω resistor at R19.
Prototyping Area
If additional components are needed to evaluate the gate drive function for a particular load, there is a prototyping area just below Q2
locations.
1.3 Demonstrating Driver Functionality
Even with no load present, the basic functionality of the Si8284 can be demonstrated.
1. Apply 24 V to VDDP to power both sides of the Si8284. With jumpers installed at JP4–JP8, D5–D8 will illuminate indicating supplies are biased.
2. Leave VPWR unpowered. Install a jumper at JP9. This disables desaturation detection and allows for normal operation of the
Si8284. Since both sides of the Si8284 have been powered on, RDY will output 5 V, which can be observed at J8.
3. Apply 5 V to both J9, IN+ and J10, IN-. VL will turn on and –9 V will be observed across pins 1 and 3 of Q1.
4. Remove 5 V from J10 and allow IN- to be pulled to GNDA. VH will turn on and +15 V will be observed across pins 1 and 3 of Q1.
5. Remove the short between VPWR and VMID at JP9.
6. With no path for DSAT current, the voltage at the DSAT pin rises and the Si8284 will drive the output low and FLTb to 0V which
can be observed at J7.
7. Once again, place the short between VPWR and VMID at JP9. Apply 0 V to RSTb input at J6. This clears the fault and normal
operation is restored.
1.4 Quick Reference Tables
Test Point Description Referenced to:
TP1 VDDA GNDA
TP3 VPWR VMID
TP4 VDDB VMID
TP5 VMID N/A
TP6 VSSB VMID
TP7 VDDP GNDA
TPV8 IGBT_GATE VMID
TP9 GNDA N/A
TPV9 DSAT VMID
TPV10 MOSFET_D GNDA
TPV11 MOSFET_G GNDA
TPV12 CLMP VSSB
Table 1.2. Test Point Descriptions
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2. Schematics
UG168: Si8284-EVB User's Guide
Schematics
SF1
BUMPER
VDDA
INPUT
SF3
BUMPER
VDDP
GNDA
SF2
TP7
VDDP
J1
1
2
3
TP1
VDDA
TP2
GNDA
VDDP
VDDA
TP9
GNDA
GNDA
Si8284
VDDP
VDDA
GNDA
VPWR
VDDB
VMID
VSSB
TP3
VPWR
TP4
VDDB
TP5
VMID
TP6
VSSB
VPWR
VDDB
VMID
VSSB
TP8
VMID
INPUT
J3
OUTPUT
VPWR
2
1
J2
VMID
VDDB
3
2
1
VSSB
BUMPER
VMID
SF4
BUMPER
Figure 2.1. Si8284-EVB Top Level Schematic
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