Silicon Laboratories Si8281-EVB User Manual
UG167: Si8281-EVB User's Guide
This document describes the operation of the Si8281-EVB.
The Si8281 Evaluation Kit contains the following items:
• Si8281-EVB
Si8281CD-IS installed on the evaluation board.
•
KEY POINTS
• Discusses hardware overview and setup,
including:
• Si8281 low voltage side connections.
•
DC-DC operation.
• Si8281 isolated gate drive connections.
• Offers alternative configurations.
• Demonstrates driver functionality.
• Shows Si8281-EVB schematics and
silkscreen/copper layout.
• Includes the bill of materials and ordering
guide.
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UG167: Si8281-EVB User's Guide
Overview and Setup
1. Overview and Setup
1.1 Hardware
Si8281-EVB can be used to demonstrate the isolated gate drive capabilities of the installed Si8281CD-IS. The Si8281 includes a DCDC converter used to supply isolated power to the gate driver.
Si8281 Low Voltage Side Connections
Supply power to the input side of Si8281 by applying 5.0 VDC to VIN at terminal block J1. LED D4 above terminal block J1 illuminates to
show power applied. A jumper must be installed at JP2 as VDDA is powered by the same supply as VIN.
J6–J10 single pin headers provide access to the IN+, IN–, RSTb inputs, and FLTb and RDY outputs of the Si8281. These signals can
be brought out to an external microcontroller using a ribbon cable (not supplied). FLTb is an open drain output and has a weak pull-up
resistor and LED D11 in series to VDDA. The open drain output allows multiple gate drivers' FLTb outputs to share the same microcontroller input.
Driver functionality can be exercised without microcontroller by applying a GNDA referenced PWM signal from a function generator to
the IN+ and IN– inputs. Maximum input voltage is VDDA.
DC-DC Operation
The isolated DC-DC converter is set to generate (with respect to VMID) 15 V for VDDB and –11 V for VSSB. LED D5 illuminates when
VDDB is powered. A jumper must be installed at JP1 to power VDDB from the DC-DC output.
Si8281 Isolated Gate Drive Connections
There are four different load options for Si8281 gate driver:
1. Through holes for a MOSFET or an IGBT in a TO-247 package (not supplied) at Q1.
2. Through holes for a MOSFET or an IGBT in a TO-220 package (not supplied) at Q2.
3. Through holes for a capacitor (not supplied) at C17.
4. Pads for a 1206-size surface mount capacitor (not supplied) at C11.
From top to bottom, the through holes for the transistor leads are Source, Drain, and Gate. Load transistors are biased by applying
voltage across VPWR and VMID terminals of J2. This voltage should not exceed the rated VDS of the transistor or 300 V, whichever is
lower. Supply voltage constraints are summarized in the table below.
Note: Si8281 can drive the gate of either high-side or low-side MOSFET or IGBT in a bridge configuration. When used as a high-side
gate driver, VMID is connected to the load. When used as a low-side gate driver, VMID is the return for the load.
For capacitive loads, capacitor value should be chosen to match the gate capacitance of the desired transistor. Supply voltage constraints are summarized in the table below.
Table 1.1. Supply Voltage Constraints
3.0 V ≤ VIN – GNDA = VDDA – GNDA ≤ 5.5 V
VSSB ≤ VMID < VDDB
UVLO+ < VDDB – VSSB < 30 V
Note:
1.
UVLO+ for the Si8281CD-IS is 12.3 V typically.
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VPWR < VDS (Q)
VPWR < 300 V
|GNDA – VSSB| < 5 kV
1.2 Alternative Configurations
Positive Voltage Gate Drive Only
UG167: Si8281-EVB User's Guide
Overview and Setup
The standard
configuration for the gate driver to apply positive voltage, VDDB–VMID, to the gate during the high drive portion of the
PWM cycle and negative voltage, VSSB–VMID, during the low drive portion of the PWM cycle. Alternatively, if only positive drive voltage is desired, remove R13 and install a 0 Ω resistor at R14.
Prototyping Area
If additional components are needed to evaluate the gate drive function for a particular load, there is a prototyping area just below Q2
locations.
1.3 Demonstrating Driver Functionality
Even with no load present, the basic functionality of the Si8281 can be demonstrated.
1. Ensure JP1 and JP2 have jumpers installed.
2. Apply 5 V to VIN to power both sides of the Si8281.
3. Short VPWR to VMID at J2 using a wire between the terminals of J2. This disables DSAT detection and allows for normal operation of the Si8281. Since both sides of Si8281 have been powered on, RDY will output 5 V, which can be observed at J8.
4. Apply 5 V to both J9, IN+ and J10, IN–. The Si8281 will drive low and –11 V can be observed across C17.
5. Apply 5 V to J9, IN+ and 0 V to J10, IN–. The Si8281 will drive high and 15 V can be observed across C17.
6. Remove the short between VPWR and VMID at J2.
7. With no path for DSAT current, the voltage at the DSAT pin rises and the Si8281 will drive the output low and pull FLTb to 0 V
which can be observed by D11 illuminating.
8. Once again, place the short between VPWR and VMID at J2. Pull RSTb to 0 V by pushing S1. This clears the fault and D11 will
turn off.
1.4 Quick Reference Tables
Test Point Description Referenced to:
TP1 VIN GNDA
TP2 GNDA N/A
TP3 VPWR VMID
TP4 VDDB VMID
TP5 VMID N/A
TP6 VSSB VMID
TP7 GNDA N/A
TP8 VSW GNDA
TP9 T1_SEC8 VMID
TP10 T1_SEC5 VMID
TP11 VMID/GNDB N/A
TP13 VSNS VSSB
Table 1.2. Test Point Descriptions
TP14 VMID N/A
TPV12 CLMP VSSB
TPV13 GATE VMID
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2. Schematics
UG167: Si8281-EVB User's Guide
Schematics
SF1
BUMPER
J1
SF3
BUMPER
INPUT
VIN
1
2
GNDA
TP1
VIN
TP2
GNDA
GNDA
VIN
TP7
GNDA
1
Si8281
VIN
GNDA
VPWR
VDDB
VMID
VSSB
Figure 2.1. Si8281-EVB Top Level Schematic
VPWR
VDDB
TP5
VMID
VMID
VSSB
TP3
VPWR
TP4
VDDB
TP14
VMID
TP6
VSSB
VMID
INPUT
VPWR
VMID
OUTPUT
VDDB
VSSB
2
1
3
2
1
SF2
BUMPER
J2
J3
SF4
BUMPER
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