Si5600
PRELIMINARY DATA SHEET
SiPHY™ OC-192/STM-64 SONET/SDH TRANSCEIVER
Features
Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
! Data Rates Supported: OC-192/
STM-64, 10GbE, and 10.7 Gbps FEC
! Low Power Operation 1.2 W (typ)
! DSPLL™ Based Clock Multiplier Unit
w/ Selectable Loop Filter Bandwidths
! Integrated Limiting Amplifier
! Loss-of-Signal (LOS) Alarm
! Diagnostic and Line Loopbacks
! SONET Compliant Loop Timed
Operation
! Programmable Slicing Level and
Sample Phase Adjustment
! SFI-4 Compliant Low Speed
Interface
! Single Supply 1.8 V Operation
! 15 x 15 mm BGA Package
Si5600
Bottom View
Applications
! Sonet/SDH Transmission
Systems
! Optical Transceiver Modules
! Sonet/SDH Test Equipment
Description
The Si5600 is a complete low-power transceiver for high-speed serial
communication systems operating between 9.9 Gbps and 10.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’
™
DSPLL
technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing, and sample phase
adjustment are supported.
The Si5600 operates from a single 1.8 V supply over the industrial temperature
range (–40°C to 85°C).
Functional Block Diagram
LOS
LOSLVL
RXDIN
REFSEL
REFCLK
LPTM
REFRATE
TXLOL
BWSEL
TXCLKDSBL
TXCLKOUT
TXSQLCH
TXDOU T
RESET
SLICELVL
2
Limiting
AMP
2
TXCLK16IN
2
2
PHASEADJ
RESET
Control
LTR
CDR
DSPLL
TX CM U
RXLOL
TM
Loopback Control
DLBKLLBK
RXSQLCH
1:16
÷
÷
16:1
TXMSBSEL
DEMUX
MUX
32
2
2
32
FIFO
FIFOERR
RXMSBSEL
RXDOUT[15:0]
RXCLK1
RXCLK2
RXCLK2DIV
RXCLK2DSBL
2
2
TXCLK16IN
TXDIN[15:0]
FIFORST
TXCLK16OUT
Ordering Information:
See page 25.
Preliminary Rev. 0.31 8/01 Copyright © 2001 by Silicon Laboratories Si5600-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5600
2 Preliminary Rev. 0.31
Si5600
TABLE OF CONTENTS
Section Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Si5600 Pinout: 195-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Descriptions: Si5600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Preliminary Rev. 0.31 3
Si5600
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition
Ambient Temperature T
LVTTL Output Supply Voltage V
Si5600 Supply Voltage V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
A
DD33
DD
*
Min
Typ
–40 25 85 °C
1.71 — 3.47 V
1.71 1.8 1.89 V
Max
*
Unit
V
SIGNAL +
Differential
I/Os
V
ICM
SIGNAL –
, V
OCM
V
IS
Single Ended Voltage
(SIGNAL +) – (SIGNAL –)
Differential
Voltage Swing
VID,VOD (V
= 2VIS)
ID
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement
(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN)
TXDOUT,
TXDIN
TXCLKOUT,
TXCLK16IN
RXDOUT
RXCLK1
t
cq2
t
hd
t
su
t
cq1
Figure 2. Data to Clock Delay
t
t
CH
CP
4 Preliminary Rev. 0.31
Si5600
All Differential
IOs
t
F
t
R
80%
20%
Figure 3. Rise/Fall Time Measurement
Table 2. DC Characteristics
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Supply Current I
Power Dissipation P
Voltage Reference (VREF) V
Common Mode Input Voltage (RXDIN) V
Differential Input Voltage Swing (RXDIN) V
Common Mode Output Voltage
V
(TXDOUT, TXCLKOUT)
Differential Output Voltage Swing
V
(TXDOUT, TXCLKOUT), Differential pk-pk
LVPECL Input Voltage HIGH (REFCLK) V
LVPECL Input Voltage LOW (REFCLK) V
LVPECL Input Voltage Swing,
Differential pk-pk (REFCLK)
LVPECL Internally Generated Input Bias
(REFCLK)
LVDS Input High Voltage
(TXDIN, TXCLK16IN)
LVDS Input Low Voltage
(TXDIN, TXCLK16IN)
LVDS Input Voltage, Single Ended pk-pk
V
(TXDIN, TXCLK16IN)
LVDS Output High Voltage
V
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)
LVDS Output Low Voltage
V
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)
LVDS Output Voltage, Differential pk-pk
V
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)
DD
D
REF
ICM
ID
OCM
OD
IH
IL
V
ID
V
IB
V
IH
V
IL
ISE
OH1
OL1
OSE
VREF driving
Ω load
10 k
See Figure 1 20 — 1.0 mV
See Figure 1 800 1000 1200 mV
Figure 1 250 — 2400 mV
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line
100 Ω Load
Line-to-Line,
Figure 1
—611TBDmA
—1.2TBDW
1.21 1.25 1.29 V
TBD 0.1 TBD V
(pk-pk)
.8 0.9 1.0 V
(pk-pk)
1.975 2.3 2.59 V
1.32 1.6 1.99 V
(pk-pk)
1.6 1.95 2.3 V
——2.4V
0.0 — — V
100 — 600 mV
(pk-pk)
TBD — 1.475 mV
0.925 — TBD V
500 — 800 mV
(pk-pk)
Preliminary Rev. 0.31 5
Si5600
Table 2. DC Characteristics (Continued)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
LVDS Common Mode Voltage
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)
Input Impedance (TXDIN, TXCLK16IN,
REFCLK, RXDIN)
Output Short to GND
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT, TXDOUT, TXCLKOUT)
Output Short to V
DD
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT, TXDOUT, TXCLKOUT)
LVTTL Input Voltage Low
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK
, REFSEL, LTR, RESET,
,
, LLBK, LPTM)
LVTTL Input Voltage High
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK
, REFSEL, LTR, RESET,
,
, LLBK, LPTM)
LVTTL Input Low Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK
, REFSEL, LTR, RESET,
,
, LLBK, LPTM)
LVTTL Input High Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK
, REFSEL, LTR, RESET,
,
, LLBK, LPTM)
LVTTL Input Impedance
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK
, REFSEL, LTR, RESET,
,
, LLBK, LPTM)
LVTTL Output Voltage Low
(LOS
, RXLOL, FIFOERR, TXLOL)
LVTTL Output Voltage High
(LOS
, RXLOL, FIFOERR, TXLOL)
V
CM
R
IN
I
SC(–)
I
SC(+)
V
IL2
V
IH2
I
IL
I
IH
R
IN
V
OL2
V
OH2
1.125 — 1.275 V
Each input to
42 50 58 Ω
common mode
—25TBDmA
TBD –100 — µA
VDD33 = 3.3 V — — 0.8 V
VDD33 = 1.8 V — — 0.7
VDD33 = 3.3 V 2.0 — — V
VDD33 = 1.8 V 1.7
——10µA
——10µA
10 — — kΩ
VDD33 = 1.8 V — — 0.4 V
VDD33 = 3.3 V — — 0.4
VDD33 = 1.8 V 1.4 — — V
VDD33 = 3.3 V 2.4 — —
6 Preliminary Rev. 0.31
Si5600
Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)
(VDD = 1.8 V ±5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Clock Frequency
f
clkout
—622667MHz
(RXCLK1)
Duty Cycle (RXCLK1, RXCLK2) tch/tcp, Figure 2 45 — 55 %
Output Rise and Fall Times
t
R,tF
Figure 3 — 50 — ps
(RXCLK1, RXCLK2,RXDOUT)
Data Invalid Prior to RXCLK1 t
Data Invalid After RXCLK1 t
cq1
cq2
Input Return Loss (RXIN) 400 kHz–10.0 GHz
Figure 2 — — 200 ps
Figure 2 — — 200 ps
10.0 GHz–16.0 GHz
18.7
TBD
—
—
—
—
dB
dB
Slicing Adjust Dynamic Range SLICELVL = 200–800 mV –20 — 20 mV
Slicing Level Offset
1
SLICELVL = 200–800 mV –500 — 500
µV
(referred to RXDIN)
Slicing Level Accuracy VSLICE –5 — 5 %
Sampling Phase Adjustment
2
PHASEADJ = 200–800 mV –45° —45
o
LOS Threshold Dynamic Range LOSLVL = 200–800 mV 10 — 50 mV
pk-pk
LOS Threshold Offset
3
LOSLVL = 200–800 mV –500 — 500
µV
(referred to RXDIN)
LOS Threshold Accuracy VLOS –5 — 5 %
Note:
1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL – 0.4"VREF)/15.
2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 45° (PHASEADJ – 0.4
3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL – 0.4"VREF)/15.
"
VREF)/0.3
Preliminary Rev. 0.31 7
Si5600
Table 4. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)
(V
1.8 V ± 5%, TA = –40°C to 85°C)
DD =
Parameter Symbol Test Condition Min Typ Max Unit
TXCLKOUT Frequency f
clkout
—9.9510.7GHz
TXCLKOUT Duty Cycle tch/tcp, Figure 2 45 — 55 %
Output Rise Time
t
R
Figure 3 — 25 — ps
(TXCLKOUT, TXDOUT)
Output Fall Time
t
F
Figure 3 — 25 — ps
(TXCLKOUT, TXDOUT)
TXCLKOUT Setup to TXDOUT t
TXCLKOUT Hold From TXDOUT t
su
hd
Output Return Loss 400 kHz–10 GHz
TXCLK16OUT Frequency f
CLKIN
Figure 2 25 — — ps
Figure 2 25 — — ps
10 GHz–16 GHz
TBD
TBD
—
—
—
—
—622667MHz
dB
dB
TXCLK16OUT Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16OUT Rise & Fall Times t
TXDIN Setup to TXCLK16IN t
TXDIN Hold from TXCLK16IN t
TXCLK16IN Frequency f
R,tF
DSIN
DHIN
CLKIN
100 — 300 ps
——300ps
——300ps
—622667MHz
TXCLK16IN Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16IN Rise & Fall Times t
R,tF
100 — 300 ps
8 Preliminary Rev. 0.31
Si5600
Table 5. AC Characteristics (Receiver PLL)
(VDD = 1.8 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Tolerance J
TOL(PP)
f = 2.4 kHz 15 30 — UIpp
f = 24 kHz 1.5 3.0 — UIpp
f = 400 kHz 1.5 3.0 — UIpp
f = 4 MHz 0.15 0.3 — UIpp
Acquisition Time T
Input Reference Clock Frequency RC
AQ
FREQ
REFRATE = 1 — 622 667 MHz
REFRATE = 0 — 155 167 MHz
Reference Clock Duty Cycle RC
Reference Clock Frequency
RC
DUTY
TOL
Tolerance
Frequency Difference at which
LOL TBD 600 1000 ppm
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)
Frequency Difference at which
LOCK TBD 300 TBD ppm
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
——20 µs
40 50 60 %
–100 — 100 ppm
Preliminary Rev. 0.31 9
Si5600
Table 6. AC Characteristics (Transmitter Clock Multiplier Characteristics)
(VDD = 1.8 V ± 5%, TA = –40°C to 85°C)
Parameter Symbol Test Condition Min Typ Max Unit
Jitter Generation—Deterministic J
Jitter Generation—Random J
DET(PP)
GEN(RMS)
Jitter Transfer Bandwidth J
BW
PRBS 23 — 0.020 TBD UI
—0.005TBDUI
RMS
BWSEL = 0 — — 12 kHz
BWSEL = 1 — — 50 kHz
Jitter Transfer Peaking — 0.05 0.1 dB
Acquisition Time T
Input Reference Clock Frequency RC
AQ
FREQ
Valid REFCLK — 15 20 mS
REFRATE = 1 — 622 667 MHz
REFRATE = 0 — 155 167 MHz
Input Reference Clock Duty
RC
DUTY
40 — 60 %
Cycle
Input Reference Clock Frequency
RC
TOL
–100 — 100 ppm
Tolerance
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Table 7. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage V
LVTTL Input Voltage V
Differential Input Voltages V
DD
DD33
DIF
Maximum Current any Output PIN ±50 mA
–0.5 to TBD V
–0.5 to 3.6 V
–0.3 to (VDD+ 0.3) V
PP
Operating Junction Temperature T
Storage Temperature Range T
Package Temperature
JCT
STG
–55 to 150 °C
–55 to 150 °C
275
°C
(soldering 10 seconds)
ESD HBM To le ra nc e (1 00 pf, 1.5 k
Note: Permanent device damage may occur if the above Absolute Maximum Rati ngs are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Ω)TBDV
Table 8. Thermal Characteristics
Parameter Symbol Test Condition Value Unit
Thermal Resistance Junction to Ambient ϕ
10 Preliminary Rev. 0.31
JA
Still Air 38 °C/W
LVTTL
Control Inputs
Si5600
High Speed
0.033 µF
Serial Input
LVPECL Reference
Clock
LVDS Parallel Data
Input
LVDS Data Clock
Input
FIFORST
RESET
RXDIN±
REFCLK
16
TXDIN±
TXCLK16IN±
LTR
LOSLVL
TXCLKDSBL
REFSEL
SLICELVL
LLBK
LPTM
REFRATE
TXSQLCH
RXSQLCH
BWSEL
Si5600
PHASEADJ
TXREXT
DLBK
RXREXT
TXMSBEL
RXMSBSEL
TXCLKOUT±
TXCLK16OUT±
VDD
VDD
RXCLK2DIV
FIFOERR
TXLOL
RXLOL
RXDOUT±
RXCLK1±
RXCLK2±
TXDOUT±
VREF
0.1 µF
2200 pF
RXCLK2DSBL
LOS
GND
0.033 µF
0.033 µF
FIFO Over/Underflow
Loss-of-Lock
Indicator
Loss-of-Signal
Indicator
16
LVDS Recovered
Parallel Data
LVDS Recovered
Low Speed
Clock
High Speed
Serial Data Output
High Speed
Clock Output
Low Speed
Clock Output
Voltage Reference
Output (1.25 V)
Loss-of-Signal
Level Set
Data Slice
Level Set
Sampling Phase
Level Set
20 pF
Figure 4. Si5600 Typical Application Circuit
Preliminary Rev. 0.31 11
Si5600
Functional Description
The Si5600 transceiver is a low power, fully integrated
serializer/deserializer that provides significant margin to
all SONET/SDH jitter specifications. The device
operates from 9.9–10.7 Gbps making it suitable for OC192/STM-64, 10GbE, and OC-192/STM-64 applications
that use 15/14 forward error correction (FEC) coding.
The low speed receive/transmit interface uses LVDS I/
Os that are compliant to the Optical Interface Forum’s
SFI-4 standard.
Receiver
The receiver within the Si5600 includes a precision
limiting amplifier, high jitter tolerance clock and data
recovery unit (CDR), and 1:16 demultiplexer. In
addition, programmable data slicing and sampling
phase adjustment are provided to support bit-error-rate
(BER) optimization for long haul applications.
Limiting Amplifier
The Si5600 incorporates a high sensitivity limiting
amplifier with sufficient gain to directly accept the output
of transimpedance amplifiers. High sensitivity is
achieved by using a digital calibration algorithm to
cancel out amplifier offsets. This algorithm achieves
superior offset cancellation by using statistical
averaging to remove noise that may degrade more
traditional calibration routines.
The limiting amplifier provides sufficient gain to fully
saturate with input signals that are less than 20 mV
peak-to-peak differential. In addition, input signals that
exceed 1 V peak-to-peak differential will not cause any
performance degradation.
Loss-of-Signal (LOS) Detection
The limiting amplifier includes circuitry that generates a
loss-of-signal (LOS) alarm when the input signal
amplitude on RXDIN falls below an externally controlled
threshold. The Si5600 can be configured to drive the
output low when the differential input amplitude
LOS
drops below a threshold set between ~10 mV and
50 mV pk-pk differential. Approximately 3 dB of
hysteresis prevents unnecessary switching on LOS
The LOS threshold is set by applying a voltage between
0.20 V and 0.80 V to the LOSLVL input. The voltage
present on LOSLVL maps to an input signal threshold
as follows:
V
LOSLVL
V
is the differential pk-pk LOS threshold referred to
V
LOS
the RXDIN input, V
---------------------------------------------------------------
LOS
LOSLVL
0.4xVREF–()
15
30 mV+=
is the voltage applied to the
.
LOSLVL pin, and VREF is reference voltage output on
the VREF pin.
The LOS detection circuitry is disabled by tieing the
LOSLVL input to the supply (VDD). This forces the LOS
output high.
Slicing Level Adjustment
To support applications that require BER optimization,
the limiting amplifier provides circuitry that supports
adjustment of the 0/1 decision threshold (slicing level)
over a range of ±20 mV when referred to the int ernally
biased RXDIN input. The slicing level is set by applying
a voltage between 0.20 V and 0.80 V to the SLICELVL
input. The voltage present on SLICELVL sets the slicing
level as follows:
V
LEVEL
V
SLICE
V
SLICE
V
LEVEL
---------------------------------------------------------- -
=
is the slicing level referred to the RXDIN input,
is the voltage applied to the SLICE_LVL pin, and
0.4xVREF–()
15
VREF is reference voltage output on the VREF pin.
The slicing level adjustment may be disabled by tieing
the SLCLVL input to the supply (VDD). When slicing is
disabled, the slicing offset is set to 0.0 V relative to
internally biased input common mode voltage for
RXDIN.
Clock and Data Recovery (CDR)
The Si5600 uses an integrated CDR to recover clock
and data from a non-return to zero (NRZ) signal input on
RXDIN. The recovered data clock is used to regene rate
the incoming data by sampling the output of the limiting
amplifier at the center of the NRZ bit period. The
recovered clock and data is then deserialized by a 1:16
demultiplexer and output via a LVDS compatible low
speed interface (RXDOUT[15:0], RXCLK1, and
RXCLK2).
Sample Phase Adjustment
In applications where it is not desirable to recover data
by sampling in the center of the data eye, the Si5600
supports adjustment of the CDR sampling phase across
the NRZ data period. When sample phase adjustment is
enabled, the sampling instant used for data recovery
can be moved over a range of ±45
of the incoming NRZ bit period. Adjustment of the
sampling phase is desirable when data eye distortions
are introduced by the transmission medium.
The sample phase is set by applying a voltage between
0.20 V and 0.80 V to the PHASEADJ input. The voltage
present on PHASEADJ maps to sample phase offset as
follows:
° relative to the center
12 Preliminary Rev. 0.31
Si5600
45° xV
PHASE
--------------------------------------------------------------------------
Phase Offset
Phase Offset is the sampling offset in degrees from the
center of the data eye, V
the PHASEADJ pin, and VREF is reference voltage
output on the VREF pin. A positive phase offset will
adjust the sampling point to lead the default sampling
point in the center of the data eye, and a negative phase
offset will adjust the sampling point to lag the default
sampling point.
Data recovery using a sampling phase offset is disabled
by tieing the PHASEADJ input to the supply (VDD). This
forces a phase offset of 0
Lock Detect
The Si5600 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. This circuit compares the frequency of a
divided down version of the recovered clock with the
frequency of the supplied reference clock (REFCLK). If
the recovered clock frequency deviates from that of the
reference clock by the amount specified in Table 5 on
page 9, the PLL is declared out of lock, and the loss-oflock (RXLOL
try to reacquire lock with the incoming data stream.
During reacquisition, the recovered clock frequency
(RXCLK1 and RXCLK2) will drift over a ±1000 ppm
range relative to the supplied reference clock. The
RXLOL
clock frequency is within the REFCLK frequency by the
amount specified in Table 5 on page 9.
Lock-to-Reference
In applications where it is desirable to maintain a stable
output clock during an alarm condition like loss-ofsignal, the lock-to-reference input (LTR
force a stable output clock. When LTR
CDR is prevented from acquiring the data signal and the
CDR will lock the RXCLKOUT1 and RXCLKOUT2
outputs to the provided REFCLK. In typical applications,
the LOS
stable output clock.
) pin is asserted. In this state, the PLL will
output will remain asserted until the recovered
output would be tied to the LTR input to force a
=
PHASE
° to be used for data recovery.
0.4xVREF–()
0.30
is the voltage applied to
) can be used to
is asserted, the
Deserialization
The Si5600 uses a 1:16 demultiplexer to deserialize the
high speed input. The deserialized data is output on a
16-bit parallel data bus RXDOUT[15:0] synchronous
with the rising edge of RXCLK1. This clock output is
derived by dividing down the recovered clock by a factor
of 16.
Serial Input to Parallel Output Relationship
The Si5600 provides the capability to select the order in
which the received serial data is mapped to the parallel
output bus RXDOUT[15:0]. The mapping of the receive
bits to the output data word is controlled by the
RXMSBSEL input. If RXMSBSEL is tied low, the first bit
received is output on RXDOUT0 and the following bits
are output in order on RXDOUT1 through RXDOUT15.
If RXMSBSEL is tied high, the first bit received is output
on RXDOUT15, and the following bits are output in
order on RXDOUT14 through RXDOUT0.
Auxiliary Clock Output
To support the widest range of system timing
configurations, a second clock output is provided on
RXCLK2. This output can be configured to provide a
clock that is a 1/16th or 1/64th submultiple of the high
speed recovered clock. The divide factor used to
generate RXCLK2 is controlled via the RXCLKDIV2
input as described in "Pin Descriptions: Si5600‚" on
page 19. In applications which do not use RXCLK2, this
output can be powered down by forcing the
RSCLK2DSBL input high.
Data Squelch
During some system error conditions, such as LOS, it
may be desirable to force the receive data output to 0 in
order to avoid propagation of erroneous data into the
downstream electronics. In these applications, the
Si5600 provides a data squelching control input,
RXSQLCH
RXDOUT will be forced to 0. Data squelch is disabled if
the device is operating in diagnostic loopback mode
(DLBK
. When this input is active low, the data on
= 0).
Transmitter
The transmitter consists of a low jitter, clock multiplier
unit (CMU) with a 16:1 serializer. The CMU uses a
phase-locked loop (PLL) architecture based on Silicon
Laboratories’ proprietary DSPLL
technology is used to generate ul tra-low jitter clock an d
data outputs that provide significant margin to the
SONET/SDH specifications. The DSPLL architecture
also utilizes a digitally implemented loop filter that
eliminates the need for external loop filter components.
As a result, sensitive noise coupling nodes that typically
cause degraded jitter performance in crowded PCB
environments are removed.
™
The DSPLL
performance requirements of reference clock
distribution strategies for OC-192/STM-64 optical port
cards. This is possible because the DSPLL provides
selectable wideband and narrowband loop filter settings
that allow the user to set the jitter attenuation
characteristics of the CMU to accommodate reference
clock sources that have a high jitter content. Unlike
also reduces the complexity and
™
technology. This
Preliminary Rev. 0.31 13
Si5600
traditional analog PLL implementations, the loop filter
bandwidth is controlled by a digital filter inside the
DSPLL and can be changed without any modification to
external components.
DSPLL™ Clock Multiplier Unit
The Si5600’s clock multiplier unit (CMU) uses Silicon
Laboratories’ proprietary DSPLL technology to gener ate
a low jitter, high frequency clock source capable of
producing a high speed serial clock and dat a outp ut with
significant margin to the SONET/SDH specifications.
This is achieved by using a digital signal processing
(DSP) algorithm to replace the loop filter commonly
found in analog PLL designs. This algorithm processes
the phase detector error term and generates a digital
control value to adjust the frequency of the voltage
controlled oscillator (VCO). Because external loop filter
components are not required, sensitive noise entry
points are eliminated, thus making the DSPLL less
susceptible to board-level noise sources. Therefore,
SONET/SDH jitter compliance is easier to attain in the
application.
Programmable Loop Filter Bandwidth
The digitally implemented loop filter allows for two
bandwidth settings that provide either wideband or
narrowband jitter transfer characteristics. The filter
bandwidth is selected via the BWSEL con trol input. In
traditional PLL implementations, changing the loop filter
bandwidth would require changing the values of
external loop filter components.
In narrowband mode, a loop filter cutoff of 12 kHz is
provided. This setting makes the Si5600 more tolerant
to jitter on the reference clock source. As a result,
distribution circuitry used to generate the physical layer
reference clocks can be simplified without
compromising jitter margin to the SONET/SDH
specification.
In wideband mode, the loop filter provides a cutoff of
50 kHz. This setting is desirable in applications where
the reference clock is provided by a low jitter source like
the Si5364 Clock Synchronization IC or Si5320
Precision Clock Multiplier/Jitter Attenuator IC. This
allows the DSPLL to more closely track the precision
reference source, resulting in the best possible jitter
performance.
Serialization
The Si5600 includes serialization circuitry that
combines a FIFO with a parallel to serial shift register.
Low speed data on the parallel input bus, TXDIN[15:0],
is latched into the FIFO on the rising edge of
TXCLK16IN. The data in the FIFO is clocked into the
shift register by an output clock, TXCLK16OUT, that is
produced by dividing down the high speed transmit
clock, TXCLKOUT , by a factor of 16. The TXCLK16OUT
clock output is provided to support 16-bit word transfers
between the Si5600 and upstream devices using a
counter clocking scheme. The high-speed serial data
stream is clocked out of the shift register using
TXCLKOUT.
Input FIFO
The Si5600 integrates a FIFO to decouple data
transferred into the FIFO via TXCLK16IN from data
transferred into the shift register via T XCLK16O UT. The
FIFO is eight parallel words deep and accommodates
any static phase delay that may be introduced between
TXCLK16OUT and TXCLK16IN in counter clocking
schemes. Furthermore, the FIFO will accommodate a
phase drift or wander between TXCLK16IN and
TXCLK16OUT of up to three parallel data words.
The FIFO circuitry indicates an overflow or underflow
condition by asserting FIFOERR high. This output can
be used to recenter the FIFO read/write pointers by
tieing it directly to the FIFORST input. The Si5600 will
also recenter the read/write pointers after the device’s
power on reset, external reset via RESET
time the DSPLL transitions from an out of lock state to a
locked state (TXLOL
Parallel Input To Serial Output Relationship
The Si5600 provides the capability to select the order in
which data on the parallel input bus is transmitted
serially . Data on this bus can be transmitted MSB first or
LSB first depending on the setting of TXMSBSEL. If
TXMSBSEL is tied low, TXDIN0 is transmitted first
followed in order by TXDIN1 through TXDIN15. If
TXMSBSEL is tied high, TXDIN15 is transmitted first
followed in order by TXDIN14 through TXDIN0. This
feature simplifies board routing wh en ICs are mounted
on both sides of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the
network, the Si5600 provides a control pin that can be
used to force TXDOUT to 0. By driving TXSQLCH
the high speed serial output, TXDOUT will be forced to
0. Transmit dat a sq ue lch ing is d isa ble d when the d evice
is in line loopback mode (LLBK
Clock Disable
The Si5600 provides a clock disable pin, TXCL KDSBL,
that is used to disable the high-speed serial data clock
output, TXCLKOUT. When the TXCLKDSBL pin is
asserted, the positive and negative terminals of
CLKOUT are tied to 1.5 V through 50
resistors. This feature is used to reduce power
transitions from low to high).
= 0).
, and each
low,
Ω on-chip
14 Preliminary Rev. 0.31
Si5600
consumption in applications that do not use the high
speed transmit data clock.
Loop Timed Operation
The Si5600 may be configured to provide SONET/SDH
compliant loop timed operation. When LP TM is asserted
high, the transmit clock and data timing is derived from
the recovered clock output by the CDR. This is achieved
by dividing down the recovered clock and using it as a
reference source for the transmit CMU. This will
produce a transmit clock and data that are locked to the
timing recovered from the received data path. In this
mode, a narrow band loop filter setting is
recommended.
Diagnostic Loopback
The Si5600 supports diagnostic loopback which
establishes a loopback path from the serializer output to
the deserializer input. This provides a mechanism for
looping back data input via the low speed transmit
interface TXDIN to the low speed receive data interface
RXDOUT. This mode is enabled by forcing DLBK
low.
Line Loopback
The Si5600 supports line loopback which establishes a
loopback path from the high speed receive input to the
high speed transmit output. This provides a mechanism
for looping back the high-speed clock and data
recovered from RXDIN to the transmit data output
TXDOUT and clock TXCLKOUT. This mode is enabled
by forcing LLBK
low.
Bias Generation Circuitry
The Si5600 makes use of two external resistors,
RXREXT and TXREXT, to set internal bias currents for
the receive and transmit sections of the Si5600. The
external resistors allows precise generation of bias
currents that significantly reduce power consumption.
The bias generation circuitry requires 3.09 k
resistors connected between RXREXT/TXREXT and
GND.
Ω (1%)
reference clock submultiples of the data rate.
The Si5600 supports operation with two selectable
reference clock sources. The first configuration uses an
externally provided reference clock that is input via
REFCLK. The second configuration uses the parallel
data clock, TXCLK16IN, as the reference clock source.
When using TXCLK16IN as the reference source, the
narrowband loop filter setting in the CMU may be
preferable to remove jitter that may be present on the
data clock. The selection of reference clock source is
controlled via the REFSEL input.
The CMU in the Si5600’s transmit section multiplies up
the provided reference to the serial transmit data rate.
When the CMU has achieved lock with the selected
reference, the TXLOL
CDR in the receive section of the Si5600 uses a
reference clock to center the PLL frequency so that it is
close enough to the data frequency to achieve lock with
the incoming data. When the CDR has locked to the
data, RXLOL
is driven high.
output will be driven high.The
Reset
The Si5600 is reset by holding the RESET pin low for at
least 1
pointers reset and the digital control circuitry initializes.
When RESET transitions high to start normal oper ation ,
the CMU will be calibrated.
µs. When RESET is asserted low, the input FIFO
Voltage Reference Output
The Si5530 provides an output voltage reference that
can be used by an external circuit to set the LOS
threshold, slicing level, or sampling phase adjust. One
possible implementation would use a resistor divider to
set the control voltage for LOSLVL, SLICELVL, or
PHASEADJ. A second alternative would use a DAC to
set the control voltage. Using this approach, VREF
would be used to establish the range of a DAC output.
The reference voltage is nominally 1.25 V.
Reference Clock
The Si5600 is designed to operate with reference clock
sources that are either 1/16th or 1/64th the desired
transceiver data rate. The device will support operation
with data rates between 9.9 Gbps and 10.7 Gbps and
the reference clock should be scaled accordingly. For
example, to support 10.66 Gbps operation the reference
clock source would be approximately 167 MHz or
666 MHz. The REFRATE input pin is used to configure
the device for operation with one of the two supported
Preliminary Rev. 0.31 15
Si5600
Transmit Differential Output Circuitry
The Si5600 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on
TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 5. In ap plic ation s
where direct dc coupling is possible, the 25 0 nF capacitors may be omitted. The differential peak-to-peak voltage
swing of the CML architecture is listed in Table 2 on page 5.
50 Ω
1.5 V
50 Ω
24 mA
250 nF
250 nF
Zo = 50 Ω
Zo = 50 Ω
VDD
50 Ω
50 Ω
VDD
Figure 5. CML Output Driver Termination (TXCLKOUT, TXDOUT)
16 Preliminary Rev. 0.31
Si5600 Pinout: 195 BGA
11 23456781014 13 12 19
Si5600
RXDOUT
[10]+
RXDOUT
[10]–
RXDOUT
[12]+
RXDOUT
[12]–
RXDOUT
[14]+
RXDOUT
[14]–
REF
CLK+
REF
CLK–
TXDIN
[14]+
TXDIN
[14]–
RXDOUT
[8]–
RXDOUT
[9]–
RXDOUT
[11]+
RXDOUT
[11]–
RXDOUT
[13]+
RXDOUT
[13]–
RXDOUT
[15]+
RXDOUT
[15]–
TXDIN
[15]+
TXDIN
[15]–
[4]–
[5]–
RXDOUT
RXDOUT
RXDOUT
RXDOUT
RXDOUT
[8]+
RXDOUT
[9]+
RXCLK2
DIV
RXMSB
SEL
RSVD_
GND
DLBK VDDGND VDD VDD VDD VDD VDD
RSVD_
VDD33
LLBK
LPTM VDDGND VDD VDD VDD VDD
TXCLK
DSBL
RXDOUT
[6]–
RXDOUT
[7]–
RXREXT NC VREF SLICELVL
RXDOUT
[6]+
RXDOUT
[7]+
VDDGND VDD VDD VDD VDD VDD
VDDGND VDD VDD VDD VDD VDD
VDDGND VDD VDD VDD VDD VDD
VDDGND VDD VDD VDD
[4]+
[5]+
RXCLK2
DSBL
RXDOUT
[2]–
RXDOUT
[3]–
RSVD_
GND
RXDOUT
[2]+
RXDOUT
[3]+
RSVD_
GND
VDD
RXDOUT
RXDOUT
[0]–
[1]–
VDD
VDD
RXDOUT
[0]+RXCLK[1]–RXCLK[1]+
RXDOUT
[1]+RXCLK[2]–RXCLK[2]+
LOSLVLRXSQLCH
GND
GND
RSVD_
GND
LTR
RXLOL
LOS
VDD33
GNDGND
FIFOERR
PHASEADJ RXDIN+GND GNDGND GNDGNDGNDGND
RSVD_
VDD33
RSVD_
RESET
REFRATE
RSVD_
GND
GND
GND
GND
GND
GND
GND
GNDGND
RXDIN–
GND
TXCLKOUT+
TXCLKOUT–
GNDGND
TXDOUT+
A
B
C
D
E
F
G
H
J
K
TXDIN
[12]+
TXDIN
[12]–
TXDIN
[11]+
TXDIN
[10]+
TXDIN
REFSEL GND GNDGNDGND
[13]+
TXDIN
TXSQLCH
[13]–
TXDIN
TXDIN
[11]–
[10]–
TXDIN
[9]+
TXDIN
[8+]
GNDGND GND
GND
[9]–
[8]–
RSVD_
GND
TXDIN
[7]+
TXDIN
[6]+
TXMSB
SEL
TXDIN
[7]–
TXDIN
[6]–
RSVD_
GND
TXDIN
[5]+
TXDIN
[4]+
BWSEL TXLOL
FIFORST
TXDIN
TXDIN
[5]–
[4]–
TXDIN
[3]+
TXDIN
[2]+
TXDIN
[3]–
TXDIN
[2]–
TXDIN
[1]+
TXDIN
[0]+
RSVD_
TXDIN
TXDIN
Bottom View
Figure 6. Si5600 Pin Configuration (Bottom View)
Preliminary Rev. 0.31 17
TXREXTNC
GNDGND
TXDIN
[1]–
TXDIN
[0]–
GND
GND
TXCLK16
IN+
TXCLK16
OUT+
TXDOUT–
GND
TXCLK16
IN–
TXCLK16
OUT–
L
M
N
P
Si5600
112345678 10 14131219
[2]+
[3]+
RSVD_
GND
RXDOUT
RXDOUT
[0]+
[1]+
PHASE
ADJ
RSVD_
VDD33
RSVD_
GND
RSVD_
GND
RXDOUT
RXDOUT
RXDOUT
A
B
C
D
E
F
GND
GND GND
RXDIN+ GNDGND GNDGND GND GND GND
RXDIN– GND LTR
GND GND RXLOL
RX
CLK1+
RX
CLK[2]+
GND
G
H
J
K
GND GND GND GND VDD VDDVDDVDDVDD
TXDOUT+ FIFOERRGND
GND REFRATEVDD33TXCLKOUT– VDDVDDVDDVDDVDDVDD
RX
CLK1-
RXDOUT
RX
CLK[2]–
LOSLVL RXSQLCH
RSVD_
GND
LOSGNDTXCLKOUT+ RESET
RXDOUT
[0]–
RXDOUT
[1]–
VDD VDD VDD
[2]–
[3]–
RSVD_
GND
RXDOUT
[4]+
RXDOUT
[5]+
RXCLK2
DSBL
RXDOUT
[4]–
RXDOUT
[5]–
RXDOUT
[6]+
RXDOUT
[7]+
VDD GNDVDDVDDVDDVDDVDD
VDD GNDVDDVDDVDDVDDVDD
VDD GNDVDDVDDVDDVDDVDD
VDD GNDVDDVDD
RXDOUT
[6]–
RXDOUT
[7]–
RXREXTNCVREFSLICELVL
GND
RXDOUT
[8]+
RXDOUT
[9]+
RXCLK2
DIV
RXMSB
SEL
RSVD_
GND
DLBK
RSVD_
VDD33
LLBK
LPTMVDD GND
TXCLK
DSBL
RXDOUT
[8]–
RXDOUT
[9]–
RXDOUT
[11]+
RXDOUT
[11]–
RXDOUT
[13]+
RXDOUT
[13]–
RXDOUT
[15]+
RXDOUT
[15]–
TXDIN
[15]+
TXDIN
[15]–
RXDOUT
[10]+
RXDOUT
[10]–
RXDOUT
[12]+
RXDOUT
[12]–
RXDOUT
[14]+
RXDOUT
[14]–
REF
CLK+
REF
CLK–
TXDIN
[14]+
TXDIN
[14]–
[13]+
[13]–
[11]–
[10]–
TXDIN
[12]+
TXDIN
[12]–
TXDIN
[11]+
TXDIN
[10]+
[9]+
[8]+
TXDIN
TXDIN
TXDIN
TXDIN
L
TXDOUT–
M
N
P
GND GND GND
TXCLK16
TXCLK16
IN–
TXCLK16
TXCLK16
OUT–
TXREXT NC GND GNDGND
GND
GND
IN+
OUT+
TXDIN
TXDIN
[1]–
[0]–
TXDIN
[1]+
TXDIN
[0]+
TXDIN
[3]–
TXDIN
[2]–
FIFORST
TXDIN
[3]+
TXDIN
[2]+
BWSELTXLOL
TXDIN
[5]–
TXDIN
[4]–
RSVD_
GND
TXDIN
[5]+
TXDIN
[4]+
TXMSB
SEL
TXDIN
[7]–
TXDIN
[6]–
RSVD_
GND
TXDIN
[7]+
TXDIN
[6]+
RSVD_
GND
TXDIN
[9]–
TXDIN
[8]–
REFSELGNDGND GND GND
TXSQLCH
TXDIN
TXDIN
Top View
Figure 7. Si5600 Pin Configuration (Transparent Top View)
18 Preliminary Rev. 0.31
Pin Descriptions: Si5600
Pin Number(s) Name I/O Signal Level Description
Si5600
M7 BWSEL I LVTTL
F12 DLBK
K3 FIFOERR O LVTTL
M6 FIFORST I LVTTL
B1, C1–2, D5–
1 1, D2, E1 1, E2,
F11, F1–2, G1 1,
G2, H11, H2,
J11, J1–4, K2,
K1 1, L5–11, L2,
M1–4
GND GND
I LVTTL
Bandwidth Select DSPLL.
This input selects loop bandwidth of the DSPLL.
BWSEL = 0: Loop bandwidth set to 12 kHz.
BWSEL = 1: Loop bandwidth set to 50 kHz.
Diagnostic Loopback.
When this input is active low the transmit clock
and data are looped back for output on RXDOUT ,
RXCLK1 and RXCLK2. This pin should be held
high for normal operation.
FIFO Error.
This output is driven high when a FIFO overflow/
underflow has occurred. This output will stick
high until reset by asserting FIFORST.
FIFO RESET.
This input when asserted high resets the read/
write FIFO pointers to their initial state.
Supply Ground.
H12 LLBK I LVTTL
G3 LOS
C3 LOSLVL I
O LVTTL
Preliminary Rev. 0.31 19
Line Loopback.
When this input is active low the recovered clock
and data are looped back for output on TXDOUT ,
and TXCLKOUT. This pin should be held high for
normal operation.
Loss-of-Signal.
This output is driven low when the peak-to-peak
signal amplitude is below threshold set via
LOSLVL.
LOS Threshold Level.
Applying an analog voltage to this pin allows
adjustment of the threshold used to declare LOS.
Tieing this input high disables LOS detectio n and
forces the LOS
output high.
Si5600
Pin Number(s) Name I/O Signal Level Description
J12 LPTM I LVTTL
E3 LTR
C10, L4 NC
D4 PHASEADJ I
G14, H14 REFCLK+,
REFCLK–
I LVTTL
I LVPECL
Loop Timed Operation.
When this input is forced high, the recovered
clock from the receiver is divided down and used
as the reference source for the transmit CMU.
The narrowband setting for the DSPLL CMU will
be sufficient to provide SONET compliant jitter
generation and transfer on the transmit data and
clock outputs (TXDOUT,TXCLKOUT). This pin
should be held low for normal operation.
Lock-to-Reference
This input forces a stable output clock by locking
RXCLK1 and RXCLK2 to the provided reference.
Driving LTR
No Connect.
Reserved for device testing leave electrically
unconnected.
Sampling Phase Adjust.
Applying an analog voltage to this pin allows
adjustment of the sampling phase acro ss the
data eye. Ti eing this in put h igh nomina lly ce nters
the sampling phase.
Differential Reference Clock.
The reference clock sets the operating frequency
of the PLL used to generate the high speed transmit clock. In addition, REFCLK sets the initial
operating frequency used by the onboard PLL for
clock and data recovery. The Si5600 will operate
with reference clock frequencies that are either
1/16th or 1/64th the serial data rate (nominally
155 MHz or 622 MHz).
low activates this feature.
H4 REFRATE I LVTTL
L12 REFSEL I LVTTL
20 Preliminary Rev. 0.31
Reference Clock Select.
This input configures the Si5600 to operate with
one of two reference clock frequencies. If
REFRATE is held high, the device requires a reference clock that is 1/16 the serial data rate. If
REFRATE is low, a reference clock at 1/64 the
serial data rate is required.
Reference Clock Selection.
This inputs selects the reference clock source
used by the CMU. When REFSEL = 0, the low
speed data input clock, TXCLK16IN, is used as
the CMU reference. When REFSEL = 1, the reference clock provided on REFCLK is used.
Pin Number(s) Name I/O Signal Level Description
Si5600
G4 RESET I LVTTL
C6–7, D3, E12,
F4, K4, M10–11,
M8
E4, G12 RSVD_VDD33
A2–3 RXCLK1+,
B2–3 RXCLK2+,
C12 RXCLK2DIV I LVTTL
C8 RXCLK2DSBL I LVTTL
D1, E1 RXDIN+,
A4–14, B4–14,
C13–14, D13–
14, E13–14,
F13–14, G13,
H13
RSVD_GND
RXCLK1–
RXCLK2–
RXDIN–
RXDOUT[15:0]+,
RXDOUT[15:0]–
OLVDS
OLVDS
I High Speed
OLVDS
Differential
Device Reset.
Forcing this input low for a at least 1 µs will cause
a device reset. For normal operation, this pin
should be held high.
Reserved Tie to Ground.
Must tie directly to GND for proper operation.
Reserved Tie to VDD33.
Must tie directly to VDD33 for proper operation.
Differential Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down by 16 and output on CLKOUT. In the absence of data, a stable clock on
RXCLK1 can be maintained by asserting LTR
Differential Clock Output 2.
An auxiliary output clock is provided on this pin
that may be a divided down version of the high
speed clock recovered from the signal present on
RXDIN. The divide factor used in generating
RXCLK2 is set via RXCLK2DIV.
Clock Divider Select.
This input selects the divide factor used to generate the RXCLK2 output. When this input is driven
low, RXCLK2 is 1/16th the recovered high speed
clock. When driven high, RXCLK2 is 1/64th the
recovered high speed clock rate.
RXCLK2 Disable.
Driving this input high will disable the RXCLK2
output. This would be used to save power in
applications that do not require an auxiliary clock.
Differential Data Input.
Clock and data are recovered from the high
speed data signal present on these pins.
Differential Parallel Data Output.
The data recovered from the signal present on
RXDIN is demultiplexed and output as a 16-bit
parallel word via RXDOUT[15:0]. These outputs
are updated on the rising edge of RXCLK1.
.
F3 RXLOL
O LVTTL
Preliminary Rev. 0.31 21
Loss-of-Lock.
This output is driven low when the recovered
clock frequency deviates from the reference
clock by the amount specified in Table 5.
Si5600
Pin Number(s) Name I/O Signal Level Description
D12 RXMSBSEL I LVTTL
C11 RXREXT
C9 RXSQLCH
C4 SLICELVL I
N1–2 TXCLK16IN+,
TXCLK16IN–
I LVTTL
ILVDS
Data Bus Receive Order.
This determines the order of the received data
bits on the output bus.
For RXMSBSEL = 0, the first data bit received is
output on RXDOUT[0] and following data bits are
output on RDOUT[1] through RXDOUT[15].
For RXMSBSEL = 1, the first data bit is output on
RXDOUT[15] and following data bits are output
on RXDOUT[14] through RXDOUT[0].
External Bias Resistor.
This resistor is used by the receiver circuitry to
establish bias currents within the device. This pin
must be connected to GND through a 3.09 k
(
1%) resistor.
Data Squelch.
When this input is low the data on RXDOUT is
forced to 0. Set high for normal operation.
Slicing Level Adjustment.
Applying an analog voltage to this pin allows
adjustment of the slicing level applied to the input
data eye. Tieing this input hig h nominally sets the
slicing offset to 0.
Differential Data Clock Input.
The rising edge of this input clocks data present
on TXDIN into the device.
Ω
P1–2 TXCLK16OUT+,
TXCLK16OUT–
K12 TXCLKDSBL I LVTTL
G1, H1 TXCLKOUT+,
TXCLKOUT–
OLVDS
OCML
Divided Down Output Clock.
This clock output is generated by dividing down
the high speed output clock, TXCLKOUT, by a
factor of 16. It is intended for use in counter
clocking schemes that transfer data between the
system ASIC and the Si5600.
High Speed Clock Disable
When this input is high, the output driver for
TXCLKOUT is disabled. In applications that do
not require the output data clock, the output clock
driver should be disabled to save power.
High Speed Clock Output.
The high speed output clock, TXCLKOUT, is generated by the PLL in the clock multiplier unit. Its
frequency is nominally 16 or 64 times the
selected reference source.
22 Preliminary Rev. 0.31
Pin Number(s) Name I/O Signal Level Description
Si5600
J13–14, K13–
14, L13–14,
M13–14, N3–
14, P3–14
K1, L1 TXDOUT+,
M5 TXLOL
M9 TXMSBSEL I LVTTL
L3 TXREXT
M12 TXSQLCH
E5–10, F5–10,
G5–10, H5–10,
J5–10, K5–10
TXDIN[15:0]+,
TXDIN[15:0]–
TXDOUT–
VDD VDD 1.8 V
ILVDS
OCML
O LVTTL
I LVTTL
Differential Parallel Data Input.
The 16-bit data word present on these pins is
multiplexed into a high speed serial stream and
output on TXDOUT. The data on these inputs is
clocked into the device by the rising edge of
TXCLK16IN.
Differential High Speed Data Output.
The 16-bit word input on TXDIN[15:0] is multiplexed into a high speed serial stream that is output on these pins. Input data is multiplexed in
sequence from TXDIN0 to TXDIN15 with TXDIN0
transmitted first. This output is updated by the rising edge of TXCLKOUT.
CMU Loss-of-Lock.
The output is asserted low when the CMU is not
phase locked to the selected reference source .
Data Bus Transmit Order.
For TXMSBSEL = 0, data on TXDIN[0] is transmitted first followed by TXDIN[1] through
TXDIN[15].
For TXMSBSEL = 1, TXDIN[15] is transmitted
first followed by TXDIN[14] through TXDIN[0].
External Bias Resistor.
This resistor is used by the transmitter circuitry to
establish bias currents within the device. This pin
must be connected to GND through a 3.09 k
(
1%) resistor.
Transmit Data Squelch.
If TXSQLCH is asserted low, the output data
stream on TXDOUT will be forced to 0s. If
TXSQLCH
Supply Voltage.
Nominally 1.8 V.
= 1, TX squelching is turned off.
Ω
Preliminary Rev. 0.31 23
Si5600
Pin Number(s) Name I/O Signal Level Description
H3 VDD33 VDD33 1.8 V or 3.3 V
C5 VREF O Voltage Ref
Digital Output Supply.
Must be tied to either 1.8 V or 3.3 V. When tied to
3.3 V, LVTTL compatible output voltage swings
on RXLOL
ported.
Voltage Reference.
The Si5600 provides an output voltage reference
that can be used by an external circuit to set the
LOS threshold, slicing level, or sampling phase
adjustment. The equivalent resistance between
this pin and GND should not be less than 10 k
The reference voltage is nominally 1.25 V.
and LOS, TXLOL, FIFOERR are sup-
Ω.
24 Preliminary Rev. 0.31
Ordering Guide
Si5600
Table 9. Ordering Guide
Part Number Package Temperature
Si5600-BC 195 BGA –40°C to 85°C
Preliminary Rev. 0.31 25
Si5600
Package Outline
Figure 8 illustrates the package details for the Si5600. Table 10 lists the values for the dimensions shown in the
illustration.
P
N
M
L
K
J
H
G
F
E
D
C
B
A
12345678910111213
14
Figure 8. 195-Ball Grid Array (BGA)
Table 10. Package Diagram Dimensions (mm)
Symbol Min Nom Max
A 3.503.653.80
A1 0.65 0.70 0.75
A2 1.35 1.45 1.55
b 0.650.700.75
D 14.90 15.00 15.10
D1 — 13.00 —
e — 1.00 —
L 12.95 13.00 13.05
S — 0.50 —
26 Preliminary Rev. 0.31
NOTES:
Si5600
Preliminary Rev. 0.31 27
Si5600
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: productinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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28 Preliminary Rev. 0.31
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