Silicon Laboratories Si3024-KT, Si5600-BC Datasheet

Si5600

PRELIMINARY DATA SHEET

SiPHY™ OC-192/STM-64 SONET/SDH TRANSCEIVER

Features

Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX

! Data Rates Supported: OC-192/

STM-64, 10GbE, and 10.7 Gbps FEC

! Low Power Operation 1.2 W (typ)
! DSPLL™ Based Clock Multiplier Unit

w/ Selectable Loop Filter Bandwidths

! Integrated Limiting Amplifier
! Loss-of-Signal (LOS) Alarm
! Diagnostic and Line Loopbacks

! SONET Compliant Loop Timed

Operation

! Programmable Slicing Level and

Sample Phase Adjustment

! SFI-4 Compliant Low Speed

Interface

! Single Supply 1.8 V Operation
! 15 x 15 mm BGA Package

Si5600

Bottom View

Applications

! Sonet/SDH Transmission

Systems

! Optical Transceiver Modules
! Sonet/SDH Test Equipment

Description

The Si5600 is a complete low-power transceiver for high-speed serial
communication systems operating between 9.9 Gbps and 10.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’

™

DSPLL

technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing, and sample phase
adjustment are supported.

The Si5600 operates from a single 1.8 V supply over the industrial temperature
range (–40°C to 85°C).

Functional Block Diagram

LOS

LOSLVL

RXDIN

REFSEL

REFCLK

LPTM

REFRATE

TXLOL

BWSEL

TXCLKDSBL

TXCLKOUT

TXSQLCH

TXDOU T

RESET

SLICELVL

2

Limiting

AMP

2

TXCLK16IN

2

2

PHASEADJ

RESET

Control

LTR

CDR

DSPLL

TX CM U

RXLOL

TM

Loopback Control

DLBKLLBK

RXSQLCH

1:16

÷

÷

16:1

TXMSBSEL

DEMUX

MUX

32

2

2

32

FIFO

FIFOERR

RXMSBSEL

RXDOUT[15:0]

RXCLK1
RXCLK2
RXCLK2DIV

RXCLK2DSBL

2

2

TXCLK16IN
TXDIN[15:0]

FIFORST

TXCLK16OUT

Ordering Information:

See page 25.

Preliminary Rev. 0.31 8/01 Copyright © 2001 by Silicon Laboratories Si5600-DS031

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si5600

2 Preliminary Rev. 0.31

Si5600

TABLE OF CONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Si5600 Pinout: 195-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pin Descriptions: Si5600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Preliminary Rev. 0.31 3

Si5600

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition

Ambient Temperature T
LVTTL Output Supply Voltage V
Si5600 Supply Voltage V

*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.

A

DD33

DD

*

Min

Typ

–40 25 85 °C

1.71 — 3.47 V

1.71 1.8 1.89 V

Max

*

Unit

V

SIGNAL +

Differential
I/Os

V

ICM

SIGNAL –

, V

OCM

V

IS

Single Ended Voltage

(SIGNAL +) – (SIGNAL –)

Differential
Voltage Swing

VID,VOD (V

= 2VIS)

ID

Differential Peak-to-Peak Voltage

t

Figure 1. Differential Voltage Measurement

(RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK16OUT, TXCLK16IN)

TXDOUT,

TXDIN

TXCLKOUT,

TXCLK16IN

RXDOUT

RXCLK1

t

cq2

t

hd

t

su

t

cq1

Figure 2. Data to Clock Delay

t

t

CH

CP

4 Preliminary Rev. 0.31

Si5600

All Differential
IOs

t

F

t

R

80%
20%

Figure 3. Rise/Fall Time Measurement

Table 2. DC Characteristics

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Supply Current I
Power Dissipation P
Voltage Reference (VREF) V

Common Mode Input Voltage (RXDIN) V
Differential Input Voltage Swing (RXDIN) V

Common Mode Output Voltage

V

(TXDOUT, TXCLKOUT)
Differential Output Voltage Swing

V

(TXDOUT, TXCLKOUT), Differential pk-pk
LVPECL Input Voltage HIGH (REFCLK) V
LVPECL Input Voltage LOW (REFCLK) V
LVPECL Input Voltage Swing,

Differential pk-pk (REFCLK)
LVPECL Internally Generated Input Bias

(REFCLK)
LVDS Input High Voltage

(TXDIN, TXCLK16IN)
LVDS Input Low Voltage

(TXDIN, TXCLK16IN)
LVDS Input Voltage, Single Ended pk-pk

V

(TXDIN, TXCLK16IN)
LVDS Output High Voltage

V

(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)

LVDS Output Low Voltage

V
(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT)

LVDS Output Voltage, Differential pk-pk

V
(RXDOUT, RXCLK1, RXCLK2,

TXCLK16OUT)

DD

D

REF

ICM

ID

OCM

OD

IH

IL

V

ID

V

IB

V

IH

V

IL

ISE

OH1

OL1

OSE

VREF driving

Ω load

10 k

See Figure 1 20 — 1.0 mV

See Figure 1 800 1000 1200 mV

Figure 1 250 — 2400 mV

100 Ω Load

Line-to-Line

100 Ω Load

Line-to-Line

100 Ω Load

Line-to-Line,

Figure 1

—611TBDmA
—1.2TBDW

1.21 1.25 1.29 V

TBD 0.1 TBD V

(pk-pk)

.8 0.9 1.0 V

(pk-pk)

1.975 2.3 2.59 V

1.32 1.6 1.99 V

(pk-pk)

1.6 1.95 2.3 V

——2.4V

0.0 — — V

100 — 600 mV

(pk-pk)

TBD — 1.475 mV

0.925 — TBD V

500 — 800 mV

(pk-pk)

Preliminary Rev. 0.31 5

Si5600

Table 2. DC Characteristics (Continued)

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

LVDS Common Mode Voltage
(RXDOUT, RXCLK1, RXCLK2,

TXCLK16OUT)
Input Impedance (TXDIN, TXCLK16IN,

REFCLK, RXDIN)
Output Short to GND

(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT, TXDOUT, TXCLKOUT)

Output Short to V

DD

(RXDOUT, RXCLK1, RXCLK2,
TXCLK16OUT, TXDOUT, TXCLKOUT)

LVTTL Input Voltage Low
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK

, REFSEL, LTR, RESET,

,

, LLBK, LPTM)

LVTTL Input Voltage High
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,

RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK

, REFSEL, LTR, RESET,

,

, LLBK, LPTM)

LVTTL Input Low Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,

RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK

, REFSEL, LTR, RESET,

,

, LLBK, LPTM)

LVTTL Input High Current
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,
RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK

, REFSEL, LTR, RESET,

,

, LLBK, LPTM)

LVTTL Input Impedance
(RXMSBSEL, RXCLK2DIV, RXCLK2DSBL,

RXSQLCH
TXCLKDSBL, FIFORST, TXSQLCH
BWSEL, TXMSBSEL, DLBK

, REFSEL, LTR, RESET,

,

, LLBK, LPTM)

LVTTL Output Voltage Low
(LOS

, RXLOL, FIFOERR, TXLOL)

LVTTL Output Voltage High
(LOS

, RXLOL, FIFOERR, TXLOL)

V

CM

R

IN

I

SC(–)

I

SC(+)

V

IL2

V

IH2

I

IL

I

IH

R

IN

V

OL2

V

OH2

1.125 — 1.275 V

Each input to

42 50 58 Ω

common mode

—25TBDmA

TBD –100 — µA

VDD33 = 3.3 V — — 0.8 V
VDD33 = 1.8 V — — 0.7

VDD33 = 3.3 V 2.0 — — V
VDD33 = 1.8 V 1.7

——10µA

——10µA

10 — — kΩ

VDD33 = 1.8 V — — 0.4 V
VDD33 = 3.3 V — — 0.4
VDD33 = 1.8 V 1.4 — — V
VDD33 = 3.3 V 2.4 — —

6 Preliminary Rev. 0.31

Si5600

Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)

(VDD = 1.8 V ±5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Output Clock Frequency

f

clkout

—622667MHz

(RXCLK1)
Duty Cycle (RXCLK1, RXCLK2) tch/tcp, Figure 2 45 — 55 %

Output Rise and Fall Times

t

R,tF

Figure 3 — 50 — ps

(RXCLK1, RXCLK2,RXDOUT)
Data Invalid Prior to RXCLK1 t

Data Invalid After RXCLK1 t

cq1

cq2

Input Return Loss (RXIN) 400 kHz–10.0 GHz

Figure 2 — — 200 ps
Figure 2 — — 200 ps

10.0 GHz–16.0 GHz

18.7
TBD

—
—

—
—

dB
dB

Slicing Adjust Dynamic Range SLICELVL = 200–800 mV –20 — 20 mV
Slicing Level Offset

1

SLICELVL = 200–800 mV –500 — 500

µV

(referred to RXDIN)
Slicing Level Accuracy VSLICE –5 — 5 %
Sampling Phase Adjustment

2

PHASEADJ = 200–800 mV –45° —45

o

LOS Threshold Dynamic Range LOSLVL = 200–800 mV 10 — 50 mV

pk-pk

LOS Threshold Offset

3

LOSLVL = 200–800 mV –500 — 500

µV

(referred to RXDIN)
LOS Threshold Accuracy VLOS –5 — 5 %

Note:

1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL – 0.4"VREF)/15.

2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 45° (PHASEADJ – 0.4

3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL – 0.4"VREF)/15.

"

VREF)/0.3

Preliminary Rev. 0.31 7

Si5600

Table 4. AC Characteristics (TXCLK16OUT, TXCLK16IN, TXCLKOUT, TXDIN, TXDOUT)

(V

1.8 V ± 5%, TA = –40°C to 85°C)

DD =

Parameter Symbol Test Condition Min Typ Max Unit

TXCLKOUT Frequency f

clkout

—9.9510.7GHz
TXCLKOUT Duty Cycle tch/tcp, Figure 2 45 — 55 %
Output Rise Time

t

R

Figure 3 — 25 — ps

(TXCLKOUT, TXDOUT)
Output Fall Time

t

F

Figure 3 — 25 — ps

(TXCLKOUT, TXDOUT)
TXCLKOUT Setup to TXDOUT t

TXCLKOUT Hold From TXDOUT t

su
hd

Output Return Loss 400 kHz–10 GHz

TXCLK16OUT Frequency f

CLKIN

Figure 2 25 — — ps
Figure 2 25 — — ps

10 GHz–16 GHz

TBD
TBD

—
—

—
—

—622667MHz

dB
dB

TXCLK16OUT Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16OUT Rise & Fall Times t
TXDIN Setup to TXCLK16IN t
TXDIN Hold from TXCLK16IN t
TXCLK16IN Frequency f

R,tF

DSIN

DHIN

CLKIN

100 — 300 ps

——300ps

——300ps

—622667MHz
TXCLK16IN Duty Cycle tch/tcp, Figure 2 40 — 60 %
TXCLK16IN Rise & Fall Times t

R,tF

100 — 300 ps

8 Preliminary Rev. 0.31

Si5600

Table 5. AC Characteristics (Receiver PLL)

(VDD = 1.8 V ± 5%, TA = –40°C to 85°C)

Parameter Symbol Test Condition Min Typ Max Unit

Jitter Tolerance J

TOL(PP)

f = 2.4 kHz 15 30 — UIpp

f = 24 kHz 1.5 3.0 — UIpp

f = 400 kHz 1.5 3.0 — UIpp

f = 4 MHz 0.15 0.3 — UIpp
Acquisition Time T
Input Reference Clock Frequency RC

AQ

FREQ

REFRATE = 1 — 622 667 MHz

REFRATE = 0 — 155 167 MHz
Reference Clock Duty Cycle RC
Reference Clock Frequency

RC

DUTY

TOL

Tolerance
Frequency Difference at which

LOL TBD 600 1000 ppm
Receive PLL goes out of Lock
(REFCLK compared to the
divided down VCO clock)

Frequency Difference at which

LOCK TBD 300 TBD ppm
Receive PLL goes into Lock
(REFCLK compared to the
divided down VCO clock)

Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.

——20 µs

40 50 60 %

–100 — 100 ppm

Preliminary Rev. 0.31 9