Silicon Laboratories Si475X Series, Si475x-A40, Si475x-A30, Si475x-A55, Si475xC-A55 Programming Manual
...
AN543
Si475X PROGRAMMING GUIDE
1. Introduction
This document provides an overview of the programming requirements for the Si475x-A10/A20/A30/A40/A55 and
Si475xC-A55 AM/FM receiver. The hardware control interface and software commands are detailed along with
several examples of the required steps to configure the device for various modes of operation. Table 1 provides a
programming guide cross-reference for each Si475x part released by Silicon Labs to date. This programming guide
focuses on the Si475x/5xC-A55 release; however, features, properties, ranges, and defaults that differ from the
Si475x-A10 to Si475x-A40 are noted as well. Refer to previous versions of this document for earlier firmware
revisions.
Table 1. Si475x Firmware Revisions
Part # Part Revision FMRX Component AMRX Component
Si475x-A10 1.0 3.2.3 3.2.3
Si475x-A20 2.0 8.0.8 7.0.5
Si475x-A30 3.0 10.0.8 9.0.6
Si475x-A40 4.0 13.0.11 12.0.10
Si475x-A55 5.5 15.0.2 14.0.1
Si475xC-A55 5.5 15.0.2 14.0.1
2. Overview
This devices in this product family are programmed using commands and responses. To perform an action, the
system controller writes a command byte and associated arguments, which cause the device to execute the given
command. The device will, in turn, provide a response depending on the type of command that was sent.
The device has a slave control interface that allows the system controller to send commands to and receive
responses from the device using 2-wire mode (I
2
C compatible).
3. Terminology
CTS—Clear to send
STC—Seek/Tune Complete
NVM—Non-volatile internal device memory
Device—Refers to the AM/FM Receiver
System Controlle r —Refers to the system microcontroller
CMD—Command byte
ARGn—Argument byte (n = 1 to 7)
STATUS—Status byte
RESPn—Response byte (n = 1 to 15)
Rev. 0.9 10/16 Copyright © 2016 by Silicon Laboratories AN543
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
AN543
SCL
70%
30%
SDA
70%
30%
START
STARTSTOP
t
f:IN
t
r:IN
t
LOW
t
HIGH
t
HD:STA
t
SU:STA
t
SU:STO
t
SP
t
BUF
t
SU:DAT
t
r:IN
t
HD:DAT
t
f:IN,
t
f:OUT
t
PD:DAT
SCL
SDA
(Write)
START STOPADDRESS + R/W ACK DATA ACK DATA ACK
A6-A0, 0
Command
7-0
Arg1
7-0
SDA
(Read)
START STOPADDRESS + R/W ACK DATA ACK DATA ACK
A6-A0, 1
Status
7-0
Response
7-0
4. Control Interface
The Si475x provides an I2C-compatible, 2-wire control interface.
In powerdown mode, all circuitry is disabled except for the device control interface. The device comes out of
powerdown mode when the POWER_UP command is written to the command register. Once in powerup mode,
the device accepts additional commands such as tuning. The device will not accept commands while in
powerdown mode, with the exception of the powerup command. If the system controller writes a command other
than POWER_UP when in powerdown mode, the device does not respond, and the command is ignored.
Setting the RSTB pin low places the device in reset mode. In reset mode, all circuitry is disabled including the
device control interface; registers are set to their default settings, and the control bus is disabled.
4.1. 2-Wire Control Interface
Figure 1 and Figure 2 show the 2-wire control interface read and write timing parameters and diagrams,
respectively. Refer to the Si475x data sheet for timing parameter values.
Figure 1. I2C Control Interface Read and Write Timing Parameters
2 Rev. 0.9
Figure 2. I
2
C Control Interface Read and Write Timing Diagram
AN543
Two-wire bus mode uses the SCL and SDA pins for signaling. A transaction begins with the START condition,
which occurs when SDA falls while SCL is high. Next, the system controller drives an 8-bit control word serially on
SDA, which is captured by the device on rising edges of SCL. The control word consists of a seven-bit device
address followed by a read/write bit (read = 1, write = 0). The device acknowledges the control word by driving
SDA low on the next falling edge of SCL.
For write operations, the system controller next sends a data byte on SDA, which is captured by the device on
rising edges of SCL. The device acknowledges each data byte by driving SDA low for one cycle on the next falling
edge of SCL. For each write transaction, the first byte is a command and the following bytes are arguments.
For read operations, after the device has acknowledged the control byte, it will drive an eight-bit data byte on SDA,
changing the state of SDA on the falling edges of SCL. The system controller acknowledges each data byte by
driving SDA low for one cycle on the next falling edge of SCL. If a data byte is not acknowledged by the system
controller, the transaction will end. For each read transaction, the first byte is the status byte and the following bytes
are the response data from the receiver.
A 2-wire transaction ends with the STOP condition, which occurs when SDA rises while SCL is high.
5. Powerup and Powerdown
There are two procedures for powering up a receiver to move it from powerdown mode to the powerup mode. The
first is a powerup from internal receiver memory. The second is a powerup from a firmware component patch that is
stored in system controller memory. Patches can be applied to a firmware component by the system controller via
a download mechanism to address field issues, errata, or adjust device behavior. Patches are encrypted and
unique to a particular device firmware version, cannot be generated by customers, and can be used to replace a
portion of the component (to address errata, for example) or to download an entirely new component. The user
must verify that the device contains the correct base firmware to support the patch as described later in this
section.
It has been noted that some crystals require greater startup current and settling times than others. The procedure
below is meant to apply to a wide variety of such crystals, providing maximum current and 40 ms for crystal
oscillation to stabilize. If there are still difficulties with POWER-UP that may be related to your choice of crystal,
please refer to the settings and hardware options in “AN750: Si475x 4 MHz Crystal Compatibility Power-Up
Procedure”.
Rev. 0.9 3
AN543
Supply VA, VD, and VIO while
keeping the RSTB = 0
START
After a minimum of 100 µs,
set RSTB = 1
After a minimum of 100 µs,
continue to the next step
Send second POWER_UP
command for the desired
function (AM, FM)
Commence normal operation
Send POWER_DOWN
command
Send the POWER_UP
command for desired function
(AM, FM)
Wait at least 100 ms
Send command
to force CTS = 1
5.1. Powerup Receiver from Internal Memory
1. Supply VA, VD, and VIO while keeping the RSTB = 0. Power supplies may be sequenced in any order.
2. After a minimum of 100 µs, set RSTB = 1.
3. After a minimum of 100 µs, continue to the next step.
4. Send the POWER_UP command for the desired function (AM, FM).
4 Rev. 0.9
Example (with crystal 4 MHz, FM function):
1. Provide the initial POWER_UP Command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
Note: Change this value to the capacitance that matches the crystal in use.
ARG3 0x27 SETS CRYSTAL BIAS = 7 w/ FASTBOOT
AN543
ARG4 0x00
0x10
0x20
ARG5 0x00 DIGITAL CORE DISABLED/CRYSTAL OSCILLATOR DISABLED
STATUS NO CTS bit returned
2. Apply a wait time of at least 100 ms.
3. Apply the following command:
Action Data Description
CMD 0xFB CONTROL REGISTER WRITE COMMAND
ARG1 0X06 CONTROL REGISTER ADDRESS
ARG2 0x80 FORCES CTS = 1
STATUS NO CTS bit returned
4. Apply the following command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
ARG3 0x23 SETS CRYSTAL BIAS = 3 w/ FASTBOOT
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
Note: Change this value to the capacitance that matches the crystal in use.
ARG4 0x00
0x10
0x20
ARG5 0x11 DIGITAL CORE ENABLED/CRYSTAL OSCILLATOR ENABLED
STATUS CTS = 1
Note: For more details on the external circuit for the 4 MHz crystal, see “AN750: Si475x 4 MHz Crystal Circuit and Power-Up
Procedure”.
5. The device is ready to commence normal operation and accept additional commands. Refer to Figure 3.
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
Rev. 0.9 5
AN543
VIO
VD
VA
RSTB
SCL
SDA
POWER_UP Command
100 µs min
100 µs min
> 10 µs
Figure 3. Powerup Timing
6. If desired, send the POWER_DOWN command.
Example:
POWER_DOWN Command
Action Data Description
CMD 0x11 POWER_DOWN
ARG1 0x00 Disable oscillator (ARG1 may be omitted with the same result)
STATUS →0x80 CTS = 1
7. It is now possible to move to the powerup state by returning to step 4.
6 Rev. 0.9
5.2. Powerup Receiver from a Patch
Supply V A, V D, and VIO
while keeping the RSTB = 0
START
After a minimum of 100 µs,
set RSTB = 1
After a minimu m of 100 µs,
continue to the next step
Send the POWER_UP
command for the desired
function (AM, FM)
Send POWER_DOWN
command
A
B
Verify Firmw are and R OM
revision?
A
B
Send PART_INFO command
Wait at least 100 ms
Send second POWER_UP
command for the desired
function (AM, FM)
C
Send the POWER_UP
command with boot loader
function
Send patch data.
Send the POWER_UP
command for the desired
function (A M, FM )
Commence normal operation.
Send POWER_DOWN
command.
Wait at least 100 ms
Send second POWER_UP
command with bootloader
function
B
C
Send comm and to force
CTS = 1
Send command to force
CTS = 1
AN543
1. Supply VA, VD, and VI0 while keeping the RSTB = 0. Power supplies may be sequenced in any order.
2. After a minimum of 100 µs, set RSTB = 1.
3. After a minimum of 100 µs, proceed to the next step.
4. (Optional – step 1 of 3 to verify part firmware revision and ROM revision.) Both part firmware revision and ROM
revision must be compatible with a partial patch and ROM revision must be compatible with a full patch. Send
the POWER_UP command for the desired function (AM, FM).
Rev. 0.9 7
AN543
Example (with crystal 4 MHz, FM function):
1. Provide the initial POWER_UP Command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
Note: Change this value to the capacitance that matches the crystal in use.
ARG3 0x27 SETS CRYSTAL BIAS = 7 w/ FASTBOOT
ARG4 0x00
0x10
0x20
ARG5 0x00 DIGITAL CORE DISABLED/CRYSTAL OSCILLATOR DISABLED
STATUS NO CTS bit returned
2. Apply a wait time of at least 100 ms.
3. Apply the following command:
Action Data Description
CMD 0xFB CONTROL REGISTER WRITE COMMAND
ARG1 0X06 CONTROL REGISTER ADDRESS
ARG2 0x80 FORCES CTS = 1
STATUS NO CTS bit returned
4. Apply the following command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
ARG3 0x23 SETS CRYSTAL BIAS = 3 w/ FASTBOOT
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
Note: Change this value to the capacitance that matches the crystal in use.
ARG4 0x00
0x10
0x20
ARG5 0x11 DIGITAL CORE ENABLED/CRYSTAL OSCILLATOR ENABLED
STATUS CTS = 1
Note: For more details on the external circuit for the 4 MHz crystal, see “AN750: Si475x 4 MHz Crystal Circuit and Power-Up
Procedure”.
5. (Optional – step 2 of 3 to verify part firmware revision and ROM revision). Verify part firmware revision and
ROM revision. Send the PART_INFO command.
8 Rev. 0.9
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
AN543
Example:
PART_INFO Command
Action Data Description
CMD 0x02 PART_INFO
STATUS →0x80 CTS = 1
RESP1 →0x06 Chip revision, 6
RESP2 →0x35 Part number (last two digits) 0x35 = 53, or Si4753
RESP3 →0x32 Firmware major revision = ASCII character “2”
RESP4 →0x30 Firmware minor revision = ASCII character “0”
RESP5 →0x00 Firmware build version = 0
RESP6 →0x00 Reserved, values will vary
RESP7 →0x00 Reserved, values will vary
RESP8 →0x04 ROM ID
In this example, the part revision is 2.0.0 and the ROM ID is 4. Ensure that partial patches received from Silicon
Labs are intended for use with the part firmware revision and ROM, and that full patches are intended for use with
the ROM ID as shown in Table 2. It is possible to verify the FM and AM component firmware revisions with the
FUNC_INFO command, however, this is not necessary because there is always a unique mapping of component
revision to part revision.
Table 2. Si475x Firmware and ROM Compatibility
Part # Part Revision ROM ID FM Revision AM Revision
Si475x-A10 1.0 2 3.2.3 3.2.3
Si475x-A20 2.0 4 8.0.8 7.0.5
Si475x-A30 3.0 5 10.0.8 9.0.6
6. (Optional—step 3 of 3 to verify part firmware revision and ROM revision.) Send the POWER_DOWN
command. This step is required before proceeding with the patching procedure if steps 4 and 5 have been
followed.
Example
POWER_DOWN Command
Action Data Description
CMD 0x11 POWER_DOWN
ARG1 0x00 Disable oscillator (ARG1 may be omitted with the same result)
STATUS →0x80 CTS = 1
7. Send the POWER_UP command for boot loader function.
Rev. 0.9 9
AN543
Example (with crystal 4 MHz, boot loader function):
1. Provide the initial POWER_UP Command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
Note: Change this value to the capacitance that matches the crystal in use.
ARG3 0x27 SETS CRYSTAL BIAS = 7 w/ FASTBOOT
ARG4 0x00
0x10
0x20
ARG5 0x00 DIGITAL CORE DISABLED/CRYSTAL OSCILLATOR DISABLED
STATUS NO CTS bit returned
2. Apply a wait time of at least 100 ms.
3. Apply the following command:
Action Data Description
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
CMD 0xFB CONTROL REGISTER WRITE COMMAND
ARG1 0X06 CONTROL REGISTER ADDRESS
ARG2 0x80 FORCES CTS = 1
STATUS NO CTS bit returned
4. Apply the following command:
Action Data Description
CMD 0x01 POWER_UP
ARG1 0X77 NORMAL OPERATION, 4 MHz Crystal
ARG2 0x1F SETS CRYSTAL LOAD CAPACITANCE
Note: Change this value to the capacitance that matches the crystal in use.
ARG3 0x23 SETS CRYSTAL BIAS = 3 w/ FASTBOOT
ARG4 0x00
0x10
0x20
ARG5 0x11 DIGITAL CORE ENABLED/CRYSTAL OSCILLATOR ENABLED
STATUS CTS = 1
5. Send the patch data.
BOOT LOADER
FM Receive, 4 MHz Crystal
AM Receive, 4 MHz Crystal
The patch file provided by Silicon Labs typically has a .sg extension. The system controller must send each line of
8 bytes, wait for a CTS, then send the next line of 8 bytes, etc., until the entire patch has been sent. An example
showing the first few lines and final line of a patch file is shown below. Note that the “#” character indicates a
comment and the patch file indicates the required ROM ID for a partial or full download. If the checksum fails, the
part issues an error code, ERR (bit 6 of the STATUS byte received after each 8-byte transfer), and halts. The part
must be reset to recover from this error condition.
10 Rev. 0.9
The following is an example of a patch file:
# COPYRIGHT=2011 Silicon Laboratories, Inc.
# GENERATED=13:53 May 23 2011
# ROMID=0x04
# PATCHID=0x228C
# REQUIRES=NONE
# SIZE=8272
# FUNCTION=FMRX
# MAJOR=8
# MINOR=0
# BUILD=8
# CRCT=0x81CF
# CRCM=0x0A6C
# CRCP=0xEC8D
# CRCX=0x66EE
AN543
# CRCY=0x6381
# CRCZ=0xA805
0x04,0x11,0x81,0xCF,0x00,0x00,0x0D,0xC6
0x05,0xAE,0xE1,0xBD,0xB4,0x90,0x07,0x33
0x06,0xD9,0x3D,0x11,0xF7,0x25,0xCB,0x06
0x17,0x7A,0xF8,0xD0,0x71,0x10,0x3F,0xB7
0x1F,0xBF,0xFF,0x7E,0x42,0xE7,0x53,0x05
…
[Additional Lines]
…
0x08,0x21,0xAB,0xB5,0xF1,0x7A,0xD6,0x5A
0x08,0x10,0x0E,0x9E,0x3B,0xD1,0x01,0xF4
0x08,0xBF,0x8D,0x94,0xB0,0x2D,0xCF,0xFF
0x05,0x8D,0xB1,0x22,0xF2,0x8D,0x22,0x8C
# END
Rev. 0.9 11
AN543
Example:
First line of the patch file example
Action Data Description
CMD 0x04
ARG1 0x11
ARG2 0x81
ARG3 0xCF
ARG4 0x00
ARG5 0x00
ARG6 0x0D
ARG7 0xC6
STATUS →0x80 CTS = 1
Second line of the patch file example
CMD 0x05
ARG1 0xAE
ARG2 0xE1
ARG3 0xBD
ARG4 0xB4
ARG5 0x90
ARG6 0x07
ARG7 0x33
STATUS →0x80 CTS = 1
6. Send the POWER_UP command for the desired function (AM, FM).
Example (with crystal 4 MHz, FM function):
POWER_UP Command
Action Data Description
CMD 0x01 POWER_UP
ARG1 0x77 Normal operation
ARG2 0x27 Crystal load capacitance = 15.803 pF each pin
ARG3 0x23 Disables CTS interrupt, crystal bias = 3, enable fastboot
ARG4 0x10 FM function, crystal frequency 4 MHz
ARG5 0x11 Crystal
STATUS →0x80 CTS = 1
Example (with external clock 4 MHz, FM function):
12 Rev. 0.9
POWER_UP Command
Action Data Description
CMD 0x01 POWER_UP
ARG1 0x77 Normal operation
ARG2 0x00 Crystal load capacitance = 5 pF each pin
ARG3 0x23 Disables CTS interrupt, crystal bias = 3, enable fastboot
ARG4 0x10 FM function, clock frequency 4 MHz
ARG5 0x12 External clock
STATUS →0x80 CTS = 1
7. The device is ready to commence normal operation and accept additional commands.
8. If desired, send the POWER_DOWN command.
Example:
POWER_DOWN Command
Action Data Description
CMD 0x11 POWER_DOWN
AN543
ARG1 0x00 Disable oscillator (ARG1 may be omitted with the same result)
STATUS →0x80 CTS = 1
9. It is now possible to move to the powerup state by returning to step 7.
Rev. 0.9 13
AN543
Command
FM_TUNE_FREQ
Control
Bus
t
STC
t
INT
CTS
Bit
STC
Bit
Command
FM_RSQ_STATUS
INTB
t
CTS
6. Timing
6.1. Command and Property Timing
When the user reads a response over the I2C bus, the first 8 bits returned are the STATUS register. Bit 7 of the
STATUS register is the CTS bit (Clear to Send). When CTS is 1, it indicates that the chip is ready to receive a new
command. Seek and Tune commands may take longer to complete than most other commands, so they also use
the STC bit (Seek/Tune Complete) to indicate they have completed. STC is bit 0 of the STATUS register.
When the user sends any command, the CTS bit will immediately reset to 0. CTS will remain 0 while the chip
processes the command. When the chip is finished processing the command, the CTS bit will be set back to 1.
Before sending another command, the user may poll CTS by reading the first byte of response until CTS = 1. If the
user has enabled the optional CTS interrupt, then the INTB pin will pulse low immediately after CTS has been set
to 1, to notify the user that the previous command has completed. For information on how to enable the CTS
interrupt, see the INT_CTL_ENABLE property and CTSIEN bit in the arguments for the POWER_UP command.
The commands for seek and tune (FM_TUNE_FREQ, FM_SEEK_START, etc.) will cause CTS to reset to 0 for a
short time, but they will set CTS back to 1 after the seek or tune has started. The seek or tune is progressing even
though CTS has been set back to 1. Although the user is free to send another command at this time, it is highly
recommended to wait until the STC (Seek/Tune Complete) bit has been set to 1 before sending another command.
The only exception is the AM/FM_RSQ_STATUS command, which may be sent at any time because it can be used
to cancel the seek/tune in progress and check the status of which station seek is currently on.
When the seek/tune completes, the STC bit will be set to 1. The user may poll STC by reading the first byte of
response until STC = 1. If the user has enabled the optional STC interrupt, then the INTB pin will pulse low
immediately after STC has been set to 1, to notify the user that the seek or tune has completed. For information on
how to enable the STC interrupt, see the INT_CTL_ENABLE property.
After the seek or tune has completed, the user may acknowledge the completion by sending the AM/
FM_RSQ_STATUS command with the STCACK bit set to 1. This will reset the STC bit back to 0. After this, the
user may send another seek or tune command. Alternatively a new seek or tune command will also clear the STC
bit when it begins.
Figure 4 shows a seek or tune command with the optional CTS and STC interrupts enabled. The timing parameters
are shown in Table 3.
Figure 4. CTS and STC Timing Model
14 Rev. 0.9
Table 3. Command Timing Parameters for Common Commands
FM_SEEK_BAND_TOP FM_SEEK_BAND_BOTTOM–
FM_SEEK_FREQ_SPACING
--------------------------------------------------------------------------------------------------------------------------------------------------
1+
t
STC
AN543
Command t
t
CTS
STC
t
INT
POWER_UP 100ms — 3µs
POWER_DOWN <1000 µs — 3 µs
FUNC_INFO <200 µs — 3 µs
SET_PROPERTY <200 µs — 3 µs
GET_PROPERTY <200 µs — 3 µs
GET_INT_STATUS <200 µs — 3 µs
AGC_STATUS <200 µs — 3 µs
ANA_AUDIO_PIN_CFG <200 µs — 3 µs
Table 4. Command Timing Parameters for FM Receiver
Command t
FM_TUNE_FREQ <200 µs 21 ms 3 µs
FM_TUNE_FREQ (fast tune) <200 µs 5 ms 3 µs
FM_SEEK_START <200 µs See Note below. 3 µs
FM_RSQ_STATUS <200 µs — 3 µs
FM_ACF_STATUS <200 µs — 3 µs
t
CTS
STC
t
INT
FM_RDS_STATUS <200 µs — 3 µs
FM_RDS_BLOCKCOUNT <200 µs — 3 µs
*Note: t
is seek time per channel. Total seek time depends on bandwidth, channel spacing, and
STC
number of channels to next valid channel.
Worst case seek time complete for FM_SEEK_START is:
For Si475x-A30, the seek time will require an additional t
spacings other than 200 kHz.
STC
+ t
STC(FAST)
for channel
Table 5. Command Timing Parameters for AM Receiver
Command t
AM_TUNE_FREQ 100 µs 40 ms 3 µs
AM_SEEK_START 100 µs See Note below. 3 µs
AM_RSQ_STATUS 100 µs — 3 µs
AM_ACF_STATUS 100 µs — 3 µs
*Note: t
is seek time per channel. Total seek time depends on bandwidth, channel spacing, and
STC
number of channels to next valid channel.
t
CTS
STC
t
INT
Rev. 0.9 15
AN543
AF Tune
command
issued
AF Tune
Initiated
F
1
F1 F
2
AF station metrics qualified:
Above thresholds
Tuner stays on AF station
Audio Audio
F
2
}
F
2
T
2
T
3
T
1
T
1
T1 ~ 0.5 ms
T
2
~ 1 ms
T
3
~ 4.8 ms
6.2. Alternate Frequency (AF) Timing
The Si4754/55/56/57 features a flexible FM tune command that allows for a number of operational choices. While
tuned to the current station, the receiver can quickly tune to candidate FM stations and perform one of three
operations.
1. Tune to the FM station and stay tuned.
2. Tune to the FM station; check the selected signal metrics, and jump back to the original station (AF check).
3. Tune to the FM station; check the selected signal metrics, and decide if the receiver is kept tuned to the FM
station (AF Jump) or re-tuned to the original station.
The timing diagrams for AF tune and AF check are shown in Figure 5 and Figure 6, respectively.
Figure 5. AF Tune Diagram
16 Rev. 0.9
AN543
AF Check
command
issued
AF Check
Initiated
F
1
F1 F
2
F
2 F1
F
1
AF Station metrics
measured and qualified.
Tuner jumps back to F
1
Audio Audio
F
2
}
}
T
2
T
4
T
2
T
1
T
1
T1 ~ 0.5 ms
T
2
~ 1 ms
T
4
~ 7 ms
Figure 6. AF Check Timing Diagram
Rev. 0.9 17
AN543
Fast Tune
command
issued
Fast Tune
Initiated
F
1
F1 F
2
F
2
Audio
Audio
}
T1 ~ 0.5 ms
T
2
~ 1 ms
T
2
T
1
T
1
6.3. Fast Tune Timing
The timing diagram for fast tune is shown in Figure 7.
Figure 7. Fast Tune Timing Diagram
18 Rev. 0.9
7. Commands and Properties
7.1. Common Commands and Properties
The following properties and commands are common to all receiver modes.
Table 6. Common Receiver Command Summary
Number Name Summary
AN543
0x01 POWER_UP
0x02 PART_INFO Returns the part information of the device.
0x11 POWER_DOWN Power-down the device.
0x12 FUNC_INFO Returns the firmware revision and patch revision.
0x13 SET_PROPERTY Sets the value of a property.
0x14 GET_PROPERTY Retrieve a property's value.
0x15 GET_INT_STATUS Read interrupt status bits.
0x17 AGC_STATUS Reports the status of the AGC.
0x1B ANA_AUDIO_PIN_CFG Configures the analog audio pins.
0x1C INTB_PIN_CFG Configures behavior of INTB and A1 pins.
Power-up device and mode selection. Modes include operational
function (AM, FM) and audio interface configuration.
Table 7. Common Receiver Property Summary
Number Name Default Summary
A10 A20 A30 A40 A55
0x0000 INT_CTL_ENABLE
0x0300 AUDIO_ANALOG_VOLUME
0x0301 AUDIO_MUTE
0x0000 0x0000 0x0000 0x0000 0x0000
0 0 000
0x003F 0x003F 0x003F 0x003F 0x003F
63 63 63 63 63
0x0000 0x0000 0x0000 0x0000 0x0000
0 0 000
Rev. 0.9 19
Interrupt enable property.
Sets the analog audio
volume.
Audio mute property.
AN543
Table 8. Status Response for the FM Receiver
Bit 76543210
STATUS
Bit Name Function
7CTS
6ERR
5:4 Reserved Values may vary.
3RSQINT
2RDSINT
1ACFINT
0STCINT
CTS ERR XX RSQINT RDSINT ACFINT STCINT
Clear to Send.
0 = Wait before sending next command.
1 = Clear to send next command.
Error.
0=No error.
1=Error.
Received Signal Quality Interrupt.
0 = Received Signal Quality measurement has not been triggered.
1 = Received Signal Quality measurement has been triggered.
Radio Data System Interrupt.
0 = Radio data system interrupt has not been triggered.
1 = Radio data system interrupt has been triggered.
Automatically Controlled Features Interrupt.
0 = ACF measurement has not been triggered.
1 = ACF measurement has been triggered.
Seek/Tune Complete Interrupt.
0 = Tune complete has not been triggered.
1 = Tune complete has been triggered.
20 Rev. 0.9
AN543
Table 9. Status Response for the AM Receiver
Bit 76543210
STATUS
Bit Name Function
7CTS
6ERR
5:4 Reserved Values may vary.
3RSQINT
2 Reserved Value may vary.
CTS ERR XX RSQINT X ACFINT STCINT
Clear to Send.
0 = Wait before sending next command.
1 = Clear to send next command.
Error
0=No error.
1=Error.
Received Signal Quality Interrupt
0 = Received Signal Quality measurement has not been triggered.
1 = Received Signal Quality measurement has been triggered.
Automatically Controlled Features Interrupt.
1ACFINT
0STCINT
0 = ACF measurement has not been triggered.
1 = ACF measurement has been triggered.
Seek/Tune Complete Interrupt.
0 = Tune complete has not been triggered. Do not send a new TUNE/SEEK
command.
1 = Tune complete has been triggered. It is safe to send a new TUNE/
SEEK command.
Rev. 0.9 21
AN543
If the ERR bit in the STATUS response is set for a command or property, the response is redefined as follows:
Table 10. Response When ERR Bit is Set
Bit 7 6 5 4 3 2 1 0
STATUS CTS 1 XX RSQINT RDSINT ACFINT STCINT
RESP1 ERROR
RESP Bit Name Function
Error definitions.
0x10 = Bad command.
0x11 = Bad ARG1.
0x12 = Bad ARG2.
0x13 = Bad ARG3.
17:0ERROR
0x14 = Bad ARG4.
0x18 = Command busy.
0x20 = Bad internal memory.
0x30 = Bad patch.
0x31 = Bad boot mode.
0x40 = Bad property.
22 Rev. 0.9
AN543
7.1.1. Common Receiver Commands
Command 0x01 POWER_UP
The POWER_UP command initiates the boot process to move the device from powerdown to powerup mode. The
boot can occur from internal device memory or a system controller downloaded patch. This command powers up
the device with the specified function (FM Receive and AM Receive). Power-up is complete when the CTS bit is
set. This is the only command that may be sent while the device is powered down. Due to variation of the 4 MHz
crystal from vendor to vendor, two power up commands are required for reliably powering up: a 4 MHz crystal preboot POWER_UP command, and a POWER_UP command to boot the part with the desired function (AM, FM).
Command
Bit 7 6 5 4 3 2 1 0
CMD
ARG1
ARG2 00 XCLOAD[5:0]
ARG3 CTSIEN INTSEL FASTBOOT
ARG4 FUNC[3:0] 0000
ARG5 CTEN[4:0]
0x01
XSTART[7:0]
00 XIBIAS[2:0]
XMODE[2:0]
ARG Bit Name Function
Oscillator startup
01110101 = 4 MHz crystal pre-boot (first command in 4 MHz crystal
1 7:0 XSTART[7:0]
2 7:6 Reserved Always write 00.
2 5:0 XCLOAD[5:0]
3 7 CTSIEN
3 6 INTSEL
3 5 FASTBOOT
3 4:3 Reserved Always write 00.
sequence)
01110111 = boot (normal operation with external clock, or the second
command in a 4 MHz crystal sequence)
Selects the amount of additional on-chip capacitance to be connected
between XTAL1 and gnd and between XTAL2 and gnd. One half of the
capacitance value shown here is the additional load capacitance presented to the xtal. The minimum step size is 0.25 pF. The required value
will be layout-dependent. Range is 0–0x3F (i.e. 5–20.75 pF) The EVB
sets XCLOAD = 0x27.
CTS interrupt enable
0 = Disable.
1 = Enable.
CTS interrupt pin select
0=A1 pin.
1=INTB pin.
Speeds boot time when set. It is required to set this bit with Si475x-A20
and later only.
3 2:0 XBIAS[2:0]
Crystal bias current
3 = 4 MHz crystal or external clock
7 = 4 MHz crystal for boot-up
Rev. 0.9 23
AN543
ARG Bit Name Function
Selects the boot function of the device.
0 = Boot Loader.
4 7:4 FUNC[3:0]
4 3:0 Reserved Always write 0000.
5 7:3 CNTEN[4:0]
5 2:0 XMODE[2:0]
1=FM Receive.
2=AM Receive.
Note: Values other than those listed may result in unpredictable behavior.
Enable counter
00000 = 4 MHz crystal pre-boot (first command in 4 MHz crystal
sequence)
00010 = boot (normal operation with external clock, or the second com-
mand in a 4 MHz crystal sequence)
Crystal mode
1 = Crystal
2 = External clock
24 Rev. 0.9
AN543
Command 0x02 PART_INFO
The PART_INFO command returns the chip revision, part firmware major, minor, and build revision, and ROM ID.
The command is complete when the CTS bit (and optional interrupt) is set. The command may only be sent in
powerup mode.
Command
Bit76543210
CMD
Response
Bit 7 6 5 4 3 2 1 0
0x02
STATUS
RESP1
RESP2
RESP3
RESP4
RESP5
RESP6
RESP7
RESP8
RESP Bit Name Function
1
2 7:0 PART Part Number, last two digits of part number
3 7:0 PMAJOR Part Major Revision (ASCII Character Value)
4 7:0 PMINOR Part Minor Revision (ASCII Character Value)
CTS ERR XX RSQINT RDSINT ACFINT STCINT
CHIPREV[7:0]
PART[7:0]
PMAJOR[7:0]
PMINOR[7:0]
PBUILD[7:0]
Reserved
Reserved
ROMID[7:0]
7:0 CHIPPREV Chip Revision
5 7:0 PBUILD Part Build Version
6 7:0 Reserved Values may vary.
7 7:0 Reserved Values may vary.
8 7:0 ROMID ROM ID
Rev. 0.9 25
AN543
Command 0x11 POWER_DOWN
The POWER_DOWN command moves the device from powerup to powerdown mode. The CTS bit (and optional
interrupt) is set when it is safe to send the next command. This command may only be sent when in powerup
mode. Note that only the POWER_UP command is accepted in powerdown mode. If the system controller writes a
command other than POWER_UP when in powerdown mode, the device will not respond. The device will only
respond when a POWER_UP command is written. It is possible to power down a device and leave the oscillator
running.
Command
Bit76543210
CMD
ARG1 0000000 XOSC
ARG Bit Name Function
1 7:1 Reserved Always write 0000000.
10XOSC
Response
Bit76543210
STATUS
Note: The above response shows status bits for FM Receive mode (see Table 8). See Table 9 for status bits for AM Receive
mode.
CTS ERR XX RSQINT RDSINT ACFINT STCINT
0x11
0 = Full powerdown.
1 = Powerdown and leave oscillator running.
26 Rev. 0.9
AN543
Command 0x12 FUNC_INFO
The FUNC_INFO command returns the firmware revision and patch revision for currently-loaded functional mode
firmware (AM and FM). The command is complete when the CTS bit (and optional interrupt) is set. This command
may only be sent in powerup mode.
Command
Bit76543210
CMD
Response
Bit 76543210
STATUS
RESP1 FWMAJOR[7:0]
RESP2 FWMINOR1[7:0]
RESP3 FWMINOR2[7:0]
RESP4 PATCHH[7:0]
RESP5 PATCHL[7:0]
RESP6 FUNC[7:0]
Note: The above response shows status bits for FM Receive mode (see Table 8 on page 20). See Table 9 on page 21 for
status bits for AM Receive mode.
RESP Bit Name Function
1 7:0 FWMAJOR[7:0] Firmware Major Revision.
2 7:0 FWMINOR1[7:0] Firmware Minor1 Revision.
3 7:0 FWMINOR2[7:0] Firmware Minor2 Revision.
4 7:0 PATCHH[7:0] Patch ID High Byte (HEX).
5 7:0 PATCHL[7:0] Patch ID Low Byte (HEX).
6 7:0 FUNC[7:0]
CTS ERR XX RSQINT RDSINT ACFINT STCINT
Returns the current functional mode:
1 = FM Receive
2=AM Receive
0x12
Rev. 0.9 27
AN543
Command 0x13 SET_PROPERTY
The SET_PROPERTY command sets the value of a property. The CTS bit (and optional interrupt) is set when it is
safe to send the next command. This command may only be sent in powerup mode.
Command
Bit76543210
CMD
ARG1 00000000
ARG2 PROPH[7:0]
ARG3 PROPL[7:0]
ARG4 PROPDH[7:0]
ARG5 PROPDL[7:0]
ARG Bit Name Function
1 7:0 Reserved Always write to 0.
27:0
37:0
47:4
57:0
PROPH
[7:0]
PROPL
[7:0]
PROPDH
[7:0]
PROPDL
[7:0]
Property Address High Byte
This byte, in combination with PROPL, is used to specify the property to modify.
Property Address Low Byte
This byte, in combination with PROPH, is used to specify the property to modify.
Property Data High Byte
This byte, in combination with PROPDL, is used to set the property value.
Property Data Low Byte
This byte, in combination with PROPDH, is used to set the property value.
0x13
Response
Bit76543210
STATUS
Note: The above response shows status bits for FM Receive mode (see Table 8 on page 20). See Table 9 on page 21 for
status bits for AM Receive mode.
28 Rev. 0.9
CTS ERR XX RSQINT RDSINT ACFINT STCINT
AN543
Command 0x14 GET_PROPERTY
The GET_PROPERTY command retrieves a property's value. The CTS bit (and optional interrupt) is set when it is
safe to send the next command. This command may only be sent in powerup mode
Command
Bit76543210
CMD
0x14
ARG1 00000000
ARG2 PROPH[7:0]
ARG3 PROPL[7:0]
ARG Bit Name Function
1 7:0 Reserved Always write 0.
Property Address High Byte.
27:0PROP
[7:0]
H
This byte, in combination with PROPL, is used to specify
the property to get.
Property Address Low Byte.
37:0PROP
[7:0]
L
This byte, in combination with PROPH, is used to specify
the property to get.
Response
Bit 76543210
STATUS
CTS ERR XX RSQINT RDSINT ACFINT STCINT
RESP1 XXXXXXXX
RESP2 PROPD
RESP3 PROPD
Note: The above response shows status bits for FM Receive mode (see Table 8 on page 20). See Table 9 on page 21 for
status bits for AM Receive mode.
[7:0]
H
[7:0]
L
RESP Bit Name Function
1 7:0 Reserved Response values may vary.
27:0PROPD
[7:0] Property Data High Byte.
H
This byte, in combination with PROPDL, represents
the requested property value.
37:0PROPD
[7:0] Property Data Low Byte.
L
This byte, in combination with PROPDH, represents
the requested property value.
Rev. 0.9 29
AN543
Command 0x15 GET_INT_STATUS
The GET_INT_STATUS command updates the bits of the status byte. This command should be called after any
command that sets the STCINT, ACFINT, RDSINT, ASQINT, or RSQINT bits. When polling, this command should
be periodically called to monitor the STATUS byte, and, when using interrupts, this command should be called after
the interrupt is set to update the STATUS byte. The CTS bit (and optional interrupt) is set when it is safe to send the
next command. This command may only be set in powerup mode.
Command
Bit76543210
CMD
Response
Bit 76543210
STATUS
Note: The above response shows status bits for FM Receive mode (see Table 8 on page 20). See Table 9 on page 21 for
status bits for AM Receive mode.
Command 0x17 AGC_STATUS
The AGC_STATUS command reports the current status of the AGC for FM mode. AM_AGC_STATUS (command
0x47) is used in AM/LW/SW modes. The command is complete when the CTS bit (and optional interrupt) is set.
This command may only be sent when in powerup mode.
Bit76543210
CMD
RESP76543210
CTS ERR XX RSQINT RDSINT ACFINT STCINT
0x15
0x17
STATUS
RESP1 XX
RESP2 FMAGC1
RESP3 FMAGC2
RESP4 PGAGAIN
RESP5 FMLNAG
Note: The above response shows status bits for FM Receive mode (see Table 8 on page 20). See Table 9 on page 21 for
status bits for AM Receive mode.
30 Rev. 0.9
CTS ERR XX RSQINT RDSINT ACFINT STCINT
MIXHI MIXLO LNAHI LNALO X X
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