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SI4734-35-B20
User Manual
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Silicon Laboratories SI4734-35-B20 User Manual

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Si4734/35-B20
BROADCAST AM/FM/SW/LW RADIO RECEIVER

Features

Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support (2.3–21.85 MHz)LW band support (153–279 KHz)Excellent real-world performanceFreq synthesizer with integrated VCOAutomatic frequency control (AFC)Automatic gain control (AGC)Integrated LDO regulatorDigital FM stereo decoderProgrammable de-emphasisAdaptive noise suppressionAM/FM/SW/LW digital tuning
No manual alignment necessaryAdjustable channel filtersEN55020 complaintProgrammable reference clockDigital volume controlAdjustable soft mute controlRDS/RBDS processor (Si4735 only)Optional digital audio out (Si4735 only)2-wire and 3-wire control interf ace2.7 to 5.5 V supply voltageWide range of ferrite loop sticks and air
loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
z Pb-free/RoHS compliant

Applications

Table and portable radiosStereosMini/micro systemsCD/DVD playersPortable media playersBoom boxes
Cellular handsetsModulesClock radiosMini HiFiEntertainment systems

Description

The Si4734/35 is the first digital CMOS AM/FM/SW/LW radio receiver IC that integrates the complete tuner function from antenna input to audio output.
Ordering Information:
See page 31.
Pin Assignments
Si4734/35-GM
(Top View)
NC
GPO1
1
NC
2
FMI
AMI
3 4 5
6
SEN
GND PAD
7 8 9
SDIO
SCLK
RFGND
GPO2/INT
GPO3/DCLK
DFS
17181920
16
15
DOUT LOUT
14 13
ROUT GNDRST
12
11
10
RCLK
VDD
VIO
AM / LW
ANT
2.7 - 5.5 V
FM / SW
ANT
RFGND
FMI
AMI
VDD GND
LNA
AGC
LNA
AGC
LDO
ADC
ADC
AFC
RCLK
Si4734/35
RDS
(Si4735)
LOW-IF
DSP
CONTROL
INTERFACE
SEN
SCLK
DIGITAL
AUDIO
(Si4735)
DAC
DAC
SDIO
Patents pending
DOUT DFS GPO/DCLK
ROUT
LOUT
VIO
1.5-3.6V
RST
Notes:
1. To ensure proper operation and
receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
Rev. 1.0 4/08 Copyright © 2008 by Silicon Laboratories Si4734/35-B20
Si4734/35-B20
2 Rev. 1.0
Si4734/35-B20
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
26
Rev. 1.0 3
Si4734/35-B20

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage V Interface Supply V oltage V Power Supply Powerup Rise Time V
Interface Power Supply Powerup Rise Time V Ambient Temperature T
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V otherwise stated.
Table 2. Absolute Maximum Ratings
= 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
DD
1,2
DD
IO
DDRISE
IORISE
A
2.7 — 5.5 V
1.5 — 3.6 V 10 — — µs
10 — — µs
–20 25 85 °C
Parameter Symbol Value Unit
Supply Voltage V Interface Supply V oltage V Input Current Input Voltage
3 3
Operating Temperature T Storage Temperature T RF Input Level
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability.
2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rati ng of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
DD
IO
I
IN
V
OP
STG
IN
–0.5 to 5.8 V –0.5 to 3.9 V
10 mA
–0.3 to (VIO + 0.3) V
–40 to 95 °C
–55 to 150 °C
0.4 V
pK
4 Rev. 1.0

Table 3. DC Characteristics

(V
= 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
Parameter Symbol Test Condition Min Typ Max Unit
FM Mode
Si4734/35-B20
Supply Current I Supply Current RDS Supply Current Supply Current
1
2
2
FM
I
FM
I
FM
I
FMD
Low SNR level — 19.8 23 mA
Digital Output Mode — 18.0 20.5 mA
—19.222mA
—19.923mA
AM/SW/LW Mode
Supply Current I Supply Current
2
AM
I
AMD
Analog Output Mode — 17.3 20.5 mA
Digital Output Mode — 15.5 20.5 mA
Supplies and Interface
Interface Supply Current I V
Powerdown Current I
DD
V
Powerdown Current I
IO
High Level Input Volt age Low Level Input Voltage High Level Input Current Low Level Input Current
High Level Output Voltage Low Level Output Voltage
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
3
3
3
3
4
4
IO
DDPD
IOPD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
SCLK, RCLK inactive — 1 10 µA
VIN = VIO = 3.6 V –10 — 10 µA
VIN=0V,
=3.6V
V
IO
I
= 500 µA 0.8 x V
OUT
I
= –500 µA — — 0.2 x V
OUT
—320600µA —1020 µA
0.7 x V
IO
—VIO+0.3 V
–0.3 — 0.3 x V
–10 — 10 µA
IO
——V
IO
IO
V
V
Rev. 1.0 5
Si4734/35-B20
Table 4. Reset Timing Characteristics
(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
1,2,3
Parameter Symbol Min Typ Max Unit
RST
Pulse Width and GPO1, GPO2/INT Setup to RST↑
GPO1, GPO2/INT
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST
4. If GPO1 and GPO2 are actively driven by the user, then minimum t minimum t GPO2 low.
Hold from RST↑ t
.
is 100 µs, to provide time for on-chip 1 MΩ devices (active while RST is low) to pull GPO1 high and
SRST
70%
RST
30%
4
t
SRST
t
SRST
HRST
t
HRST
100 — — µs
30 — — ns
, and stays high until
is only 30 ns. If GPO1 or GPO2 is hi-Z, then
SRST
INT
70% 30%
70% 30%
GPO1
GPO2/

Figure 1. Reset Timing Parameters for Busmode Select

6 Rev. 1.0
Si4734/35-B20
Table 5. 2-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
1,2,3
Parameter Symbol Test Condition M in Typ M ax Unit
SCLK Frequency f SCLK Low Time t SCLK High Time t SCLK Input to SDIO
↓ Setup
t
SCL
LOW
HIGH
SU:STA
0—400kHz
1.3 — — µs
0.6 — — µs
0.6 — — µs
(START) SCLK Input to SDIO
SDIO Input to SCLK SDIO Input to SCLK SCLK input to SDIO
↓ Hold (START) t ↑ Setup t ↓ Hold
4,5
↑ Setup (STOP) t
t
STOP to START Time t SDIO Output Fall Time t
HD:STA SU:DAT HD:DAT SU:STO
BUF
f:OUT
0.6 — — µs
100 — — ns
0—900ns
0.6 — — µs
1.3 — — µs —250ns
C
b
20 0.1
---------- -
+
1pF
SDIO Input, SCLK Rise/Fall Time t
SCLK, SDIO Capacitive Loading C Input Filter Pulse Suppression t
Notes:
1. When VIO= 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high)
does not occur within 300 ns before the rising edge of RST
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST after the first start condition.
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the V t
specification.
HD:DAT
5. The maximum t as long as all other timing parameters are met.
has only to be met when f
HD:DAT
t
f:IN r:IN
SP
C
b
20 0.1
b
---------- -
+
1pF
— — 50 pF — — 50 ns
.
threshold of SCLK to comply with the minimum
IH
= 400 kHz. At frequencies below 400 KHz, t
SCL
—300ns
, and stays high until
may be violated
HD:DAT
Rev. 1.0 7
Si4734/35-B20
SCLK
SDIO
SCLK
SDIO
70% 30%
70% 30%
t
SU:STA
t
HD:STA
START
t
LOW
t
r:IN
t
HIGH
t
HD:DAT
t
SU:DAT
t
r:IN
t
f:IN
t
SP
t
f:IN,
t
f:OUT

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

A6-A0,
R/W
D7-D0 D7-D0
t
SU:STO
t
BUF
STARTSTOP
START STOPADDRESS + R/W ACK DATA ACK DATA ACK

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

8 Rev. 1.0
Si4734/35-B20

Table 6. 3-Wire Control Interface Characteristics

(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Un i t
SCLK Frequency f SCLK High Time t SCLK Low Time t SDIO Input, SEN
to SCLK↑ Setup t
SDIO Input to SCLK↑ Hold t
Input to SCLK↓ Hold t
SEN SCLK↑ to SDIO Output Valid t SCLK↑ to SDIO Output High Z t SCLK, SEN
, SDIO, Rise/Fall time tR, t
CLK
HIGH
LOW
S
HSDIO
HSEN
CDV
CDZ
F
Read 2 — 25 ns Read 2 — 25 ns
0—2.5MHz 25 — — ns 25 — — ns 20 — — ns 10 — — ns 10 — — ns
— — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
SEN
70% 30%
70% 30%
SCLK
.
t
t
R
t
S
F
t
HSDIO
t
S
t
HIGHtLOW
t
HSEN
SDIO
SCLK
SEN
SDIO
70% 30%
A7 A0
A6-A5,
R/W,
D15 D14-D1 D0
A4-A1
Address In Data In

Figure 4. 3-Wire Control Interface Write Timing Parameters

70% 30%
70% 30%
70%
30%
t
S
t
HSDIO
t
S
A6-A5,
A7 A0
R/W,
A4-A1
Address In Data Out
½ Cycle Bus
Turnaround
t
CDV
D15 D14-D1 D0

Figure 5. 3-Wire Control Interface Read Timing Parameters

t
HSEN
t
CDZ
Rev. 1.0 9
Si4734/35-B20

Table 7. SPI Control Interface Characteristics

(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Un i t
SCLK Frequency f SCLK High Time t SCLK Low Time t SDIO Input, SEN
to SCLK↑ Setup t
SDIO Input to SCLK↑ Hold t
Input to SCLK↓ Hold t
SEN
↓ to SDIO Output Valid t
SCLK
↓ to SDIO Output High Z t
SCLK SCLK, SEN
, SDIO, Rise/Fall time
CLK
HIGH
LOW
S
HSDIO
HSEN
CDV
CDZ
, t
t
R
F
Read 2 — 25 ns Read 2 — 25 ns
0—2.5MHz 25 — — ns 25 — — ns 15 — — ns 10 — — ns
5——ns
— — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
SEN
70% 30%
70% 30%
SCLK
.
t
t
F
R
t
HIGHtLOW
t
S
t
S
t
HSDIO
t
HSEN
SDIO
SCLK
SEN
SDIO
70% 30%
70% 30%
70% 30%
70%
30%
C7 C0
C6–C1
Control Byte In 8 Da ta By te s In
D7 D6–D1 D0

Figure 6. SPI Control Interface Write Timing Parameters

t
CDV
t
S
t
S
C7 C0C6–C1
Control Byte In
t
HSDIO
Turnaround
D7 D6–D1 D0
Bus
16 Data Bytes Out
(SDIO o r G P O 1 )
t
HSEN

Figure 7. SPI Control Interface Read Timing Parameters

t
CDZ
10 Rev. 1.0

Table 8. Digital Audio Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si4734/35-B20
DCLK Cycle Time t DCLK Pulse Width High t DCLK Pulse Width Low t DFS Set-up Time to DCLK Rising Edge t DFS Hold Time from DCLK Rising Edge t DOUT Propagation Delay from DCLK Falling
t
PD:DOUT
Edge
t
DCH
t
DCL
DCLK
t
DCT
DFS
DCT DCH
DCL SU:DFS HD:DFS
t
HD:DFS
t
SU:DFS
26 — 1000 ns 10 — — ns 10 — — ns
5—— ns 5—— ns 0—12ns
DOUT
t
PD:OUT

Figure 8. Digital Audio Interface Timing Parameters, I2S Mode

Rev. 1.0 11
Si4734/35-B20
Table 9. FM Receiver Characteristics
(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
1,2
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency f Sensitivity with Headphone
Network Sensitivity with 50 Ω Network
RDS Sensitivity
3,4,5
3,4,5,6
6
RF
(S+N)/N = 26 dB — 2.2 3.5 µV EMF
(S+N)/N = 26 dB — 1.1 — µV EMF
Δf = 2 kHz,
76 — 108 MHz
—15—µV EMF
RDS BLER < 5%
LNA Input Resistance LNA Input Capacitance Input IP3
6,8
AM Suppression
6,7
6,7
3,4,6,7
Adjacent Channel Selectivity Alternate Channel Selectivity Spurious Response Rejection Audio Output Voltage
3,4,7
Audio Output L/R Imbalance
6
3,7,9
Audio Frequency Response Low Audio Frequency Response High Audio Stereo Separation Audio Mono S/N Audio Stereo S/N Audio THD
3,4,5,7,10
4,5,7,10,11
3,7,9
De-emphasis Time Constant
7,9
6
m = 0.3 40 50 — dB ±200 kHz 35 50 — dB ±400 kHz 60 70 — dB
In-band 35 — — dB
6
6
–3 dB — — 30 Hz –3 dB 15 — — kHz
FM_DEEMPHASIS = 2 70 75 80 µs
345kΩ 456pF
100 105 — dBµV EMF
72 80 90 mV
—— 1 dB
25 — — dB 55 63 — dB
—58— dB —0.10.5 %
FM_DEEMPHASIS = 1 45 50 54 µs Audio Output Load Resistance Audio Output Load Capacitance
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schemati cs an d layouts for qualified customers.
3. F
4. Δf =22.5 kHz.
5. B
6. Guaranteed by characterization.
7. V
8. |f
9. Δf =75 kHz.
10. At L
11. Analog audio output mode.
12. At temperature (25°C).
=1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
= 300 Hz to 15 kHz, A-weighted.
AF
=1 mV.
EMF
– f1| > 2 MHz, f
2
and R
OUT
OUT
0
pins.
6,10
6,10
=2xf1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
R
L
C
L
Single-ended 10 — — kΩ Single-ended — — 50 pF
RMS
12 Rev. 1.0
Si4734/35-B20
Table 9. FM Receiver Characteristics
(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
1,2
(Continued)
Parameter Symbol Test Condition Min Typ Max Unit
Seek/Tune Time
6
RCLK tolerance
— — 80 ms/channel
=100ppm Powerup Time RSSI Offset
12
6
From powerdown — — 110 ms
Input levels of 8 and
–3 — 3 dB
60 dBµV at RF Input
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schemati cs an d layouts for qualified customers.
3. F
4. Δf =22.5 kHz.
5. BAF= 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. V
8. |f2 – f1| > 2 MHz, f
9. Δf =75 kHz.
10. At L
11. Analog audio output mode.
12. At temperature (25°C).
=1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
=1 mV.
EMF
OUT
and R
=2xf1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
0
pins.
OUT
Rev. 1.0 13
Si4734/35-B20
Table 10. 64–75.9 MHz Input Frequency FM Receiver Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
1
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency f Sensitivity with Headphone
Network LNA Input Resistance
LNA Input Capacitance Input IP3 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity Audio Output Voltage Audio Output L/R Imbalance Audio Frequency Response Low Audio Frequency Response High Audio Mono S/N Audio THD
2,3,4,5
5,6
5,6
5,7
2,3,5,6
5
5
2,3,5,6
2,6,8
5
5
2,3,4,5,6,9
2,5,6,8
RF
(S+N)/N = 26 dB — 4.0 — µV EMF
m = 0.3 40 50 — dB ±200 kHz — 50 — dB ±400 kHz — 70 — dB
–3 dB — — 30 Hz –3 dB 15 — — kHz
64 — 75.9 MHz
345kΩ 456pF
100 105 — dBµV EMF
72 80 90 mV —— 1 dB
55 63 — dB —0.10.5 %
De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Audio Common Mode Voltage
9
Audio Output Load Resistance Audio Output Load Capacitance Seek/Tune Time
5
5,9
5,9
R
L
C
L
Single-ended 10 — — kΩ Single-ended — — 50 pF
RCLK tolerance
0.7 0.8 0.9 V
— — 80 ms/channel
=100ppm Powerup Time From powerdown — — 110 ms RSSI Offset
10
Input levels of 8 and
–3 — 3 dB
60 dBµV EMF
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. Tested at RF = 98.1 MHz.
2. F
3. Δf = 22.5 kHz.
4. B
5. Guaranteed by characterization.
6. V
7. |f
8. Δf = 75 kHz.
9. At LOUT and ROUT pins.
10. At temperature 25 °C.
= 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
= 300 Hz to 15 kHz, A-weighted.
AF
= 1 mV.
EMF
– f1| > 2 MHz, f
2
= 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
0
RMS
14 Rev. 1.0
Si4734/35-B20
Table 11. AM/SW/LW Receiver Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
1
Parameter Symbol Test Condition Min Typ Max Unit
Long Wave (LW) 153 — 279 kHz
Input Frequency
f
RF
Medium Wave (AM) 520 — 1710 kHz
Short Wave (SW) 2.3 — 21.85 MHz Sensitivity Large Signal V olt age Handling Power Supply Rejection Ratio ΔVDD=100 mV Audio Output Voltage Audio S/N Audio THD
2,3,4,5, 6
2,3,4,6,8
2,4,8
2,8
5,7
(S+N)/N = 26 dB — 25 35 µV EMF
THD < 8% — 300 — mV
, 100 Hz — 40 — dB
RMS
54 60 67 mV 50 56 — dB — 0.1 0.5 %
Long Wave (LW) — 2800 —
Antenna Inductance
Medium Wave (AM) 180 — 450
Powerup Time From powerdown — — 110 ms
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schemati cs an d layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. B
4. f
5. Guaranteed by characterization.
6. Analog audio output mode.
7. See “AN388: Evaluation Board Test Procedure” for evaluation method.
8. V
9. Stray capacitance on antenna and board must be < 10 pF to achieve full tuning range at higher inductance levels.
= 300 Hz to 15 kHz, A-weighted.
AF
= 1000 kHz, Δf = 10 kHz.
RF
= 5 mVrms.
IN
RMS
RMS
µH
Rev. 1.0 15
Si4734/35-B20

Table 12. Reference Clock and Crystal Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Reference Clock
RCLK Supported Frequencies RCLK Frequency Tolerance –50 — 50 ppm REFCLK_PRESCALE 1 — 4095 REFCLK 31.130 32.768 34.406 kHz
Crystal Oscillator Frequency — 32.768 — kHz Crystal Frequency Tolerance* –100 — 100 ppm Board Capacitance — — 3.5 pF
*Note: The Si4734/35 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See AN332, Table 6 for more details.
*
Crystal Oscillator
31.130 32.768 40000.0 kHz
16 Rev. 1.0

2. Typical Application Schematic

Si4734/35-B20
GPO1 GPO2/INT
FMI
L2
RST SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
L1
C4
C5
1
NC
2
FMI
3
RFGND
4
AMI
5
RST
20
19
18
17
NC
GPO1
GPO2
GPO3
U1
Si4734/35-GM
SEN
SCLK
SDIO
6
7
8
9
RCLK
16
10
DFS
VIO
DOUT
LOUT
ROUT
GND
VDD
15
R1
R2
R3
DCLK DFS
DOUT
Optional: Digital Audio Output
14 13
LOUT ROUT
12 11
C1
GPO3
VBATTERY
2.7 to 5.5 V
X1
RCLK
C2 C3
Optional: fo r cr y s ta l os c illator option
Notes:
1. Place C1 close to V
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
8. See “AN382: Si4734/35 Designer’s Guide” for further recommendations.
DD
pin.
Rev. 1.0 17
Si4734/35-B20

3. Bill of Materials

Component(s) Value/Description Supplier
C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C4 Capacitor, 18 pF, ±20%, Z5U/X7R Murata C5 Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R Murata L1 Ferrite loop stick, 180 L2 4.7 µH Coilcraft U1 Si4734/35 AM/FM Radio Tuner Silicon Laboratories
C2, C3 Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson
R1, R2 Resistor, 2 kΩ Venkel
R3 Resistor, 600 Ω Venkel
–450 µH Jiaxin
Optional Components
Venkel
18 Rev. 1.0

4. Functional Description

4.1. Overview

Si4734/35-B20
FM / SW
ANT
FMI
LNA
AGC
AM / LW
ANT
2.7 - 5.5 V
AMI
RFGND
VDD
GND
LNA
AGC
LDO

Figure 9. Functional Block Diagram

The Si4734/35 is the industry's first fully integrated, 100% CMOS AM/FM/SW/LW radio receiver IC. Offering unmatched integration and PCB space savings, the Si4734/35 requires minimal external components and less than 20 mm inputs. The Si4734/35 AM/FM/SW/LW radio provides the space savings and low power consumption necessary for portable devices while delivering the high performance and design simplicity desired for all AM/FM/SW/LW solutions.
Leveraging Silicon Laboratories' proven and patented Si4700/01 FM tuner's digital low intermediate frequency (low-IF) receiver architecture, the Si4734/35 delivers superior RF performance and interference rejection in AM, FM, and short wave and long wave bands. The high integration and complete system production test simplifies design-in, increases system quality, and improves manufacturability.
The Si4734/35 is a feature-rich solution including advanced seek algorithms, soft mute, auto-calibrated digital tuning, and FM stereo processing. In additio n, the Si4734/35 provides analog or digital audio output and a programmable reference clock. The device supports
2
C-compatible 2-wire control interface, SPI, and a
I
2
of board area, excluding the antenna
Si4734/35
RDS
(Si4735)
LOW-IF
ADC
DSP
ADC
AFC
RCLK
Si4700/01 backwards-compatible 3-wire control interface.
The Si4734/35 utilizes digital processing to achieve high fidelity, optimal performance, and design flexibility. The chip provides excellent pilot rejection, selectivity, and unmatched audio performance, and offers both the manufacturer and the end-user extensive programmability and flexibility in the listening experience.
The Si4735 incorporates a digital processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS), including all required symbol decoding, block synchronization, error detection, and error correction functions. Using RDS, the Si4735 enables broadcast data such as station identification and song name to be displayed to the user.
DIGITAL
AUDIO
(Si4735)
DAC
DAC
CONTROL
INTERFACE
SEN
SCLK
SDIO
RST
DOUT
DFS
GPO/DCLK
ROUT
LOUT
VIO
1.5-3.6V
Rev. 1.0 19
Si4734/35-B20

4.2. Operating Modes

The Si4734/35 operates in either an FM receive or an AM/SW/LW receive mode. In FM mode, radio signals are received on FMI (pin 2) and proce ssed by the FM front-end circuitry. In AM/SW/LW mode, radio signals are received on AMI (pin 4) and proce ssed by the AM front-end circuitry. In addition to the receiver mode, a clocking mode allows the Si4734/35 to be clocked from a reference clock or crystal. On the Si4735, an audio output mode is available as analog and/or digital audio output. In the analog audio output mode, pin 13 is ROUT, pin 14 is LOUT, pin 17 is GPO3. In the digital audio mode, pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK. Concurrent analog/digital audio output mode requires pins 13, 14, 15,16, and 17. The rece iver mode and the audio output mode are set by the POWER_UP command listed in Table 12. Si473x Command Summary.

4.3. FM Receiver

The Si4734/35's patented digital low-IF architecture reduces external components and eliminates the need for factory adjustments. The Si4734/35 receiver supports the worldwide FM broadcast band (76 to 108 MHz) as well as an extended FM band (64 to 76 MHz), which may include region-specific programming such as educational channels, emergency alerts, and/or television audio. An automatic gain control (AGC) circuit controls the gain of the integrated low noise amplifier (LNA) to optimize sensitivity and rejection of strong interferers. An image-reject mixer downconverts the RF signal to low-IF. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (ADCs). This advanced architecture allows the Si4734/35 to perform channel selection, FM demodulation, and stereo audio processing to achieve superior perfo rmance compared to traditional analog architectures.
The Si4734/35 provides highly accurate digital AM tuning without factory adjustments. To offer maximum flexibility, the receiver supports a wide range of ferrite loop sticks from 180–450 µH. An air loop antenna is supported by using a transformer to increase the effective inductance from the air loop. Using a 1:5 turn ratio inductor, the inductance is increased by 25 times, easily supporting all typical AM air loop antennas which generally vary between 10 and 20 µH.

4.5. SW Receiver

The Si4734/35 is the first fully integrated IC to support AM and FM, as well as short wave (SW) band reception from 2.3 to 21.85 MHz fully covering the 120 meter to 13 meter bands. The Si4734/35 offers extensive shortwave features such as continuous digital tuning with minimal discrete components and no factory adjustments. Other SW features include adjustable channel step sizes in 1 kHz increments, adjustable channel bandwidth settings, advanced seek algorithm, and soft mute.
The Si4734/35 uses the FM antenna to capture short wave signals. These signals are then fed directly into the AMI pin in a wide band configuration. See “AN382: Si4734/35 Designer’s Guide” for more details.

4.6. LW Receiver

The Si4734/35 supports the long wave (LW) band from 153 to 279 kHz. The highly integrated Si4734/35 offers continuous digital tuning with minimal discrete components and no factory adjustment s. The Si47 34/35 also offers adjustable channel step sizes in 1 kHz increments, adjustable channel bandwidth settings, advanced seek algorithm, and soft mute.
The Si4734/35 uses a separate ferrite bar antenna to capture long wave signals.

4.4. AM Receiver

The highly integrated Si4734/35 supports worldwid e AM band reception from 520 to 1710 kHz using a digit al low­IF architecture with a minimum number of external components and no manual alignment required. This digital low-IF architecture allows for high-precision filtering, offering excellent selectivity and noise suppression. The DSP also provides 9 or 10 kHz channel selection, AM demodulation, soft mute, and additional features such as adjustable channel bandwidth settings. Similar to the FM receiver, the integrated LNA and AGC optimize sensitivity and rejection of strong interfer ers allowing better reception of weak stations.
20 Rev. 1.0

4.7. Digital Audio Interface (Si4735 Only)

The digital audio interface operates in slave mode and supports three different audio data formats:
2
I
S
Left-JustifiedDSP Mode

4.7.1. Audio Data Formats

2
In I
S mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high.
In Left-Justified mode, by default the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low.
In DSP mode, the DFS becomes a pulse with a width of 1 DCLK period. The left channel is transferred first, followed right away by the right channel. When transferring the digital audio data in DSP mode, the MSB of the left channel can be transfer red on the first rising edge of DCLK following the DFS p ulse or on the second rising edge.
In all audio formats, depending on the word size, DCLK frequency, and sample rates, there may be unused DCLK cycles after the LSB of each word and before the next DFS transition and MSB of the next word. In addition, if preferred, the user can configure the MSB to be captured on the falling edge of DCLK via properties.
The number of audio bits can be configured for 8, 16, 20, or 24 bits.

4.7.2. Audio Sample Rates

The device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 kHz. The digital audio interface enables low-power operation by eliminating the need for redundant DACs on the audio baseband processor.
Si4734/35-B20
Rev. 1.0 21
Si4734/35-B20
(OFALL = 1)
(OFALL = 0)
2
S
I
(OMODE = 0000)
(OFALL = 1)
(OFALL = 0)
Left-Justified
(OMODE = 0110)
(OFALL = 0)
(OMODE = 1100)
(OMODE = 1000)
INVERTED
DOUT
INVERTED
(MSB at 1
(MSB at 2
DCLK
DCLK
DFS
DCLK
DCLK
DFS
DOUT
st
rising edge)
nd
rising edge)
DCLK
DFS
DOUT
DOUT
LEFT CHANNEL
1 DCLK 1 DCLK
132nn-1
n-2
LSBMSB

Figure 10. I2S Digital Audio Format

LEFT CHANNEL
132nn-1n-2
LSBMSB
132

Figure 11. Left-Justified Digital Audio Format

132nn-1n-2
1 DCLK
132nn-1n-2
LEFT CHANNEL
LEFT CHANNEL
132
LSBMSB
LSBMSB

Figure 12. DSP Digital Audio Format

RIGHT CHANNEL
132n
RIGHT CHANNEL
n-2
RIGHT CHANNEL
RIGHT CHANNEL
132
n-1n-2
LSBMSB
nn-1
LSBMSB
nn-1n-2
LSBMSB
nn-1n-2
LSBMSB
22 Rev. 1.0
Si4734/35-B20

4.8. Stereo Audio Processing

The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 13.
Mono Audio
Left + Right
Modulation Level
0575338231915

Figure 13. MPX Signal Spectrum

4.8.1. Stereo Decoder

The Si4734/35's integrated stereo decoder automatically decodes the MPX signal using DSP techniques. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L–R) signal. Output left and right channels are obtained by adding and subtracting the (L+R) and (L–R) signals respectively. The Si4735 uses frequency information from the 19 kHz stereo pilot to recover the 57 kHz RDS/RBDS signal.

4.8.2. Stereo-Mono Blending

Adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. Stereo/mono status can be monitored with the FM_RSQ_STATUS command. Mono operation can be forced with the FM_BLEND_MONO_THRESHOLD property.
Stereo
Pilot
Frequency (kHz)
Stereo Audio
Left - Right
RDS/
RBDS

4.9. De-emphasis

Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si4734/35 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions. The de­emphasis time constant is programmable to 50 or 75 µs and is set by the FM_DEEMPHASIS property.

4.10. Stereo DAC

High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted. Volume is adjusted digitally with the RX_VOLUME property.

4.11. Soft Mute

The soft mute feature is available to attenuate the aud i o outputs and minimize audible noise in very weak signal conditions. The softmute attenuation level is adjustable using the FM_SOFT_MUTE_MAX_ATTENUATION and AM_SOFT_MUTE_MAX_ATTENUATION properties.

4.12. RDS/RBDS Processor (Si4735 Only)

The Si4735 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction.
The Si4735 device is user configurable and provides an optional interrupt when RDS is synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met.
The Si4735 reports RDS decoder synchronization status, and detailed bit errors in the information word for each RDS block with the FM_RDS_STATUS command. The range of reportable block errors is 0, 1–2, 3–5, or 6+. More than six errors indicates that the corresponding block information word contains six or more non-correctable errors, or that the block checkword contains errors.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
Rev. 1.0 23
Si4734/35-B20

4.13. Tuning

The frequency synthesizer uses Silicon Laboratories’ proven technology, including a completely integrated VCO. The frequency synthesizer generates the quadrature local oscillator signal used to downconvert the RF input to a low intermediate frequ ency. The VCO frequency is locked to the reference clock and adjusted with an automatic frequency control (AFC) servo loop during reception. The tuning frequency can be directly programmed using the FM_TUNE_FREQ and AM_TUNE_FREQ commands. The Si4734/35 supports channel spacing steps of 10 kHz in FM mode and 1 kHz in AM/SW/LW mode.

4.14. Seek

Seek tuning will search up or down for a valid channel. Valid channels are found when the receive signal strength indicator (RSSI) and the signal-to-noise ratio (SNR) values exceed the set threshold. Using the SNR qualifier rather than solely relying on the more traditional RSSI qualifier can reduce false stops and increase the number of valid stations detected. Seek is initiated using the FM_SEEK_START and AM_SEEK_START commands. The RSSI and SNR threshold settings are adjustable using properties (see Table 15).
Two seek options are available. The device will either wrap or stop at the band limits. If the seek operation is unable to find a channel, the device will indicate failure and return to the channel selected before the seek operation began.

4.15. Reference Clock

The Si4734/35 reference clock is programmable, supporting RCLK frequencies in Table 12. Refer to Table 3, “DC Characteristics,” on page 5 for switching voltage levels and Table 9, “FM Receiver Characteristics” on page 12 for frequency tolerance information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load capacitors are provided. Refer to "2. Typical Application Schematic" on page 17. This mode is enabled using the POWER_UP command, see Table 14, “Si473x Command Summary,” on page 27.
The Si4734/35 performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4734/35 is performing the seek/tune function, the crystal oscillator may experience jitter, which may result in mistunes, false stops, and/or lower SNR.
For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4734/35 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The seek/tune complete (STC) interrupt should be used instead of polling to determine when a seek/tune operation is complete.

4.16. Control Interface

A serial port slave interface is provided, which allows an external controller to send commands to the Si4734/35 and receive responses from the device. The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4734/35 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST an internal pull-up resistor, which is connected while
is low, and the GPO2 pin includes an internal pull-
RST down resistor, which is connected while RST Therefore, it is only necessary for the user to actively drive pins which differ from these states. See Table 13.
Table 13. Bus Mode Select on Rising Edge of
Bus Mode GPO1 GPO2
2-Wire 1 0
SPI 1 1 (must drive)
3-Wire 0 (must drive) 0
After the rising edge of RST are used as general purpose output (O) pins, as described in Section “4.17. GPO Outputs”. In any bus mode, commands may only be sent after V supplies are applied.
In any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (CTS bit is high).

4.16.1. 2-Wire Control Interface Mode

When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST high until after the first start condition. Also, a start condition must not occur within 300 ns before the rising edge of RST
The 2-wire bus mode uses only the SCLK and SDIO pins for signaling. A transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the user drives an 8-bit contro l word serially on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 7-bit device address, followed by a read/write bit (read = 1, write = 0). The Si4734/35 acknowledges the control
.
. The GPO1 pin includes
is low.
RST
, the pins GPO1 and GPO2
and V
IO
, and stays
DD
24 Rev. 1.0
Si4734/35-B20
word by driving SDIO low on the next falling edge of SCLK.
Although the Si4734/35 will respond to only a single device address, this address can be changed with the
pin (note that the SEN pin is not used for signaling
SEN in 2-wire mode). When SEN address is 0010001b. When SEN
= 0, the 7-bit device
= 1, the address is
1100011b. For write operations, the user then sends an 8-bit data
byte on SDIO, which is captured by the de vice on ris ing edges of SCLK. The Si4734/35 acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The user may write up to 8 data bytes in a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments.
For read operations, after the Si4734/35 has acknowledged the control byte, it will drive an 8-bit data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The user acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction will end. The user may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si4734/35.
A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer to Table 5, “2-Wire Control Interface Characteristics” on page 7; Figure 2, “2-Wire Control Interface Read and Write Timing Parameters,” on page 8, and Figure 3, “2­Wire Control Interface Read and Write T iming Diagram,” on page 8.

4.16.2. 3-Wire Control Interface Mode

When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST
.
The 3-wire bus mode uses the SCLK, SDIO, and SEN pins. A transaction begins when the user drives SEN low. Next, the user drives a 9-bit control word on SDIO, which is captured by the device on rising edges of SCLK. The control word consists of a 9-bit device address (A7:A5 = 101b), a read/write bit (read = 1, write = 0), and a 5-bit register address (A4:A0).
For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising edges of SCLK.
For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4734/35 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK.
A transaction ends when the user sets SEN
high, then pulses SCLK high and low one final time. SCLK may either stop or continue to toggle while SEN
is high.
In 3-wire mode, commands are sent by first writing each argument to register(s) 0xA1–0xA3, then writing the command word to register 0xA0. A response is retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer to Table 6, “3-Wire Control Interface Characteristics,” on page 9; Figure 4, “3-Wire Control Interface Write Timing Parameters,” on page 9, and Figure 5, “3-Wire Control Interface Read Timing Parameters,” on page 9.

4.16.3. SPI Control Interface Mode

When selecting SPI mode, the user must ensu re that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST
.
SPI bus mode uses the SCLK, SDIO, and SEN read/write operations. The system controller can choose to receive read data from the device on either SDIO or GPO1. A transaction begins when the system controller drives SEN
= 0. The system controller then pulses SCLK eight times, while driving an 8-bit control byte serially on SDIO. The device captures the data on rising edges of SCLK. The control byt e must have one of five values:
0x48 = write a command (controller drives 8
additional bytes on SDIO).
0x80 = read a response (device drives 1additional
byte on SDIO).
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
0xA0 = read a response (device drives 1 additional
byte on GPO1).
0xE0 = read a response (device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
_
exactly 8 data bytes (a command and seven argument s) on SDIO after the control byte. The data is captured by the device on the rising edge of SCLK.
For read operations, the controller must read exactly 1 byte (STATUS) after the control byte or exactly 16 data bytes (STATUS and RESP1–RESP15) after the control byte. The device changes the state of SDIO (or GPO1, if specified) on the falling edge of SCLK. Data must be captured by the system controller on the rising edge of SCLK.
Keep SEN
low until all bytes have transferred. A transaction may be aborted at any time by setting SEN high and toggling SCLK high and then low. Commands
pins for
Rev. 1.0 25
Si4734/35-B20
will be ignored by the device if the transaction is aborted.
For details on timing specifications and diagrams, refer to Figure 6 and Figure 7 on page 10.

4.17. GPO Outputs

The Si4734/35 provides five general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. GPO2/INT GPO3 can be configured to provide external crystal support or as DCLK in digital audio output mode. In digital output mode (Si4735 only), GPO6 and GPO7 can be configured as DFS and DOUT respectively.
can be configured to provide interrupts and

4.18. Firmware Upgrades

The Si4734/35 contains on-chip program RAM to accommodate minor changes to the firmware. This allows Silicon Labs to provide future firmware updates to optimize the characteristics of new radio designs and those already deployed in the field.

4.19. Reset, Power Up, and Power Down

Setting the RST pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. Setting the RST pin high will bring the device out of reset.
A power down mode is available to reduce power consumption when the part is idle. Putting the device in power down mode will disable analog and digital circuitry while keeping the bus active.

4.20. Programming with Commands

To ease development time and offer maximum customization, the Si4734/35 provides a simple yet powerful software interface to prog ram the r eceiver. The device is programmed using commands, arguments, properties and responses.
To perform an action, the user writes a command byte and associated arguments, causing the chip to execute the given command. Commands control an action such as power up the device, shut down the device, or tune to a station. Arguments are sp ecific to a given command and are used to modify the command. A complete list of commands is available in Table 14, “Si473x Command Summary,” on page 27.
Properties are a special command argument used to modify the default chip operation and are generally configured immediately after power up. Examples of properties are de-emphasis level, RSSI seek threshold, and soft mute attenuation threshold. A complete list of properties is available in Table 15, “Si473x Property Summary,” on page 28.
Responses provide the user information and are echoed after a command and associated arguments are issued. All commands provide a one-byte status update indicating interrupt and clear-to-s en d status infor m at i on . For a detailed description of the commands and properties for the Si4734/35, see “AN332: Universal Programming Guide.”
26 Rev. 1.0

5. Commands and Properties

Table 14. Si473x Command Summary

Cmd Name Description
Si4734/35-B20
0x01 POWER_UP 0x10 GET_REV Returns revision information on the device.
0x11 POWER_DOWN Power down device. 0x12 SET_PROPERTY Sets the value of a property. 0x13 GET_PROPERTY Retrieves a property’s value. 0x14 GET_INT_STATUS Read interrupt status bits. 0x15 PATCH_ARGS Reserved command used for firmware file downloads. 0x16 PATCH_DATA Reserved command used for firmware file downloads. 0x20 FM_TUNE_FREQ Selects the FM tuning frequency. 0x21 FM_SEEK_START Begins searching for a valid frequency
0x22 FM_TUNE_STATUS
0x23 FM_RSQ_STATUS
0x24 FM_RDS_STATUS 0x40 AM_TUNE_FREQ Tunes to a given AM or SW/LW frequency. 0x41 AM_SEEK_START
0x42 AM_TUNE_STATUS 0x43 AM_RSQ_STATUS Queries the status of the RSQ for the current channel.
0x80 GPO_CTL Configures GPO pins. 0x81 GPO_SET Sets the value of the GPO pins.
Power up device and mode selection. Modes include AM/SW/LW or FM receive, analog or digital output, and referenc e cloc k or cry s tal support.
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START command.
Queries the status of the Received Signal Quality (RSQ) of the current chan­nel (Si4735 only).
Returns RDS information for current channel and reads an entry from the RDS FIFO (Si4735 only).
Begins searching for a valid AM or SW/LW frequency depending on the AM_SEEK_BAND_BOTTOM and AM_SEEK_BAND_TOP settings.
Queries the status of the already issued AM_TUNE_FREQ or AM_SEEK_START command.
Rev. 1.0 27
Si4734/35-B20

Table 15. Si473x Property Summary

Prop Name Description Default
0x0001 GPO_IEN Enables interrupt sources. 0x0000 0x0102 DIGITAL_OUTPUT_FORMAT Configures the digital output format (Si4735 only). 0x0000
0x0104
0x0201 REFCLK_FREQ 0x0202 REFCLK_PRESCALE Sets the prescaler value for RCLK input. 0x0001
0x1100 FM_DEEMPHASIS Sets de-emphasis time constant. Default is 75 us. 0x0002
0x1105
0x1106
0x1108
0x1200
0x1201
0x1202
0x1203
0x1204
0x1207
0x1302
0x1303
0x1400 0x1401 FM_SEEK_BAND_TOP Sets the top of the FM band for seek. Default is 10790. 0x2A26 0x1402
0x1403
0x1404 0x1500 RDS_INT_SOURCE Configures RDS interrupt behavior. 0x0000 0x1501 RDS_INT_FIFO_COUNT
DIGITAL_OUTPUT_
SAMPLE_RATE
FM_BLEND_STEREO_
THRESHOLD
FM_BLEND_MONO_
THRESHOLD
FM_MAX_TUNE_
ERROR
FM_RSQ_INT_
SOURCE
FM_RSQ_SNR_HI_
THRESHOLD
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
FM_SOFT_MUTE_
MAX_ATTENUATION
FM_SOFT_MUTE_
SNR_THRESHOLD
FM_SEEK_BAND_
BOTTOM
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
FM_SEEK_TUNE_
RSSI_TRESHOLD
Configures the digital output sample rate in 100 Hz steps. The digital output sample rate is disabled by default (Si4735 only).
Sets frequency of reference clock in Hz. The range is 31130 to 34406 Hz, or 0 to disable the AFC. Default is 32768 Hz.
Sets RSSI threshold for stereo blend (full stereo above thresh­old, blend below threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 49 dBuV.
Sets RSSI threshold for mono bl end (full mono below thresh old, blend above threshold). To force stereo set this to 0. To force mono set this to 127. Default value is 30 dBuV.
Sets the maximum freq error allowed before setting th e AFC rail (AFCRL) indicator. Default value is 30 kHz.
Configures interrupt related to RSQ metrics. 0x0000
Sets high threshold for SNR interrupt. 0x007F
Sets low threshold for SNR interrupt. 0x0000
Sets high threshold for RSSI interrupt. 0x007F
Sets low threshold for RSSI interrupt. 0x0000 Sets the blend threshold for blend interrupt when bou ndary is
crossed. Sets maximum attenuation during soft mute (d B). Set to 0 to dis-
able soft mute. Default is 16 dB. Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004
Sets the bottom of the FM band for seek. Default is 8750. 0x222E
Selects frequency spacing for FM seek. 0x000A Sets the SNR threshold for a valid FM Seek/T une. Default value
is 3 dB. Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
Sets the minimum number of RDS groups stored in the receive RDS FIFO required before RDS RECV is set.
0x0000
0x8000
0x0031
0x001E
0x001E
0x0081
0x0010
0x0003
0x0014
0x0000
28 Rev. 1.0
Si4734/35-B20
Table 15. Si473x Property Summary (Continued)
Prop Name Description Default
0x1502 RDS_CONFIG Configures RDS setting. 0x0000 0x3100 AM_DEEMPHASIS
0x3102 AM_CHANNEL_FILTER
0x3200 AM_RSQ_INTERRUPTS
0x3201
0x3202
0x3203
0x3204
0x3300 AM_SOFT_MUTE_RATE
0x3301 AM_SOFT_MUTE_SLOPE
AM_RSQ_SNR_HIGH_
THRESHOLD
AM_RSQ_SNR_LOW_
THRESHOLD
AM_RSQ_RSSI_HIGH_
THRESHOLD
AM_RSQ_RSSI_LOW_
THRESHOLD
Sets de-emphasis time constant. Can be set to 50 us. De­emphasis is disabled by default.
Selects the bandwidth of the channel filter for AM/SW/LW recep­tion. The choices are 6, 4, 3, 2, or 1 (kHz). The default band­width is 2 kHz.
Configures interrupt related to RSQ metrics. All interrupts are disabled by default.
Sets high threshold for SNR interrupt. The default is 0 dB. 0x007F
Sets low threshold for SNR interrupt. The default is 0 dB. 0x0000
Sets high threshold for RSSI interrupt. The default is 0 dB. 0x007F
Sets low threshold for RSSI interrupt. The default is 0 dB. 0x0000 Sets the rate of attack when entering or leaving soft mute. The
default is 278 dB/s. Sets the AM/SW/LW soft mute slope. The bigger the number,
the higher the max attenuation level. Default value is a slope of 2.0x0002
0x0000
0x0003
0x0000
0x0040
0x3302
0x3303
0x3400 0x3401 AM_SEEK_BAND_TOP Sets the top of the AM/SW/LW band for seek. Default is 1720. 0x06AE 0x3402
0x3403
0x3404
0x4000 RX_VOLUME Sets the output volume. 0x003F 0x4001 RX_HARD_MUTE
AM_SOFT_MUTE_MAX_
ATTENUATION
AM_SOFT_MUTE_SNR_
THRESHOLD
AM_SEEK_BAND_
BOTTOM
AM_SEEK_FREQ_
SPACING
AM_SEEK_SNR_
THRESHOLD
AM_SEEK_RSSI_
THRESHOLD
Sets maximum attenuation during soft mute (d B). Set to 0 to dis­able soft mute. Default is 16 dB.
Sets SNR threshold to engage soft mute. Default is 10 dB. 0x000A
Sets the bottom of the AM/SW/LW band for seek. Default is 520. 0x0208
Selects frequency spacing for AM/SW/LW seek. Default is 10 kHz spacing.
Sets the SNR threshold for a valid AM/SW/LW Seek/Tune. If the value is zero then SNR threshold is not considered when doing a seek. Default value is 5 dB.
Sets the RSSI threshold for a valid AM/SW/LW Seek/Tune. If the value is zero then RSSI threshold is not considered when doing a seek. Default value is 25 dBuV.
Mutes the audio output. L and R audio outputs may be muted independently in FM mode.
0x0010
0x000A
0x0005
0x0019
0x0000
Rev. 1.0 29
Si4734/35-B20

6. Pin Descriptions: Si4734/35-GM

NC
1
FMI
2
NC
GPO1
GPO2/INT
GPO3/DCLK
DFS
17181920
16
15
DOUT
RFGND
AMI
3 4
GND
PAD
5
6
7 8 9
SEN
Pin Number(s) Name Description
1, 20 NC No connect. Leave floating.
2FMIFM RF inputs. 3 RFGND RF ground. Connect to ground plane on PCB. 4 AMI AM/SW/LW RF input. 5RST 6 SEN 7 SCLK Serial clock input. 8 SDIO Serial data input/output.
Device reset (active low) input. Serial enable input (active low).
SCLK
SDIO
10
VIO
RCLK
14 13 12
11
LOUT ROUT GNDRST VDD
9 RCLK External reference oscillator input. 10 V 11 V
12, GND PAD GND Ground. Connect to ground plane on PCB.
13 ROUT Right audio line output in analog output mode. 14 LOUT Left audio line output in analog output mode. 15 DOUT Digital output data in digital output mode. 16 DFS Digital frame synchronization input in digital output mode. 17 GPO3/DCLK General purpose output, crystal oscillator, or digital bit synchronous clock input
18 GPO2/INT 19 GPO1 General purpose output.
30 Rev. 1.0
IO
DD
I/O supply voltage. Supply voltage. May be connected directly to battery.
in digital output mode. General purpose output or interrupt pin.

7. Ordering Guide

Si4734/35-B20
Part Number* Description Package
Type
Si4734-B20-GM AM/FM/SW/LW Broadcast Radio Receiver QFN
Pb-free
Si4735-B20-GM AM/FM/SW/LW Broadcast Radio Receiver with
RDS/RBDS
*Note: Add an “(R)” at th e end of the device part number to denote tape and reel option; 2500 quantity per reel.
QFN
Pb-free
Operating
Temperature
–20 to 85 °C
–20 to 85 °C
Rev. 1.0 31
Si4734/35-B20

8. Package Markings (Top Marks)

8.1. Si4734/35 Top Mark

3420 BTTT
3520 BTTT
YWW

8.2. Top Mark Explanation

Mark Method: YAG Laser Line 1 Marking: Part Number 34 = Si4734, 35 = Si4735
Firmware Revision 20 = Firmware Revision 2.0
Line 2 Marking: Die Revision B = Revision B Die
TTT = Internal Code Internal tracking code.
Line 3 Marking: Circle = 0.5 mm Diameter
(Bottom-Left Justified) Y = Year
WW = Workweek
Pin 1 Identifier
Assigned by the Assembly House. Corresponds to the last sig­nificant digit of the year and workweek of the mold date.
YWW
32 Rev. 1.0
Si4734/35-B20

9. Package Outline: Si4734/35 QFN

Figure 14 illustrates the package details for the Si4734/35. Table 16 lists the values for the dimensions shown in the illustration.

Figure 14. 20-Pin Quad Flat No-Lead (QFN)

Table 16. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.50 0.55 0.60 f 2.53 BSC
A1 0.00 0.02 0.05 L 0.35 0.40 0.45
b 0.200.250.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05
D 3.00 BSC bbb — — 0.05
D2 1.65 1.70 1.75 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 3.00 BSC eee — — 0.10
E2 1.65 1.70 1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0 33
Si4734/35-B20

10. PCB Land Pattern: Si4734/35 QFN

Figure 15 illustrates the PCB land pattern details for the Si4734/35-GM. Table 17 lists the values for the dimensions shown in the illustration.

Figure 15. PCB Land Pattern

34 Rev. 1.0
Si4734/35-B20

Table 17. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters
Min Max Min Max
D 2.71 REF GE 2.10 —
D2 1.60 1.80 W — 0.34
e 0.50 BSC X — 0.28
E 2.71 REF Y 0.61 REF
E2 1.60 1.80 ZE — 3.31
f 2.53 BSC ZD — 3.31
GD 2.10 —
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.0 35
Si4734/35-B20

11. Additional Reference Resources

EN55020 Compliance Test CertificateAN231: Si4700/01 Headphone and Antenna InterfaceAN332: Universal Programming GuideAN383: Antenna Selection and Universal Layout GuidelinesAN386: Si473x Ferrite Loop Stick Antenna InterfaceAN388: Universal Evaluation Board Test ProcedureAN389: Si473x EVB Quick-Start GuideSi47xx Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation boar d schematics and layouts, an d evaluation softwa re. NDA is required for access. To request access, register at http://www.mysila bs.com and send user’s first and last name, company, NDA reference number, and mysilabs user name to fminfo@silabs.com. Silicon Labs recommends an all lower case user name.
36 Rev. 1.0

DOCUMENT CHANGE LIST

Revision 0.4 to Revision 1.0
Updated Table 1, “Recommended Operating
Conditions,” on page 4.
Updated Table 3, “DC Characteristics,” on page 5.Updated Table 5, “2 -Wir e Co ntr o l Inte rf ace
1,2,3
Characteristics
Updated Table 8, “Dig ital Audio Inte rf ace
Characteristics,” on page 11.
Updated Table 9, “F M Re ce iver Cha ra cte r istics
on page 12.
Updated Table 10, “64–75.9 MHz Input Frequency
FM Receiver Characteristics
Updated Table 12, “Reference Clock and Crystal
Characteristics,” on page 16.
Updated "2. Typical Application Schematic" on page
17.
Updated "3. Bill of Materials" on page 18.Updated "11. Additional Reference Resources" on
page 36.
,” on page 7.
1
,” on page 14.
1,2
,”
Si4734/35-B20
Rev. 1.0 37
Si4734/35-B20

CONTACT INFORMATION

Silicon Laboratories Inc.
400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032
Email: FMinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep­resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse­quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per­sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap­plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
38 Rev. 1.0
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