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SI4734-35-B20
User Manual
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Silicon Laboratories SI4734-35-B20 User Manual

Si4734/35-B20
BROADCAST AM/FM/SW/LW RADIO RECEIVER

Features

Worldwide FM band support
(64–108 MHz)
Worldwide AM band support
(520–1710 kHz)
SW band support (2.3–21.85 MHz)LW band support (153–279 KHz)Excellent real-world performanceFreq synthesizer with integrated VCOAutomatic frequency control (AFC)Automatic gain control (AGC)Integrated LDO regulatorDigital FM stereo decoderProgrammable de-emphasisAdaptive noise suppressionAM/FM/SW/LW digital tuning
No manual alignment necessaryAdjustable channel filtersEN55020 complaintProgrammable reference clockDigital volume controlAdjustable soft mute controlRDS/RBDS processor (Si4735 only)Optional digital audio out (Si4735 only)2-wire and 3-wire control interf ace2.7 to 5.5 V supply voltageWide range of ferrite loop sticks and air
loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
z Pb-free/RoHS compliant

Applications

Table and portable radiosStereosMini/micro systemsCD/DVD playersPortable media playersBoom boxes
Cellular handsetsModulesClock radiosMini HiFiEntertainment systems

Description

The Si4734/35 is the first digital CMOS AM/FM/SW/LW radio receiver IC that integrates the complete tuner function from antenna input to audio output.
Ordering Information:
See page 31.
Pin Assignments
Si4734/35-GM
(Top View)
NC
GPO1
1
NC
2
FMI
AMI
3 4 5
6
SEN
GND PAD
7 8 9
SDIO
SCLK
RFGND
GPO2/INT
GPO3/DCLK
DFS
17181920
16
15
DOUT LOUT
14 13
ROUT GNDRST
12
11
10
RCLK
VDD
VIO
AM / LW
ANT
2.7 - 5.5 V
FM / SW
ANT
RFGND
FMI
AMI
VDD GND
LNA
AGC
LNA
AGC
LDO
ADC
ADC
AFC
RCLK
Si4734/35
RDS
(Si4735)
LOW-IF
DSP
CONTROL
INTERFACE
SEN
SCLK
DIGITAL
AUDIO
(Si4735)
DAC
DAC
SDIO
Patents pending
DOUT DFS GPO/DCLK
ROUT
LOUT
VIO
1.5-3.6V
RST
Notes:
1. To ensure proper operation and
receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. Place Si4734/35 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
Rev. 1.0 4/08 Copyright © 2008 by Silicon Laboratories Si4734/35-B20
Si4734/35-B20
2 Rev. 1.0
Si4734/35-B20
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4. AM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.5. SW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6. LW Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.7. Digital Audio Interface (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.9. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.11. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.12. RDS/RBDS Processor (Si4735 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.13. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.14. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.18. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.19. Reset, Power Up, and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Pin Descriptions: Si4734/35-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si4734/35 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Package Outline: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10. PCB Land Pattern: Si4734/35 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
26
Rev. 1.0 3
Si4734/35-B20

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage V Interface Supply V oltage V Power Supply Powerup Rise Time V
Interface Power Supply Powerup Rise Time V Ambient Temperature T
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V otherwise stated.
Table 2. Absolute Maximum Ratings
= 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
DD
1,2
DD
IO
DDRISE
IORISE
A
2.7 — 5.5 V
1.5 — 3.6 V 10 — — µs
10 — — µs
–20 25 85 °C
Parameter Symbol Value Unit
Supply Voltage V Interface Supply V oltage V Input Current Input Voltage
3 3
Operating Temperature T Storage Temperature T RF Input Level
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability.
2. The Si4734/35 devices are high-performance RF integrated circuits with certain pins having an ESD rati ng of < 2 kV HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
DD
IO
I
IN
V
OP
STG
IN
–0.5 to 5.8 V –0.5 to 3.9 V
10 mA
–0.3 to (VIO + 0.3) V
–40 to 95 °C
–55 to 150 °C
0.4 V
pK
4 Rev. 1.0

Table 3. DC Characteristics

(V
= 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
DD
Parameter Symbol Test Condition Min Typ Max Unit
FM Mode
Si4734/35-B20
Supply Current I Supply Current RDS Supply Current Supply Current
1
2
2
FM
I
FM
I
FM
I
FMD
Low SNR level — 19.8 23 mA
Digital Output Mode — 18.0 20.5 mA
—19.222mA
—19.923mA
AM/SW/LW Mode
Supply Current I Supply Current
2
AM
I
AMD
Analog Output Mode — 17.3 20.5 mA
Digital Output Mode — 15.5 20.5 mA
Supplies and Interface
Interface Supply Current I V
Powerdown Current I
DD
V
Powerdown Current I
IO
High Level Input Volt age Low Level Input Voltage High Level Input Current Low Level Input Current
High Level Output Voltage Low Level Output Voltage
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, and DFS.
4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
3
3
3
3
4
4
IO
DDPD
IOPD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
SCLK, RCLK inactive — 1 10 µA
VIN = VIO = 3.6 V –10 — 10 µA
VIN=0V,
=3.6V
V
IO
I
= 500 µA 0.8 x V
OUT
I
= –500 µA — — 0.2 x V
OUT
—320600µA —1020 µA
0.7 x V
IO
—VIO+0.3 V
–0.3 — 0.3 x V
–10 — 10 µA
IO
——V
IO
IO
V
V
Rev. 1.0 5
Si4734/35-B20
Table 4. Reset Timing Characteristics
(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
1,2,3
Parameter Symbol Min Typ Max Unit
RST
Pulse Width and GPO1, GPO2/INT Setup to RST↑
GPO1, GPO2/INT
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST after the first start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the rising edge of RST
4. If GPO1 and GPO2 are actively driven by the user, then minimum t minimum t GPO2 low.
Hold from RST↑ t
.
is 100 µs, to provide time for on-chip 1 MΩ devices (active while RST is low) to pull GPO1 high and
SRST
70%
RST
30%
4
t
SRST
t
SRST
HRST
t
HRST
100 — — µs
30 — — ns
, and stays high until
is only 30 ns. If GPO1 or GPO2 is hi-Z, then
SRST
INT
70% 30%
70% 30%
GPO1
GPO2/

Figure 1. Reset Timing Parameters for Busmode Select

6 Rev. 1.0
Si4734/35-B20
Table 5. 2-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
1,2,3
Parameter Symbol Test Condition M in Typ M ax Unit
SCLK Frequency f SCLK Low Time t SCLK High Time t SCLK Input to SDIO
↓ Setup
t
SCL
LOW
HIGH
SU:STA
0—400kHz
1.3 — — µs
0.6 — — µs
0.6 — — µs
(START) SCLK Input to SDIO
SDIO Input to SCLK SDIO Input to SCLK SCLK input to SDIO
↓ Hold (START) t ↑ Setup t ↓ Hold
4,5
↑ Setup (STOP) t
t
STOP to START Time t SDIO Output Fall Time t
HD:STA SU:DAT HD:DAT SU:STO
BUF
f:OUT
0.6 — — µs
100 — — ns
0—900ns
0.6 — — µs
1.3 — — µs —250ns
C
b
20 0.1
---------- -
+
1pF
SDIO Input, SCLK Rise/Fall Time t
SCLK, SDIO Capacitive Loading C Input Filter Pulse Suppression t
Notes:
1. When VIO= 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high)
does not occur within 300 ns before the rising edge of RST
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST after the first start condition.
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the V t
specification.
HD:DAT
5. The maximum t as long as all other timing parameters are met.
has only to be met when f
HD:DAT
t
f:IN r:IN
SP
C
b
20 0.1
b
---------- -
+
1pF
— — 50 pF — — 50 ns
.
threshold of SCLK to comply with the minimum
IH
= 400 kHz. At frequencies below 400 KHz, t
SCL
—300ns
, and stays high until
may be violated
HD:DAT
Rev. 1.0 7
Si4734/35-B20
SCLK
SDIO
SCLK
SDIO
70% 30%
70% 30%
t
SU:STA
t
HD:STA
START
t
LOW
t
r:IN
t
HIGH
t
HD:DAT
t
SU:DAT
t
r:IN
t
f:IN
t
SP
t
f:IN,
t
f:OUT

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

A6-A0,
R/W
D7-D0 D7-D0
t
SU:STO
t
BUF
STARTSTOP
START STOPADDRESS + R/W ACK DATA ACK DATA ACK

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

8 Rev. 1.0
Si4734/35-B20

Table 6. 3-Wire Control Interface Characteristics

(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Un i t
SCLK Frequency f SCLK High Time t SCLK Low Time t SDIO Input, SEN
to SCLK↑ Setup t
SDIO Input to SCLK↑ Hold t
Input to SCLK↓ Hold t
SEN SCLK↑ to SDIO Output Valid t SCLK↑ to SDIO Output High Z t SCLK, SEN
, SDIO, Rise/Fall time tR, t
CLK
HIGH
LOW
S
HSDIO
HSEN
CDV
CDZ
F
Read 2 — 25 ns Read 2 — 25 ns
0—2.5MHz 25 — — ns 25 — — ns 20 — — ns 10 — — ns 10 — — ns
— — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
SEN
70% 30%
70% 30%
SCLK
.
t
t
R
t
S
F
t
HSDIO
t
S
t
HIGHtLOW
t
HSEN
SDIO
SCLK
SEN
SDIO
70% 30%
A7 A0
A6-A5,
R/W,
D15 D14-D1 D0
A4-A1
Address In Data In

Figure 4. 3-Wire Control Interface Write Timing Parameters

70% 30%
70% 30%
70%
30%
t
S
t
HSDIO
t
S
A6-A5,
A7 A0
R/W,
A4-A1
Address In Data Out
½ Cycle Bus
Turnaround
t
CDV
D15 D14-D1 D0

Figure 5. 3-Wire Control Interface Read Timing Parameters

t
HSEN
t
CDZ
Rev. 1.0 9
Si4734/35-B20

Table 7. SPI Control Interface Characteristics

(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Un i t
SCLK Frequency f SCLK High Time t SCLK Low Time t SDIO Input, SEN
to SCLK↑ Setup t
SDIO Input to SCLK↑ Hold t
Input to SCLK↓ Hold t
SEN
↓ to SDIO Output Valid t
SCLK
↓ to SDIO Output High Z t
SCLK SCLK, SEN
, SDIO, Rise/Fall time
CLK
HIGH
LOW
S
HSDIO
HSEN
CDV
CDZ
, t
t
R
F
Read 2 — 25 ns Read 2 — 25 ns
0—2.5MHz 25 — — ns 25 — — ns 15 — — ns 10 — — ns
5——ns
— — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST
SEN
70% 30%
70% 30%
SCLK
.
t
t
F
R
t
HIGHtLOW
t
S
t
S
t
HSDIO
t
HSEN
SDIO
SCLK
SEN
SDIO
70% 30%
70% 30%
70% 30%
70%
30%
C7 C0
C6–C1
Control Byte In 8 Da ta By te s In
D7 D6–D1 D0

Figure 6. SPI Control Interface Write Timing Parameters

t
CDV
t
S
t
S
C7 C0C6–C1
Control Byte In
t
HSDIO
Turnaround
D7 D6–D1 D0
Bus
16 Data Bytes Out
(SDIO o r G P O 1 )
t
HSEN

Figure 7. SPI Control Interface Read Timing Parameters

t
CDZ
10 Rev. 1.0

Table 8. Digital Audio Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si4734/35-B20
DCLK Cycle Time t DCLK Pulse Width High t DCLK Pulse Width Low t DFS Set-up Time to DCLK Rising Edge t DFS Hold Time from DCLK Rising Edge t DOUT Propagation Delay from DCLK Falling
t
PD:DOUT
Edge
t
DCH
t
DCL
DCLK
t
DCT
DFS
DCT DCH
DCL SU:DFS HD:DFS
t
HD:DFS
t
SU:DFS
26 — 1000 ns 10 — — ns 10 — — ns
5—— ns 5—— ns 0—12ns
DOUT
t
PD:OUT

Figure 8. Digital Audio Interface Timing Parameters, I2S Mode

Rev. 1.0 11
Si4734/35-B20
Table 9. FM Receiver Characteristics
(VDD= 2.7 to 5.5 V, VIO= 1.5 to 3.6V, TA= –20 to 85 °C)
1,2
Parameter Symbol Test Condition Min Typ Max Unit
Input Frequency f Sensitivity with Headphone
Network Sensitivity with 50 Ω Network
RDS Sensitivity
3,4,5
3,4,5,6
6
RF
(S+N)/N = 26 dB — 2.2 3.5 µV EMF
(S+N)/N = 26 dB — 1.1 — µV EMF
Δf = 2 kHz,
76 — 108 MHz
—15—µV EMF
RDS BLER < 5%
LNA Input Resistance LNA Input Capacitance Input IP3
6,8
AM Suppression
6,7
6,7
3,4,6,7
Adjacent Channel Selectivity Alternate Channel Selectivity Spurious Response Rejection Audio Output Voltage
3,4,7
Audio Output L/R Imbalance
6
3,7,9
Audio Frequency Response Low Audio Frequency Response High Audio Stereo Separation Audio Mono S/N Audio Stereo S/N Audio THD
3,4,5,7,10
4,5,7,10,11
3,7,9
De-emphasis Time Constant
7,9
6
m = 0.3 40 50 — dB ±200 kHz 35 50 — dB ±400 kHz 60 70 — dB
In-band 35 — — dB
6
6
–3 dB — — 30 Hz –3 dB 15 — — kHz
FM_DEEMPHASIS = 2 70 75 80 µs
345kΩ 456pF
100 105 — dBµV EMF
72 80 90 mV
—— 1 dB
25 — — dB 55 63 — dB
—58— dB —0.10.5 %
FM_DEEMPHASIS = 1 45 50 54 µs Audio Output Load Resistance Audio Output Load Capacitance
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and Universal Layout Guidelines.” Silicon Laboratories will evaluate schemati cs an d layouts for qualified customers.
3. F
4. Δf =22.5 kHz.
5. B
6. Guaranteed by characterization.
7. V
8. |f
9. Δf =75 kHz.
10. At L
11. Analog audio output mode.
12. At temperature (25°C).
=1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
MOD
= 300 Hz to 15 kHz, A-weighted.
AF
=1 mV.
EMF
– f1| > 2 MHz, f
2
and R
OUT
OUT
0
pins.
6,10
6,10
=2xf1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4734/35-GM" on page 30.
R
L
C
L
Single-ended 10 — — kΩ Single-ended — — 50 pF
RMS
12 Rev. 1.0
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