Silicon Laboratories SI4421 User Manual

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Si4421 Universal ISM Band
FSK Transceiver

DESCRIPTION

Silicon Labs’ Si4421 is a single chip, low power, multi-channel FSK

ransceiver designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 433, 868 and 915 MHz bands.
The Si4421 transceiver is a part of Silicon Labs’ EZRadio
line, which produces a flexible, low cost, and highly integrated solution

hat does not require production alignments. The chip is a complete
analog RF and baseband transceiver including a multi-band PLL
synthesizer with PA, LNA, I/Q down converter mixers, baseband filters
and amplifiers, and an I/Q demodulator. All required RF functions are
integrated. Only an external crystal and bypass filtering are needed for
operation.

The Si4421 features a completely integrated PLL for easy RF design,
and its rapid settling time allows for fast frequency-hopping, bypassin
multipath fading and interference to achieve robust wireless links. The
PLL’s high resolution allows the usage of multiple channels in any o

he bands. The receiver baseband bandwidth (BW) is programmable to
accommodate various deviation, data rate and crystal tolerance
requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external componen
and decoupling) are needed in most applications.

The Si4421 dramatically reduces the load on the microcontroller with

he integrated digital data processing features: data filtering, clock
recovery, data pattern recognition, integrated FIFO and TX data
register. The automatic frequency control (AFC) feature allows the use
of a low accuracy (low cost) crystal. To minimize the system cost, the
Si4421 can provide a clock signal for the microcontroller, avoiding the
need for two crystals.

For low power applications, the Si4421 supports low duty cycle
operation based on the internal wake-up timer.

FUNCTIONAL BLOCK DIAGRAM

MIX

I

MIX

AMP OC

Q

AMP OC

BB Amp/Filt./Limiter

WTM

with cal.

Low Power parts

Self cal.

I/Q

DEMOD

RSSI

15

ARSSI

2

1

SCK nSEL SDO nIRQ

SDI

3 4

DQDCOMP

AFC

ControllerXosc LBD

10

5

nRES

13

RF1

RF2

LNA

12

PA

PLL & I/Q VCO

ith cal.

CLK div

8 9

CLK

w

XTL /
REF

RF Parts Data processing units

TM

product

s (except crystal

DCLK /

7

CFIL /
FFIT /

clk

nINT /

Data Filt
CLK Rec

FIFO

16

VDI

FSK /

data

6

DATA /
nFFS

Bias

11

14

VDD

VSS

Si4421

PIN ASSIGNMENT

This document refers to Si4421-IC rev A1.

See www.silabs.com/integration for any applicable errata.

See back page for ordering information.

FEATURES

 Fully integrated (low BOM, easy design-in)
 No alignment required in production
 Fast-settling, programmable, high-resolution PLL synthesizer
 Fast frequency-hopping capability
 High bit rate (up to 115.2 kbps in digital mode and 256 kbps

in analog mode)

 Direct differential antenna input/output
 Integrated power amplifier
 Programmable TX frequency deviation (15 to 240 kHz)
 Programmable RX baseband bandwidth (67 to 400 kHz)
 Analog and digital RSSI outputs
 Automatic frequency control (AFC)
 Data quality detection (DQD)
 Internal data filtering and clock recovery
 RX synchron pattern recognition
 SPI compatible serial control interface
 Clock and reset signals for microcontroller
 16-bit RX Data FIFO
 Two 8-bit TX data registers
 Low power duty cycle mode
 Standard 10 MHz crystal reference with on-chip tuning
 Wake-u

p timer

 2.2 to 3.8 V supply voltage
 Low power consumption
 Low standby current (0.3 A)
 Compact 16 pin TSSOP package
 Supports very short packets (down to 3 bytes)
 Excellent temperature stability of the RF parameters
 Good adjacent channel rejection/blocking

TYPICAL APPLICATIONS

 Home security and alarm
 Remote control, keyless entry
 Wireless keyboard/mouse and other PC peripherals
 Toy controls
 Remote keyless entry
 Tire pressure monitoring
 Telemetry
 Personal/patient data logging
 Remote automatic meter reading

1

Si4421-DS rev 2.4r 0708

www.silabs.com

Si4421

DETAILED FEATURE-LEVEL DESCRIPTION

The Si4421 FSK transceiver is designed to cover the unlicensed
frequency bands at 433, 868 and 915 MHz. The device
facilitates compliance with FCC and ETSI requirements.

The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The Si4421 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna
tuning, an LNA with switchable gain, I/Q down converter mixers,
baseband filters and amplifiers, and an I/Q demodulator
followed by a data filter.

PLL

The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip crystal­controlled reference oscillator. The PLL’s high resolution allows the
usage of multiple channels in any of the bands.

RF Power Amplifier (PA)

The power amplifier has an open-collector differential output and
can directly drive different PCB antennas with a programmable
output power level. An automatic antenna tuning circuit is built in
to avoid costly trimming procedures and the so-called “hand
effect”.

LNA

The LNA has approximately 250 Ohm input impedance, which
functions well with the proposed antennas (see: Application
Notes available from www.silabs.com/integration)

If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct
matching and to minimize the noise figure of the receiver.

The LNA gain can be selected in four steps (between 0 and

-20dB relative to the highest gain) according to RF signal
strength. It can be useful in an environment with strong
interferers.

Baseband Filters

The receiver bandwidth is selectable by programming the
bandwidth (BW) of the baseband filters. This allows setting up
the receiver according to the characteristics of the signal to be
received.

An appropriate bandwidth can be chosen to accommodate
various FSK deviation, data rate and crystal tolerance
requirements. The filter structure is 7
pass with 40 dB suppression at 2 · BW frequency. Offset
cancellation is done by using a high-pass filter with a cut-off
frequency below 7 kHz.

th

order Butterworth low-

Full Baseband Amplifier Transfer Function

BW=67kHz

Data Filtering and Clock Recovery

Output data filtering can be completed by an external capacitor
or by using digital filtering according to the final application.

Analog operation: The filter is an RC type low-pass filter followed

a Schmitt-trigger (St). The resistor (10 kOhm) and the St are

by
integrated on the chip. An (external) capacitor can be chosen
according to the actual bit rate. In this mode, the receiver can
handle up to 256 kbps data rate. The FIFO cannot be used in this
mode and clock is not provided for the demodulated data.

Digital operation: A digital filter is used with a clock frequency at

mes the bit rate. In this mode, there is a clock recovery

29 ti
circuit (CR), which can provide synchronized clock to the data.
Using this clock the received data can fill a FIFO. The CR has
three operation modes: fast, slow, and automatic. In slow mode,
its noise immunity is very high, but it has slower settling time and
requires more accurate data timing than in fast mode. In
automatic mode, the CR automatically changes between fast and
slow mode. The CR starts in fast mode, then after locking, it
automatically switches to slow mode

(Only the digital data filter and the clock recovery use the bit rate
clock. For analog operation, there is no need for setting the
correct bit rate.)

2

Si4421

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level.
It goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available.
The RSSI settling time depends on the external filter capacitor.
Pin 15 is used as analog RSSI output. The digital RSSI can be
monitored by reading the status register.

Typical Analog ARSSI Voltage vs. RF Input Power

DQD

The operation of the Data Quality Detector is based on counting
the spikes on the unfiltered received data. High output signal
indicates an operating FSK transmitter within baseband filter
bandwidth from the local oscillator. DQD threshold parameter
can be set by using the Data Filter Command (page 19).

AFC

By using an integrated Automatic Frequency Control (AFC)
feature, the receiver can minimize the TX/RX offset in discrete
steps, allowing the use of:

 Narrower receiver bandwidth (i.e. increased

sensitivity)

 Higher data rate
 Inexpensive crystals

Crystal Oscillator

The Si4421 has a single-pin crystal oscillator circuit, which
provides a 10 MHz reference signal for the PLL. To reduce
external parts and simplify design, the crystal load capacitor is
internal and programmable. Guidelines for selecting the
appropriate crystal can be found later in this datasheet.

The transceiver can supply a clock signal for the microcontroller;
so accurate timing is possible without the need for a second
crystal.

When the microcontroller turns the crystal oscillator off by
clearing the appropriate bit using the Power Management
Command (page 15), the chip provides a fixed number (192)
further clock pulses (“clock tail”) for the microcontroller to let it
go to idle or sleep mode. If this clock output is not used, it is

of

suggested to turn the output buffer off by the Power
Management Command (page 15).

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA
typical) and can be programmed from 1 ms to several days with
an accuracy of ±10%.

The wake-up timer calibrates itself to the crystal oscillator at
every startup. For proper calibration of the wake-up timer the
crystal oscillator must be running before the wake-up timer is
enabled. The calibration process takes approximately 0.5ms.
For the crystal start up time (tsx), see page 11.

Event Handling

In order to minimize current consumption, the transceiver
supports different power saving modes. Active mode can be
initiated by several wake-up events (negative logical pulse on
nINT input, wake-up timer timeout, low supply voltage detection,
on-chip FIFO filled up or receiving a request through the serial
interface).

If any wake-up event occurs, the wake-up logic generates an
interrupt signal, which can be used to wake up the
microcontroller, effectively reducing the period the
microcontroller has to be active. The source of the interrupt can
be read out from the transceiver by the microcontroller through
the SDO pin.

Interface and Controller

An SPI compatible serial interface lets the user select the
frequency band, center frequency of the synthesizer, and the
bandwidth of the baseband signal path. Division ratio for the
microcontroller clock, wake-up timer period, and low supply
voltage detector threshold are also programmable. Any of these
auxiliary functions can be disabled when not needed. All
parameters are set to default after power-on; the programmed
values are retained during sleep mode. The interface supports
the read-out of a status register, providing detailed information
about the status of the transceiver and the received data.

The transmitter block is equipped with two 8-bit wide TX data
registers. It is possible to write 8 bits into the register in burst
mode and the internal bit rate generator transmits the bits out
with the predefined rate. For further details, see the TX Register
Buffered Data Transmission section (page 28).

is also possible to store the received data bits into a FIFO

It
register and read them out in a buffered mode.

3

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin Name Type Function

1 SDI DI Data input of the serial control interface

2 SCK DI Clock input of the serial control interface

3 nSEL DI Chip select input of the serial control interface (active low)

4 SDO DO Serial data output with bus hold

5 nIRQ DO Interrupt request output (active low)

FSK DI Transmit FSK data input (internal pull up resistor 133 k)

DATA DO Received data output (FIFO not used)

6

nFFS DI

DLCK DO Received data clock output (Digital filter used, FIFO not used)

7

CFIL AIO External data filter capacitor connection (Analog filter used)

FFIT DO FIFO interrupt (active high). In FIFO mode, when bit ef is set in Configuration Setting Command

8 CLK DO Microcontroller clock output

XTL AIO Crystal connection (the other terminal of crystal to VSS) or external reference input

9

REF AIO External reference input. Use 33 pF series coupling capacitor

10 nRES DIO Open drain reset output with internal pull-up and input buffer (active low)

11 VSS S Ground reference voltage

12 RF2 AIO RF differential signal input/output

13 RF1 AIO RF differential signal input/output

14 VDD S Positive supply voltage

15 ARSSI AO Analog RSSI output

nINT DI Interrupt input (active low)

16

VDI DO Valid data indicator output

Note: The actual mode of the multipurpose pins (pin 6 and 7) is dete

FIFO select input (active low). In FIFO mode, when bit ef is set in Configuration Setting Command,
page 15 (internal pull up resistor 133 k)

rmined by the TX/RX data I/O settings of the transceiver.

Si4421

4

Internal Pin Connections

Pin Name Internal connection

Si4421

Pin Name Internal connection

1 SDI

2 SCK

3 nSEL

4 SDO

5 nIRQ

FSK

6

DATA

PAD

VDD

VSS

1.5k

10 nRES

11 VSS

12 RF2

13 RF1

14 VDD

nFFS

DLCK

7

CFIL

FFIT

8 CLK

XTL

9

REF

PAD

VDD

VSS

15 ARSSI

nINT

16

10

VDI

5

PIN6 Logic Diagram (FSK /

Si4421

DATA / nFFS)

PIN10 Logic Diagram (nRES

* Note: These pins can be left floating.

I/O)

6

Typical Application

P7

P6

P5

P4

P3

P2

P1

P0

CLKin

nRESin

Typical application with FIFO usage

VDD

C1

2.2u

(optional)

VDI

SDI

SCK

nSEL

SDO

nIRQ

nFFS

FFIT

CLK

nRES

(optional)*

(optional)*

(optional)

(optional)

1

2
3

4

5

Si4421

6

7

8

16

15

14

13

12

11

10

9

Si4421

C3 C2

10n

TP

C4

2.2n

(opt.)

PCB

X1

10MHz

Antenna

Note: * Connections needed only in time critical applications

Recommended supply decoupling capacitor values

C2 and C3 should be 0603 size ceramic capacitors to achieve the best supply decoupling.

Band [MHz] C1 C2 C3

433 2.2µF 10nF 220pF

868 2.2µF 10nF 47pF

915 2.2µF 10nF 33pF

Pin Function vs. Operation Mode

Mode Bit setting Function Pin 6 Pin 7

el = 0 Internal TX data register disabled TX data input

Transmit

el = 1 Internal TX data register enabled

ef = 0 Receiver FIFO disabled RX data output

Receive

ef = 1 Receiver FIFO disabled

The el and ef bits can be found in the Configuration Setting Command on page 15. Bit el
Bit ef enables the FIFO mode.

Property C1 C2 C3

SMD size A 0603 0603

Dielectric Tantalum Ceramic Ceramic

nFFS input

(TX data register can be accessed)

RX data clock

nFFS input

(RX data FIFO can be accessed)

enables the internal TX data register.

Not used

output

FFIT output

7

GENERAL DEVICE SPECIFICATIONS

All voltages are referenced to Vss, the potential on the ground reference pin VSS.

Absolute Maximum Ratings (non-operating)

Symbol Parameter Min Max Units

Vdd Positive supply voltage -0.5 6 V

Vin Voltage on any pin (except RF1 and RF2) -0.5 Vdd+0.5 V

Voc Voltage on open collector outputs (RF1, RF2) -0.5 Vdd+1.5 (Note 1) V

I

Input current into any pin except VDD and VSS -25 25 mA

in

ESD Electrostatic discharge with human body model 1000 V

T

Storage temperature -55 125

st

Tld Lead temperature (soldering, max 10 s) 260

Recommended Operating Range

Symbol Parameter Min Max Units

Vdd Positive supply voltage 2.2 3.8 V

Voc Voltage range on open collector outputs (RF1, RF2) Vdd-1.5 (Note 2) Vdd+1.5 V

Top Ambient operating temperature -40 85

Note 1: The voltage on RF1 and RF2 pins can be higher than the actual Vdd but cannot exceed 7 V.

Note 2: The actual voltage on RF1 and RF2 pins can be lower than the current Vdd but never should go below 1.2 V.

o

C

o

C

o

C

Si4421

8

Si4421

ELECTRICAL SPECIFICATION

Test Conditions: Top = 27 oC; Vdd = Voc = 3.3 V

DC Characteristics

Symbol Parameter Conditions/Notes Min Typ Max Units

I

dd_TX_0

I

dd_TX_PMAX

I

dd_RX

Supply current
(TX mode, P

Supply current
(TX mode, P

= 0 dBm)

out

= P

out

max

)

Supply current (RX mode)

Ipd Standby current (Sleep mode) All blocks disabled 0.3 1 µA

Ilb

Low battery voltage detector current
consumption

Iwt Wake-up timer current consumption 1.5 3.5 µA

Ix Idle current Crystal oscillator on (Note 1) 0.6 1.2 mA

Vlb Low battery detect threshold Programmable in 0.1 V steps 2.25 3.75 V

V

Low battery detection accuracy ± 3 %

lba

Vil Digital input low level voltage 0.3·Vdd V

Vih Digital input high level voltage 0.7·Vdd V

Iil Digital input current V

Iih Digital input current V

Vol Digital output low level I

Voh Digital output high level I

433 MHz band 15

868 MHz band 16

915 MHz band 17

433 MHz band 22 26

868 MHz band 23 27

915 MHz band 24 28

433 MHz band 11 13

868 MHz band 12 14

915 MHz band 13 15

0.5 1.7 µA

= 0 V -1 1 µA

il

= Vdd, V

ih

= 2 mA 0.4 V

ol

= -2 mA Vdd-0.4 V

oh

= 3.8 V -1 1 µA

dd

mA

mA

mA

Notes are on page 12.

9

Si4421

AC Characteristics (PLL parameters)

Symbol Parameter Conditions/Notes Min Typ Max Units

f

PLL reference frequency (Note 2) 9 10 11 MHz

ref

fo

t

lock

t

stP

Receiver LO/Transmitter carrier
frequency

PLL lock time

PLL startup time (Note 10) With a running crystal oscillator 200 300 µs

AC Characteristics (Receiver)

Symbol Parameter Conditions/Notes Min Typ Max Units

BW Receiver bandwidth

BRRX FSK bit rate (Note 10) With internal digital filters 0.6 115.2 kbps

BRARX FSK bit rate (Note 10) With analog filter 256 kbps

P

Receiver Sensitivity

min

AFC

AFC locking range

range

IIP3

Input IP3

inh

IIP3

Input IP3 Out of band interferers l f-fo l > 4 MHz -18 dBm

outh

IIP3

IIP3 (LNA –6 dB gain)

inl

IIP3

IIP3 (LNA –6 dB gain) Out of band interferers l f-fo l > 4 MHz -12 dBm

outl

P

Maximum input power LNA: high gain 0 dBm

max

Cin RF input capacitance 1 pF

RSa RSSI accuracy ± 6 dB

RSr RSSI range 46 dB

RSps RSSI power supply dependency

C

Filter capacitor for ARSSI 1 nF

ARSSI

RS

RSSI programmable level steps 6 dB

step

RS

DRSSI response time

resp

P

Receiver spurious emission -60 dBm

sp_rx

433 MHz band, 2.5 kHz resolution 430.24 439.75

868 MHz band, 5.0 kHz resolution 860.48 879.51

915 MHz band, 7.5 kHz resolution 900.72 929.27

Frequency error < 1kHz
after 10 MHz step

30 µs

mode 0 67

mode 1 134

mode 2 200

mode 3 270

mode 4 340

mode 5 400

-3

BER 10
868 MHz Band (Note 3)

δf
signal

In band interferers in high bands
(868 MHz, 915 MHz)

In band interferers in low band (433
MHz)

When input signal level lower than -54
dBm and greater than -100 dBm

, BW=67 kHz, BR=1.2 kbps,

: FSK deviation in the received

FSK

-110 dBm

0.8·δf

FSK

-21 dBm

-15 dBm

+35 mV/V

Until the RSSI signal goes high after
the input signal exceeds the
preprogrammed limit C

ARRSI

= 4.7 nF

500 µs

MHz

kHz

Notes are on page 12.

10

AC Characteristics (Transmitter)

Symbol Parameter Conditions/Notes Min Typ Max Units

I

Open collector output DC current Programmable 0.5 6 mA

OUT

P

max_50

Ohm load over a suitable matching
network (Note 4)

Max. output power delivered to 50

P

P

max_ant

P

out

Psp

harm

Co

Qo

L

out

Max. EIRP with suitable selected
PCB antenna (Note 6)

Typical output power Selectable in 2.5 dB steps (Note 7) P

Spurious emission
l f-f

> 1 MHz

sp l

Harmonic suppression

Output capacitance (set by the
automatic antenna tuning circuit)

Quality factor of the output
capacitance

Output phase noise

BRTX FSK bit rate Via internal TX data register 172 kbps

BRATX FSK bit rate TX data connected to the FSK input 256 kbps

df

FSK frequency deviation Programmable in 15 kHz steps 15 240 kHz

fsk

In 433 MHz band 7

In 868 MHz / 915 MHz bands 5

In 433 MHz band with monopole antenna
with matching network (Note 4)

7

In 868 MHz / 915 MHz bands (Note 5) 7

-17.5 P

max

max

At max power 50 Ohm load (Note 4) -55

With PCB antenna (Note 5) -60

At max power 50 Ohm load (Note 4) -35

With PCB antenna (Note 5) -42

In 433 MHz band 2 2.6 3.2

In 868 MHz / 915 MHz bands 2.1 2.7 3.3

In 433 MHz band 13 15 17

In 868 MHz / 915 MHz bands 8 10 12

100 kHz from carrier, in 868 MHz band -80

1 MHz from carrier, in 868 MHz band -103

dBm

Si4421

dBm

dBm

dBc

dBc

pF

dBc/Hz

AC Characteristics (Turn-on/Turnaround timings)

Symbol Parameter Conditions/Notes Min Typ Max Units

Default capacitance bank setting, crystal

tsx Crystal oscillator startup time

ESR < 50 Ohm (Note 9). Crystal load

2 7 ms

capacitance = 16 pF.

T

tx_XTAL_ON

T

rx_XTAL_ON

T

tx_rx_SYNT_ON

T

rx_tx_SYNT_ON

Transmitter turn-on time

Receiver turn-on time

Transmitter – Receiver turnover time

Receiver – Transmitter turnover time

Synthesizer off, crystal oscillator on with
10 MHz step

Synthesizer off, crystal oscillator on with
10 MHz step

Synthesizer and crystal oscillator on
during TX/RX change with 10 MHz step

Synthesizer and crystal oscillator on
during RX/TX change with 10 MHz step

250 µs

250 µs

150 µs

150 µs

AC Characteristics (Others)

Symbol Parameter Conditions/Notes Min Typ Max Units

Cxl

t

POR

t

PBt

C

inD

Crystal load capacitance,
see crystal selection guide

Internal POR timeout

Wake-up timer clock accuracy

Digital input capacitance 2 pF

tr, tf Digital output rise/fall time 15 pF pure capacitive load 10 ns

Programmable in 0.5 pF steps, tolerance
± 10%

After V

has reached 90% of final value

dd

(Note 8)

Crystal oscillator must be enabled to
ensure proper calibration at the start up.
(Note 9)

8.5 16 pF

100 ms

± 10 %

Notes are on page 12.

11

Si4421

Note 1: Measured with disabled clock output buffer

Note 2: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters

will change accordingly

Note 3: See the BER diagrams in the measurement results section (page 37) for detailed information

Note 4: See reference design with 50

Note 5: See reference design with Resonant PCB Antenna (BIFA) on page 41 for details

Note 6: Optimal antenna admittance/impedance:

Si4421 Y
433 MHz 2 – j5.9 52 + j152 62
868 MHz 1.2 - j11.9 7.8 + j83 15.4
915 MHz 1.49 - j12.8 9 + j77 13.6

Note 7: Adjustable in 8 steps

Note 8: During the Power-On Reset period, commands are not accepted by the

Command, page 25) the reset timeout is 0.25ms typical.

Note 9: The crystal oscillator start up time strongly depends on the cap

ESR crystal is recommended with low parasitic PCB layout design.

Note 10: By design

Ohm Matching Network (page 39) for details

[mS] Z

antenna

[Ohm] L

antenna

[nH]

antenna

chip. In case of software reset (see Wake-Up Timer

acitance seen by the oscillator. Low capacitance and low

12

Si4421

CONTROL INTERFACE

Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands
consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16­bit command). Bits having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built­in hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used to control the
nSEL pin to ensure the low level during the whole duration of the command or a software serial control interface should be
implemented. The Power-On Reset (POR) circuit sets default values in all control and command registers.

The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:

 The TX register is ready to receive the next byte (RGIT)

 The RX FIFO has received the preprogrammed amount of bits (FFIT)

 Power-on reset (POR)

 RX FIFO overflow (FFOV) / TX register underrun (RGUR)

 Wake-up timer timeout (WKUP)

 Negative pulse on the interrupt input pin nINT (EXT)

 Supply voltage below the preprogrammed value is detected (LBD)

FFIT and FFOV are applicable when the RX FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To
identify the source of the IT, the status bits should be read out.

Timing Specification

Symbol Parameter Minimum value [ns]

tCH Clock high time 25

tCL Clock low time 25

tSS Select setup time (nSEL falling edge to SCK rising edge) 10

tSH Select hold time (SCK falling edge to nSEL rising edge) 10

t

Select high time 25

SHI

tDS Data setup time (SDI transition to SCK rising edge) 5

tDH Data hold time (SCK rising edge to SDI transition) 5

tOD Data delay time 10

Timing Diagram

t

SHI

t

SH

nSEL

SCK

SDI

t

SS

t

t

CH

CL

t

t

DS

DH

BIT15 BIT14 BIT13

t

OD

BIT8 BIT 7

BIT1 BIT0

SDO

FFIT FFOV AT SCRL

OFFS (0) F IFO OU T

13

Si4421

Control Commands

Control Command Related Parameters/Functions Related control bits

1 Configuration Setting Command

2 Power Management Command

3 Frequency Setting Command Frequency of the local oscillator/carrier signal f11 to f0
4 Data Rate Command Bit rate cs, r6 to r0

5 Receiver Control Command

6 Data Filter Command Data filter type, clock recovery parameters al, ml, s, f2 to f0

7 FIFO and Reset Mode Command

8 Synchron Pattern Command Synchron pattern b7 to b0

9 Receiver FIFO Read Command RX FIFO read

10 AFC Command AFC parameters a1 to a0, rl1 to rl0, st, fi, oe, en
11 TX Configuration Control Command Modulation parameters, output power mp, m3 to m0, p2 to p0
12 PLL Setting Command CLK out buffer speed, dithering, PLL bandwidth ob1 to ob0, ddit, dly, bw0
13 Transmitter Register Write Command TX data register write t7 to t0
14 Wake-Up Timer Command Wake-up time period r4 to r0, m7 to m0
15 Low Duty-Cycle Command Enable and set low duty-cycle mode d6 to d0, en

Low Battery Detector and

16

Microcontroller Clock Divider
Command

17 Status Read Command Status bit readout

Frequency band, crystal oscillator load capacitance,
RX FIFO and TX register enable

Receiver/Transmitter mode change, synthesizer,
crystal oscillator, PA, wake-up timer, clock output
enable

Function of pin 16, Valid Data Indicator, baseband
bandwidth, LNA gain, digital RSSI threshold

Data FIFO IT level, FIFO start control, FIFO enable
and FIFO fill enable, POR sensitivity

LBD voltage and microcontroller clock division ratio d2 to d0, v3 to v0

el, ef, b1 to b0, x3 to x0

er, ebb, et, es, ex, eb, ew, dc

p16, d1 to d0, i2 to i0, g1 to g0, r2
to r0

f3 to f0, sp, ff, al, dr

In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default
values of the command registers after power-on.

Control Register Default Values

Control Register Power-On Reset Value

1 Configuration Setting Command 8008h

2 Power Management Command 8208h

3 Frequency Setting Command A680h

4 Data Rate Command C623h

5 Receiver Control Command 9080h

6 Data Filter Command C22Ch

7 FIFO and Reset Mode Command CA80h

8 Synchron Pattern Command CED4h

9 Receiver FIFO Read Command B000h

10 AFC Command C4F7h

11 TX Configuration Control Command 9800h

12 PLL Setting Command CC77h

13 Transmitter Register Write Command B8AAh

14 Wake-Up Timer Command E196h

15 Low Duty-Cycle Command C80Eh

16 Low Battery Detector and Microcontroller Clock Divider Command C000h

17 Status Read Command 0000h

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