Silicon Laboratories Si4113G-BM, Si4113G-BT, Si4122G-BM, Si4122G-BT, Si4123G-BM Datasheet

Si4133G

Si4123G/22G/13G/12G

D

UAL-BAND

F

GSM

OR

RF S

GPRS W

AND

YNTHESIZER WITH INTEGRATED

IRELESS COMMUNICATIONS

Features

!

Dual-Band RF Synthesizers

RF1: 900 MHz to 1.8 GHz

"

RF2: 750 MHz to 1.5 GHz

"

!

IF Synthesizer

IF: 500 MHz to 1000 MHz

"

!

Integrated VCOs, Loop Filters,
Varactors, and Resonators

!

Minimal External Components
Required

!

Fast Settling Time: 140 µs

!

Low Phase Noise

!

Programmable Power Down Modes

!

1 µA Standby Current

!

18 mA Typical Supply Current

!

2.7 V to 3.6 V Operation

!

Packages: 24-Pin TSSOP and
28-Pin MLP

Applications

!

GSM, DCS1800, and PCS1900
Cellular Telephones

!

GPRS Data Terminals

!

HSCSD Data Terminals

Description

The Si4133G is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. Th e Si4133G includes th ree VCOs, loop fi lters, reference and
VCO dividers, and phase detectors. Divider and power down settings are
programmable through a three-wi re serial interface.

Functional Block Diagram

XIN

PWDNB

SDATA

SCLK

SENB

AUXOUT

Reference

Amplif ier

Power

Down

Control

Serial

Interfa c e

22-bit

Data

Register

Test
Mux

÷

65

Phase
Detector

Phase
Detector

Phase
Detector

÷

÷N

÷N

RF1

N

RF2

IF

RFLA
RFLB

RFOUT

RFLC
RFLD

IFOUT

IFLA
IFLB

VCO

S

Si4133G-BT

Ordering Information:

See page 28.

Pin Assignments

Si4133G-BT

SCLK

1

SDATA

2

GNDR

3

RFLD

4

RFLC

5

GNDR

6

RFLB

7

RFLA

8

GNDR

9

GNDR

10

RFOUT

11

VDDR

12

Si4133G-BM

GNDR

SDATA

SCLK

1

GNDR

2

RFLD

3

RFLC

4

GNDR

5

RFLB

6

RFLA

7

GNDR

8 9 10 11 12 13 14

SENB

SENB

24

VDDI

23

IFOU T

22

GNDI

21

IFLB

20

IFLA

19

GNDD

18

VDDD

17

GNDD

16

XIN

15

PWDNB

14

AUXOUT

13

VDDI

IFOU T

GNDI

22232425262728

21

GNDI

20

IFLB

19

IFLA

18

GNDD

17

VDDD

16

GNDD

15

XIN

GNDR

VDDR

GNDR

RFOUT

GNDD

PWDNB

AUXOUT

Patents pending

Rev. 1.1 4/01 Copyright © 2001 by Silicon Laboratories Si4133G-DS11

Si4133G

2 Rev. 1.1

Si4133G

T

ABLE OF

C

ONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Pin Descriptions: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pin Descriptions: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Si4133G Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package Outline: Si4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package Outline: Si4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Rev. 1.1 3

Si4133G

Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Temperature T
Supply Voltage V
Supply Voltages Difference V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at 3.0 V and an operating temperature of 25°C unless otherwise stated.

Table 2. Absolute Maximum Ratings

1,2

DD

A

(V

(V

DDR

DDI

– V
– V

∆

DDD
DDD

),
)

–20 25 85 °C

2.7 3.0 3.6 V

–0.3 — 0.3 V

Parameter Symbol Value Unit

DC Supply Voltage V
Input Current

Input Voltage

3

3

Storage Temperature Range T

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2. This device is a high performan ce RF integrated circ uit with an ESD rating of < 2 kV. Handling and assembly of
this device should only be done at ESD-protected workstations.

3. For signals SCLK, SDATA, SENB, PWDNB and XIN.

I

V

DD

IN

IN

STG

–0.5 to 4.0 V

±10 mA

–0.3 to VDD+0.3 V

–55 to 150

o

C

4 Rev. 1.1

Si4133G

Table 3. DC Characteristics

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C

Parameter Symbol Test Condition Min Typ Max Unit

Typical Supply Current
RF1 Mode Supply Current
RF2 Mode Supply Current
IF Mode Supply Current

1

1
1

1

Standby Current PWDNB = 0 — 1 — µA
High Level Input Voltage
Low Level Input Voltage
High Level Input Current

Low Level Input Current

High Level Output Voltage
Low Level Output Voltage

Notes:

1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 800 MHz

2. For signals SCLK, SDATA, SENB, and PWDNB.

3. For signal AUXOUT.

2

2

2

2

3

3

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

RF1 and IF Operating — 18 31 mA

—1317mA
—1217mA
—1014mA

0.7 V

DD

——V

——0.3 VDDV

=

V

V

V

V

IH

= 3.6 V

DD

=

IL

=

DD

3.6 V,

0V,

3.6 V

–10 — 10 µA

–10 — 10 µA

IOH = –500 µA VDD–0.4 — — V

IOH = 500 µA — — 0.4 V

Rev. 1.1 5

Si4133G

Table 4. Serial Interface Timing

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter

1

SCLK Cycle Time t
SCLK Rise Time t
SCLK Fall Time t
SCLK High Time t
SCLK Low Time t
SDATA Setup Time to SCLK↑
SDATA Hold Time from SCLK↑
SENB↓ to SCLK↑ Delay Time
SCLK↑ to SENB↑ Delay Time
SENB↑ to SCLK↑ Delay Time

2

2
2
2
2

SENB Pulse Width t

Symbol Test Condition Min Typ Max Unit

Figure 1 40 — — ns
Figure 1 — — 50 ns
Figure 1 — — 50 ns
Figure 1 10 — — ns
Figure 1 10 — — ns
Figure 2 5 — — ns
Figure 2 0 — — ns
Figure 2 10 — — ns
Figure 2 12 — — ns
Figure 2 12 — — ns
Figure 2 10 — — ns

t
t
t
t

clk

t

su

hold

en1

en2

en3

w

r

f

h

l

Notes:

1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.

2. Timing is not referenced to 50% level of waveform. See Figure 2.

SCLK

80%
50%
20%

t

r

t

f

t

h

t

l

t

clk

Figure 1. SCLK Timing Diagram

6 Rev. 1.1

Si4133G

SCLK

SDATA

SENB

t

su

First bit

cloc ked in

t

hold

D17 D16 D15 A1 A0

t

en1

Figure 2. Serial Interface Timing Diagram

cloc ked in

t

en2

Last bit

t

en3

t

w

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A1A

data

field

address

field

Figure 3. Serial Word Format

0

Rev. 1.1 7

Si4133G

Table 5. RF and IF Synthesizer Characteristics

(VDD = 2.7 to 3.6 V, TA = –20 to 85°C)

Parameter

1

XIN Input Frequency f
Reference Amplifier Sensit ivity V

Symbol Test Condition Min Typ Max Unit

REF

REF

—13—MHz

0.5 — V

DD

V

PP

+0.3

Phase Detector Update Frequency f
RF1 Center Frequency Range

f

RF2 Center Frequency Range f
IF VCO Center Frequency f
Tuning Range from f

CEN

φ

CEN
CEN

CEN

f

φ

Note: L

= f

/R 200 KHz

REF

947 — 1720 MHz
789 — 1429 MHz

526 — 952 MHz

±10% –5 — 5 %

EXT

RF1 VCO Pushing Open loop — 0.5 — MHz/V
RF2 VCO Pushing — 0.4 — MHz/V
IF VCO Pushing — 0.3 — MHz/V
RF1 VCO Pulling VSWR = 2:1, all
RF2 VCO Pulling — 0.1 — MHz

phases, open loop

IF VCO Pulling — 0.1 — MHz

—0.4—MHz

PP
PP
PP

RF1 Phase Noise 1 MHz offset — –132 — dBc/Hz

3 MHz offset — –142 — dBc/Hz
RF1 Integrated Phase Error 100 Hz to 100 kHz — 0.9 — deg rms
RF2 Phase Noise 1 MHz offset — –134 — dBc/Hz

3 MHz offset — –144 — dBc/Hz
RF2 Integrated Phase Error 100 Hz to 100 kHz — 0.7 — deg rms
IF Phase Noise 100 kHz offset — –117 — dBc/Hz
IF Integrated Phase Error 100 Hz to 100 kHz — 0.4 — deg rms
RF1 Harmonic Suppression Second Harmonic — –26 — dBc
RF2 Harmonic Suppressio n — –26 — dBc
IF Harmonic Suppression — –26 — dBc
RFOUT Power Level
IFOUT Power Level

ZL = 50 Ω
ZL = 50 Ω

–7 –2 1 dBm
–8 –6 –1 dBm

RF1 Reference Spurs Offset = 200 kHz — –70 — dBc

Offset = 400 kHz — –75 — dBc
Offset = 600 kHz — –80 — dBc

R

F2 Reference Spurs Offset = 200 kHz — –75 — dBc

Offset = 400 kHz — –80 — dBc
Offset = 600 kHz — –80 — dBc

Power Up Request to Synthesizer
Ready Time, RF1, RF2, IF

2

Power Down Request to Synthesizer Off

3

Time

Notes:

1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550MHz for all parameters unless otherwise noted.

2. From power up request (PWDNB↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF

synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs.

3. From power down request (PWDNB↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to I

PWDN

.

t

t

pup

pdn

Figures 4, 5 — 140 — µs

Figures 4, 5 — — 100 ns

8 Rev. 1.1

Si4133G

RF and IF syn thesize r s se t tled to
w i t hi n 0.1 ppm frequency error.

I

PWDN

t

I

T

pup

t

pdn

SENB

SDATA

PDIB = 1

PDRB = 1

PDIB = 0

PDRB = 0

Figure 4. Software Power Management Timing

Diagram

RF and IF synthesizers settled to
within 0.1 p pm frequency error.

I

PWD N

t

I

T

pup

t

pdn

PWDNB

Figure 5. Hardware Power Management Timing

Diagram

Rev. 1.1 9

Si4133G

TRACE A: Ch1 FM Gate Time

800

Real

160

/div

Axis is 0.1 ppm/div

Hz

Hz

A Offset

133.59375 us

-800
Hz

Start: 0 s

Figure 6. Typical Transient Response RF1 at 1.6 GHz

with 200 kHz Phase Detector Update Frequency

Stop: 299.21875 us

10 Rev. 1.1