Silicon Laboratories Si3460, Si3460-EVB User Manual

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Si3460-EVB

Si3460 EVALUATION BOARD USER’S GUIDE

1. Introduction

This document is intended to be used in conjunction with the Si3460 data sheet for designers interested in:

An introduction to Power-over-Ethernet (PoE) and Power Sourcing Equipment (PSE) design

considerations

How the Si3460 PSE controller operates in the Si3460-EVB reference design Configuring and operating the Si3460 - EVB

2. Overview of the Si3460 and Evaluation Board

The Si3460 is a single-port –48 V power management controller for IEEE 802.3af compliant Power Sourcing Equipment (PSE). The Si3460 operates directly from a 12 or 15 V isolated input supply and integrates a digital PWM-based dc-dc converter for generating the –48 V PSE output supply. The nega tive polarity on the PSE supply provides safety-extra-low-voltage (SELV) compatibility with telephony ports in the same system. The complete Si3460 reference design (i.e., the Si3460-EVB) also provides full IEEE-compliant classification and detection as well as a robust disconnect algorithm. Intelligent protection circuitry includes input under-voltage lockout (UVLO), current limiting, and output short-circuit protection.

The Si3460 is designed to operate completely independently of host processor control. A reset input and an optional LED status signal is provided to indicat e the port status, including detect, power good and output fault event information for use within the host system.

The Si3460 is pin programmable to support:

Endpoint and midspan applications, with support for either 10/100BASE-T or 10/100/1000BASE-T All four classification power levels specified by the IEEE 802.3 standard Classification-based current limiting Automatic or manual restart after various fault events are detected

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3. Introduction to PoE

IEEE 802.3-2005 clause 33 (formerly IEEE 802.3af) is the standard for providing power to a remote Ethernet device on the same cable that is carrying data. The power is either carried common mode on one of the data pairs (for 10/100/1000BASE-T) or on the spare pairs for 10/100BASE-T only applications.

Figures 1 and 2 show the possible connections for the power. The connections shown in Figure 1 should be used for power injection in an Ethernet midspan, and the connections shown in Figure 2 ca n be u s ed for either midspan or endpoint (switch) applications. Designed for use on the PSE side for providing power to a single Ethernet PD port, the Si3460 can be configured to operate in either midspan or endpoint applications. Although at this time the existing IEEE specification doesn't specifically allow or prohibit gigabit (10/100/1000BASE-T) midspans, in midspan mode, the Si3460-EVB is designed to operate in 10/100BASE-T mode, as the power is carried on the spare pairs. However, the Si3460 controller can also be designed into gigabit endpoints with the power connected to either the data or spare pair s.

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Si3460-EVB

POWER SOURCING

EQUIPMENT (PSE)

POWERED DEVICE

(PD)

48 V

+ _

4 5

1 2

3 6 7

SPARE PAIR

SIGNAL PAIR

SPARE PAIR

4 5

1 2

3 6 7

PD I/F

and

DC-DC

Converter

POWER SOURCING

EQUIPMENT (PSE)

POWERED DEVICE

(PD)

48 V

4 5

1 2

3 6 7

SPARE PAIR

SIGNAL PAIR

SPARE PAIR

4 5

1 2

3 6 7

DC-DC

Converter

and

PD I/F

Figure 1. Power Carried Over the Spare Pair (10/100BASE-T Applications Only)

Note: This is the connection scheme implemented on the Si3460-EVB reference design.

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Figure 2. Power Carried Over the Signal (Data) Pair

Si3460-EVB

Voltage

ClassificationDetection

Apply Power

Turn off

Time

2.8 V

10 V

15.5 V

44 V

57 V

20.5 V

4. PSE Detection, Classification, Power-Up, and Power Removal

The basic sequence for applying power is shown in Figure3. Following is a description of the functions that must be performed in each phase.

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Figure 3. Detection, Classification, Powerup, and Disconnect Sequence

4.1. Detection

During the detection phase, the PSE probes with limited current and voltage to determine if a 25 k signature is present. A valid PD must present be tween 23.75 a nd 26.2 5 k  in the range of 2.7 to 10.1 V, with an offset (due to the bridge diodes) of up to 1.9 V, and a parallel capacitance of between 0.05 and 0.12 µF. An IEEE-compliant PSE probes 2.8 and 10 V, with at least a 1 V step and current limit of <5 mA. The PSE must accept signatures in the range of 19–26.5 k with capacitance of up to 0.15 µF and must reject resistance <15 k or >33 k as well as capacitive signatures >10 µF.

The strict limits on the detection phase ensure that non PoE enabled devices are not inadvertently powered. For endpoint applications, detection must be completed within 500 ms of applying a valid signature. When configured as a midspan there is a possibility that the PSE circuit will compete with an endpoint PSE, and, as required by the IEEE specifications, the Si3460 is therefore required to wait at least 2 seconds after an unsuccessful detection cycle to repeat the detection process.

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4.2. Classification

Classification is optional and is performed by applying between 15.5 and 20.5 V to the PD and measuring the current. The maximum power level that can be drawn by the PD is determined according the following table.

Table 1. Classification Levels

Classification Level Minimum PSE Power Level Current Measured

Class 0 15.4 W <5 mA Class 1 4 W 8–13 mA Class 2 7 W 16–21 mA Class 3 15.4 W 25–31 mA Class 4 15.4 W 35–45 mA

Currents not falling in these ranges maybe be treated as the higher or lower classification level. Currents above 45 mA may be treated as class level 0 or 4, which is 15.4 W in either case.

4.3. Power-Up

After the optional classification step, power is applied. Per the IEEE specification, the PSE must supply between 44 and 57 V to the PD. For longer durations above 50 ms the power may be removed if the maximum power level of either 4, 7, or 15.4 W is exceeded. If the current exceeds 400 mA, the power must be removed in 75 ms. For short-circuit protection, outpu t power is removed immediat ely if the output current exceeds 800 mA or the output voltage drops below 30 V. If power is removed due to an overload condition, detection must not be attempted again for at least 2 s.

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4.4. Disconnect (Power Removal)

The Si3460 supports a robust disconnect algorithm to avoid false disconnection. Removal of a PD can be sensed by determining that the dc current is less than 5 mA for between 300 and 400 ms. If the current then exceeds 10 mA for at least 60 ms, the power must not be removed, and the 300–400 ms timer restarts.

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5. The Si3460 PSE Controller

In addition to providing a complete dc-dc controller to gene rate the PSE output supp ly, the Si3460 is a fully IEEE compliant PSE power management controller. The Si3460 is specifically designed and configured to work with an applications circuit (Si3460-EVB) that together implement a single port PSE solution for either midspans or endpoints.

Referring to the detailed evaluation board schematics in Section “8. Si3460-EVB Schematics and PCB Layout”, the overall functionality is described for each ope ra tin g state of the Si346 0 as follows:

5.1. Initialization and Operating Mode Configuration

The Si3460 is initialized at power up, or whenever pin 8 (RST) is held low and then allowed to transition high . Upon reset (RST determine the operating mode of the Si3460. The detection process begins immediately after initialization.

Any combination of the following thr ee operating m odes can be set by the R28 and R30 resistor pair, as indicated below:

asserted), the voltage at the STATUS pin (as determined by resistors R28 and R30) is sensed to

Classification level: sets what maximum power level the Si3460 will support. Endpoint or midspan mode: controls the backoff timing per the IEEE specifications. Restart action on fault or overload: determines whether or not the Si3460 will automatically rest art af ter 2 s

when a fault or overload condition (e.g., input UVLO, output short-circuit event, classification power level exceeded) is detected, or wait to restart until the RST

pin is asserted.

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Table 2. Operating Modes

Nominal Status Pin

Voltage

R28, R30 Power Level

Supported (W)

Operating Mode

Supported

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Pin voltage at VEE 2 k, NP 15.4 All class levels Endpoint Auto restart after 2 s

3.0 V 2.21 k, 22.1 k 7.0 Class 1 or 2

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Classes

Endpoint/

Midspan

Restart Action on Fault or Overload

Event

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2.75 V 2.37 k, 11 .8 k 4.0 Class 1

2.5 V 2.61 k, 8.06 k 15.4 All class levels Restart on RST

2.25 V 2.94 k, 6.19 k 7.0 Class 1 or 2

2.0 V 3.32 k, 4.99 k 4.0 Class 1

1.75 V 3.83 k, 4.22 k 4.0 Class 1 Midspan Restart on RST

1.5 V 4.42 k, 3.57 k 7.0 Class 1 or 2

1.25 V 5.36 k, 3.16 k 15.4 All class levels

1.0 V 6.81 k, 2.80 k 4.0 Class 1 Auto restart after 2 s

0.5 V 14 k, 2.26 k 7.0 Class 1 or 2 < 0.25 V NP, 2 k 15.4 All class levels

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5.2. CTRL1 and CTRL2

These two pins are the output of two 96 kHz 8-bit pulse width modulators. The output of these pins is averaged using R15, R29, and C5 to produce a dc level across C5 that is controllable with 16-bit resolution. This dc voltage is used to control both the detection process and the pulse width modulator for the dc-dc converter.

5.3. Detection

During the detection phase, the pass transistor M2 is held off by driving the GATE pin high. The 250 kHz clock for the PWM circuit is held low, forcing the switcher FET M1 off.

In the detect state, the output voltage is determin ed by the outp ut of U18A feeding the resistive bridge R1, R2, and R3. The PD at the other end of a cable forms the fourth leg of the bridge. The return path to Vee is through D8 and L1. The bridge null is read through amplifier U18B, which is fed to the Si3460 pin DETA.

The output of U18A is controlled by the CTRL1 and CTRL2 pins as noted earlier. For most of the detection cycle, the CTRL pins are held high which forces U18A low, producing no output. The bridge voltage is varied to force IEEE compliant detection voltages of approximately 4.5 and 7.5 V across the bridge with 20 ms delay and robust three-point detection algorithm at 4.5, 7.5, and back to 4.5 V. To robustly insure that the PD has a valid resistive signature, the bridge null is checked as the voltage increases and then checked again as the voltage decreases. Relevant waveforms are shown in Figure 4 and Figure 5 on page 11.

5.4. PWM

In order to apply power to the load, M2 is turned on by driving the Si3460's GATE pin high. At the same time, the PWM circuitry is enabled by turning on the 250 kHz clock (250 kHz pin). The 250 kHz square wave is converted to a triangular shape by the filter R1 4 and C6. The dc level set by CTRL1 and CTRL2 is used to control the PWM comparator U19B that drives the switcher FET through gate driver U3.

The output voltage is sensed through resistor divider R43 and R44, and the output current is sensed through resistor R4. The Si3460 integrates an A/D that measures these quantities and varies the CTRL1 and CTRL2 duty cycle to regulate the output current and voltage as desired.

5.5. Classification

For classification, M2 is turned on and the PWM is enabled. The Si3460 is programmed to perform classification at 18 V output voltage, with a current limit of between 50 and 100 mA. Classification is performed after allowing 20 ms of settling time.

Since the Si3460-EVB is designed for a single port PSE application, the classification information is only used to determine if the load is in the range that is supported, according to the mode of the Si3460 determined at powe r up (refer to STATUS pin in Section “5.1. Initialization and Operating Mode Configuration”).

Classification

Mode

Full power 15.4 W Always apply full power 400 mA 450 mA

PSE Minimum

Output Power

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Table 3. Classification Levels

Action Performed Overload Current

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Overload Current

CUT

(Max)

Limit I

LIM

(Max)

Class 1 only 4 W Only apply power if the current

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Class 1 or Class 2 7 W Only apply full power if the

If the measured classification level is not in the supported range, an error is declared and the Si3460 will either time

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out and retry and wait for a reset as determined by the power up mode of operation. Relevant waveforms are shown in Figure 5 on page 11 and Figure 6 on page 12. If the class level is in the supported range, the Si3460 proceeds to powerup.

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98 mA 450 mA

is between 8 and 13 mA

(class 1)

180 mA 450 mA

current is between 8 and

21 mA (class 1 or class 2)

Si3460-EVB

5.6. Power-Up

After successful classification, the Si3460 is configured to produce a nominal –50 V output voltage. The overload current limits are set based on the cla ssification voltage on the STATUS pin at powerup. Refer to Table 1 of the Si3460 data sheet for more information.

For output current durations lasting longer than 60 ms, the power is removed if the maximum power level of either 4, 7, or 15.4 W is exceeded by approximately 10%, as determined by the opera ting mode detected at st art up (refer to Section “5.1. Initialization and Operating Mode Configuration”). In the event of an output short circuit, the Si3460 will immediately disconnect so as to prevent shorting the input supply through D8 and L1.

The Si3460 can be configured to operate in a mode where it will automatically retry detection and power up after an overload. Alternatively, the Si3460 can be programmed to signal an error condition has occurred, in which case the user must assert RST cycle.

As set by the initial voltage on the STATUS pin at powerup, the Si3460 will then automatically resume the detection process for "automatic restart configuration" unless the Si3460 is configured in a "restart after a RESET condition" mode and a fault condition is detected; in that case, the LED will flash rapidly, and the detection process will automatically start again after 2.2 seconds. Power will not be provided until an open-circuit condition is detected. Once the Si3460-EVB detects an open-circuit condition (normally by removing the Ethernet cable from the Si3460-EVB’s RJ-45 jack labeled “To PD”), the detection process begins, the status LED blinks at the rate of 3 times per second, and the Si3460 is then allowed to go into classification an d powerup mode if a valid PD signatur e resistance is detected. The relevant waveform is shown in Figure 6 on page 12.

5.7. Disconnect (Power Removal)

The Si3460 supports a robust disconnect algorithm. If the current drops below 5 mA for between 300 and 400 ms, the power is removed. If the output current then exceeds 10 mA for at least 60 ms, the power is not removed. The Si3460 will continue to provide power unless a disconnect or overload condition is sensed. The only other way to force the Si3460 to disconnect power is by doing a reset. The relevant waveform is shown in Figure 7 on page 12.

(e.g., by pushing the reset switch on the Si 346 0- EVB) to start a new detection and power up

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5.8. Current Limit Control

The Si3460's overcurrent trip point is determined by the output power set during the classification stage power granting process. If the output current exceeds the threshold, a timer counts up towards a time-out of 60 ms. If the current drops below the set threshold, the timer co unts down towards zero at 1/16t h the rate. If the timer reac hes 60 ms, an overcurrent fault is declared, and the channel is shut down by turning off the dc-dc converter clock and then turning off the FET M1. After an overcurrent fault event, the LED will flash rapidly.

5.9. UVLO

The Si3460-EVB reference design is optimized for 12 to 15 V nominal input voltages* (11 V minimum to 16 V maximum). If the input voltage drops below 10 V in detection mode or if the output voltage drops below 10 V in classification or power up mode, a UVLO condition is declared which generates the error condition (LED flashing rapidly). An under-voltage event is a fault condition which is reported through the status LED as a rapid blinking of 10 flashes per second. The UVLO condition is continuously monitored in all operating states.

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*Note: Some MOSFET gate drivers operate at a maximum supply voltage of 14 V (for example, TPS2828). In that case, the

input voltage must be limited to a maximum of 12 V.

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5.10. Status LED Function

During the normal detection sequence, the STATUS LED flashes at approximately 3 times per second as the detection process continues. After successful power up, the LED glows continuously. If there is an error condition (i.e., class level is beyond programmed value, or a fault or over current condition has been detected), the LED flashes rapidly at 10 times per second). This occurs for two seconds for normal error delay and, in the case of the "restart after a RESET condition," the LED will flash rapidly, and the detection process will automatically start again after 2.2 s and power will not be provided until an open circuit condition is detected. Once the Si3460-EVB detects an open circuit condition, the LED blinks at 3 times per second.

If the Powered Device (PD) is disconnected so that a disconnect event occurs, the LED will start flashing at 3 times per second once the detect process resumes .

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8 Rev. 1.2

+ 18 hidden pages

Silicon Laboratories Si3460, Si3460-EVB User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual