The Si3035 is an integrat ed direct ac cess arrange ment (DAA) c hipset that
provides a digital, low-cost, solid-state interface to a telephone line.
Available in two 16-pin small outline packages, it eliminates the need for an
analog front end (AFE), a n is olation transformer, relays, opto-isolators, and
a 2- to 4-wire hybrid. The Si3035 dramatically reduces the number of
discrete components and cost require d to achieve compliance with FCC
Part 68. The Si3035 interfaces directly to standard modem DSPs and
supports all FCC and J ATE out-of-band noise require ments. International
support is provided by the pin compatible Si3034.
Ambient TemperatureT
Si3021 Supply Voltage, AnalogV
Si3021 Supply Voltage, Digital
Notes:
1.
The Si3035 specifications are guaranteed when the typical application circuit (including component
3
SymbolTest Condition
A
A
V
D
K-Grade02570°C
Min
2
Typ
Max
2
Unit
4.755.05.25V
3.03.3/5.05.25V
tolerances) and any Si3021 and any Si3012 are used. See Figure 16 on page 15 for typical application
circuit.
2.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, V
operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals
RGDT, OFHK, RESET, M0, and M1.
, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when
D
Table 2. Loop Characteristics
(VA = Charge Pump, VD = +3.3 V ± 0. 3 V, TA = 0 to 70°C for K-Grade, Refer to Figure 1)
ParameterSymbolTest ConditionMinTypMaxUnit
DC Termination VoltageV
DC Termination VoltageV
DC Ring Current (
DC Ring Current
with caller ID)
(w/o caller ID)
AC Termination ImpedanceZ
Operating Loop CurrentI
I
RDC
I
RDC
ACT
LP
TR
TR
Loop Current Sense BitsLCSLCS = Fh180155—mA
IL = 20 mA——7.7V
IL = 105 mA12——V
—— 1 mA
—— 20µA
—600— Ω
20—120mA
Ring Voltage DetectV
Ring FrequencyF
On-Hook Leakage CurrentI
Ringer Equivalence Num. (
Ringer Equivalence Num.
with caller ID)
(w/o caller ID)
Si3012
RING
RD
R
LK
V
BAT
REN—1.01.67—
REN—0.2——
TIP
+
600
Ω
V
TR
10 µF
–
Figure 1. Test Circuit for Loop Characteristics
4Rev. 1.2
131826V
RMS
15—68Hz
= –48 V——1µA
I
L
Si3035
Table 3. DC Characteristics, VD = +5 V
(VA = +5 V ±5%, VD = +5 V ±5%, TA = 0 to 70°C for K-Grade)
ParameterSymbolTest ConditionMinTypMaxUnit
High Level Input VoltageV
Low Level Input VoltageV
High Level Output VoltageV
Low Level Output VoltageV
Input Leakage CurrentI
Power Supply Current, AnalogI
Power Supply Current, Digital
Total Supply Current, Sleep Mode
Total Supply Current, Deep Sleep
Notes:
1. All inputs at 0.4 or V
= 0 mA).
OUT
is not functional in this state.
2.
(Static I
RGDT
1
1
1,2
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade)
ParameterSymbolTest ConditionMinTypMaxUnit
High Level Input VoltageV
Low Level Input VoltageV
High Level Output VoltageV
Low Level Output VoltageV
Input Leakage CurrentI
Power Supply Current, Analog
Power Supply Current, Digital
Total Supply Current, Sleep Mode
Total Supply Current, Deep Sleep
Power Supply Voltage, Analog
Notes:
1. Only a decoupling capacitor should be connected to V
2. There is no I
to the V
3. All inputs at 0.4 or V
(Static I
4. RGDT
5. The charge pump is rec om m end ed to be used only when V
applied to the device before V
current consumption when the internal charge pump is enabled and only a decoupling cap is connected
A
pin.
A
= 0 mA).
OUT
is not functional in this state.
1,2
3
3
3,4
1,5
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
D
is applied on power up if driven from separate supplies.
AOUT Output Impedance—10—kΩ
Mute Level (call progress AOUT)–90——dB
Dynamic Range (caller ID mode)DR
Caller ID Full Scale Level (0 dB gain)
Notes:
1. See Figure 23 on page 22.
2. Parameter measured at TIP and RING of Figure16 on page 15.
3. Receive Full Scale Level will produce – 0.9 dBFS at SDO.
4.
DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth
is 300 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
5.
DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth
is 15 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
6. THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths.
Sample Rate = 9.6 kHz, Loop Current = 40 mA.
2
V
CID
VIN = 1 kHz, –13 dBFS—60—dB
CID
—0.8—V
PEAK
6Rev. 1.2
Si3035
Table 6. Absolute Maximum Ratings
ParameterSymbolValueUnit
DC Supply VoltageV
Input Current, Si3021 Digital Input PinsI
Digital Input VoltageV
Operating Temperature RangeT
Storage Temperature RangeT
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
, V
D
IN
IND
STG
A
–0.5 to 6.0V
±10mA
–0.3 to (VD + 0.3)V
A
–40 to 100°C
–65 to 150°C
Table 7. Switching Characteristics—General Inputs
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter
1
Cycle Time, MCLKt
MCLK Duty Cyclet
Rise Time, MCLKt
Fall Time, MCLKt
MCLK Before RESET
RESET
Pulse Width
M0, M1 Before RESET
Notes:
1.
All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET
3. M0 and M1 are typically connected to V
↑t
2
3
↑
pulse width is the greater of 250 ns or 10 MCLK cycle times.
or GND and should not be changed during normal operation.
D
SymbolMinTypMaxUnit
16.67—1000ns
405060%
—— 5 ns
—— 5 ns
10——cycles
250——ns
150——ns
t
mc
dty
mr
t
rl
mxr
r
f
MCLK
RESET
M0, M1
t
t
r
t
rl
t
mxr
mc
t
mr
Figure 2. General Inputs Timing Diagram
Rev. 1.27
t
f
V
IH
V
IL
Si3035
Table 8. Switching Characteristics—Serial Int erface (DCE = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
ParameterSymbolMinTypMaxUnit
Cycle time, SCLKt
SCLK duty cy clet
Delay time, SCLK ↑ to FSYNC
↓t
Delay time, SCLK ↑ to SDO validt
Delay time, SCLK ↑ to FSYNC
↑t
Setup time, SDI before SCLK ↓t
Hold time, SDI after SCLK ↓t
Setup time, FC ↑ before SCLK ↑t
Hold time, FC ↑ after SCLK ↑t
Table 11. Digital FIR Filter Characteristics—Transmit and Receive
(VA = Charge Pump, VD = +5 V ±5%, Sample Rate = 8kHz, TA = 0 to 70°C for K-Grade)
ParameterSymbolMinTypMaxUnit
Si3035
Passband (0.1 dB)
Passband (3 dB)
F
(0.1 dB)
F
(3 dB)
0—3.3kHz
0—3.6kHz
Passband Ripple Peak-to-Peak–0.1—0.1dB
Stopband—4.4—kHz
Stopband Attenuation–74——dB
Group Delay
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.
t
gd
—12/Fs—sec
Table 12. Digital IIR Filter Characteri stics—Transmit and Receive
(VA = Charge Pump, VD = +5 V ±5%, Sample Rate = 8 kHz, TA = 0 to 70°C for K-Grade)
ParameterSymbolMinTypMaxUnit
Passband (3 dB)
F
(3 dB)
Passband Ripple Peak-to-Peak–0.2—0.2dB
Stopband—4.4—kHz
Stopband Attenuation–40——dB
Group Delay
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show
group delay versus input frequency.
t
gd
0—3.6kHz
—1.6/Fs—sec
Rev. 1.211
Si3035
Attenuation—dB
Input Frequency—Hz
Figure 6. FIR Receive Filter Response
Attenuation—dB
Attenuation—dB
Input Frequency—Hz
Figure 8. FIR Transmit Filter Response
Attenuation—dB
Input Frequency—Hz
Figure 7. FIR Receive Filter Passband Ripple
For Figures 6–9, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F
where Fs is the sample frequency.
12Rev. 1.2
(0.1 dB)
F
(– 3 dB)
= 0.4125 Fs
= 0.45 Fs
Input Frequency—Hz
Figure 9. FIR T ransmi t Filter Passband Ripple
Si3035
Attenuation—dB
Input Frequency—Hz
Figure 10. IIR Receive Filter Response
Attenuation—dB
Attenuation—dB
Input Frequency—Hz
Figure 12. IIR T ransmit Filter Response
Attenuation—dB
Input Frequency—Hz
Figure 11. IIR Receive Filter Passband Ripple
For Figures 10–13, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
F
(–3 dB)
where Fs is the sample frequency.
Input Frequency—Hz
Figure 13. IIR Transmit Filter Passband Ripple
= 0.45 Fs
Rev. 1.213
Si3035
Delay—µs
Input Frequency—Hz
Figure 14. IIR Receive Group DelayFigure 15. IIR Transmit Group Delay
Delay—µs
Input Frequency—Hz
14Rev. 1.2
Typical Application Circuit
p
Decoupling cap for U1 VD
VCC
C10
RGDTb
OFHKb
MCLK
FSYNCb
SCLK
SDO
RESETb
AOUT
M0
SDI
FC
M1
R3
Decoupling cap for U1 VA
10
C3
Z4
U1
1
MCLK
2
FSYNC
3
SCLK
4
VD
5
SDO
6
SDI
7
FC
89
RESETAOUT
SOIC Pinout
Si3021
OFHK
RGDT
GND
16
15
14
M0
13
VA
12
11
C1A
10
M1
D3
BAV99
R27
C30
Rev. 1.215
No Ground Plane In DAA Section
R28
C1
D4
BAV99
C2
Z5
U2
Si3012
1
2
3
4
5
6
7
89
TSTA
TSTB
NC2
IGND
C1B
REXT
RNG1
DCT
RNG2
HYBD
QB
VREG2
QE VREG
16
TX
15
14
RX
13
12
11
10
C6
C16
R23
R1
R4
C12
R2
C8
R21
+
C5
C23
+
R18
Z1
R10
Q1
R5
Q2
R6
C20
Q3
FB2
RING
Note 1: R3 is not required when Vcc=3.3 V and the charge pump is
enabled (CPE = 1).
Note 2: If JATE support is not required, R21, C12 and C23
may be removed (R21 is effectively 0 ohms) and R4 should
be changed to a 604 ohm, 1/4 W, +- 1%.
Note 3: See Appendix for applications requiring UL 1950
3rd Edition com
1. The following reference designators were intentionally omitted: C13–C15, C17–C22, C26–C29, R7, R8, R11–R17,
R19, and R20.
2. If JATE support is not required, C12, and C23 may be removed.
3.
Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, ±10% and C31, C32 not installed).
4. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
5. Several diode bridge configurations are acc ep tab le (sup pl iers incl ude General Semi, Diodes Inc.)
6. If the charge pump is not enabl ed (with th e CPE bit in Register 6), V
a 10 Ω, 1/10 W, ±5% if V
is also 4.75 to 5.25 V.
D
must be 4.75 to 5.25 V. R3 can be installed with
A
16Rev. 1.2
Si3035
Analog Output
Figure 17 illustrates an optional application circuit to support the analo g output capability of the Si3035 for call
progress monitoring purp oses . T he AR M bi ts in Regi s ter 6 allow the receive path to be atte nua ted by 0 dB, –6 dB,
or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20 dB, –26 dB,
or –32 dB. Both the transmit and receive paths can also be independently muted.
+5 V
AOUT
C2
C1
R3
C6R1
6
3
+
5
2
–
4
C3
R2
C4
+
C5
Speaker
Figure 17. Optional Connection to AOUT for a Call Progress Speaker
‘
Table 14. Component Values—Optional Connection to AOUT