Silicon Laboratories Si3012-KS, Si3012-KT, Si3014-KS, Si3014-KT, Si3015-BS Datasheet

...
Si3035
3.3 V FCC/JATE D
IRECT
A
CCESS
A
Features
!
3.3 V to 5 V Digital/Analog Power Supplies
!
JATE Filter Option
!
86 dB Dynamic Range TX/RX Paths
!
Daisy-Chaining for Up to Eight Devices
!
Integrated Ring Detec t or
!
3000 V Isolation
!
Support for Caller ID
!
Low Profile SOIC Packages
!
Direct Interface to DSPs
!
Integrated Modem Codec
!
Compliant with FCC Part 68
!
Low-Power Standb y Mode
!
Proprietary ISOcap™ Technology
!
Pin Compatible with Si3034, Si3032
!
Optional IIR Digital Filter
Applications
!
V.90 Modems
!
Voice Mail Systems
!
Fax Machines
!
Set Top Boxes
Description
The Si3035 is an integrat ed direct ac cess arrange ment (DAA) c hipset that provides a digital, low-cost, solid-state interface to a telephone line. Available in two 16-pin small outline packages, it eliminates the need for an analog front end (AFE), a n is olation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3035 dramatically reduces the number of discrete components and cost require d to achieve compliance with FCC Part 68. The Si3035 interfaces directly to standard modem DSPs and supports all FCC and J ATE out-of-band noise require ments. International support is provided by the pin compatible Si3034.
Functional Block Diagram
Si3021 Si3012
RRANGEMENT
Ordering Information
See page 50.
Pin Assignments
Si3021 (SOIC)
MCLK
FSYNC
SCLK
FC/RGDT
RESET
FC/RGDT
RESET
AOUT
1 2 3
V
4
D
SDO
5
SDI
6 7 8
Si3021 (TSSOP)
1
SDO
SDI
2 3 4 5
M1
6
C1A
7
GND
8
16 15 14 13 12 11 10
9
16 15 14 13 12 11 10
9
OFHK RGDT/FSD M0 V
A
GND C1A M1 AOUT
V
D
SCLK FSYNC MCLK OFHK RGDT/FSD M0 V
A
MCLK
SCLK
FSYNC
SDI
SDO
FC/RGT
RGDT/FSD
OFHK
MODE
RESET
AOUT
Digital
Interfa ce
Control
Interfa ce
Isolation Interfa ce
Isolation Interfa ce
Hybrid
DC
Termination
Ring Detect
Off-H o o k
Out
TX
In
RX
HYBD
VREG2 VREG DCT REXT IGND
RNG1 RNG2 QB QE
Si3012 (SOIC or TSSOP)
TSTA TSTB
IGND
RNG1 RNG2
C1B
QB QE
1 2 3 4 5 6 7 8
US Patent # 5,870,046
TX
16
NC
15
RX
14
REXT
13
DCT
12
HYBD
11
VREG2
10
VREG
9
US Patent # 6,061,009 Other Patents Pending
Rev. 1.2 12/00 Copyright © 2000 by Silicon Laboratories Si3035-DS12
Si3035
2 Rev. 1.2
Si3035
T
ABLE OF
C
ONTENTS

Section Page

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Improved JATE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Appendix—UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Rev. 1.2 3
Si3035

Electrical Specifications

Table 1. Recommended Operating Conditions
Parameter
1
Ambient Temperature T Si3021 Supply Voltage, Analog V Si3021 Supply Voltage, Digital
Notes:
1.
The Si3035 specifications are guaranteed when the typical application circuit (including component
3
Symbol Test Condition
A A
V
D
K-Grade 0 25 70 °C
Min
2
Typ
Max
2
Unit
4.75 5.0 5.25 V
3.0 3.3/5.0 5.25 V
tolerances) and any Si3021 and any Si3012 are used. See Figure 16 on page 15 for typical application circuit.
2.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
3. The digital supply, V operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals RGDT, OFHK, RESET, M0, and M1.
, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when
D
Table 2. Loop Characteristics
(VA = Charge Pump, VD = +3.3 V ± 0. 3 V, TA = 0 to 70°C for K-Grade, Refer to Figure 1)
Parameter Symbol Test Condition Min Typ Max Unit
DC Termination Voltage V DC Termination Voltage V DC Ring Current ( DC Ring Current
with caller ID)
(w/o caller ID)
AC Termination Impedance Z Operating Loop Current I
I
RDC
I
RDC
ACT
LP
TR TR
Loop Current Sense Bits LCS LCS = Fh 180 155 mA
IL = 20 mA 7.7 V
IL = 105 mA 12 V
—— 1 mA —— 2A
—600— 20 120 mA
Ring Voltage Detect V Ring Frequency F On-Hook Leakage Current I Ringer Equivalence Num. ( Ringer Equivalence Num.
with caller ID)
(w/o caller ID)
Si3012
RING
RD
R
LK
V
BAT
REN 1.0 1.67 — REN 0.2
TIP
+
600
V
TR
10 µF
Figure 1. Test Circuit for Loop Characteristics
4 Rev. 1.2
13 18 26 V
RMS
15 68 Hz
= –48 V 1 µA
I
L
Si3035
Table 3. DC Characteristics, VD = +5 V
(VA = +5 V ±5%, VD = +5 V ±5%, TA = 0 to 70°C for K-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage V Low Level Input Voltage V High Level Output Voltage V Low Level Output Voltage V Input Leakage Current I Power Supply Current, Analog I Power Supply Current, Digital Total Supply Current, Sleep Mode Total Supply Current, Deep Sleep
Notes:
1. All inputs at 0.4 or V
= 0 mA).
OUT
is not functional in this state.
2.
(Static I RGDT
1
1
1,2
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
D
IA + I IA + I
OH
OL
I
D
IH IL
IO = –2 mA 3.5 V
IO = 2 mA 0.4 V
L A
VA pin 0.3 1 mA VD pin 14 18 mA
D D
PDN = 1, PDL = 0 1.3 2.5 mA PDN = 1, PDL = 1 0.04 0.5 mA
3.5 V ——0.8V
–10 10 µA
Table 4. DC Characteristics, VD = +3.3 V
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage V Low Level Input Voltage V High Level Output Voltage V Low Level Output Voltage V Input Leakage Current I Power Supply Current, Analog Power Supply Current, Digital Total Supply Current, Sleep Mode Total Supply Current, Deep Sleep Power Supply Voltage, Analog
Notes:
1. Only a decoupling capacitor should be connected to V
2. There is no I
to the V
3. All inputs at 0.4 or V (Static I
4. RGDT
5. The charge pump is rec om m end ed to be used only when V
applied to the device before V
current consumption when the internal charge pump is enabled and only a decoupling cap is connected
A
pin.
A
= 0 mA).
OUT
is not functional in this state.
1,2
3
3
3,4
1,5
– 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded
D
is applied on power up if driven from separate supplies.
D
IH IL
OH
OL
L
I
A
I
D
IA + I IA + I
V
D D
A
2.0 V ——0.8V
IO = –2 mA 2.4 V
IO = 2 mA 0.35 V
–10 10 µA VA pin 0.3 1 mA VD pin 9 12 mA
PDN = 1, PDL = 0 1.2 2.5 mA PDN = 1, PDL = 1 0.04 0.5
Charge Pump On 4.3 4.6 5.00 V
when the charge pump is on.
A
< 4.5 V. When the charge pum p is not use d, VA should be
D
Rev. 1.2 5
Si3035
Table 5. AC Characteristics
(VA = Charge Pump, VD = +3.3 V ± 0.3 V, TA = 0 to 70°C for K-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Sample Rate
1
PLL1 Output Clock Frequency F Transmit Frequency Response Low –3 dB corner 16 Hz Receive Frequency Response Low –3 dB corner 16 Hz
2
Transmit Full Scale Level Receive Full Scale Level Dynamic Range Dynamic Range
4 5
Total Harmonic Distortion
(0 dB gain) V
2,3
(0 dB gain) V
6
Fs Fs = F
PLL1
FPLL1 = F
TX RX
/5120 7.2 11.025 kHz
PLL2
"
MCLK
M1/N1 36 58 MHz
—0.98—V —0.98—V
PEAK PEAK
DR VIN = 1 kHz, –3 dBFS 80 86 dB DR VIN = 1 kHz, –3 dBFS 84 dB
THD VIN = 1 kHz, –3 dBFS –84 dB Dynamic Range (call progress AOUT) DR THD (call progress AOUT) THD
AO
AO
AOUT Full Scale Level 0.75 V
VIN = 1 kHz 60 dB VIN = 1 kHz 1.0 %
—V
D
PP
AOUT Output Impedance 10 k Mute Level (call progress AOUT) –90 dB Dynamic Range (caller ID mode) DR Caller ID Full Scale Level (0 dB gain)
Notes:
1. See Figure 23 on page 22.
2. Parameter measured at TIP and RING of Figure16 on page 15.
3. Receive Full Scale Level will produce – 0.9 dBFS at SDO.
4.
DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth is 300 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
5.
DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth is 15 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
6. THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
2
V
CID
VIN = 1 kHz, –13 dBFS 60 dB
CID
—0.8—V
PEAK
6 Rev. 1.2
Si3035
Table 6. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage V Input Current, Si3021 Digital Input Pins I Digital Input Voltage V Operating Temperature Range T Storage Temperature Range T
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
, V
D
IN
IND
STG
A
–0.5 to 6.0 V
±10 mA
–0.3 to (VD + 0.3) V
A
–40 to 100 °C –65 to 150 °C
Table 7. Switching Characteristics—General Inputs
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter
1
Cycle Time, MCLK t MCLK Duty Cycle t Rise Time, MCLK t Fall Time, MCLK t MCLK Before RESET RESET
Pulse Width
M0, M1 Before RESET
Notes:
1.
All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET
3. M0 and M1 are typically connected to V
t
2
3
pulse width is the greater of 250 ns or 10 MCLK cycle times.
or GND and should not be changed during normal operation.
D
Symbol Min Typ Max Unit
16.67 1000 ns 40 50 60 % —— 5 ns —— 5 ns 10 cycles
250 ns 150 ns
t
mc dty
mr
t
rl
mxr
r f
MCLK
RESET
M0, M1
t
t
r
t
rl
t
mxr
mc
t
mr
Figure 2. General Inputs Timing Diagram
Rev. 1.2 7
t
f
V
IH
V
IL
Si3035
Table 8. Switching Characteristics—Serial Int erface (DCE = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter Symbol Min Typ Max Unit
Cycle time, SCLK t SCLK duty cy cle t Delay time, SCLK ↑ to FSYNC
t Delay time, SCLK to SDO valid t Delay time, SCLK ↑ to FSYNC
t Setup time, SDI before SCLK t Hold time, SDI after SCLK t Setup time, FC before SCLK t Hold time, FC after SCLK t
c dty d1 d2 d3
su
h sfc hfc
354 1/256 Fs ns
—50—% ——10ns ——20ns ——10ns 25 ns 20 ns 40 ns 40 ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are V
t
c
SCLK
t
d1
FSYNC (mode 0)
= VD – 0.4 V, VIL = 0.4 V
IH
t
d3
V
OH
V
OL
FSYNC (mode 1)
16 Bit SDO
16 Bit SDI
FC
t
d3
t
d2
D15 D14 D1 D0
t
su
t
h
Figure 3. Serial Interface Timing Diagr am
D0D1D14D15
t
sfc
t
hfc
8 Rev. 1.2
Table 9. Switching Characteristics—Serial Int erface (DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Si3035
Parameter
1,2
Cycle Time, SCLK t SCLK Duty Cycle t Delay Time, SCLK ↑ to FSYNC Delay Time, SCLK ↑ to FSYNC
t
t Delay Time, SCLK to SDO valid t Delay Time, SCLK to SDO Hi-Z t Delay Time, SCLK ↑ to RGDT Delay Time, SCLK ↑ to RGDT
t
t Setup Time, SDO Before SCLK t Hold Time, SDO After SCLK t Setup Time, SDI Before SCLK t Hold Time, SDI After SCLK t
Symbol Min Typ Max Unit
c
dty
d1 d2 d3 d4 d5 d6 su
h
su2
h2
354 1/256 Fs ns
—50 —% — 10 ns — 10 ns
0.25tc – 20 0.25tc + 20 ns — 20 ns — 20 ns — 20 ns 25 ns 20 ns 25 ns 20 ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
32 SCLKs
t
c
16 SCLKs 16 SCLKs
= VD – 0.4 V, VIL = 0.4 V.
IH
SCLK
t
d1
FSYNC
(mode 1)
FSYNC
(mode 0)
t
SDO
(ma ster)
SDO
(slave 1)
FSD
(Mode 0)
FSD
(Mode 1)
SDI D15 D0
t
d2
t
d5
d3
t
su
D15 D14 D13 D0
t
su2
D14
t
h
t
h2
D13
t
d2
t
d6
t
d4
t
d5
t
d3
D15
t
d5
t
d2
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
Rev. 1.2 9
Si3035
Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter
1,2
Cycle Time, SCLK t SCLK Duty Cycle t Delay Time, SCLK ↑ to FSYNC Delay Time, SCLK ↑ to FSYNC
t
t Delay Time, SCLK to SDO valid t Delay Time, SCLK to SDO Hi-Z t Delay Time, SCLK ↑ to RGDT
t Setup Time, SDO Before SCLK t Hold Time, SDO After SCLK t Setup Time, SDI Before SCLK t Hold Time, SDI After SCLK t
Symbol Min Typ Max Unit
c
dty
d1 d2 d3 d4 d5 su
h
su2
h2
354 1/256 Fs ns
—50 —% — 10 ns — 10 ns
0.25tc – 20 0.25tc + 20 ns — 20 ns — 20 ns 25 ns 20 ns 25 ns 20 ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
= VD – 0.4 V, VIL = 0.4 V.
IH
SCLK
FSYNC
(mode 1)
SDO
(ma ste r)
SDO
(slave 1)
FSD
SDI
t
c
t
d1
t
d3
t
d2
D15
t
su
t
h
D14 D13 D0
t
d4
t
d3
D15
t
d5
D14
t
h2
t
su2
D15 D1 D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
10 Rev. 1.2
Table 11. Digital FIR Filter Characteristics—Transmit and Receive
(VA = Charge Pump, VD = +5 V ±5%, Sample Rate = 8kHz, TA = 0 to 70°C for K-Grade)
Parameter Symbol Min Typ Max Unit
Si3035
Passband (0.1 dB) Passband (3 dB)
F
(0.1 dB)
F
(3 dB)
0—3.3kHz
0—3.6kHz Passband Ripple Peak-to-Peak –0.1 0.1 dB Stopband 4.4 kHz Stopband Attenuation –74 dB Group Delay
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.
t
gd
12/Fs sec
Table 12. Digital IIR Filter Characteri stics—Transmit and Receive
(VA = Charge Pump, VD = +5 V ±5%, Sample Rate = 8 kHz, TA = 0 to 70°C for K-Grade)
Parameter Symbol Min Typ Max Unit
Passband (3 dB)
F
(3 dB)
Passband Ripple Peak-to-Peak –0.2 0.2 dB Stopband 4.4 kHz Stopband Attenuation –40 dB Group Delay
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show
group delay versus input frequency.
t
gd
0—3.6kHz
1.6/Fs sec
Rev. 1.2 11
Si3035
Attenuation—dB
Input Frequency—Hz
Figure 6. FIR Receive Filter Response
Attenuation—dB
Attenuation—dB
Input Frequency—Hz
Figure 8. FIR Transmit Filter Response
Attenuation—dB
Input Frequency—Hz
Figure 7. FIR Receive Filter Passband Ripple
For Figures 6–9, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows:
F
where Fs is the sample frequency.
12 Rev. 1.2
(0.1 dB)
F
(– 3 dB)
= 0.4125 Fs
= 0.45 Fs
Input Frequency—Hz
Figure 9. FIR T ransmi t Filter Passband Ripple
Si3035
Attenuation—dB
Input Frequency—Hz
Figure 10. IIR Receive Filter Response
Attenuation—dB
Attenuation—dB
Input Frequency—Hz
Figure 12. IIR T ransmit Filter Response
Attenuation—dB
Input Frequency—Hz
Figure 11. IIR Receive Filter Passband Ripple
For Figures 10–13, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows:
F
(–3 dB)
where Fs is the sample frequency.
Input Frequency—Hz
Figure 13. IIR Transmit Filter Passband Ripple
= 0.45 Fs
Rev. 1.2 13
Si3035
Delay—µs
Input Frequency—Hz
Figure 14. IIR Receive Group Delay Figure 15. IIR Transmit Group Delay
Delay—µs
Input Frequency—Hz
14 Rev. 1.2

Typical Application Circuit

p
Decoupling cap for U1 VD
VCC
C10
RGDTb OFHKb
MCLK
FSYNCb
SCLK
SDO
RESETb
AOUT
M0
SDI
FC
M1
R3
Decoupling cap for U1 VA
10
C3
Z4
U1
1
MCLK
2
FSYNC
3
SCLK
4
VD
5
SDO
6
SDI
7
FC
89
RESET AOUT
SOIC Pinout
Si3021
OFHK RGDT
GND
16 15 14
M0
13
VA
12 11
C1A
10
M1
D3 BAV99
R27
C30
Rev. 1.2 15
No Ground Plane In DAA Section
R28
C1
D4 BAV99
C2
Z5
U2
Si3012 1 2 3 4 5 6 7 89
TSTA TSTB
NC2 IGND C1B
REXT
RNG1
DCT RNG2
HYBD
QB
VREG2
QE VREG
16
TX
15 14
RX
13 12 11 10
C6
C16
R23
R1
R4
C12
R2
C8
R21
+
C5
C23
+
R18
Z1
R10
Q1
R5
Q2
R6
C20
Q3
FB2
RING
Note 1: R3 is not required when Vcc=3.3 V and the charge pump is enabled (CPE = 1).
Note 2: If JATE support is not required, R21, C12 and C23 may be removed (R21 is effectively 0 ohms) and R4 should be changed to a 604 ohm, 1/4 W, +- 1%.
Note 3: See Appendix for applications requiring UL 1950 3rd Edition com
liance.
D2
C9
C11
R22
C4
C7
R9
RV2
D1
C25
RV1
C24
FB1
C32
C31
TIP
Si3035
Figure 16. Typical Application Schematic
Si3035

Bill of Materials

Table 13. Component Values—Typical Application
Component
1
Value Supplier(s)
C1,C4 150 pF, 3 kV, X7R, ±20% Novacap, Venkel, Johanson, Murata,
Panasonic, SMEC C2 Not Installed C3 0.22 µF, 16 V, X7R, ±20% C5 1 µF, 16 V, Tant/Elec, ±20%
C6,C10,C16 0.1 µF, 16 V, X7R, ±20%
C7,C8,C9 15 nF, 250 V, X7R, ±20% Novacap, Johanson, Murata, Panasonic, SMEC
C11 39 nF, 16 V, X7R, ±20%
2
C12
2
C23
C24, C25, C31,C32
4
C30
5
D1,D2
3
2.7 nF, 16 V, X7R, ±20%
0.1 µF, 16 V, Tant/Elec/X7R, ±20% 1000 pF, 3 kV, X7R, ±10% Novacap, Venkel, Johanson, Murata, Panasonic, SMEC
Not Installed
Dual Diode, 300 V, 225 mA Central Semiconductor
D3,D4 BAV99 Dual Diode, 70 V, 350 mW Diodes, Inc., OnSemiconductor, Fairchild
FB1,FB2 Ferrite B ead Murata
Q1,Q3 A42, NPN, 300 V OnSemiconductor, Fairchild
Q2 A92, NPN, 300 V OnSemiconductor, Fairchild RV1 Sidactor, 275 V, 100 A Teccor, ST Microelectronics, Microsemi, TI RV2 MOV, 240 V Panasonic
R1 51 Ω, 1/2 W ±5%
R2 15 Ω, 1/4 W ±5%
R4
2
6
R3
,R18,R21
2
Not Installed
301 Ω, 1/10 W, ±1%
R5,R6 36 kΩ, 1/10 W ±5%
R9,R10 2 kΩ, 1/10 W ±5% R22,R23 20 k, 1/10 W ±5% R27,R28 10 , 1/10 W ±5%
U1 Si3021 Silicon Labs U2 Si3012 Silicon Labs Z1 Zener diode , 18 V Vishay, Rohm, OnSemiconductor
Z4,Z5 Zener diode, 5.6 V, 1/2 W Diodes, Inc., OnSemiconductor, Fairchild
Notes:
1. The following reference designators were intentionally omitted: C13–C15, C17–C22, C26–C29, R7, R8, R11–R17,
R19, and R20.
2. If JATE support is not required, C12, and C23 may be removed.
3.
Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, ±10% and C31, C32 not installed).
4. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, ±10%).
5. Several diode bridge configurations are acc ep tab le (sup pl iers incl ude General Semi, Diodes Inc.)
6. If the charge pump is not enabl ed (with th e CPE bit in Register 6), V
a 10 , 1/10 W, ±5% if V
is also 4.75 to 5.25 V.
D
must be 4.75 to 5.25 V. R3 can be installed with
A
16 Rev. 1.2
Si3035

Analog Output

Figure 17 illustrates an optional application circuit to support the analo g output capability of the Si3035 for call progress monitoring purp oses . T he AR M bi ts in Regi s ter 6 allow the receive path to be atte nua ted by 0 dB, –6 dB, or –12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by –20 dB, –26 dB, or –32 dB. Both the transmit and receive paths can also be independently muted.
+5 V
AOUT
C2
C1
R3
C6 R1
6
3
+
5
2
– 4
C3
R2
C4
+
C5
Speaker
Figure 17. Optional Connection to AOUT for a Call Progress Speaker
Table 14. Component Values—Optional Connection to AOUT
Symbol Value
C1 2200 pF, 16 V, ±20%
C2, C3, C5 0.1 µF, 16 V, ±20%
C4 100 µF, 16 V, Elec. ±20% C6 820 pF, 16 V, ±20% R1 3 k, 1/10 W, ±5% R2 10 , 1/10 W, ±5% R3 47 kΩ, 1/10 W, ±5% U1 LM386
Rev. 1.2 17
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