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Silicon Laboratories
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CP2200
User Manual
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Silicon Laboratories CP2200 User Manual

SINGLE-CHIP ETHERNET CONTROLLER
CP2200/1
Ethernet Controller
Integrated IEEE 802.3 MAC and 10 BASE-T PHYFully compatible with 100/1000 BASE-T networksFull/Half duplex with auto-negotiationAutomatic polarity detection and correctionAutomatic retransmission on collisionAutomatic padding and CRC generationSupports broadcast and multi-cast MAC addressing
Parallel Host Interface (30 Mbps Transfer Rate)
8-bit multiplexed or non-multiplexed modeOnly 11 I/O pins required in multiplexed mode
®
IntelInterrupt on received packets and Wake-on-LAN
or Motorola® Bus Format
8 kB Flash Memory
8192 bytes ISP non-volatile memoryFactory pre-programmed unique 48-bit MAC AddressNo external EEPROM required
Other Features
LED output drivers (Link/Activity)Dedicated 2 kB RAM transmit buffer and 4 kB RAM
receive FIFO buffer
Power-on Reset 5 V Tolerant I/O
Software Support
Royalty-free TCP/IP stack with device driversTCP/IP Stack Configuration WizardHardware diagnostic software and example code
Example Applications
Remote sensing and monitoringInventory managementVoIP phone adaptersPoint-of-sale devicesNetwork clocksEmbedded Web ServerRemote Ethernet-to-UART bridge
Supply Voltage
3.1 to 3.6 V
Package
Pb-free 48-pin TQFP (9x9 mm footprint)Pb-free 28-pin QFN (5x5 mm footprint)
Ordering Part Number
CP2200-GQ (48-pin)CP2201-GM (28-pin)
Temperature Range: –40 to +85 °C
20 MHz
XTAL
CP2200
8 kB
Clock
Flash
Host
Interface
Parallel Bus
2 kB
Tx Buffer
Ethernet
MAC
4 kB
Rx FIFO
LED
Control
Ethernet
PHY
TX+/TX-
RX+/RX-
RJ-45
ACT LED
LINK LED

Figure 1. Example System Diagram

Rev. 1.0 5/07 Copyright © 2007 by Silicon Laboratories CP2200/1
CP2200/1
2 Rev. 1.0
CP2200/1
TABLE OF CONTENTS
Section Page
1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Pinout and Package Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6.2. Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6.3. Interrupt Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6.4. Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6.5. LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.6. Sending and Receiving Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Internal Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7.1. Random Access to RAM Transmit and Receive Buffers . . . . . . . . . . . . . . . . . . . . . . 23
7.2. Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
8. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9. Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1. Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
9.2. Power-fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.3. Oscillator-Fail Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.4. External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
9.5. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.6. Determining the Source of the Last Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.7. De-Selecting Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
10.1. Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
10.2. Link Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
10.3. Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.4. Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.5. Disabling Secondary Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11. Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
11.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
11.2. Transmitting a Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
11.3. Overriding Transmit Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.4. Transmit Buffer and AutoWrite Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.5. Transmit Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
12. Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
12.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
12.2. Reading a Packet Using the Autoread Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .58
12.3. Timing and Buffer Overflow Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.4. Initializing the Receive Buffer, Filter and Hash Table . . . . . . . . . . . . . . . . . . . . . . .59
Rev. 1.0 3
CP2200/1
12.5. Receive Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.6. Advanced Receive Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.7. Receive Buffer Advanced Status and Control Registers . . . . . . . . . . . . . . . . . . . . . 67
13. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
13.1. Programming the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
13.2. Reading the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
13.3. Flash Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14. Media Access Controller (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
14.1. Initializing the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
14.2. Accessing the Indirect MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.3. Indirect MAC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
15. Physical Layer (PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
15.1. Auto-Negotiation and Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
15.2. Auto-Negotiation Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
15.3. Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
15.4. Link Integrity Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
15.5. Receiver Smart Squelch and Automatic Polarity Correction . . . . . . . . . . . . . . . . . . 89
15.6. Transmitter Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
15.7. Initializing the Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
16. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
16.1. Non-Multiplexed Intel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
16.2. Multiplexed Intel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
16.3. Non-Multiplexed Motorola Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16.4. Multiplexed Motorola Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
4 Rev. 1.0
CP2200/1

1. System Overview

The CP2200/1 is a single-chip Ethernet controller containing an integrated IEEE 802.3 Ethernet Media Access Controller (MAC), 10BASE-T Physical Layer (PHY), and 8 kB Non-Volatile Flash Memory available in a compact 5 x 5 mm QFN-28 package (sometimes called “MLF” or “MLP”) and a 48-pin TQFP package. The CP2200/1 can add Ethernet connectivity to any microcontroller or host processor with 11 or more Port I/O pins. The 8-bit parallel interface bus supports both Intel and Motorola bus formats in multiplexed and non-multiplexed mode. The data transfer rate in non-multiplexed mode can exceed 30 Mbps.
The on-chip Flash memory may be used to store user constants, web server content, or as general purpose non­volatile memory. The Flash is factory preprogrammed with a unique 48-bit MAC address stored in the last six memory locations. Having a unique MAC address stored in the CP2200/1 often removes the serialization step from the product manufacturing process of most embedded systems.
The CP2200/1 has four power modes with varying levels of functionality that allow the host processor to manage the overall system power consumption. The optional interrupt pin also allows the host to enter a “sleep” mode and awaken when a packet is received or when the CP2200/1 is plugged into a network. Auto-negotiation allows the device to automatically detect the most efficient duplex mode (half/full duplex) supported by the network.
The Ethernet Development Kit (Ethernet-DK) bundles a C8051F120 MCU Target Board, CP2200 Ethernet Development Board (AB4), the Silicon Laboratories IDE, all necessary debug hardware, and a TCP/IP Configuration Wizard. The Ethernet Development Kit includes all hardware, software, and examples necessary to design an embedded system using the CP2200. The CP2200 Ethernet Development Board is also compatible with the C8051F020TB and C8051F340TB. Individual target boards may be purchased online by visiting www.silabs.com.
Rev. 1.0 5
CP2200/1

2. Typical Connection Diagram

Figure 2 and Figure 3 show typical connection diagrams for the 48-pin CP2200 and 28-pin CP2201.
+3VD
0.1 uF 0.1 uF 0.1 uF 10 uF
20 MHz
10 MΩ
22 pF22 pF
MCU
A15
A[7:0]
D[7:0] D[7:0]
RD RD
WR WR
Optional
8
8
Optional
XTAL1
XTAL2
CS
A[7:0]
INTINT
DGND1
AV+
VDD1
VDD2
CP2200
+3VD
4.7 kΩ
RST
MUXEN
MOTEN
Integrated RJ-45 Jack
LINK
ACT ACT LINK
TX+
TX–
RX+
RX–
8 Ω
0.001 uF
0.001 uF
8 Ω
0.1 uF
100 Ω
TXP
TXN TCT
RXP
RXN
1:2.5
1:1
RJ-45
1
2
3
4
5
6
7
8
DGND2
GND AGND
0.1 uF
Note: The CP220x should be placed within 1 inch of the transformer for optimal performance.

Figure 2. Typical Connection Diagram (Non-Multiplexed)

RCT
Chassis Ground
6 Rev. 1.0
+3VD
CP2200/1
0.1 uF 0.1 uF 0.1 uF 10 uF
XTAL1
20 MHz
MCU
AD[7:0] AD[7:0]
10 MΩ
22 pF22 pF
XTAL2
CS
8
RD RD
WR WR
ALE ALE
Optional
INTINT
DGND1
DGND2
GND AGND
AV+
VDD1
VDD2
CP2201
+3VD
4.7 kΩ
RST
MOTEN
LA LINK/ACTIVITY
Integrated RJ-45 Jack
8 Ω
TX+
TX–
RX+
RX–
0.001 uF
0.001 uF
8 Ω
0.1 uF
0.1 uF
100 Ω
TXP
TXN TCT
RXP
RXN
RCT
1:2.5
1:1
RJ-45
1
2
3
4
5
6
7
8
Note: The CP220x should be placed within 1 inch of the transformer for optimal performance.

Figure 3. Typical Connection Diagram (Multiplexed)

Chassis Ground
Rev. 1.0 7
CP2200/1

3. Absolute Maximum Ratings

Table 1. Absolute Maximum Ratings

Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any I/O Pin or RST
Voltage on V
Maximum Total current through V
Maximum output current sunk by RST
Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional
operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
with respect to GND –0.3 — 4.2 V
DD
with respect to GND –0.3 — 5.8 V
and GND — — 500 mA
DD
or any I/O pin — — 100 mA
8 Rev. 1.0
CP2200/1

4. Electrical Characteristics

Table 2. Global DC Electrical Characteristics

VDD= 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Supply Voltage 3.1 3.3 3.6 V
Supply Current in Normal Mode (Transmitting) V
Supply Current in Normal Mode (No Network
= 3.3 V — 75 155 mA
DD
V
=3.3 V — 60 — mA
DD
Traffic)
Supply Current with Transmitter and Receiver
V
=3.3 V — 47 — mA
DD
Disabled (Memory Mode)
Supply Current in Reset V
Supply Current in Shutdown Mode V
= 3.3 V — 15 — mA
DD
=3.3 V — 6.5 — mA
DD
Specified Operating Temperature Range –40 — +85 °C

Table 3. Digital I/O DC Electrical Characteristics

VDD= 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max UNITS
Output High Voltage (V
Output Low Voltage (V
Input High Voltage (V
Input Low Voltage (V
Input Leakage Current — 25 50 µA
)I
OH
)I
OL
)2.0——V
IH
)——0.8V
IL
OH
I
=–10µA
OH
I
=–10mA
OH
=8.5mA
OL
I
OL
I
OL
=–3mA
=10µA =25mA
– 0.7
V
DD
V
– 0.1
DD
—
— — —
— —
V
– 0.8
DD
— —
1.0
— — —
0.6
0.1 —
V
V
Rev. 1.0 9
CP2200/1

5. Pinout and Package Definitions

Table 4. CP2200/1 Pin Definitions

Name Pin Numbers Type Description
48-pin 28-pin
AV+ 5 3 Power In 3.1–3.6 V Analog Power Supply Voltage Input.
AGND 4 2 Analog Ground
V
DD1
DGND1 14 9 Digital Ground
V
DD2
DGND2 31 20 Digital Ground
RST
LINK 3* — D Out Link LED. Push-pull output driven high when valid 10BASE-T link
ACT 2* — D Out Activity LED. Push-pull output driven high for 50 ms when any
LA — 1* D Out Link or Activity LED. Push-pull output driven high when valid link
XTAL1 46 28 A In Crystal Input. This pin is the return for the external oscillator driver.
XTAL2 45* 27* A Out Crystal Output. This pin is the excitation driver for a quartz crystal.
13 8 Power In 3.1–3.6 V Digital Power Supply Voltage Input.
30 19 Power In 3.1–3.6 V Digital Power Supply Voltage Input.
15 10 D I/O Device Reset. Open-drain output of internal POR and VDD monitor.
An external source can initiate a system reset by driving this pin low for at least 15 µs.
pulses are detected (Link Good) and driven low when valid 10BASE-T link pulses are not detected (Link Fail).
packet is transmitted or received and driven low all other times.
pulses are detected (Link Good) and driven low otherwise (Link Fail). The output is toggled for each packet transmitted or received, then returns to its original state after 50 ms.
This pin can be overdriven by an external CMOS clock.
TX+ 9 6 A Out 10BASE-T Transmit, Differential Output (Positive).
TX– 10 7 A Out 10BASE-T Transmit, Differential Output (Negative).
RX+ 7 5 A In 10BASE-T Receive, Differential Input (Positive).
RX– 6 4 A In 10BASE-T Receive, Differential Input (Negative).
MOTEN 43 26 D In Motorola Bus Format Enable. This pin should be tied directly to V
for Motorola bus format or directly to GND for Intel bus format.
MUXEN 44 — D In Multiplexed Bus Enable. This pin should be tied directly to V
multiplexed bus mode or directly to GND for non-multiplexed bus mode.
INT
*Note: Pins can be left unconnected when not used.
10 Rev. 1.0
42 25 D Out Interrupt Service Request. This pin provides notification to the host.
DD
for
DD
CP2200/1
Table 4. CP2200/1 Pin Definitions (Continued)
Name Pin Numbers Type Description
48-pin 28-pin
CS 41 24 D In Device Chip Select.
RD
/(DS) 39 22 D In Read Strobe (Intel Mode) or
Data Strobe (Motorola Mode)
WR
/(R/W) 40 23 D In Write Strobe (Intel Mode) or
Read/Write Strobe (Motorola Mode)
D0/AD0 16 11 D I/O Bit 0, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D1/AD1 17 12 D I/O Bit 1, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D2/AD2 18 13 D I/O Bit 2, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D3/AD3 19 14 D I/O Bit 3, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D4/AD4 20 15 D I/O Bit 4, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D5/AD5 21 16 D I/O Bit 5, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D6/AD6 22 17 D I/O Bit 6, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
D7/AD7 23 18 D I/O Bit 7, Non-Multiplexed Data Bus or Multiplexed Address/Data Bus
A0 27* — D In Bit 0, Non-Multiplexed Address Bus
A1 28* — D In Bit 1, Non-Multiplexed Address Bus
A2 29* — D In Bit 2, Non-Multiplexed Address Bus
A3/ALE/(AS) 32 — D In Bit 3, Non-Multiplexed Address Bus
ALE Strobe (Multiplexed Intel Mode) Address Strobe (Multiplexed Motorola Mode)
ALE/(AS) — 21 D In ALE Strobe (Intel Mode)
Address Strobe (Motorola Mode)
A4 33* — D In Bit 4, Parallel Interface Non-Multiplexed Address Bus
A5 34* — D In Bit 5, Parallel Interface Non-Multiplexed Address Bus
A6 37* — D In Bit 6, Parallel Interface Non-Multiplexed Address Bus
A7 38* — D In Bit 7, Parallel Interface Non-Multiplexed Address Bus
NC 1, 8,
11,12
24–26
35,36
47, 48
— These pins should be left unconnected or tied to V
DD
.
*Note: Pins can be left unconnected when not used.
Rev. 1.0 11
CP2200/1
NC
48
NC
47
46
XTAL2
45
MUXEN
44
XTAL1
INT
MOTEN
43
42
CS
41
40
WR/(R/W)
39
38
A6
37
A7
RD/(DS)
NC
ACT
LINK
AGND
AV+
RX-
RX+
NC
TX+
TX-
NC
NC
10
11
12
1
2
3
4
5
6
7
8
9
13
14
15
CP2200
Top View
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A5
A4
A3/ALE/(AS)
DGND2
VDD2
A2
A1
A0
NC
NC
VDD1
RST
DGND1
D1/AD1
D0/AD0
D2/AD2
D3/AD3

Figure 4. 48-pin TQFP Pinout Diagram

12 Rev. 1.0
D4/AD4
NC
D5/AD5
D6/AD6
D7/AD7
48
PIN 1
IDENTIFIER
CP2200/1
D
D1
E1
E
1
Table 5. TQFP-48 Package
Dimensions
MM
Min Typ Max
A——1.20 A1 0.05 — 0.15 A2 0.95 1.00 1.05
b 0.17 0.22 0.27
D — 9.00 —
D1 — 7.00 —
E — 9.00 —
e — 0.50 — E1 — 7.00 —
A2
e
A
A1
b

Figure 5. 48-pin TQFP Package Dimensions

Rev. 1.0 13
CP2200/1
GND
LA
AGND
AV+
RX-
RX+
TX+
TX-
XTAL1
28
1
2
3
XTAL2
27
MOTEN
26
INT
25
CS
24
WR/(R/W)
23
RD/(DS)
22
21
20
19
ALE/(AS)
DGND2
VDD2
CP2201
4
18
AD7
Top View
5
6
GND
7
8
9
10
11
12
13
14
17
16
15
AD6
AD5
AD4
VDD1
RST
DGND1
AD0
AD1
AD2
AD3

Figure 6. QFN-28 Pinout Diagram (Top View)

14 Rev. 1.0
CP2200/1
Bottom View
8
9
10
L
7
6
b
5
4
e
3
2
1
DETAIL 1
28
D2
27
D2
2
26
6 x e
12
13
E2
23
14
R
22
15
16
17
18
19
20
21
6 x e
11
2
E2
24
25
D
Side View
A2
A
Table 6. QFN-28 Package
Dimensions
Min Typ Max
A 0.80 0.90 1.00 A1 0 0.02 0.05 A2 0 0.65 1.00
E
A3 — 0.25 —
b 0.18 0.23 0.30
D—5.00— D2 2.90 3.15 3.35
E—5.00— E2 2.90 3.15 3.35
e—0.5—
L 0.45 0.55 0.65
N—28—
ND — 7 — NE — 7 —
R0.09— —
AA — 0.435 — BB — 0.435 — CC — 0.18 — DD — 0.18 —
MM
A3
e
A1
DETAIL 1
AA
BB
CC
DD

Figure 7. QFN-28 Package Drawing

Rev. 1.0 15
CP2200/1
Top View
0.85 mm
0.50 mm
0.20 mm
0.30 mm
0.20 mm
Connection
0.85 mm
0.50 mm
0.20 mm
Optional
GND
0.20 mm
0.30 mm
0.50 mm
0.10 mm
0.35 mm
b
D2
L
E2
e
0.50 mm
0.35 mm
0.10 mm
D

Figure 8. Typical QFN-28 Landing Diagram

16 Rev. 1.0
E
0.50 mm
0.20 mm
Top View
0.20 mm
CP2200/1
0.85 mm
0.30 mm
0.85 mm
0.50 mm
0.20 mm
0.20 mm
0.30 mm
0.50 mm
0.10 mm
0.60 mm
0.60 mm
0.70 mm
b
L
e
E2
0.50 mm
0.35 mm
0.10 mm
0.30 mm
0.20 mm
0.40 mm
0.35 mm
D2
D
E

Figure 9. Typical QFN-28 Solder Paste Diagram

Rev. 1.0 17
CP2200/1

6. Functional Description

6.1. Overview

In most systems, the CP2200/1 is used for transmitting and receiving Ethernet packets, non-volatile data storage, and controlling Link and Activity LEDs. The device is controlled using direct and indirect internal registers accessible through the parallel host interface. All digital pins on the device are 5 V tolerant.

6.2. Reset Initialization

After every CP2200/1 reset, the following initialization procedure is recommended to ensure proper device operation:
Step 1: Wait for the reset pin to rise. This step takes the longest during a power-on reset. Step 2: Wait for Oscillator Initialization to complete. The host processor will receive notification through the
interrupt request signal once the oscillator has stabilized.
Step 3: Wait for Self Initialization to complete. The INT0 interrupt status register on page 31 should be
checked to determine when Self Initialization completes.
Step 4: Disable interrupts (using INT0EN and INT1EN on page 33 and page 36) for events that will not be
monitored or handled by the host processor. By default, all interrupts are enabled after every reset.
Step 5: Initialize the physical layer. See “15.7. Initializing the Physical Layer” on page 90 for a detailed
physical layer initialization procedure. Step 6: Enable the desired Activity, Link, or Activity/Link LEDs using the IOPWR register on page 45. Step 7: Initialize the media access controller (MAC). See “14.1. Initializing the MAC” on page 78 for a
detailed MAC initialization procedure. Step 8: Configure the receive filter. See “12.4. Initializing the Receive Buffer, Filter and Hash Table” on
page 59 for a detailed initialization procedure. Step 9: The CP2200/1 is ready to transmit and receive packets.

6.3. Interrupt Request Signal

The CP2200/1 has an interrupt request signal (INT) that can be used to notify the host processor of pending interrupts. The INT dedicate a port pin to the INT generating events have occurred. If the /INT signal is not used, pending interrupts such a Receive FIFO Full must still be serviced.
The 14 interrupt sources are listed below. Interrupts are enabled on reset and can be disabled by software. Pending interrupts can be cleared (allowing the INT registers. See “8. Interrupt Sources” on page 30 for a complete description of the CP2200/1 interrupts.
End of Packet Reached Packet Received
Receive FIFO Empty “Wake-on-LAN” Wakeup Event
Receive FIFO Full Link Status Changed
Oscillator Initialization Complete Jabber Detected
Self Initialization Complete Auto-Negotiation Failed
Flash Write/Erase Complete Remote Fault Notification
Packet Transmitted Auto-Negotiation Complete
signal is asserted upon detection of any enabled interrupt event. Host processors that cannot
signal can periodically poll the interrupt status registers to see if any interrupt
signal to de-assert) by reading the self-clearing interrupt
18 Rev. 1.0
CP2200/1

6.4. Clocking Options

The CP2200/1 can be clocked from an external parallel-mode crystal oscillator or CMOS clock. Figure 10 and Figure 11 show typical connections for both clock source types. If a crystal oscillator is chosen to clock the device, the crystal is started once the device is released from reset and remains on until the device reenters the reset state or loses power.
XTAL1
10 MΩ20 MHz
XTAL2

Figure 10. Crystal Oscillator Example

Important note on external crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal
should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with a ground plane from any other traces that could introduce noise or interference.
20 MHz
XTAL1
CMOS
Clock
XTAL2
No Connect

Figure 11. External CMOS Clock Example

Table 7 lists the clocking requirements of the CP2200/1 when using a crystal oscillator or CMOS clock. Table 8 shows the electrical characteristics of the XTAL1 pin. These characteristics are useful when selecting an external CMOS clock.
Rev. 1.0 19
CP2200/1

Table 7. Clocking Requirements

VDD= 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max UNITS
Frequency — 20 — MHz
Frequency Error — —
Duty Cycle 455055%

Table 8. Input Clock Pin (XTAL1) DC Electrical Characteristics

VDD= 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameters Conditions Min Typ Max UNITS
XTAL1 Input Low Voltage — — 0.7 V
XTAL1 Input High Voltage 2.0 — — V
±50 ppm
20 Rev. 1.0
CP2200/1

6.5. LED Control

The CP2200/1 can be used to control link status and activity LEDs. The CP2200 (48-pin TQFP) has two push-pull LED drivers that can source up to 10 mA each. The CP2201 (28-pin QFN) has a single push-pull LED driver that turns the LED on or off based on the link status and blinks the LED when activity is detected on a good link. Table 9 shows the function of the LED signals available on the CP2200/1.
Table 9 .
Signal Device Description
LINK CP2200 Asserted when valid link pulses are detected.
ACT CP2200 Asserted for 50 ms for each packet transmitted or received.
LA CP2201 Asserted when valid link pulses are detected and toggled for 50 ms for
each packet transmitted or received.
Figure 12 shows a typical LED connection for the CP2200. The CP2201 uses an identical connection for the LA (link/activity) pin. The LED drivers are enabled and disabled using the IOPWR register on page 45.
LED Control Signals
LINK
ACT

Figure 12. LED Control Example (CP2200)

Rev. 1.0 21
CP2200/1

6.6. Sending and Receiving Packets

After reset initialization is complete, the CP2200/1 is ready to send and receive packets. Packets are sent by loading data into the transmit buffer using the AutoWrite register and writing ‘1’ to TXGO. See “11.2. Transmitting a Packet” on page 48 for detailed information on how to transmit a packet using the transmit interface. A Packet Transmitted interrupt will be generated once transmission is complete.
Packet reception occurs automatically when reception is enabled in the MAC and the receive buffer is not full. Once a packet is received, the host processor is notified by generating a Packet Received interrupt. The host may read the packet using the AutoRead interface. See “12.2. Reading a Packet Using the Autoread Interface” on page 58 and “12.4. Initializing the Receive Buffer, Filter and Hash Table” on page 59 for additional information on using and initializing the receive interface.
22 Rev. 1.0
CP2200/1

7. Internal Memory and Registers

The CP2200/1 is controlled through direct and indirect registers accessible through the parallel host interface. The host interface provides an 8-bit address space, of which there are 114 valid direct register locations (see Table 11 on page 25). All remaining addresses in the memory space are reserved and should not be read or written. The direct registers provide access to the RAM buffers, Flash memory, indirect MAC configuration registers, and other status and control registers for various device functions.
Figure 13 shows the RAM and Flash memory organization. The transmit and receive RAM buffers share the same address space and are both accessed using the RAMADDRH:RAMADDRL pointer. Each of the buffers has a dedicated data register. The Flash memory has a separate address space and a dedicated address pointer and data register. See “13. Flash Memory” on page 73 for detailed information on how to read and write to Flash.
Transmit Buffer (2K)
0x0000 – 0x07FF
Receive Buffer (4K)
0x0000 – 0x0FFF
Flash Memory (8K)
0x0000 – 0x1FFF
RAMADDRH:RAMADDRL FLASHADDRH:FLASHADDRL

Figure 13. RAM Buffers and Flash Memory Organization

7.1. Random Access to RAM Transmit and Receive Buffers

The most common and most efficient methods for accessing the transmit and receive buffers are the AutoWrite and AutoRead interfaces. These interfaces allow entire packets to be written or read at a time. In very few cases, the transmit and receive buffers may need to be accessed randomly. An example of this is a system in which a specific byte in the packet is checked to determine whether to read the packet or discard it. The following procedure can be used to read or write data to either RAM buffer:
Step 1: Write the address of the target byte to RAMADDRH:RAMADDRL. Step 2: Transmit Buffer:
Read or write 8-bit data to RAMTXDATA to read or write from the target byte in the transmit buffer.
Receive Buffer:
Read or write 8-bit data to RAMRXDATA to read or write from the target byte in the receive buffer.
Note: Reads and writes of the RAM buffers using the random access method are independent of the
AutoRead and AutoWrite interfaces. Each of the interfaces has a dedicated set of address and data
registers. See “11.2. Transmitting a Packet” on page 48 and “12.2. Reading a Packet Using the
Autoread Interface” on page 58 for additional information about the AutoRead and AutoWrite
interfaces.
Rev. 1.0 23
CP2200/1

Register 1. RAMADDRH: RAM Address Pointer High Byte

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address:
Bits7–0: RAMADDRH: RAM Address Register High Byte
Holds the most significant eight bits of the target RAM address.

Register 2. RAMADDRL: RAM Address Pointer Low Byte

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address:
Bits7–0: RAMADDRL: RAM Address Register Low Byte
Holds the least significant eight bits of the target RAM address.
00000000
0x08
00000000
0x09

Register 3. RAMTXDATA: RAM Transmit Buffer Data Register

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address:
Bits7–0: RAMTXDATA: Transmit Buffer Data Register
Read: Returns data in the transmit buffer at location RAMADDRH:RAMADDRL. Write: Writes data to the transmit buffer at location RAMADDRH:RAMADDRL.

Register 4. RAMRXDATA: RAM Receive Buffer Data Register

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address:
Bits7–0: RAMRXDATA: Receive Buffer Data Register
Read: Returns data in the receive buffer at location RAMADDRH:RAMADDRL. Write: Writes data to the receive buffer at location RAMADDRH:RAMADDRL.
0x04
0x02
24 Rev. 1.0
CP2200/1

7.2. Internal Registers

The CP2200/1 has 114 direct internal registers and 9 indirect registers. The registers are grouped into ten categories based on function. Table 10 lists the register groups and provides links to the detailed register descriptions for each group. Table 11 lists all direct registers available on the device.

Table 10. CP2200/1 Register Groups

RAM Access Registers Section 7.1 on page 23
Interrupt Status and Control Registers Section 8 on page 30
Reset Source Registers Section 9 on page 37
Power Mode Registers Section 10 on page 43
Transmit Status and Control Registers Section 11.5 on page 49
Receive Interface Status and Control Registers Section 12.5 on page 60
Receive Buffer Status and Control Registers Section 12.7 on page 67
FLASH Access Registers Section 13.3 on page 75
MAC Access Registers Section 14.2 on page 78
MAC Indirect Registers Section 14.3 on page 80
PHY Status and Control Registers Section 15 on page 88

Table 11. Direct Registers

Register Address Description Page No.
CPADDRH 0x21 Current RX Packet Address High Byte page 65
CPADDRL 0x22 Current RX Packet Address Low Byte page 65
CPINFOH 0x1D Current RX Packet Information High Byte page 63
CPINFOL 0x1E Current RX Packet Information Low Byte page 64
CPLENH 0x1F Current RX Packet Length High Byte page 64
CPLENL 0x20 Current RX Packet Length Low Byte page 64
CPTLB 0x1A Current RX Packet TLB Number page 67
FLASHADDRH 0x69 Flash Address Pointer High Byte page 76
FLASHADDRL 0x68 Flash Address Pointer Low Byte page 76
FLASHAUTORD 0x05 Flash AutoRead w/ increment page 77
FLASHDATA 0x06 Flash Read/Write Data Register page 77
FLASHERASE 0x6A Flash Erase page 77
FLASHKEY 0x67 Flash Lock and Key page 76
FLASHSTA 0x7B Flash Status page 75
Rev. 1.0 25
CP2200/1
Register Address Description Page No.
INT0 0x63 Interrupt Status Register 0 (Self-Clearing) page 31
INT0EN 0x64 Interrupt Enable Register 0 page 33
INT0RD 0x76 Interrupt Status Register 0 (Read-Only) page 32
INT1 0x7F Interrupt Status Register 1 (Self-Clearing) page 34
INT1EN 0x7D Interrupt Enable Register 1 page 36
INT1RD 0x7E Interrupt Status Register 1 (Read-Only) page 35
IOPWR 0x70 Port Input/Output Power page 45
MACADDR 0x0A MAC Address Pointer page 79
MACDATAH 0x0B MAC Data Register High Byte page 79
MACDATAL 0x0C MAC Data Register Low Byte page 79
MACRW 0x0D MAC Read/Write Initiate page 79
Table 11. Direct Registers
OSCPWR 0x7C Oscillator Power page 46
PHYCF 0x79 Physical Layer Configuration page 92
PHYCN 0x78 Physical Layer Control page 91
PHYSTA 0x80 Physical Layer Status page 93
RAMADDRH 0x08 RAM Address Pointer High Byte page 24
RAMADDRL 0x09 RAM Address Pointer Low Byte page 24
RAMRXDATA 0x02 RXFIFO RAM Data Register page 24
RAMTXDATA 0x04 TXBUFF RAM Data Register page 24
RSTEN 0x72 Reset Enable Register page 42
RSTSTA 0x73 Reset Source Status Register page 41
RXAUTORD 0x01 RXFIFO AutoRead w/ increment page 62
RXCN 0x11 Receive Control page 61
RXFIFOHEADH 0x17 Receive Buffer Head Pointer High Byte page 71
RXFIFOHEADL 0x18 Receive Buffer Head Pointer Low Byte page 71
RXFIFOSTA 0x5B Receive Buffer Status page 72
RXFIFOTAILH 0x15 Receive Buffer Tail Pointer High Byte page 71
RXFIFOTAILL 0x16 Receive Buffer Tail Pointer Low Byte page 71
RXFILT 0x10 Receive Filter Configuration page 62
26 Rev. 1.0
CP2200/1
Table 11. Direct Registers
Register Address Description Page No.
RXHASHH 0x0E Receive Hash Table High Byte page 62
RXHASHL 0x0F Receive Hash Table Low Byte page 63
RXSTA 0x12 Receive Status page 61
SWRST 0x75 Software Reset Register page 40
TLB0ADDRH 0x27 TLB0 Address High Byte page 70
TLB0ADDRL 0x28 TLB0 Address Low Byte page 70
TLB0INFOH 0x23 TLB0 Information High Byte page 68
TLB0INFOL 0x24 TLB0 Information Low Byte page 69
TLB0LENH 0x25 TLB0 Length High Byte page 69
TLB0LENL 0x26 TLB0 Length Low Byte page 70
TLB1ADDRH 0x2D TLB1 Address High Byte page 70
TLB1ADDRL 0x2E TLB1 Address Low Byte page 70
TLB1INFOH 0x29 TLB1 Information High Byte page 68
TLB1INFOL 0x2A TLB1 Information Low Byte page 69
TLB1LENH 0x2b TLB1 Length High Byte page 69
TLB1LENL 0x2C TLB1 Length Low Byte page 70
TLB2ADDRH 0x33 TLB2 Address High Byte page 70
TLB2ADDRL 0x34 TLB2 Address Low Byte page 70
TLB2INFOH 0x2F TLB2 Information High Byte page 68
TLB2INFOL 0x30 TLB2 Information Low Byte page 69
TLB2LENH 0x31 TLB2 Length High Byte page 69
TLB2LENL 0x32 TLB2 Length Low Byte page 70
TLB3ADDRH 0x39 TLB3 Address High Byte page 70
TLB3ADDRL 0x3A TLB3 Address Low Byte page 70
TLB3INFOH 0x35 TLB3 Information High Byte page 68
TLB3INFOL 0x36 TLB3 Information Low Byte page 69
TLB3LENH 0x37 TLB3 Length High Byte page 69
TLB3LENL 0x38 TLB3 Length Low Byte page 70
TLB4ADDRH 0x3F TLB4 Address High Byte page 70
Rev. 1.0 27
CP2200/1
Table 11. Direct Registers
Register Address Description Page No.
TLB4ADDRL 0x40 TLB4 Address Low Byte page 70
TLB4INFOH 0x3B TLB4 Information High Byte page 68
TLB4INFOL 0x3C TLB4 Information Low Byte page 69
TLB4LENH 0x3D TLB4 Length High Byte page 69
TLB4LENL 0x3E TLB4 Length Low Byte page 70
TLB5ADDRH 0x45 TLB5 Address High Byte page 70
TLB5ADDRL 0x46 TLB5 Address Low Byte page 70
TLB5INFOH 0x41 TLB5 Information High Byte page 68
TLB5INFOL 0x42 TLB5 Information Low Byte page 69
TLB5LENH 0x43 TLB5 Length High Byte page 69
TLB5LENL 0x44 TLB5 Length Low Byte page 70
TLB6ADDRH 0x4B TLB6 Address High Byte page 70
TLB6ADDRL 0x4C TLB6 Address Low Byte page 70
TLB6INFOH 0x47 TLB6 Information High Byte page 68
TLB6INFOL 0x48 TLB6 Information Low Byte page 69
TLB6LENH 0x49 TLB6 Length High Byte page 69
TLB6LENL 0x4A TLB6 Length Low Byte page 70
TLB7ADDRH 0x51 TLB7 Address High Byte page 70
TLB7ADDRL 0x52 TLB7 Address Low Byte page 70
TLB7INFOH 0x4D TLB7 Information High Byte page 68
TLB7INFOL 0x4E TLB7 Information Low Byte page 69
TLB7LENH 0x4F TLB7 Length High Byte page 69
TLB7LENL 0x50 TLB7 Length Low Byte page 70
TLBVALID 0x1C TLB Valid Indicators page 68
TXAUTOWR 0x03 Transmit Data AutoWrite page 53
TXBUSY 0x54 Transmit Busy Indicator page 51
TXCN 0x53 Transmit Control page 51
TXENDH 0x57 Transmit Data Ending Address High Byte page 53
TXENDL 0x58 Transmit Data Ending Address Low Byte page 53
28 Rev. 1.0
CP2200/1
Table 11. Direct Registers
Register Address Description Page No.
TXPAUSEH 0x55 Transmit Pause High Byte page 52
TXPAUSEL 0x56 Transmit Pause Low Byte page 52
TXPWR 0x7A Transmitter Power page 46
TXSTA0 0x62 Transmit Status Vector 0 page 57
TXSTA1 0x61 Transmit Status Vector 1 page 56
TXSTA2 0x60 Transmit Status Vector 2 page 56
TXSTA3 0x5F Transmit Status Vector 3 page 55
TXSTA4 0x5E Transmit Status Vector 4 page 55
TXSTA5 0x5D Transmit Status Vector 5 page 54
TXSTA6 0x5C Transmit Status Vector 6 page 54
TXSTARTH 0x59 Transmit Data Starting Address High Byte page 52
TXSTARTL 0x5A Transmit Data Starting Address Low Byte page 52
VDMCN 0x13 V
Monitor Control Register page 39
DD
Rev. 1.0 29
CP2200/1

8. Interrupt Sources

The CP2200/1 can alert the host processor when any of the 14 interrupt source events listed in Table 12 triggers an interrupt. The CP2200/1 alerts the host by setting the appropriate flags in the interrupt status registers and driving the INT cleared by the host. Interrupt flags are cleared by reading the self-clearing interrupt status registers, INT0 and INT1. Interrupts can be disabled by clearing the corresponding bits in INT0EN and INT1EN.
If the host processor does not utilize the INT if any interrupt-generating events have occurred. The INT0RD and INT1RD read-only registers provide a method of checking for interrupts without clearing the interrupt status registers.
pin low. The INT pin will remain asserted until all interrupt flags for enabled interrupts have been
pin, it can periodically read the interrupt status registers to determine

Table 12. Interrupt Source Events

Event Description Pending
Flag
End of Packet The last byte of a packet has been read from the
receive buffer using the AutoRead interface.
Receive FIFO Empty The last packet in the receive buffer has been unloaded
or discarded.
Self Initialization Complete The device is ready for Reset Initialization. See “6.2.
Reset Initialization” on page 18.
Oscillator Initialization Complete The external oscillator has stabilized. INT0.4 INT0EN.4
Flash Write/Erase Complete A Flash write or erase operation has completed. INT0.3 INT0EN.3
Packet Transmitted The transmit interface has transmitted a packet. INT0.2 INT0EN.2
Receive FIFO Full The receive buffer is full or the maximum number of
packets has been exceeded. Decode the RXFIFOSTA status register to determine the receive buffer status.
Packet Received A packet has been added to the receive buffer. INT0.0 INT0EN.0
“Wake-on-LAN” Wakeup Event The device has been connected to a network. INT1.5 INT1EN.5
Link Status Changed The device has been connected or disconnected from
the network.
INT0.7 INT0EN.7
INT0.6 INT0EN.6
INT0.5 INT0EN.5
INT0.1 INT0EN.1
INT1.4 INT1EN.4
Enable
Flag
Jabber Detected The transmit interface has detected and responded to a
jabber condition. See IEEE 802.3 for more information about jabber conditions.
Auto-Negotiation Failed An auto-negotiation attempt has failed. Software should
check for a valid link and re-try auto-negotiation.
Reserved
Auto-Negotiation Complete An auto-negotiation attempt has completed. This inter-
rupt only indicates completion, and not success. Occa­sionally, Auto-Negotiation attempts will not complete and/or fail; therefore, a 3 to 4 second timeout should be implemented. A successful auto-negotiation attempt is one that completes without failure.
30 Rev. 1.0
INT1.3 INT1EN.3
INT1.2 INT1EN.2
INT1.0 INT1EN.0
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