Silicon Laboratories CP2120 User Manual
CP2120
SPI TO I2C BRIDGE AND GPIO PORT EXPANDER
Single Chip SPI to I2C Transfer
Integrated clock; no external clock required
On-Chip Voltage Monitor
Slave Serial Peripheral Interface (SPI)
Up to 1.0 Mbit/s Transfers
Configurable to Least Significant Bit or Most Significant
Bit first byte transfers
I2C Master Interface
Operates at configurable rates up to 400 kHz
255 RX and TX Data Buffers
Voltage
Monitor
MISO
MOSI
SCK
CS
SPI
Interface
Internal Registers
Input and Output Port Pins
8 Pins Configurable as Push-Pull or Open-Drain
1 Pin Configurable as an edge-triggered interrupt
source
All pins 5 V Tolerant
INT active low interrupt pin
Supply Voltage of 2.7 V to 3.6 V
Typical operating current: 6.4 mA
Package
Pb-free 20-pin QFN
Internal
Oscillator
2
C
Controller
I
Interface
Port Controller
SDA
SCL
Eight I/O Pins
Edge-Triggered
Interrupt Source
Figure 1. Block Diagram
Rev. 0.3 5/07 Copyright © 2007 by Silicon Laboratories CP2120
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
CP2120
2 Rev. 0.3
CP2120
TABLE OF CONTENTS
Section Page
1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Global DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4. Pinout And Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.1. Pin Out Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.2. QFN-20 Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3. QFN-20 Pinout Diagram (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.4. QFN-20 Solder Paste Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5. SPI Slave Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5.1. Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2. Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5.3. SPI Byte Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4. SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
5.5. I
6. I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
6.1. Determining Pull-Up Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2. I2C Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3. I2C Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6.4. I2C Receive Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.5. I2C Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7. Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
8. CP2120 Revision Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
C Activity During SPI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Rev. 0.3 3
CP2120
1. System Overview
The CP2120 is a highly-integrated SPI-to-I2C Bridge Controller with an SPI interface that provides a simple and
reliable method for communicating with I
(SPI), a serial I
configurable as an edge-triggered interrupt source in a compact 4x4 package. No external components other than
pull-up resisters on the I
a command set that governs all CP2120 configuration and operation.
2
C interface, 256 byte data buffers, an internal oscillator, eight input/output port pins, and one pin
2
C pins are required. The SPI Master controls the CP2120 across the SPI interface using
2
C devices. The CP2120 includes a 4-wire serial peripheral interface
2. Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 — 125 °C
Storage Temperature –65 — 150 °C
Voltage on any Port I/O Pin or RST
to GND
Voltage on V
Maximum Total current through V
Maximum output current sunk by RST
Port pin
with respect to GND –0.3 — 4.2 V
DD
with respect
or GND — — 500 mA
DD
or any
–0.3 — 5.8 V
——100mA
Note: Stresses above the absolute maximum ratings may cause permanent device damage. This is a stress rating only, and
functional operation of the devices at any conditions equal to or greater than those indicated in the operational listings
of this specification are not implied. Exposure to maximum rating conditions for extended periods may affect device
reliability.
3. Global DC Electrical Characteristics
Table 2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage V
Digital Supply Current V
Specified Operating
Temperature Range
=2.7V — TBD — mA
DD
RST
–40 — +85 °C
3.0 3.6 V
4 Rev. 0.3
4. Pinout And Package Definition
4.1. Pin Out Chart
Name Pin # Type Description
CP2120
V
DD
GND 2 Ground
RST 4 Digital I/O Device Reset. Open-drain output of internal POR or VDD monitor. An
SCLK 1 Digital In SPI Clock Input
MISO 20 Digital Out SPI Slave Output
MOSI 19 Digital In SPI Slave Input
CS 18 Digital In SPI Slave Select
SDA 17 Digital I/O I
SCL 16 Digital I/O I
GPIO 0 5 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 1 12 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 2 11 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 3 10 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 4 9 Digital I/O General Purpose Configurable Digital Input/Output
3 Power Supply Pin
external source can initiate a system reset by driving this pin low for at
least 15 µs.
2
C Data Input/Output
2
C Clock Input/Output
GPIO 5 8 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 6 7 Digital I/O General Purpose Configurable Digital Input/Output
GPIO 7 6 Digital I/O General Purpose Configurable Digital Input/Output
EINT 13 Digital I/O Edge-Triggered Interrupt Source
INT 14 Digital Out CP2120 Interrupt Indicator
NC 15 Digital Out Not connected, leave floating
Rev. 0.3 5
CP2120
4.2. QFN-20 Pinout Diagram (Top View)
SCLK
GND
VDD
/RST
GPIO 0
MISO
20
1
2
3
4
5
6
GPIO 7
MOSI
19
7
GPIO 6
CS
18
CP2120
GND
8
GPIO 5
SDA
17
9
GPIO 4
SCL
16
10
GPIO 3
15
14
13
12
11
NC
INT
EINT
GPIO 1
GPIO 2
6 Rev. 0.3
4.3. QFN-20 Pinout Diagram (Bottom View)
CP2120
Table 4.1. QFN-20
Package Dimensions
MM
MIN TYP MAX
A 0.80 0.90 1.00
A1 0 0.02 0.05
A2 0 0.65 1.00
A3 — 0.25 —
b 0.18 0.23 0.30
D—4.00—
D2 2.00 2.15 2.25
E—4.00—
E2 2.00 2.15 2.25
e—0.5—
L 0.45 0.55 0.65
N—20—
ND — 5 —
NE — 5 —
R0.09— —
AA — 0.435 —
BB — 0.435 —
CC — 0.18 —
DD — 0.18 —
Rev. 0.3 7
CP2120
4.4. QFN-20 Solder Paste Recommendations
8 Rev. 0.3
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