Silicon Laboratories C8051F300, C8051F301, C8051F302, C8051F303, C8051F304 Technical data
...
C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
• Up to 500 ksps
• Up to 8 external inputs
• Programmable amplifier gains of 4, 2, 1, & 0.5
• VREF from external pin or V
• Built-in temperature sensor
• External conversion start input
DD
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (<0.5 µA)
On-chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 5 mA @ 25 MHz;
- Typical stop mode current: 0.1 µA
11 µA @ 32 kHz
- Temperature range: –40 to +85 °C
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB Flash; In-system programmable in 512
byte sectors
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general-purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin Quad Flat No-Lead (QFN) Package
(Lead-free package available)
- 3x3 mm PWB footprint
ANALOG
DIGITAL I/O
PERIPHERALS
UART
A
M
U
X
+
-
PGA
C8051F300/2 only
VOLTAGE COMPARATOR
10-bit
200ksps
ADC
TEMP
SENSOR
SMBus
PCA
Timer 0
Timer 1
Timer 2
I/O Port
CROSSBAR
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8k/4k/2k Bytes
ISP Flash
12
INTERRUPTS
Rev. 2.6 4/05 Copyright © 2005 by Silicon Laboratories C8051F30x
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
WDT
C8051F300/1/2/3/4/5
2 Rev. 2.6
NOTES:
C8051F300/1/2/3/4/5
Rev. 2.6 3
C8051F300/1/2/3/4/5
4 Rev. 2.6
C8051F300/1/2/3/4/5
Table of Contents
1. System Overview.................................................................................................... 15
1.1. CIP-51™ Microcontroller Core.......................................................................... 18
1.1.1. Fully 8051 Compatible.............................................................................. 18
1.1.2. Improved Throughput............................................................................... 18
1.1.3. Additional Features .................................................................................. 19
1.2. On-Chip Memory............................................................................................... 20
1.3. On-Chip Debug Circuitry................................................................................... 21
1.4. Programmable Digital I/O and Crossbar ........................................................... 21
1.5. Serial Ports ....................................................................................................... 22
1.6. Programmable Counter Array ........................................................................... 23
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ..................................... 24
1.8. Comparator ....................................................................................................... 25
2. Absolute Maximum Ratings .................................................................................. 26
3. Global DC Electrical Characteristics .................................................................... 27
4. Pinout and Package Definitions............................................................................ 28
5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 33
5.1. Analog Multiplexer and PGA............................................................................. 34
5.2. Temperature Sensor ......................................................................................... 34
5.3. Modes of Operation .......................................................................................... 37
5.3.1. Starting a Conversion............................................................................... 37
5.3.2. Tracking Modes........................................................................................ 38
5.3.3. Settling Time Requirements..................................................................... 39
5.4. Programmable Window Detector ...................................................................... 43
5.4.1. Window Detector In Single-Ended Mode ................................................. 43
5.4.2. Window Detector In Differential Mode...................................................... 44
6. Voltage Reference (C8051F300/2) ......................................................................... 47
7. Comparator0 ........................................................................................................... 49
8. CIP-51 Microcontroller ........................................................................................... 55
8.1. Instruction Set ................................................................................................... 56
8.1.1. Instruction and CPU Timing ..................................................................... 56
8.1.2. MOVX Instruction and Program Memory ................................................. 57
8.2. Memory Organization........................................................................................ 61
8.2.1. Program Memory...................................................................................... 61
8.2.2. Data Memory............................................................................................ 62
8.2.3. General Purpose Registers ...................................................................... 62
8.2.4. Bit Addressable Locations........................................................................ 63
8.2.5. Stack ....................................................................................................... 63
8.2.6. Special Function Registers....................................................................... 63
8.2.7. Register Descriptions ............................................................................... 66
8.3. Interrupt Handler ............................................................................................... 70
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 70
8.3.2. External Interrupts.................................................................................... 71
8.3.3. Interrupt Priorities ..................................................................................... 71
Rev. 2.6 5
C8051F300/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 71
8.3.5. Interrupt Register Descriptions................................................................. 73
8.4. Power Management Modes .............................................................................. 78
8.4.1. Idle Mode.................................................................................................. 78
8.4.2. Stop Mode................................................................................................ 79
9. Reset Sources......................................................................................................... 81
9.1. Power-On Reset ............................................................................................... 82
9.2. Power-Fail Reset / VDD Monitor....................................................................... 82
9.3. External Reset .................................................................................................. 83
9.4. Missing Clock Detector Reset........................................................................... 83
9.5. Comparator0 Reset........................................................................................... 83
9.6. PCA Watchdog Timer Reset............................................................................. 83
9.7. Flash Error Reset.............................................................................................. 84
9.8. Software Reset ................................................................................................. 84
10.Flash Memory ......................................................................................................... 87
10.1.Programming The Flash Memory ..................................................................... 87
10.1.1.Flash Lock and Key Functions ................................................................. 87
10.1.2.Flash Erase Procedure ............................................................................ 87
10.1.3.Flash Write Procedure ............................................................................. 88
10.2.Non-Volatile Data Storage................................................................................ 88
10.3.Security Options ............................................................................................... 88
11.Oscillators ............................................................................................................... 93
11.1.Programmable Internal Oscillator ..................................................................... 93
11.2.External Oscillator Drive Circuit........................................................................ 95
11.3.System Clock Selection.................................................................................... 95
11.4.External Crystal Example ................................................................................. 97
11.5.External RC Example ....................................................................................... 98
11.6.External Capacitor Example ............................................................................. 98
12.Port Input/Output.................................................................................................... 99
12.1.Priority Crossbar Decoder .............................................................................. 100
12.2.Port I/O Initialization ....................................................................................... 102
12.3.General Purpose Port I/O ............................................................................... 104
13.SMBus ................................................................................................................... 107
13.1.Supporting Documents................................................................................... 108
13.2.SMBus Configuration...................................................................................... 108
13.3.SMBus Operation ........................................................................................... 108
13.3.1.Arbitration............................................................................................... 109
13.3.2.Clock Low Extension.............................................................................. 110
13.3.3.SCL Low Timeout................................................................................... 110
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 110
13.4.Using the SMBus............................................................................................ 111
13.4.1.SMBus Configuration Register............................................................... 112
13.4.2.SMB0CN Control Register ..................................................................... 115
13.4.3.Data Register ......................................................................................... 118
13.5.SMBus Transfer Modes.................................................................................. 119
6 Rev. 2.6
C8051F300/1/2/3/4/5
13.5.1.Master Transmitter Mode ....................................................................... 119
13.5.2.Master Receiver Mode........................................................................... 120
13.5.3.Slave Receiver Mode............................................................................. 121
13.5.4.Slave Transmitter Mode ......................................................................... 122
13.6.SMBus Status Decoding................................................................................. 123
14.UART0.................................................................................................................... 127
14.1.Enhanced Baud Rate Generation................................................................... 128
14.2.Operational Modes ......................................................................................... 129
14.2.1.8-Bit UART............................................................................................. 129
14.2.2.9-Bit UART............................................................................................. 130
14.3.Multiprocessor Communications .................................................................... 131
15.Timers.................................................................................................................... 139
15.1.Timer 0 and Timer 1 ....................................................................................... 139
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 139
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 141
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 141
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 142
15.2.Timer 2 .......................................................................................................... 147
15.2.1.16-bit Timer with Auto-Reload................................................................ 147
15.2.2.8-bit Timers with Auto-Reload................................................................ 148
16.Programmable Counter Array ............................................................................. 151
16.1.PCA Counter/Timer ........................................................................................ 152
16.2.Capture/Compare Modules ............................................................................ 153
16.2.1.Edge-triggered Capture Mode................................................................ 154
16.2.2.Software Timer (Compare) Mode........................................................... 155
16.2.3.High Speed Output Mode....................................................................... 156
16.2.4.Frequency Output Mode ........................................................................ 157
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 158
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 159
16.3.Watchdog Timer Mode ................................................................................... 160
16.3.1.Watchdog Timer Operation .................................................................... 160
16.3.2.Watchdog Timer Usage ......................................................................... 161
16.4.Register Descriptions for PCA........................................................................ 163
17.C2 Interface ........................................................................................................... 169
17.1.C2 Interface Registers.................................................................................... 169
17.2.C2 Pin Sharing ............................................................................................... 171
Rev. 2.6 7
C8051F300/1/2/3/4/5
NOTES:
8 Rev. 2.6
C8051F300/1/2/3/4/5
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 16
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings* .................................................................. 26
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ....................................................... 27
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........................................... 28
Table 4.2. QFN-11 Package Diminsions ................................................................. 30
5. ADC0 (8-Bit ADC, C8051F300/2)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 45
6. Voltage Reference (C8051F300/2)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 48
7. Comparator0
Table 7.1. Comparator0 Electrical Characteristics .................................................. 53
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 57
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 64
Table 8.3. Special Function Registers* ................................................................... 64
Table 8.4. Interrupt Summary .................................................................................. 72
9. Reset Sources
Table 9.1. User Code Space Address Limits ........................................................... 84
Table 9.2. Reset Electrical Characteristics .............................................................. 84
10.Flash Memory
Table 10.1. Flash Electrical Characteristics ............................................................ 88
Table 10.2. Security Byte Decoding ........................................................................ 89
11.Oscillators
Table 11.1. Internal Oscillator Electrical Characteristics ......................................... 95
12.Port Input/Output
Table 12.1. Port I/O DC Electrical Characteristics ................................................. 106
13.SMBus
Table 13.1. SMBus Clock Source Selection .......................................................... 112
Table 13.2. Minimum SDA Setup and Hold Times ................................................ 113
Table 13.3. Sources for Hardware Changes to SMB0CN ..................................... 117
Table 13.4. SMBus Status Decoding ..................................................................... 123
14.UART0
Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Os-
cillator ................................................................................................. 134
Table 14.2. Timer Settings for Standard Baud Rates Using an External 25 MHz Oscil-
lator ..................................................................................................... 134
Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator ............................................................................................. 135
Rev. 2.6 9
C8051F300/1/2/3/4/5
Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz
Oscillator ............................................................................................. 136
Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz
Oscillator ............................................................................................. 137
Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ
Oscillator ............................................................................................. 138
15.Timers
16.Programmable Counter Array
Table 16.1. PCA Timebase Input Options ............................................................. 152
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 153
Table 16.3. Watchdog Timer Timeout Intervals1 ................................................... 162
17.C2 Interface
10 Rev. 2.6
C8051F300/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F300/2 Block Diagram ................................................................. 17
Figure 1.2. C8051F301/3/4/5 Block Diagram ........................................................... 17
Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 18
Figure 1.4. On-Chip Clock and Reset ...................................................................... 19
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 20
Figure 1.6. Development/In-System Debug Diagram............................................... 21
Figure 1.7. Digital Crossbar Diagram ....................................................................... 22
Figure 1.8. PCA Block Diagram ............................................................................... 23
Figure 1.9. PCA Block Diagram ............................................................................... 23
Figure 1.10. 8-Bit ADC Block Diagram ..................................................................... 24
Figure 1.11. Comparator Block Diagram .................................................................. 25
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 29
Figure 4.2. QFN-11 Package Drawing ..................................................................... 30
Figure 4.3. Typical QFN-11 Solder Paste Mask ....................................................... 31
Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 32
5. ADC0 (8-Bit ADC, C8051F300/2)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 33
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 35
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 36
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 38
Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 39
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 43
Figure 5.7. ADC Window Compare Examples, Differential Mode ............................ 44
6. Voltage Reference (C8051F300/2)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 47
7. Comparator0
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 49
Figure 7.2. Comparator Hysteresis Plot ................................................................... 50
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 55
Figure 8.2. Program Memory Maps.......................................................................... 61
Figure 8.3. Data Memory Map.................................................................................. 62
9. Reset Sources
Figure 9.1. Reset Sources........................................................................................ 81
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 82
10.Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 89
11.Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 93
Rev. 2.6 11
C8051F300/1/2/3/4/5
Figure 11.2. 32.768 kHz External Crystal Example.................................................. 97
12.Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram ....................................................... 99
Figure 12.2. Port I/O Cell Block Diagram ................................................................. 99
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 100
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 101
13.SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 107
Figure 13.2. Typical SMBus Configuration ............................................................. 108
Figure 13.3. SMBus Transaction ............................................................................ 109
Figure 13.4. Typical SMBus SCL Generation......................................................... 113
Figure 13.5. Typical Master Transmitter Sequence................................................ 119
Figure 13.6. Typical Master Receiver Sequence.................................................... 120
Figure 13.7. Typical Slave Receiver Sequence...................................................... 121
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 122
14.UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 127
Figure 14.2. UART0 Baud Rate Logic .................................................................... 128
Figure 14.3. UART Interconnect Diagram .............................................................. 129
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 129
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 130
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 131
15.Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 140
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 141
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 142
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 147
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 148
16.Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 151
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 152
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 153
Figure 16.4. PCA Capture Mode Diagram.............................................................. 154
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 155
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 156
Figure 16.7. PCA Frequency Output Mode ............................................................ 157
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 158
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 159
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 160
17.C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 171
12 Rev. 2.6
C8051F300/1/2/3/4/5
List of Registers
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) . . . . . . . . . . . . 40
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) . . . . . . . . . . . . . . . 41
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) . . . . . . . . . . . . . . . . . . . 41
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) . . . . . . . . . . . . . . . . . . . . 42
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) . . . . . . 44
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2) . . . . . . . . . 44
SFR Definition 6.1. REF0CN: Reference Control Register . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 9.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 11.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 11.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 12.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 12.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 12.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 114
SFR Definition 13.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 13.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 14.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 133
SFR Definition 15.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 15.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 15.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Rev. 2.6 13
C8051F300/1/2/3/4/5
SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 150
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 150
SFR Definition 15.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 16.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
SFR Definition 16.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 165
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 166
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 166
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 167
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 167
C2 Register Definition 17.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
C2 Register Definition 17.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 169
C2 Register Definition 17.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 170
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 170
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 170
14 Rev. 2.6
C8051F300/1/2/3/4/5
1. System Overview
C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Ta bl e 1.1 on page 16 for specific product feature selection.
• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 8-bit 500 ksps 11-channel ADC with programmable gain pre-amplifier and analog multiplexer
(C8051F300/2 only)
• Precision programmable 25 MHz internal oscillator
• Up to 8 kB of on-chip Flash memory
• 256 bytes of on-chip RAM
• SMBus/I2C and Enhanced UART serial interfaces implemented in hardware
• Three general-purpose 16-bit timers
• Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer
function
• On-chip power-on reset, VDD monitor, and temperature sensor
• On-chip voltage comparator
• Byte-wide I/O port (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F300/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can
be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and /RST pins are tolerant of input signals up to 5
in the 11-pin QFN package (also referred to as MLP or MLF package) shown in
V. The C8051F300/1/2/3/4/5 are available
Figure 4.2.
-
Rev. 2.6 15
C8051F300/1/2/3/4/5
Table 1.1. Product Selection Guide
C
2
Ordering Part Number
C8051F300 25 8 k 256 3 3 3 3 3 8 3 3 1 – QFN-11
C8051F300-GM 25 8 k 256 3 3 3 3 3 8 3 3 1 3 QFN-11
C8051F301 25 8 k 256 3 3 3 3 3 8 — — 1 – QFN-11
C8051F301-GM 25 8 k 256 3 3 3 3 3 8 — — 1 3 QFN-11
C8051F302 25 8 k 256 — 3 3 3 3 8 3 3 1 – QFN-11
C8051F302-GM 25 8 k 256 — 3 3 3 3 8 3 3 1 3 QFN-11
C8051F303 25 8 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F303-GM 25 8 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
C8051F304 25 4 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F304-GM 25 4 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
C8051F305 25 2 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F305-GM 25 2 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
MIPS (Peak)
Flash Memory
RAM
Calibrated Internal Oscillator
SMBus/I
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
8-bit 500ksps ADC
Temperature Sensor
Analog Comparators
Lead-free
Package
16 Rev. 2.6
VDD
GND
/RST/C2CK
Analog/Digital
XTAL1
XTAL2
Power
C2D
POR
External
Oscillator
Circuit
Precision
Internal
Oscillator
C8051F300/1/2/3/4/5
Port I/O Mode
& Config.
Reset
8
0
8kbyte
FLASH
5
1
256 byte
SRAM
Debug HW
Brown-
Out
C
o
System Clock
SFR Bus
r
e
Clock & Reset
Configuration
Figure 1.1. C8051F300/2 Block Diagram
Timer 0, 1
ADC
Config. &
Control
CNVSTR
Port 0
Latch
UART
PCA/
WDT
SMBus
XBAR
Control
VDD
8-bit
500ksps
ADC
x2
x4
x2
CP0
VREF
P0.0/VREF
P0.1
X
B
A
R
P
0
D
r
v
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/C2D
C2D
CP0
+
-
Temp
A
AIN0-AIN7
M
PGA
U
X
VDD
/RST/C2CK
VDD
GND
Analog/Digital
XTAL1
XTAL2
Power
C2D
Port I/O Mode
POR
External
Oscillator
Circuit
Precision
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
8k/4k/2k
byte
FLASH
256 byte
SRAM
Clock & Reset
Configuration
Port 0
Latch
UART
Timer 0, 1
PCA/
WDT
SMBus
XBAR
Control
Figure 1.2. C8051F301/3/4/5 Block Diagram
& Config.
x2
X
B
A
R
x4
x2
CP0
P
0
D
r
v
C2D
CP0
+
-
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7/C2D
P0.0/VREF
Rev. 2.6 17
C8051F300/1/2/3/4/5
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Spe
cial Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
MHz. By contrast, the CIP-51 core exe-
-
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
25
20
15
MIPS
10
5
Cygnal
CIP-51
(25MHz clk)
Microchip
PIC17C75x
(33MHz clk)
Figure 1.3. Comparison of Peak MCU Execution Speeds
18 Rev. 2.6
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
C8051F300/1/2/3/4/5
1.1.3. Additional Features
The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multitasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below 2.7
level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash
read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash protection
may be disabled by the user in software. The WDT may be permanently enabled in software after a poweron reset during MCU initialization.
The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncalibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal
oscillator period may be user programmed in ~0.5% increments. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly to the external oscillator
circuit. An external oscillator can be extremely useful in low power applications, allowing the MCU to run
from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25
internal oscillator as needed.
V), a Watchdog Timer, a Missing Clock Detector, a voltage
MHz)
XTAL1
XTAL2
Internal
Oscillator
External
Oscillator
Drive
VDD
Supply
Monitor
Enable
+
-
Power On
P0.x
P0.y
System
Clock
Clock Select
Comparator 0
+
-
Missing
Clock
Detector
(oneshot)
EN
MCD
Enable
Microcontroller
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
PCA
WDT
EN
WDT
Enable
System Reset
Reset
Figure 1.4. On-Chip Clock and Reset
(Software Reset)
SWRSF
'0'
(wired-OR)
Reset
Funnel
Illegal
FLASH
Operation
/RST
Rev. 2.6 19
C8051F300/1/2/3/4/5
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the
C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and
requires no special off-chip programming voltage. See
map.
Figure 1.5 for the C8051F300/1/2/3 system memory
0x1E00
0x1DFF
0x0000
PROGRAM MEMORY
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
RESERVED
8k bytes
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
(Direct Addressing Only)
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown)
Register's
Lower 128 RAM
(Direct and Indirect
Addressing)
20 Rev. 2.6
C8051F300/1/2/3/4/5
1.3. On-Chip Debug Circuitry
The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides
non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F300DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software
with a developer's studio and debugger, an integrated 8051 assembler, and a C2 debug adapter. It also
has a target application board with the associated MCU installed and large prototyping area, plus the nec
essary communication cables and wall-mount power supply. The Development Kit requires a computer
with Windows® 98 SE or later. The Silicon Labs IDE interface is a vastly superior developing and debug
ging configuration, compared to standard MCU emulators that use onboard "ICE Chips" and require the
MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and
preserves the performance of the precision analog peripherals.
Silicon Labs Integrated
WINDOWS 98 SE or Later
Development Environment
-
-
RS-232
Debug
Adapter
C2 (x2), VDD, GND
VDD GND
C8051F300
TARGET PCB
Figure 1.6. Development/In-System Debug Diagram
1.4. Programmable Digital I/O and Crossbar
C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few
enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as
digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are
fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
Rev. 2.6 21
C8051F300/1/2/3/4/5
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switching network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). Onchip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
Highest
Priority
(Internal Digital Signals)
Lowest
Priority
UART
SMBus
CP0
Outputs
SYSCLK
PCA
T0, T1
1.5. Serial Ports
XBR0, XBR1,
XBR2 Registers
P0MDOUT,
P0MDIN Registers
Priority
Decoder
2
2
Digital
Crossbar
2
8
Cells
4
2
8
P0Port Latch
(P0.0-P0.7)
Figure 1.7. Digital Crossbar Diagram
P0
I/O
P0.0
P0.7
The C8051F300/1/2/3/4/5 Family includes an SMBus/I2C interface and a full-duplex UART with enhanced
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
22 Rev. 2.6
C8051F300/1/2/3/4/5
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro
grammable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
-
Capture/Compare
Module 0
ECI
CEX0
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Digital Crossbar
Port I/O
Figure 1.9. PCA Block Diagram
Rev. 2.6 23
C8051F300/1/2/3/4/5
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only)
The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and
programmable gain amplifier. With a maximum throughput of 500
with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both posi
tive and negative ADC inputs. Each Port pin is available as an ADC input; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may
shut down the ADC to save power.
The integrated programmable gain amplifier (PGA) amplifies the the ADC input by 0.5, 1, 2, or 4 as defined
by user software. The gain stage is especially useful when different ADC input channels have widely varied
input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset.
Conversions can be started in five ways: a software command, an overflow of Timer 0, 1, or 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a
periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status
bit and an interrupt (if enabled). The resulting 8-bit data word is latched into an SFR upon completion of a
conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
ksps, the ADC offers true 8-bit accuracy
-
-
Temp
Sensor
Analog Multiplexer
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DGND
10-to-1
AMUX
9-to-1
AMUX
Configuration, Control, an d Data Registers
Programmable Gain
Amplifier
VDD
+
X
-
8-Bit
SAR
ADC
End of
Conversion
Interrupt
Start
Conversion
8
Window Compare
Logic
Software Write
T0 Overflow
TMR2 Overflow
T1 Overflow
External
Convert Start
ADC Data
Register
Window
Compare
Interrupt
Figure 1.10. 8-Bit ADC Block Diagram
24 Rev. 2.6
C8051F300/1/2/3/4/5
1.8. Comparator
C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.
Comparator response time is programmable, allowing the user to select between high-speed and lowpower modes. Positive and negative hysteresis is also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. The comparator may also be configured as a reset source.
P0.0
P0.2
P0.4
P0.6
P0.1
P0.3
P0.5
P0.7
CP0 +
VDD
CP0 -
+
-
GND
SET
D
CLR
(SYNCHRONIZER)
SET
D
Q
Q
CLR
Q
Q
Reset
Decision
Tree
Figure 1.11. Comparator Block Diagram
Interrupt
Handler
Crossbar
Rev. 2.6 25
C8051F300/1/2/3/4/5
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or /RST with respect to
GND
Voltage on VDD with respect to GND –0.3 4.2 V
Maximum Total current through VDD and GND 500 mA
Maximum output current sunk by /RST or any Port pin 100 mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
–0.3 5.8 V
26 Rev. 2.6
C8051F300/1/2/3/4/5
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage 2.7 3.0 3.6 V
Digital Supply Current with CPU
active
Digital Supply Current with CPU
inactive (not accessing Flash)
Digital Supply Current (shutdown) Oscillator not running < 0.1 µA
Digital Supply RAM Data Retention Voltage
Specified Operating Temperature
Range
SYSCLK (system clock frequency) 0
Tsysl (SYSCLK low time) 18 ns
Tsysh (SYSCLK high time) 18 ns
*Note: SYSCLK must be at least 32 kHz to enable debugging.
V
= 2.7 V, Clock = 25 MHz
DD
V
= 2.7 V, Clock = 1 MHz
DD
V
= 2.7 V, C l o ck = 32 kHz
DD
VDD = 2.7 V, Clock = 25 MHz
V
= 2.7 V, Clock = 1 MHz
DD
V
= 2.7 V, Clock = 32 kHz
DD
5.8
0.34
12
2.1
83
2.8
1.5 V
–40 +85 °C
*
25 MHz
mA
mA
µA
mA
µA
µA
Rev. 2.6 27
C8051F300/1/2/3/4/5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Pin Number Name Type Description
1 VREF /
P0.0
2 P0.1 D I/O or
3 V
4 XTAL1 /
5 XTAL2 /
6 P0.4 D I/O or
7 P0.5 D I/O or
DD
P0.2
P0.3
A In
D I/O or
A In
A In
A In
D I/O or
A In
A Out
D I/O
A In
A In
External Voltage Reference Input.
Port 0.0. See Section 12 for complete description.
Port 0.1. See Section 12 for complete description.
Power Supply Voltage.
Crystal Input. This pin is the external oscillator circuit return
for a crystal or ceramic resonator. See
Port 0.2. See Section 12 for complete description.
Crystal Input/Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC network configurations.
See
Section 11.2.
Port 0.3. See Section 12 for complete description.
Port 0.4. See Section 12 for complete description.
Port 0.5. See Section 12 for complete description.
Section 11.2.
8 C2CK /
/RST
9 P0.6 /
CNVSTR
10 C2D /
P0.7
11 GND Ground.
28 Rev. 2.6
D I/O
D I/O
D I/O or
A In
D I/O
D I/O
D I/O or
A In
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
Port 0.6. See Section 12 for complete description.
ADC External Convert Start Input Strobe.
Data signal for the C2 Development Interface.
Port 0.7. See Section 12 for complete description.
C8051F300/1/2/3/4/5
VREF /
P0.0
P0.1
VDD
XTAL1 /
P0.2
XTAL2 /
P0.3
GND
C2D /
P0.7
P0.6 /
CNVSTR
C2CK /
/RST
P0.5
P0.4
Figure 4.1. QFN-11 Pinout Diagram (Top View)
Rev. 2.6 29
C8051F300/1/2/3/4/5
Bottom View
E2
b
L
LT
be
D2
k
e
E
LB
E3
D
D3
R
D4
Table 4.2. QFN-11
Package Diminsions
MM
MIN TYP MAX
A 0.80 0.90 1.00
A1 0 0.02 0.05
A2 0 0.65 1.00
A3 0.25
b 0.18 0.23 0.30
D3.00
D2 2.20 2.25
D3 2.00
D4 0.386
E3.00
E2 1.36
E3 1.135
e0.5
k0.27
L 0.45 0.55 0.65
LB 0.36
LT 0.37
R0.09
A3
A3
Side E View
A2
e
1
A
Side D View
A2
e
Figure 4.2. QFN-11 Package Drawing
A1
A
A
30 Rev. 2.6
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