Silicon Laboratories C8051F300, C8051F301, C8051F302, C8051F303, C8051F304 Technical data
...
C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
• Up to 500 ksps
• Up to 8 external inputs
• Programmable amplifier gains of 4, 2, 1, & 0.5
• VREF from external pin or V
• Built-in temperature sensor
• External conversion start input
DD
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (<0.5 µA)
On-chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 5 mA @ 25 MHz;
- Typical stop mode current: 0.1 µA
11 µA @ 32 kHz
- Temperature range: –40 to +85 °C
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB Flash; In-system programmable in 512
byte sectors
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general-purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin Quad Flat No-Lead (QFN) Package
(Lead-free package available)
- 3x3 mm PWB footprint
ANALOG
DIGITAL I/O
PERIPHERALS
UART
A
M
U
X
+
-
PGA
C8051F300/2 only
VOLTAGE COMPARATOR
10-bit
200ksps
ADC
TEMP
SENSOR
SMBus
PCA
Timer 0
Timer 1
Timer 2
I/O Port
CROSSBAR
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8k/4k/2k Bytes
ISP Flash
12
INTERRUPTS
Rev. 2.6 4/05 Copyright © 2005 by Silicon Laboratories C8051F30x
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR
WDT
C8051F300/1/2/3/4/5
2 Rev. 2.6
NOTES:
C8051F300/1/2/3/4/5
Rev. 2.6 3
C8051F300/1/2/3/4/5
4 Rev. 2.6
C8051F300/1/2/3/4/5
Table of Contents
1. System Overview.................................................................................................... 15
1.1. CIP-51™ Microcontroller Core.......................................................................... 18
1.1.1. Fully 8051 Compatible.............................................................................. 18
1.1.2. Improved Throughput............................................................................... 18
1.1.3. Additional Features .................................................................................. 19
1.2. On-Chip Memory............................................................................................... 20
1.3. On-Chip Debug Circuitry................................................................................... 21
1.4. Programmable Digital I/O and Crossbar ........................................................... 21
1.5. Serial Ports ....................................................................................................... 22
1.6. Programmable Counter Array ........................................................................... 23
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ..................................... 24
1.8. Comparator ....................................................................................................... 25
2. Absolute Maximum Ratings .................................................................................. 26
3. Global DC Electrical Characteristics .................................................................... 27
4. Pinout and Package Definitions............................................................................ 28
5. ADC0 (8-Bit ADC, C8051F300/2)............................................................................ 33
5.1. Analog Multiplexer and PGA............................................................................. 34
5.2. Temperature Sensor ......................................................................................... 34
5.3. Modes of Operation .......................................................................................... 37
5.3.1. Starting a Conversion............................................................................... 37
5.3.2. Tracking Modes........................................................................................ 38
5.3.3. Settling Time Requirements..................................................................... 39
5.4. Programmable Window Detector ...................................................................... 43
5.4.1. Window Detector In Single-Ended Mode ................................................. 43
5.4.2. Window Detector In Differential Mode...................................................... 44
6. Voltage Reference (C8051F300/2) ......................................................................... 47
7. Comparator0 ........................................................................................................... 49
8. CIP-51 Microcontroller ........................................................................................... 55
8.1. Instruction Set ................................................................................................... 56
8.1.1. Instruction and CPU Timing ..................................................................... 56
8.1.2. MOVX Instruction and Program Memory ................................................. 57
8.2. Memory Organization........................................................................................ 61
8.2.1. Program Memory...................................................................................... 61
8.2.2. Data Memory............................................................................................ 62
8.2.3. General Purpose Registers ...................................................................... 62
8.2.4. Bit Addressable Locations........................................................................ 63
8.2.5. Stack ....................................................................................................... 63
8.2.6. Special Function Registers....................................................................... 63
8.2.7. Register Descriptions ............................................................................... 66
8.3. Interrupt Handler ............................................................................................... 70
8.3.1. MCU Interrupt Sources and Vectors ........................................................ 70
8.3.2. External Interrupts.................................................................................... 71
8.3.3. Interrupt Priorities ..................................................................................... 71
Rev. 2.6 5
C8051F300/1/2/3/4/5
8.3.4. Interrupt Latency ...................................................................................... 71
8.3.5. Interrupt Register Descriptions................................................................. 73
8.4. Power Management Modes .............................................................................. 78
8.4.1. Idle Mode.................................................................................................. 78
8.4.2. Stop Mode................................................................................................ 79
9. Reset Sources......................................................................................................... 81
9.1. Power-On Reset ............................................................................................... 82
9.2. Power-Fail Reset / VDD Monitor....................................................................... 82
9.3. External Reset .................................................................................................. 83
9.4. Missing Clock Detector Reset........................................................................... 83
9.5. Comparator0 Reset........................................................................................... 83
9.6. PCA Watchdog Timer Reset............................................................................. 83
9.7. Flash Error Reset.............................................................................................. 84
9.8. Software Reset ................................................................................................. 84
10.Flash Memory ......................................................................................................... 87
10.1.Programming The Flash Memory ..................................................................... 87
10.1.1.Flash Lock and Key Functions ................................................................. 87
10.1.2.Flash Erase Procedure ............................................................................ 87
10.1.3.Flash Write Procedure ............................................................................. 88
10.2.Non-Volatile Data Storage................................................................................ 88
10.3.Security Options ............................................................................................... 88
11.Oscillators ............................................................................................................... 93
11.1.Programmable Internal Oscillator ..................................................................... 93
11.2.External Oscillator Drive Circuit........................................................................ 95
11.3.System Clock Selection.................................................................................... 95
11.4.External Crystal Example ................................................................................. 97
11.5.External RC Example ....................................................................................... 98
11.6.External Capacitor Example ............................................................................. 98
12.Port Input/Output.................................................................................................... 99
12.1.Priority Crossbar Decoder .............................................................................. 100
12.2.Port I/O Initialization ....................................................................................... 102
12.3.General Purpose Port I/O ............................................................................... 104
13.SMBus ................................................................................................................... 107
13.1.Supporting Documents................................................................................... 108
13.2.SMBus Configuration...................................................................................... 108
13.3.SMBus Operation ........................................................................................... 108
13.3.1.Arbitration............................................................................................... 109
13.3.2.Clock Low Extension.............................................................................. 110
13.3.3.SCL Low Timeout................................................................................... 110
13.3.4.SCL High (SMBus Free) Timeout .......................................................... 110
13.4.Using the SMBus............................................................................................ 111
13.4.1.SMBus Configuration Register............................................................... 112
13.4.2.SMB0CN Control Register ..................................................................... 115
13.4.3.Data Register ......................................................................................... 118
13.5.SMBus Transfer Modes.................................................................................. 119
6 Rev. 2.6
C8051F300/1/2/3/4/5
13.5.1.Master Transmitter Mode ....................................................................... 119
13.5.2.Master Receiver Mode........................................................................... 120
13.5.3.Slave Receiver Mode............................................................................. 121
13.5.4.Slave Transmitter Mode ......................................................................... 122
13.6.SMBus Status Decoding................................................................................. 123
14.UART0.................................................................................................................... 127
14.1.Enhanced Baud Rate Generation................................................................... 128
14.2.Operational Modes ......................................................................................... 129
14.2.1.8-Bit UART............................................................................................. 129
14.2.2.9-Bit UART............................................................................................. 130
14.3.Multiprocessor Communications .................................................................... 131
15.Timers.................................................................................................................... 139
15.1.Timer 0 and Timer 1 ....................................................................................... 139
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 139
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 141
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 141
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 142
15.2.Timer 2 .......................................................................................................... 147
15.2.1.16-bit Timer with Auto-Reload................................................................ 147
15.2.2.8-bit Timers with Auto-Reload................................................................ 148
16.Programmable Counter Array ............................................................................. 151
16.1.PCA Counter/Timer ........................................................................................ 152
16.2.Capture/Compare Modules ............................................................................ 153
16.2.1.Edge-triggered Capture Mode................................................................ 154
16.2.2.Software Timer (Compare) Mode........................................................... 155
16.2.3.High Speed Output Mode....................................................................... 156
16.2.4.Frequency Output Mode ........................................................................ 157
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 158
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 159
16.3.Watchdog Timer Mode ................................................................................... 160
16.3.1.Watchdog Timer Operation .................................................................... 160
16.3.2.Watchdog Timer Usage ......................................................................... 161
16.4.Register Descriptions for PCA........................................................................ 163
17.C2 Interface ........................................................................................................... 169
17.1.C2 Interface Registers.................................................................................... 169
17.2.C2 Pin Sharing ............................................................................................... 171
Rev. 2.6 7
C8051F300/1/2/3/4/5
NOTES:
8 Rev. 2.6
C8051F300/1/2/3/4/5
List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 16
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings* .................................................................. 26
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ....................................................... 27
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........................................... 28
Table 4.2. QFN-11 Package Diminsions ................................................................. 30
5. ADC0 (8-Bit ADC, C8051F300/2)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 45
6. Voltage Reference (C8051F300/2)
Table 6.1. External Voltage Reference Circuit Electrical Characteristics ................ 48
7. Comparator0
Table 7.1. Comparator0 Electrical Characteristics .................................................. 53
8. CIP-51 Microcontroller
Table 8.1. CIP-51 Instruction Set Summary ............................................................ 57
Table 8.2. Special Function Register (SFR) Memory Map ...................................... 64
Table 8.3. Special Function Registers* ................................................................... 64
Table 8.4. Interrupt Summary .................................................................................. 72
9. Reset Sources
Table 9.1. User Code Space Address Limits ........................................................... 84
Table 9.2. Reset Electrical Characteristics .............................................................. 84
10.Flash Memory
Table 10.1. Flash Electrical Characteristics ............................................................ 88
Table 10.2. Security Byte Decoding ........................................................................ 89
11.Oscillators
Table 11.1. Internal Oscillator Electrical Characteristics ......................................... 95
12.Port Input/Output
Table 12.1. Port I/O DC Electrical Characteristics ................................................. 106
13.SMBus
Table 13.1. SMBus Clock Source Selection .......................................................... 112
Table 13.2. Minimum SDA Setup and Hold Times ................................................ 113
Table 13.3. Sources for Hardware Changes to SMB0CN ..................................... 117
Table 13.4. SMBus Status Decoding ..................................................................... 123
14.UART0
Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Os-
cillator ................................................................................................. 134
Table 14.2. Timer Settings for Standard Baud Rates Using an External 25 MHz Oscil-
lator ..................................................................................................... 134
Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator ............................................................................................. 135
Rev. 2.6 9
C8051F300/1/2/3/4/5
Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz
Oscillator ............................................................................................. 136
Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz
Oscillator ............................................................................................. 137
Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ
Oscillator ............................................................................................. 138
15.Timers
16.Programmable Counter Array
Table 16.1. PCA Timebase Input Options ............................................................. 152
Table 16.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 153
Table 16.3. Watchdog Timer Timeout Intervals1 ................................................... 162
17.C2 Interface
10 Rev. 2.6
C8051F300/1/2/3/4/5
List of Figures
1. System Overview
Figure 1.1. C8051F300/2 Block Diagram ................................................................. 17
Figure 1.2. C8051F301/3/4/5 Block Diagram ........................................................... 17
Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 18
Figure 1.4. On-Chip Clock and Reset ...................................................................... 19
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ................................. 20
Figure 1.6. Development/In-System Debug Diagram............................................... 21
Figure 1.7. Digital Crossbar Diagram ....................................................................... 22
Figure 1.8. PCA Block Diagram ............................................................................... 23
Figure 1.9. PCA Block Diagram ............................................................................... 23
Figure 1.10. 8-Bit ADC Block Diagram ..................................................................... 24
Figure 1.11. Comparator Block Diagram .................................................................. 25
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 29
Figure 4.2. QFN-11 Package Drawing ..................................................................... 30
Figure 4.3. Typical QFN-11 Solder Paste Mask ....................................................... 31
Figure 4.4. Typical QFN-11 Landing Diagram.......................................................... 32
5. ADC0 (8-Bit ADC, C8051F300/2)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 33
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 35
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 36
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing ................................ 38
Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 39
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode........................ 43
Figure 5.7. ADC Window Compare Examples, Differential Mode ............................ 44
6. Voltage Reference (C8051F300/2)
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 47
7. Comparator0
Figure 7.1. Comparator0 Functional Block Diagram ................................................ 49
Figure 7.2. Comparator Hysteresis Plot ................................................................... 50
8. CIP-51 Microcontroller
Figure 8.1. CIP-51 Block Diagram............................................................................ 55
Figure 8.2. Program Memory Maps.......................................................................... 61
Figure 8.3. Data Memory Map.................................................................................. 62
9. Reset Sources
Figure 9.1. Reset Sources........................................................................................ 81
Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 82
10.Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 89
11.Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 93
Rev. 2.6 11
C8051F300/1/2/3/4/5
Figure 11.2. 32.768 kHz External Crystal Example.................................................. 97
12.Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram ....................................................... 99
Figure 12.2. Port I/O Cell Block Diagram ................................................................. 99
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 100
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 101
13.SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 107
Figure 13.2. Typical SMBus Configuration ............................................................. 108
Figure 13.3. SMBus Transaction ............................................................................ 109
Figure 13.4. Typical SMBus SCL Generation......................................................... 113
Figure 13.5. Typical Master Transmitter Sequence................................................ 119
Figure 13.6. Typical Master Receiver Sequence.................................................... 120
Figure 13.7. Typical Slave Receiver Sequence...................................................... 121
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 122
14.UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 127
Figure 14.2. UART0 Baud Rate Logic .................................................................... 128
Figure 14.3. UART Interconnect Diagram .............................................................. 129
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 129
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 130
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 131
15.Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 140
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 141
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 142
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 147
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 148
16.Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 151
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 152
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 153
Figure 16.4. PCA Capture Mode Diagram.............................................................. 154
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 155
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 156
Figure 16.7. PCA Frequency Output Mode ............................................................ 157
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 158
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 159
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 160
17.C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 171
12 Rev. 2.6
C8051F300/1/2/3/4/5
List of Registers
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) . . . . . . . . . . . . 40
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) . . . . . . . . . . . . . . . 41
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) . . . . . . . . . . . . . . . . . . . 41
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) . . . . . . . . . . . . . . . . . . . . 42
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) . . . . . . 44
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2) . . . . . . . . . 44
SFR Definition 6.1. REF0CN: Reference Control Register . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 9.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 11.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 11.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 104
SFR Definition 12.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 12.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 12.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 114
SFR Definition 13.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SFR Definition 13.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SFR Definition 14.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 133
SFR Definition 15.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 15.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 15.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Rev. 2.6 13
C8051F300/1/2/3/4/5
SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFR Definition 15.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 150
SFR Definition 15.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 150
SFR Definition 15.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 16.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
SFR Definition 16.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 165
SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 166
SFR Definition 16.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 166
SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 167
SFR Definition 16.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 167
C2 Register Definition 17.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
C2 Register Definition 17.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 169
C2 Register Definition 17.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 170
C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 170
C2 Register Definition 17.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 170
14 Rev. 2.6
C8051F300/1/2/3/4/5
1. System Overview
C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features are listed below. Refer to Ta bl e 1.1 on page 16 for specific product feature selection.
• High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 8-bit 500 ksps 11-channel ADC with programmable gain pre-amplifier and analog multiplexer
(C8051F300/2 only)
• Precision programmable 25 MHz internal oscillator
• Up to 8 kB of on-chip Flash memory
• 256 bytes of on-chip RAM
• SMBus/I2C and Enhanced UART serial interfaces implemented in hardware
• Three general-purpose 16-bit timers
• Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer
function
• On-chip power-on reset, VDD monitor, and temperature sensor
• On-chip voltage comparator
• Byte-wide I/O port (5 V tolerant)
With on-chip Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F300/1/2/3/4/5 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can
be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Laboratories 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins.
Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and /RST pins are tolerant of input signals up to 5
in the 11-pin QFN package (also referred to as MLP or MLF package) shown in
V. The C8051F300/1/2/3/4/5 are available
Figure 4.2.
-
Rev. 2.6 15
C8051F300/1/2/3/4/5
Table 1.1. Product Selection Guide
C
2
Ordering Part Number
C8051F300 25 8 k 256 3 3 3 3 3 8 3 3 1 – QFN-11
C8051F300-GM 25 8 k 256 3 3 3 3 3 8 3 3 1 3 QFN-11
C8051F301 25 8 k 256 3 3 3 3 3 8 — — 1 – QFN-11
C8051F301-GM 25 8 k 256 3 3 3 3 3 8 — — 1 3 QFN-11
C8051F302 25 8 k 256 — 3 3 3 3 8 3 3 1 – QFN-11
C8051F302-GM 25 8 k 256 — 3 3 3 3 8 3 3 1 3 QFN-11
C8051F303 25 8 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F303-GM 25 8 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
C8051F304 25 4 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F304-GM 25 4 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
C8051F305 25 2 k 256 — 3 3 3 3 8 — — 1 – QFN-11
C8051F305-GM 25 2 k 256 — 3 3 3 3 8 — — 1 3 QFN-11
MIPS (Peak)
Flash Memory
RAM
Calibrated Internal Oscillator
SMBus/I
UART
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
8-bit 500ksps ADC
Temperature Sensor
Analog Comparators
Lead-free
Package
16 Rev. 2.6
VDD
GND
/RST/C2CK
Analog/Digital
XTAL1
XTAL2
Power
C2D
POR
External
Oscillator
Circuit
Precision
Internal
Oscillator
C8051F300/1/2/3/4/5
Port I/O Mode
& Config.
Reset
8
0
8kbyte
FLASH
5
1
256 byte
SRAM
Debug HW
Brown-
Out
C
o
System Clock
SFR Bus
r
e
Clock & Reset
Configuration
Figure 1.1. C8051F300/2 Block Diagram
Timer 0, 1
ADC
Config. &
Control
CNVSTR
Port 0
Latch
UART
PCA/
WDT
SMBus
XBAR
Control
VDD
8-bit
500ksps
ADC
x2
x4
x2
CP0
VREF
P0.0/VREF
P0.1
X
B
A
R
P
0
D
r
v
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/C2D
C2D
CP0
+
-
Temp
A
AIN0-AIN7
M
PGA
U
X
VDD
/RST/C2CK
VDD
GND
Analog/Digital
XTAL1
XTAL2
Power
C2D
Port I/O Mode
POR
External
Oscillator
Circuit
Precision
Internal
Oscillator
Debug HW
Brown-
Out
Reset
System Clock
8
0
5
1
C
o
SFR Bus
r
e
8k/4k/2k
byte
FLASH
256 byte
SRAM
Clock & Reset
Configuration
Port 0
Latch
UART
Timer 0, 1
PCA/
WDT
SMBus
XBAR
Control
Figure 1.2. C8051F301/3/4/5 Block Diagram
& Config.
x2
X
B
A
R
x4
x2
CP0
P
0
D
r
v
C2D
CP0
+
-
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7/C2D
P0.0/VREF
Rev. 2.6 17
C8051F300/1/2/3/4/5
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Spe
cial Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
MHz. By contrast, the CIP-51 core exe-
-
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks.
25
20
15
MIPS
10
5
Cygnal
CIP-51
(25MHz clk)
Microchip
PIC17C75x
(33MHz clk)
Figure 1.3. Comparison of Peak MCU Execution Speeds
18 Rev. 2.6
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
C8051F300/1/2/3/4/5
1.1.3. Additional Features
The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multitasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below 2.7
level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash
read/write protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash protection
may be disabled by the user in software. The WDT may be permanently enabled in software after a poweron reset during MCU initialization.
The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncalibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal
oscillator period may be user programmed in ~0.5% increments. An external oscillator drive circuit is also
included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate
the system clock. If desired, the system clock source may be switched on-the-fly to the external oscillator
circuit. An external oscillator can be extremely useful in low power applications, allowing the MCU to run
from a slow (power saving) external crystal source, while periodically switching to the fast (up to 25
internal oscillator as needed.
V), a Watchdog Timer, a Missing Clock Detector, a voltage
MHz)
XTAL1
XTAL2
Internal
Oscillator
External
Oscillator
Drive
VDD
Supply
Monitor
Enable
+
-
Power On
P0.x
P0.y
System
Clock
Clock Select
Comparator 0
+
-
Missing
Clock
Detector
(oneshot)
EN
MCD
Enable
Microcontroller
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
PCA
WDT
EN
WDT
Enable
System Reset
Reset
Figure 1.4. On-Chip Clock and Reset
(Software Reset)
SWRSF
'0'
(wired-OR)
Reset
Funnel
Illegal
FLASH
Operation
/RST
Rev. 2.6 19
C8051F300/1/2/3/4/5
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the
C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and
requires no special off-chip programming voltage. See
map.
Figure 1.5 for the C8051F300/1/2/3 system memory
0x1E00
0x1DFF
0x0000
PROGRAM MEMORY
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
RESERVED
8k bytes
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
(Direct Addressing Only)
Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown)
Register's
Lower 128 RAM
(Direct and Indirect
Addressing)
20 Rev. 2.6
C8051F300/1/2/3/4/5
1.3. On-Chip Debug Circuitry
The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides
non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them synchronized.
The C8051F300DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F300/1/2/3/4/5 MCUs. The kit includes software
with a developer's studio and debugger, an integrated 8051 assembler, and a C2 debug adapter. It also
has a target application board with the associated MCU installed and large prototyping area, plus the nec
essary communication cables and wall-mount power supply. The Development Kit requires a computer
with Windows® 98 SE or later. The Silicon Labs IDE interface is a vastly superior developing and debug
ging configuration, compared to standard MCU emulators that use onboard "ICE Chips" and require the
MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and
preserves the performance of the precision analog peripherals.
Silicon Labs Integrated
WINDOWS 98 SE or Later
Development Environment
-
-
RS-232
Debug
Adapter
C2 (x2), VDD, GND
VDD GND
C8051F300
TARGET PCB
Figure 1.6. Development/In-System Debug Diagram
1.4. Programmable Digital I/O and Crossbar
C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few
enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as
digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pull-ups” that are
fixed on typical 8051 devices may be globally disabled, providing power savings capabilities.
Rev. 2.6 21
C8051F300/1/2/3/4/5
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switching network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). Onchip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
Highest
Priority
(Internal Digital Signals)
Lowest
Priority
UART
SMBus
CP0
Outputs
SYSCLK
PCA
T0, T1
1.5. Serial Ports
XBR0, XBR1,
XBR2 Registers
P0MDOUT,
P0MDIN Registers
Priority
Decoder
2
2
Digital
Crossbar
2
8
Cells
4
2
8
P0Port Latch
(P0.0-P0.7)
Figure 1.7. Digital Crossbar Diagram
P0
I/O
P0.0
P0.7
The C8051F300/1/2/3/4/5 Family includes an SMBus/I2C interface and a full-duplex UART with enhanced
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
22 Rev. 2.6
C8051F300/1/2/3/4/5
1.6. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general
purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro
grammable capture/compare modules. The PCA clock is derived from one of six sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system
clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for
real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator
drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 2 offers watchdog timer (WDT) capabilities. Following a system reset, Module 2
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
-
Capture/Compare
Module 0
ECI
CEX0
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Digital Crossbar
Port I/O
Figure 1.9. PCA Block Diagram
Rev. 2.6 23
C8051F300/1/2/3/4/5
1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only)
The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and
programmable gain amplifier. With a maximum throughput of 500
with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both posi
tive and negative ADC inputs. Each Port pin is available as an ADC input; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may
shut down the ADC to save power.
The integrated programmable gain amplifier (PGA) amplifies the the ADC input by 0.5, 1, 2, or 4 as defined
by user software. The gain stage is especially useful when different ADC input channels have widely varied
input voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset.
Conversions can be started in five ways: a software command, an overflow of Timer 0, 1, or 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by software events, a
periodic signal (timer overflows), or external HW signals. Conversion completions are indicated by a status
bit and an interrupt (if enabled). The resulting 8-bit data word is latched into an SFR upon completion of a
conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
ksps, the ADC offers true 8-bit accuracy
-
-
Temp
Sensor
Analog Multiplexer
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DGND
10-to-1
AMUX
9-to-1
AMUX
Configuration, Control, an d Data Registers
Programmable Gain
Amplifier
VDD
+
X
-
8-Bit
SAR
ADC
End of
Conversion
Interrupt
Start
Conversion
8
Window Compare
Logic
Software Write
T0 Overflow
TMR2 Overflow
T1 Overflow
External
Convert Start
ADC Data
Register
Window
Compare
Interrupt
Figure 1.10. 8-Bit ADC Block Diagram
24 Rev. 2.6
C8051F300/1/2/3/4/5
1.8. Comparator
C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and configured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.
Comparator response time is programmable, allowing the user to select between high-speed and lowpower modes. Positive and negative hysteresis is also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. The comparator may also be configured as a reset source.
P0.0
P0.2
P0.4
P0.6
P0.1
P0.3
P0.5
P0.7
CP0 +
VDD
CP0 -
+
-
GND
SET
D
CLR
(SYNCHRONIZER)
SET
D
Q
Q
CLR
Q
Q
Reset
Decision
Tree
Figure 1.11. Comparator Block Diagram
Interrupt
Handler
Crossbar
Rev. 2.6 25
C8051F300/1/2/3/4/5
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or /RST with respect to
GND
Voltage on VDD with respect to GND –0.3 4.2 V
Maximum Total current through VDD and GND 500 mA
Maximum output current sunk by /RST or any Port pin 100 mA
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
–0.3 5.8 V
26 Rev. 2.6
C8051F300/1/2/3/4/5
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage 2.7 3.0 3.6 V
Digital Supply Current with CPU
active
Digital Supply Current with CPU
inactive (not accessing Flash)
Digital Supply Current (shutdown) Oscillator not running < 0.1 µA
Digital Supply RAM Data Retention Voltage
Specified Operating Temperature
Range
SYSCLK (system clock frequency) 0
Tsysl (SYSCLK low time) 18 ns
Tsysh (SYSCLK high time) 18 ns
*Note: SYSCLK must be at least 32 kHz to enable debugging.
V
= 2.7 V, Clock = 25 MHz
DD
V
= 2.7 V, Clock = 1 MHz
DD
V
= 2.7 V, C l o ck = 32 kHz
DD
VDD = 2.7 V, Clock = 25 MHz
V
= 2.7 V, Clock = 1 MHz
DD
V
= 2.7 V, Clock = 32 kHz
DD
5.8
0.34
12
2.1
83
2.8
1.5 V
–40 +85 °C
*
25 MHz
mA
mA
µA
mA
µA
µA
Rev. 2.6 27
C8051F300/1/2/3/4/5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Pin Number Name Type Description
1 VREF /
P0.0
2 P0.1 D I/O or
3 V
4 XTAL1 /
5 XTAL2 /
6 P0.4 D I/O or
7 P0.5 D I/O or
DD
P0.2
P0.3
A In
D I/O or
A In
A In
A In
D I/O or
A In
A Out
D I/O
A In
A In
External Voltage Reference Input.
Port 0.0. See Section 12 for complete description.
Port 0.1. See Section 12 for complete description.
Power Supply Voltage.
Crystal Input. This pin is the external oscillator circuit return
for a crystal or ceramic resonator. See
Port 0.2. See Section 12 for complete description.
Crystal Input/Output. For an external crystal or resonator,
this pin is the excitation driver. This pin is the external clock
input for CMOS, capacitor, or RC network configurations.
See
Section 11.2.
Port 0.3. See Section 12 for complete description.
Port 0.4. See Section 12 for complete description.
Port 0.5. See Section 12 for complete description.
Section 11.2.
8 C2CK /
/RST
9 P0.6 /
CNVSTR
10 C2D /
P0.7
11 GND Ground.
28 Rev. 2.6
D I/O
D I/O
D I/O or
A In
D I/O
D I/O
D I/O or
A In
Clock signal for the C2 Development Interface.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
Port 0.6. See Section 12 for complete description.
ADC External Convert Start Input Strobe.
Data signal for the C2 Development Interface.
Port 0.7. See Section 12 for complete description.
C8051F300/1/2/3/4/5
VREF /
P0.0
P0.1
VDD
XTAL1 /
P0.2
XTAL2 /
P0.3
GND
C2D /
P0.7
P0.6 /
CNVSTR
C2CK /
/RST
P0.5
P0.4
Figure 4.1. QFN-11 Pinout Diagram (Top View)
Rev. 2.6 29
C8051F300/1/2/3/4/5
Bottom View
E2
b
L
LT
be
D2
k
e
E
LB
E3
D
D3
R
D4
Table 4.2. QFN-11
Package Diminsions
MM
MIN TYP MAX
A 0.80 0.90 1.00
A1 0 0.02 0.05
A2 0 0.65 1.00
A3 0.25
b 0.18 0.23 0.30
D3.00
D2 2.20 2.25
D3 2.00
D4 0.386
E3.00
E2 1.36
E3 1.135
e0.5
k0.27
L 0.45 0.55 0.65
LB 0.36
LT 0.37
R0.09
A3
A3
Side E View
A2
e
1
A
Side D View
A2
e
Figure 4.2. QFN-11 Package Drawing
A1
A
A
30 Rev. 2.6
C8051F300/1/2/3/4/5
m
m
0
1
.
b
0
0.35 mm
0.30 mm
0.20 mm
0.10 mm
0.50 mm
L
b
e
0.50 mm
k
LT
0.35 mm
0.30 mm
0.20 mm
0.30 mm
E2
0.60 mm
0.20 mm
D2
D4
D
0.70 mm
LB
e
E
Figure 4.3. Typical QFN-11 Solder Paste Mask
D4
Rev. 2.6 31
C8051F300/1/2/3/4/5
.
m
m
0
.
1
b
0
0.35 mm
0.30 mm
0.20 mm
0.10 mm
0.50 mm
L
b
e
LT
D2
E2
0.30 mm
k
0.20 mm
D4
D
LB
0.10 mm
e
E
Figure 4.4. Typical QFN-11 Landing Diagram
D4
32 Rev. 2.6
C8051F300/1/2/3/4/5
5. ADC0 (8-Bit ADC, C8051F300/2)
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500
bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in
Figure 5.1). The AMUX0, PGA, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or V
with respect to any Port pin or GND. The ADC0 subsystem is
DD
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub
system is in low power shutdown when this bit is logic 0.
ksps, 8-
-
Temp
Sensor
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND
AMUX0
10-to-1
AMUX
9-to-1
AMUX
X
AMX0N3
AMX0SL
AMX0N2
AMX0N1
VDD
+
-
AMX0N0
AD0SC4
AMX0P2
AMX0P3
AD0SC2
AD0SC3
ADC0CF
AMX0P1
AD0SC1
AMX0P0
AD0SC0
AD0EN
VDD
8-Bit
SAR
ADC
AMP0GN0
AMP0GN1
ADC0CN
AD0TM
AD0INT
SYSCLK
ADC0LT
ADC0GT
AD0BUSY
REF
AD0WINT
AD0CM1
AD0CM2
Start
Conversion
ADC0
AD0CM0
000 AD0BUSY (W)
Timer 0 Overflow
001
Timer 2 Overflow
010
Timer 1 Overflow
011
1xx
CNVSTR Input
8
AD0WINT
Comb.
16
Logic
Figure 5.1. ADC0 Functional Block Diagram
Rev. 2.6 33
C8051F300/1/2/3/4/5
5.1. Analog Multiplexer and PGA
The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin
to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the
positive power supply (V
negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential
Mode. The ADC0 input channels are selected in the AMX0SL register as described in
The conversion code format differs in Single-ended versus Differential modes, as shown below. When in
Single-ended Mode (negative input is selected GND), conversion codes are represented as 8-bit unsigned
integers. Inputs are measured from ‘0’ to VREF x 255/256. Example codes are shown below.
When in Differential Mode (negative input is not selected as GND), conversion codes are represented as
8-bit signed 2s complement numbers. Inputs are measured from –VREF to VREF x 127/128. Example
codes are shown below.
) may be selected as the positive PGA input. When GND is selected as the
DD
SFR Definition 5.1.
Input Voltage ADC0 Output (Conversion Code)
VREF x 255/256 0xFF
VREF x 128/256 0x80
VREF x 64/256 0x40
0 0x00
Input Voltage ADC0 Output (Conversion Code)
VREF x 127/128 0x7F
VREF x 64/128 0x40
0 0x00
–VREF x 64/128 0xC0
–VREF 0x80
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register P0MDIN. To force the Crossbar to skip a Port pin, set to ‘1’
the corresponding bit in register XBR0. See
O configuration details.
The PGA amplifies the AMUX0 output signal as defined by the AMP0GN1-0 bits in the ADC0 Configuration
register (
defaults to 0.5 on reset.
SFR Definition 5.2). The PGA is software-programmable for gains of 0.5, 1, 2, or 4. The gain
Section “12. Port Input/Output” on page 99 for more Port I/
5.2. Temperature Sensor
The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V
positive PGA input when the temperature sensor is selected by bits AMX0P2-0 in register AMX0SL; this
voltage will be amplified by the PGA according to the user-programmed PGA settings.
TEMP
) is the
34 Rev. 2.6
(mV)
1200
1100
1000
C8051F300/1/2/3/4/5
900
800
700
0-50 50 100
V
= 3.35*(TEMPC) + 897 mV
TEMP
(Celsius)
Figure 5.2. Typical Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Ta bl e 5.1 for linearity specifications). For absolute temperature measurements, gain and/
or offset calibration is recommended. Typically a 1-point calibration includes the following steps:
Step 1. Control/measure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile
memory for use with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
Rev. 2.6 35
C8051F300/1/2/3/4/5
5.00
4.00
3.00
2.00
1.00
0.00
-40.00 -20.00 0.00
-1.00
Error (degrees C)
-2.00
-3.00
-4.00
-5.00
20.00
Temperature (degrees C)
40.00
60.00
80.00
5.00
4.00
3.00
2.00
1.00
0.00
-1.00
-2.00
-3.00
-4.00
-5.00
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
36 Rev. 2.6
C8051F300/1/2/3/4/5
5.3. Modes of Operation
ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC
5.3.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol
lowing:
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data register, ADC0, when bit AD0INT is logic 1.
Note that when Timer 2 overflows are used as the conversion source, Timer 2 Low Byte overflows are
used if Timer 2 is in 8-bit mode; Timer 2 High byte overflows are used if Timer 2 is in 16-bit mode. See
tion “15. Timers” on page 139 for timer configuration.
+ 1) for 0 ≤ AD0SC ≤ 31).
-
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e. timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Sec-
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register XBR0. See
Input/Output” on page 99 for details on Port I/O configuration.
Section “12. Port
Rev. 2.6 37
C8051F300/1/2/3/4/5
5.3.2. Tracking Modes
According to Ta bl e 5.1 on page 45, each ADC0 conversion must be preceded by a minimum tracking time
for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-andhold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in
progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode,
each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal).
When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only
when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see
also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power trackand-hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in
Section “5.3.3. Settling Time Requirements” on page 39.
A. ADC Timing for External Trigger Source
CNVSTR
(AD0CM[2:0]=1xx)
123456789
SAR Clocks
Figure 5.4). Tracking can
AD0TM=1
Write '1' to AD0BUSY,
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0]=000, 001, 010, 011)
SAR Clocks
AD0TM=1
SAR Clocks
AD0TM=0
Figure 5.4. 8-Bit ADC Track and Conversion Example Timing
Low Power
or Convert
Track or Convert Convert TrackAD0TM=0
Track Convert Low Power Mode
B. ADC Timing for Internal Trigger Source
123456789101112
Low Power
or Convert
Track or
Convert
Track Convert Low Power Mode
123456789
Convert Track
38 Rev. 2.6
C8051F300/1/2/3/4/5
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the
accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the mini
mum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by
Sensor output or VDD with respect to GND, R
TOTAL
settling time (track/hold time) requirements.
n
2
t
------ -
×ln=
SA
R
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (8).
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
Equation 5.1. When measuring the Temperature
reduces to R
TOTALCSAMPLE
. See Ta bl e 5.1 for ADC0 minimum
MUX
-
Differential Mode
MUX Select
P0.x
RC
= R
Input
MUX
P0.y
MUX Select
Single-Ended Mode
MUX Select
R
= 5k
MUX
* C
SAMPLE
R
= 5k
MUX
Note: When the PGA gain is set to 0.5, C
C
C
SAMPLE
SAMPLE
= 5pF
= 5pF
P0.x
RC
Input
SAMPLE
= R
MUX
= 3pF
R
* C
MUX
= 5k
SAMPLE
Figure 5.5. ADC0 Equivalent Input Circuits
C
SAMPLE
= 5pF
Rev. 2.6 39
C8051F300/1/2/3/4/5
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–4: AMX0N3–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
0000–1000b: ADC0 Negative Input selected per the chart below.
AMX0N3–0 ADC0 Negative Input
0000 P0.0
0001 P0.1
0010 P0.2
0011 P0.3
0100 P0.4
0101 P0.5
0110 P0.6
0111 P0.7
1xxx GND (ADC in Single-Ended Mode)
0xBB
Bits3–0: AMX0P3–0: AMUX0 Positive Input Selection.
0000–1001b: ADC0 Positive Input selected per the chart below.
1010–1111b: RESERVED.
AMX0P3–0 ADC0 Positive Input
0000 P0.0
0001 P0.1
0010 P0.2
0011 P0.3
0100 P0.4
0101 P0.5
0110 P0.6
0111 P0.7
1000 Temperature Sensor
1001
V
DD
40 Rev. 2.6
C8051F300/1/2/3/4/5
A
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 — AMP0GN1 AMP0GN0 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements
are given in Table 5.1.
SYSCLK
D0SC
Bit2: UNUSED. Read = 0b; Write = don’t care.
Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA).
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
----------------------
CLK
SAR
1–=
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: ADC0 Data Word.
ADC0 holds the output data byte from the last ADC0 conversion. When in Single-ended
mode, ADC0 holds an 8-bit unsigned integer. When in Differential mode, ADC0 holds a 2’s
complement signed 8-bit integer.
0xBE
Rev. 2.6 41
C8051F300/1/2/3/4/5
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read: Unused.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2-0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
1xx: ADC0 conversion initiated on rising edge of external CNVSTR.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
1xx: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising
CNVSTR edge.
0xE8
42 Rev. 2.6
C8051F300/1/2/3/4/5
5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed
limits, and notifies the system when a desired condition is detected. This is especially effective in an inter
rupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.
The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The
ADC0 Greater-Than (ADC0GT) and Less-Than (ADC0LT) registers hold the comparison values. Example
comparisons for Single-ended and Differential modes are shown in
Figure 5.6 and Figure 5.7, respectively.
Notice that the window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits depending on the contents of the ADC0LT and ADC0GT registers.
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for Single-ended mode, with ADC0LT = 0x20 and
ADC0GT = 0x10. Notice that in Single-ended mode, the codes vary from 0 to VREF x (255/256) and are
represented as 8-bit unsigned integers. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0) is within the range defined by ADC0GT and ADC0LT
(if
0x10 < ADC0 < 0x20). In the right example, and AD0WINT interrupt will be generated if ADC0 is outside
of the range defined by ADC0GT and ADC0LT (if
ADC0 < 0x10 or ADC0 > 0x20).
-
ADC0 ADC0
Input Voltage
(P0.x - GND)
REF x (255/256)
REF x (32/256)
REF x (16/256)
0
0xFF
0x21
0x20
0x1F
0x11
0x10
0x0F
0x00
AD0WINT
not affected
ADC0LT
ADC0GT
AD0WINT
not affected
AD0WINT=1
Input Voltage
(P0.x - GND)
REF x (255/256)
REF x (32/256)
REF x (16/256)
0
0xFF
0x21
0x20
0x1F
0x11
0x10
0x0F
0x00
Figure 5.6. ADC Window Compare Examples, Single-Ended Mode
ADC0GT
AD0WINT
not affected
ADC0LT
AD0WINT=1
AD0WINT=1
Rev. 2.6 43
C8051F300/1/2/3/4/5
5.4.2. Window Detector In Differential Mode
Figure 5.7 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and
ADC0GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x (127/128)
and are represented as 8-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt
will be generated if the ADC0 conversion word (ADC0L) is within the range defined by ADC0GT and
ADC0LT (if
ated if ADC0 is outside of the range defined by ADC0GT and ADC0LT (if ADC0 < 0xFF (–1d) or ADC0 >
0x10 (+16d)).
REF x (127/128)
0xFF (–1d) < ADC0 < 0x10 (16d)). In the right example, an AD0WINT interrupt will be gener-
ADC0ADC0
Input Voltage
(P0.x - P0.y)
0x7F (127d)
AD0WINT
not affected
Input Voltage
(P0.x - P0.y)
REF x (127/128)
0x7F (127d)
AD0WINT=1
REF x (16/128)
REF x (-1/256)
-REF
0x11 (17d)
0x10 (16d)
0x0F (15d)
0x00 (0d)
0xFF (-1d)
0xFE (-2d)
0x80 (-128d)
ADC0LT
ADC0GT
AD0WINT
not affected
REF x (16/128)
AD0WINT=1
REF x (-1/256)
-REF
0x11 (17d)
0x10 (16d)
0x0F (15d)
0x00 (0d)
0xFF (-1d)
0xFE (-2d)
0x80 (-128d)
ADC0GT
AD0WINT
not affected
ADC0LT
AD0WINT=1
Figure 5.7. ADC Window Compare Examples, Differential Mode
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2)
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: ADC0 Greater-Than Data Word.
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2)
0xC4
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: ADC0 Less-Than Data Word.
44 Rev. 2.6
00000000
0xC6
C8051F300/1/2/3/4/5
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 8 bits
Integral Nonlinearity ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error
Full Scale Error
1
1
Differential mode
Dynamic Performance (10 kHz Sine-wave Differential Input, 1 dB below Full Scale, 500 ksps)
Signal-to-Noise Plus Distortion 45 48 dB
Total Harmonic Distortion
Up to the 5th harmonic
Spurious-Free Dynamic Range 58 dB
Conversion Rate
SAR Conversion Clock 6 MHz
Conversion Time in SAR Clocks 8 clocks
Track/Hold Acquisition Time 300 ns
Throughput Rate 500 ksps
Analog Inputs
Input Voltage Range 0 VREF V
Input Capacitance 5 pF
Temperature Sensor
1,2,3
1,2,3
1,2,3
(Temp = 0 °C)
Linearity
Gain
Offset
Power Specifications
Power Supply Current (VDD supplied to ADC0)
Operating Mode, 500 ksps
Power Supply Rejection ±0.3 mV/V
Notes:
1. Represents one standard deviation from the mean.
2. Measured with PGA Gain = 2.
3. Includes ADC offset, gain, and linearity variations.
0.5±0.6 LSB
–1±0.5 LSB
–56 dB
±0.5 °C
3350
µV / °C
±110
897±31 mV
400 900 µA
Rev. 2.6 45
C8051F300/1/2/3/4/5
NOTES:
46 Rev. 2.6
C8051F300/1/2/3/4/5
6. Voltage Reference (C8051F300/2)
The voltage reference MUX on C8051F300/2 devices is configurable to use an externally connected voltage reference or the power supply voltage, VDD (see Figure 6.1). The REFSL bit in the Reference Control
register (REF0CN) selects the reference source. For an external source, REFSL should be set to ‘0’; For
V
as the reference source, REFSL should be set to ‘1’.
DD
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and Internal Oscillator. This bit is forced to logic 1 when any of the aforementioned peripherals is enabled.
The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
SFR Definition 6.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are given in Ta bl e 6.1.
Important Note About the VREF Input: Port pin P0.0 is used as the external VREF input. When using an
external voltage reference, P0.0 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.0 as analog input, set to ‘1’ Bit0 in register P0MDIN. To configure the Crossbar to skip
P0.0, set to ‘1’ Bit0 in register XBR0. Refer to
Port I/O configuration details. The external reference voltage must be within the range 0 ≤ VREF ≤ VDD.
On C8051F300/2 devices, the temperature sensor connects to the highest order input of the ADC0 positive
input multiplexer (see
Section “5.1. Analog Multiplexer and PGA” on page 34 for details). The TEMPE
bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor
defaults to a high impedance state and any ADC0 measurements performed on the sensor result in mean
ingless data.
Section “12. Port Input/Output” on page 99 for complete
-
VDD
GND
R1
REF0CN
BIASE
REFSL
TEMPE
EN
Bias Generator
0
1
IOSCEN
EN
Temp Sensor
External
Voltage
Reference
Circuit
VREF
VDD
Figure 6.1. Voltage Reference Functional Block Diagram
To ADC, Internal
Oscillator,
Temperature Sensor
To Analog Mux
Internal
VREF
(to ADC)
Rev. 2.6 47
C8051F300/1/2/3/4/5
SFR Definition 6.1. REF0CN: Reference Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — REFSL TEMPE BIASE — 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3: REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF input pin used as voltage reference.
1: V
used as voltage reference.
DD
Bit2: TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1: BIASE: Internal Analog Bias Generator Enable Bit. (Must be ‘1’ if using ADC).
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0: UNUSED. Read = 0b. Write = don’t care.
0xD1
Table 6.1. External Voltage Reference Circuit Electrical Characteristics
VDD = 3.0 V; –40 to +85°C unless otherwise specified
Parameter Conditions Min Typ Max Units
Input Voltage Range 0 VDD V
Input Current Sample Rate = 500 ksps;
VREF
= 3.0 V
12 µA
48 Rev. 2.6
C8051F300/1/2/3/4/5
7. Comparator0
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in
Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer,
and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an
asynchronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system
clock is not active. This allows Comparator0 to operate and generate an output with the device in STOP
mode. When assigned to a Port pin, the Comparator0 output may be configured as open drain or push-pull
(see
Section “12.2. Port I/O Initialization” on page 102). Comparator0 may also be used as a reset
source (see Section “9.5. Comparator0 Reset” on page 83).
The inputs for Comparator0 are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0
negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see
CP0EN
CP0OUT
CP0RIF
CP0FIF
CMX0N1
CMX0N0
CPT0MX
CMX0P1
CMX0P0
P0.0
P0.2
P0.4
P0.6
P0.1
P0.3
P0.5
P0.7
CP0HYP1
CPT0CN
CP0HYP0
CP0HYN1
CP0HYN0
CP0 +
CP0 -
Section “12.3. General Purpose Port I/O” on page 104).
VDD
CP0
Rising-edge
Interrupt Flag
Interrupt
Logic
+
-
GND
Reset
Decision
Tree
SET
SET
D
D
Q
Q
CLR
CLR
(SYNCHRONIZER)
Q
Q
Crossbar
CP0
Falling-edge
Interrupt Flag
CP0
CP0A
CPT0MD
CP0MD1
CP0MD0
Figure 7.1. Comparator0 Functional Block Diagram
Rev. 2.6 49
C8051F300/1/2/3/4/5
The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port
pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the
system clock; the asynchronous output is available even in STOP mode (with no system clock active).
When disabled, the Comparator0 output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic
low state, and its supply current falls to less than 100
Decoder” on page 100 for details on configuring the Comparator0 output via the digital Crossbar.
Comparator0 inputs can be externally driven from –0.25 to (VDD) + 0.25 V without damage or upset. The
complete electrical specifications for Comparator0 are given in
The Comparator0 response time may be configured in software via the CP0MD1-0 bits in register
CPT0MD (see
SFR Definition 7.3). Selecting a longer response time reduces the amount of power con-
sumed by Comparator0. See Table 7.1 for complete timing and power consumption specifications.
nA. See Section “12.1. Priority Crossbar
Ta bl e 7.1.
CP0+
VIN+
CP0-
VIN-
CIRCUIT CONFIGURATION
Posi tive H ystere sis Vo ltag e
(Programmed with CP0HYP Bits)
VIN-
INPUTS
VIN+
OUTPUT
V
OL
Posi tive H ystere sis
Disabled
Figure 7.2. Comparator Hysteresis Plot
+
CP0
_
V
OH
OUT
Maximum
Posi tive Hyster esis
Negative Hysteresis
Disabled
Negative Hysteresis Vo ltage
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis
The hysteresis of Comparator0 is software-programmable via its Comparator0 Control register (CPT0CN).
The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive
and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator0 hysteresis is programmed using Bits3–0 in the Comparator0 Control Register CPT0CN
(shown in
SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of
the CP0HYN bits. As shown in Figure 7.2, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CP0HYP bits.
50 Rev. 2.6
C8051F300/1/2/3/4/5
Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For
Interrupt enable and priority control, see
is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the
Comparator0 rising-edge interrupt. Once set, these bits remain set until cleared by software. The output
state of Comparator0 can be obtained at any time by reading the CP0OUT bit. Comparator0 is enabled by
setting the CP0EN bit to logic 1, and is disabled by clearing this bit to logic 0.
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6: CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5: CP0RIF: Comparator0 Rising-Edge Interrupt Flag.
0: No Comparator0 Rising Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Rising Edge Interrupt has occurred.
Bit4: CP0FIF: Comparator0 Falling-Edge Interrupt Flag.
0: No Comparator0 Falling-Edge Interrupt has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Section “8.3. Interrupt Handler” on page 70). The CP0FIF flag
0xF8
Rev. 2.6 51
C8051F300/1/2/3/4/5
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — CMX0N1 CMX0N0 — — CMX0P1 CMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
CMX0N1 CMX0N0 Negative Input
00 P0.1
01 P0.3
10 P0.5
11 P0.7
Bits3–2: UNUSED. Read = 00b, Write = don’t care.
Bits1–0: CMX0P1–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
0x9F
CMX0P1 CMX0P0 Positive Input
00 P0.0
01 P0.2
10 P0.4
11 P0.6
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — — — CP0MD1 CP0MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–2: UNUSED. Read = 000000b, Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select.
These bits select the response time for Comparator0.
Mode CP0MD1 CP0MD0 CP0 Response Time (TYP)
0 0 0 Fastest Response Time
101 —
210 —
3 1 1 Lowest Power Consumption
0x9D
52 Rev. 2.6
Table 7.1. Comparator0 Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
C8051F300/1/2/3/4/5
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Common-Mode Rejection
Ratio
Positive Hysteresis 1 CP0HYP1–0 = 00 0 1 mV
Positive Hysteresis 2 CP0HYP1–0 = 01 3 5 7 mV
Positive Hysteresis 3 CP0HYP1–0 = 10 7 10 15 mV
Positive Hysteresis 4 CP0HYP1–0 = 11 15 20 25 mV
Negative Hysteresis 1 CP0HYN1–0 = 00 0 1 mV
Negative Hysteresis 2 CP0HYN1–0 = 01 3 5 7 mV
Negative Hysteresis 3 CP0HYN1–0 = 10 7 10 15 mV
CP0+ – CP0– = 100 mV 100 ns
CP0+ – CP0– = –100 mV 250 ns
CP0+ – CP0– = 100 mV 175 ns
CP0+ – CP0– = –100 mV 500 ns
CP0+ – CP0– = 100 mV 320 ns
CP0+ – CP0– = –100 mV 11 00 ns
CP0+ – CP0– = 100 mV 1050 ns
CP0+ – CP0– = –100 mV 5200 ns
1.5 4 mV/V
Negative Hysteresis 4 CP0HYN1–0 = 11 15 20 25 mV
Inverting or Non-Inverting
Input Voltage Range
Input Capacitance 7 pF
Input Bias Current –5 0.001 +5 nA
Input Offset Voltage –5 +5 mV
Power Supply
Power Supply Rejection 0.1 1 mV/V
Power-up Time 10 µs
Mode 0 7.6 µA
Mode 1 3.2 µA
Supply Current at DC
Mode 2 1.3 µA
Mode 3 0.4 µA
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
Rev. 2.6 53
–0.25 VDD +
0.25
V
C8051F300/1/2/3/4/5
NOTES:
54 Rev. 2.6
C8051F300/1/2/3/4/5
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
three 16-bit counter/timers (see description in
in Section 14), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (Sec-
tion 8.2.6), and one byte-wide I/O Port (see description in Section 12). The CIP-51 also includes on-chip
debug hardware (see description in Section 17), and interfaces directly with the analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction Set - Extended Interrupt Handler
- 25 MIPS Peak Throughput with 25 MHz Clock - Reset Input
- 0 to 25 MHz Clock Frequency - Power Management Modes
- 256 Bytes of Internal RAM - On-chip Debug Logic
- Byte-Wide I/O Port - Program and Data Memory Security
Section 15), an enhanced full-duplex UART (see description
Figure 8.1 for a block diagram).
-
ACCUMULATOR
DATA BUS
PROGRAM COUNTER (PC)
RESET
CLOCK
STOP
IDLE
CONTROL
D8
PSW
D8
DATA POINTER
PC INCREMENTER
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
REGISTER
D8
TMP1 TMP2
BUFFER
PIPELINE
ALU
D8
DATA BUS
D8
DATA BUS
D8
D8
DATA BUS
D8
B REGISTER
ADDRESS
REGISTER
D8
INTERFACE
D8
A16
D8
INTERRUPT
INTERFACE
D8
D8
SRAM
D8
SFR
BUS
MEMORY
INTERFACE
D8
STACK POINTER
SRAM
(256 X 8)
D8
SFR_ADDRESS
SFR_CONTROL
SFR_W RITE_DATA
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEM_WRIT E_DATA
MEM_READ_DATA
SYSTEM_IRQs
EMULATION_IRQ
Figure 8.1. CIP-51 Block Diagram
Rev. 2.6 55
C8051F300/1/2/3/4/5
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu
tion time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data stor
age as well as updating program code under software control.
MHz. By contrast, the CIP-51
-
-
-
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast
and efficient in-system device programming and debugging. Third party macro assemblers and C compil
ers are also available.
Section “17. C2 Interface” on page 169.
8.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan
dard 8051.
8.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
-
-
-
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken.
56 Rev. 2.6
Table 8.1 is the
C8051F300/1/2/3/4/5
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
8.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5
does not support external data or program memory). In the CIP-51, the MOVX instruction accesses the onchip program memory space implemented as re-programmable Flash memory. This feature provides a
mechanism for the CIP-51 to update program code and use the program memory space for non-volatile
data storage. Refer to
Mnemonic Description Bytes Clock
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
Section “10. Flash Memory” on page 87 for further details.
Table 8.1. CIP-51 Instruction Set Summary
Cycles
Arithmetic Operations
Logical Operations
Rev. 2.6 57
C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
58 Rev. 2.6
C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 2 2/3
JNC rel Jump if Carry is not set 2 2/3
JB bit, rel Jump if direct bit is set 3 3/4
JNB bit, rel Jump if direct bit is not set 3 3/4
JBC bit, rel Jump if direct bit is set and clear bit 3 3/4
Program Branching
ACALL addr11 Absolute subroutine call 2 3
LCALL addr16 Long subroutine call 3 4
RET Return from subroutine 1 5
RETI Return from interrupt 1 5
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
SJMP rel Short jump (relative address) 2 3
JMP @A+DPTR Jump indirect relative to DPTR 1 3
JZ rel Jump if A equals zero 2 2/3
Rev. 2.6 59
C8051F300/1/2/3/4/5
Table 8.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
JNZ rel Jump if A does not equal zero 2 2/3
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/4
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/4
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3
DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/4
NOP No operation 1 1
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
3 3/4
3 4/5
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x000x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
60 Rev. 2.6
C8051F300/1/2/3/4/5
8.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in
8.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of
this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x1FFF. Note: 512 bytes (0x1E00 - 0x1FFF) of this memory are reserved
for factory use and are not available for user program storage. The C8051F304 implements 4096 bytes of
reprogrammable Flash program memory space; the C8051F305 implements 2048 bytes of reprogramma
ble Flash program memory space. Figure 8.2 shows the program memory maps for C8051F300/1/2/3/4/5
devices.
Figure 8.2 and Figure 8.3.
C8051F300/1/2/3
(8k FLASH)
-
C8051F304
(4k FLASH)
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0800
0x07FF
0x0000
C8051F305
(2k FLASH)
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x1E00
0x1DFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x1000
0x0FFF
0x0000
Figure 8.2. Program Memory Maps
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro
vides a mechanism for the CIP-51 to update program code and use the program memory space for nonvolatile data storage. Refer to
Section “10. Flash Memory” on page 87 for further details.
-
Rev. 2.6 61
C8051F300/1/2/3/4/5
8.2.2. Data Memory
The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through
0xFF. The lower 128
ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting
of eight byte-wide registers. The next 16
bytes or as 128
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128
bytes of data memory. Figure 8.3 illustrates the data memory organization of the CIP-51.
bytes of data memory are used for general purpose registers and scratch pad mem-
bytes, locations 0x20 through 0x2F, may either be addressed as
bit locations accessible with the direct addressing mode.
bytes of data memory space or the SFRs. Instructions that use
INTERNAL DATA ADDRESS SPACE
0xFF
0x80
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
0x7F
(Direct and Indirect
Addressing)
0x30
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x20
0x1F
0x00
General Purpose
Registers
Figure 8.3. Data Memory Map
8.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
SFR Definition 8.4). This allows
62 Rev. 2.6
C8051F300/1/2/3/4/5
8.2.4. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128
0x00 to 0x7F. Bit
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address
8.2.5. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
individually addressable bits. Each bit has a bit address from
-
8.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the subsystems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set.
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bitaddressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in
for a detailed description of each register.
Ta bl e 8.2 lists the SFRs imple-
Ta bl e 8.3,
Rev. 2.6 63
C8051F300/1/2/3/4/5
Table 8.2. Special Function Register (SFR) Memory Map
F8 CPT0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80
BP0MDIN EIP1
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 RSTSRC
ACC XBR0 XBR1 XBR2 IT01CF EIE1
PCA0CN PCA0MD PCA0CPM0PCA0CPM1PCA0CPM
2
PSW REF0CN
TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H
SMB0CN SMB0CF SMB0DAT ADC0GT ADC0LT
IP AMX0SL ADC0CF ADC0
OSCXCN OSCICN OSCICL FLSCL FLKEY
IE
P0MDOUT
SCON0 SBUF0 CPT0MD CPT0MX
P0 SP DPL DPH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addres-
sable)
Table 8.3. Special Function Registers*
Register Address Description Page
ACC
ADC0CF
ADC0CN
ADC0GT
ADC0LT
ADC0
AMX0SL
B
CKCON
CPT0CN
CPT0MD
CPT0MX
DPH
DPL
EIE1
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
0xE0
0xBC
0xE8
0xC4
0xC6
0xBE
0xBB
0xF0
0x8E
0xF8
0x9D
0x9F
0x83
0x82
0xE6
Accumulator
ADC0 Configuration
ADC0 Control
ADC0 Greater-Than Compare Word
ADC0 Less-Than Compare Word
ADC0 Data Word
ADC0 Multiplexer Channel Select
B Register
Clock Control
Comparator0 Control
Comparator0 Mode Selection
Comparator0 MUX Selection
Data Pointer High
Data Pointer Low
Extended Interrupt Enable 1
No.
69
41
42
44
44
41
40
69
145
51
52
52
67
66
75
64 Rev. 2.6
C8051F300/1/2/3/4/5
Table 8.3. Special Function Registers* (Continued)
Register Address Description Page
EIP1
FLKEY
FLSCL
IE
IP
IT01CF
OSCICL
OSCICN
OSCXCN
P0
P0MDIN
P0MDOUT
PCA0CN
PCA0MD
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPM0
PCA0CPM1
PCA0CPM2
PCA0H
PCA0L
PCON
PSCTL
PSW
REF0CN
RSTSRC
SBUF0
SCON0
SMB0CF
SMB0CN
SMB0DAT
SP
TMR2CN
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
0xF6
0xB7
0xB6
0xA8
0xB8
0xE4
0xB3
0xB2
0xB1
0x80
0xF1
0xA4
0xD8
0xD9
0xFC
0xEA
0xEC
0xFB
0xE9
0xEB
0xDA
0xDB
0xDC
0xFA
0xF9
0x87
0x8F
0xD0
0xD1
0xEF
0x99
0x98
0xC1
0xC0
0xC2
0x81
0xC8
External Interrupt Priority 1
Flash Lock and Key
Flash Scale
Interrupt Enable
Interrupt Priority
INT0/INT1 Configuration Register
Internal Oscillator Calibration
Internal Oscillator Control
External Oscillator Control
Port 0 Latch
Port 0 Input Mode Configuration
Port 0 Output Mode Configuration
PCA Control
PCA Mode
PCA Capture 0 High
PCA Capture 1 High
PCA Capture 2 High
PCA Capture 0 Low
PCA Capture 1 Low
PCA Capture 2 Low
PCA Module 0 Mode Register
PCA Module 1 Mode Register
PCA Module 2 Mode Register
PCA Counter High
PCA Counter Low
Power Control
Program Store R/W Control
Program Status Word
Voltage Reference Control
Reset Source Configuration/Status
UART 0 Data Buffer
UART 0 Control
SMBus Configuration
SMBus Control
SMBus Data
Stack Pointer
Timer/Counter 2 Control
No.
76
91
91
73
74
77
94
94
96
105
105
106
163
164
167
167
167
167
167
167
165
165
165
166
166
79
90
68
47
85
133
132
114
116
118
67
150
Rev. 2.6 65
C8051F300/1/2/3/4/5
Table 8.3. Special Function Registers* (Continued)
Register Address Description Page
TCON
TH0
TH1
TL0
TL1
TMOD
TMR2RLH
TMR2RLL
TMR2H
TMR2L
XBR0
XBR1
XBR2
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xCB
0xCA
0xCD
0xCC
0xE1
0xE2
0xE3
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 2 High
Timer/Counter 2 Low
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
Reserved
No.
143
146
146
146
146
144
150
150
150
150
103
103
104
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic
case the reset value of the bit will be logic
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys
tem function.
l. Future product versions may use these bits to implement new features in which
0, selecting the feature's default state. Detailed descriptions of
SFR Definition 8.1. DPL: Data Pointer Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x82
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
-
66 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 8.2. DPH: Data Pointer High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
SFR Definition 8.3. SP: Stack Pointer
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x83
0x81
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
Rev. 2.6 67
C8051F300/1/2/3/4/5
SFR Definition 8.4. PSW: Program Status Word
R/W R/W R/W R/W R/W R/W R/W R Reset Value
CY AC F0 RS1 RS0 OV F1 PARITY 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
Bit5: F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1 RS0 Register Bank Address
0 0 0 0x00–0x07
0 1 1 0x08–0x0F
1 0 2 0x10–0x17
1 1 3 0x18–0x1F
0xD0
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1: F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
68 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 8.5. ACC: Accumulator
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 8.6. B: B Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
0xE0
0xF0
Rev. 2.6 69
C8051F300/1/2/3/4/5
8.3. Interrupt Handler
The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interruptpending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition,
the associated interrupt-pending flag is set to logic
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic
less of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE1). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic
all interrupt sources regardless of the individual interrupt-enable settings.
Note: Any instruction that clears the EA bit should be immediately followed by an instruction that
has two or more opcode bytes. For example:
1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables
1.
1 regard-
-
// in 'C':
EA = 0; // clear EA bit
EA = 0; // ... followed by another 2-byte opcode
; in assembly:
CLR EA ; clear EA bit
CLR EA ; ... followed by another 2-byte opcode
If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears
the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. How
ever, a read of the EA bit will return a '0' inside the interrupt service routine. When the "CLR EA" opcode is
followed by a multi-cycle instruction, the interrupt will not be taken.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will reenter the ISR after
the completion of the next instruction.
8.3.1. MCU Interrupt Sources and Vectors
The MCUs support 12 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU
will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associ
ated vector addresses, priority order and control bits are summarized in Ta bl e 8.4 on page 72. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
-
-
70 Rev. 2.6
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8.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (
or edge sensitive. The table below lists the possible configurations.
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
1 0 Active low, edge sensitive
1 1 Active high, edge sensitive
0 0 Active low, level sensitive
0 1 Active high, level sensitive
/INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 8.11).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see
“12.1. Priority Crossbar Decoder” on page 100 for complete details on configuring the Crossbar).
Section “15.1. Timer 0 and Timer 1” on page 139) select level
10
11
00
01
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
Section
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre
sponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
8.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in
Tab le 8.4.
8.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18
system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
clock cycles to execute the LCALL to the ISR. If the CPU is
-
-
Rev. 2.6 71
C8051F300/1/2/3/4/5
Table 8.4. Interrupt Summary
Interrupt
Interrupt Source
Reset 0x0000 To p None
External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5)
External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7)
UART0 0x0023 4 RI0 (SCON0.0)
Timer 2 Overflow 0x002B 5 TF2H
SMBus Interface 0x0033 6 SI (SMB0CN.0)
ADC0 Window Compare 0x003B 7 AD0WINT
ADC0 Conversion Complete
Programmable Counter
Array
Comparator0 Falling Edge 0x0053 10 CP0FIF
Comparator0 Rising Edge 0x005B 11 CP0RIF
Vector
0x0043 8 AD0INT
0x004B 9 CF (PCA0CN.7)
Priority
Order
Pending Flag
TI0 (SCON0.1)
(TMR2CN.7)
TF2L
(TMR2CN.6)
(ADC0CN.3)
(ADC0CN.5)
CCFn
(PCA0CN.n)
(CPT0CN.4)
(CPT0CN.5)
Bit addressable?
N/A N/A
YY
YY
YY
YY
YN
YN
YN
YN
YN
YN
NN
NN
Enable
Flag
Cleared by HW?
Always
Enabled
EX0 (IE.0) PX0 (IP.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
ET2 (IE.5) PT2 (IP.5)
ESMB0
(EIE1.0)
EWADC0
(EIE1.1)
EADC0C
(EIE1.2)
EPCA0
(EIE1.3)
ECP0F
(EIE1.4)
ECP0R
(EIE1.5)
Priority
Control
Always
Highest
PSMB0
(EIP1.0)
PWADC0
(EIP1.1)
PADC0C
(EIP1.2)
PPCA0
(EIP1.3)
PCP0F
(EIP1.4)
PCP0R
(EIP1.5)
72 Rev. 2.6
C8051F300/1/2/3/4/5
8.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
SFR Definition 8.7. IE: Interrupt Enable
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6: IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
Bit5: ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4: ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3: ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2: EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Bit1: ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0: EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
0xA8
Rev. 2.6 73
C8051F300/1/2/3/4/5
SFR Definition 8.8. IP: Interrupt Priority
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — PT2 PS0 PT1 PX1 PT0 PX0 11000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bits7–6: UNUSED. Read = 11b, Write = don't care.
Bit5: PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupts set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4: PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupts set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3: PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupts set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2: PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1: PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupts set to low priority level.
1: Timer 0 interrupts set to high priority level.
Bit0: PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
0xB8
74 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — ECP0R ECP0F EPCA0 EADC0C EWADC0 ESMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 Rising Edge interrupt.
0: Disable CP0 Rising Edge interrupt.
1: Enable interrupt requests generated by the CP0RIF flag.
Bit4: ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 Falling Edge interrupt.
0: Disable CP0 Falling Edge interrupt.
1: Enable interrupt requests generated by the CP0FIF flag .
Bit3: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Bit2: EADC0C: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Bit1: EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag.
Bit0: ESMB0: Enable SMBus Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
0xE6
Rev. 2.6 75
C8051F300/1/2/3/4/5
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — PCP0R PCP0F PPCA0 PADC0C PWADC0 PSMB0 11000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–6: UNUSED. Read = 11b. Write = don’t care.
Bit5: PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control.
This bit sets the priority of the CP0 rising-edge interrupt.
0: CP0 rising interrupt set to low priority level.
1: CP0 rising interrupt set to high priority level.
Bit4: PCP0F: Comparator0 (CP0) Falling Interrupt Priority Control.
This bit sets the priority of the CP0 falling-edge interrupt.
0: CP0 falling interrupt set to low priority level.
1: CP0 falling interrupt set to high priority level.
Bit3: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit2: PADC0C ADC0 Conversion Complete Interrupt Priority Control
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bit1: PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit0: PSMB0: SMBus Interrupt Priority Control.
This bit sets the priority of the SMBus interrupt.
0: SMBus interrupt set to low priority level.
1: SMBus interrupt set to high priority level.
0xF6
76 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE4
Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7: IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN1SL2–0 /INT1 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
Bit3: IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN0SL2–0 /INT0 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
Rev. 2.6 77
C8051F300/1/2/3/4/5
8.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter
rupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped (analog
peripherals remain in their selected states). Since clocks are running in Idle mode, power consumption is
dependent upon the system clock frequency and the number of peripherals left in active mode before
entering Idle. Stop mode consumes the least power.
ister (PCON) used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil
lators lowers power consuption considerably; however a reset is required to restart the MCU.
8.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
SFR Definition 8.12 describes the Power Control Reg-
-
-
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This pro
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “16.3. Watchdog Timer
Mode” on page 160 for more information on the use and configuration of the WDT.
Note: Any instruction that sets the IDLE bit should be immediately followed by an instruction that
has 2 or more opcode bytes. For example:
// in 'C':
PCON |= 0x01; // set IDLE bit
PCON = PCON; // ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h ; set IDLE bit
MOV PCON, PCON ; ... followed by a 3-cycle dummy instruction
-
If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from IDLE mode when
a future interrupt occurs.
78 Rev. 2.6
C8051F300/1/2/3/4/5
8.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral
(including the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop
mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal
reset sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
µsec.
SFR Definition 8.12. PCON: Power Control
0x87
Bits7–2: GF5–GF0: General Purpose Flags 5-0.
These are general purpose flags for use under software control.
Bit1: STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (turns off internal oscillator).
Bit0: IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode (shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active).
Rev. 2.6 79
C8051F300/1/2/3/4/5
NOTES:
80 Rev. 2.6
C8051F300/1/2/3/4/5
9. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External Port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the /RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “11. Oscillators” on page 93 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source (
Once the system clock source is stable, program execution begins at location 0x0000.
Section “16.3. Watchdog Timer Mode” on page 160 details the use of the Watchdog Timer).
XTAL1
XTAL2
Internal
Oscillator
External
Oscillator
Drive
P0.x
P0.y
System
Clock
Clock Select
Comparator 0
+
-
Missing
Clock
Detector
(oneshot)
EN
MCD
Enable
Microcontroller
Extended Interrupt
VDD
C0RSEF
CIP-51
Core
Handler
PCA
WDT
EN
WDT
Enable
Supply
Monitor
+
-
System Reset
Enable
Power On
Reset
(Software Reset)
SWRSF
'0'
Illegal
FLASH
Operation
(wired-OR)
Reset
Funnel
/RST
Figure 9.1. Reset Sources
Rev. 2.6 81
C8051F300/1/2/3/4/5
9.1. Power-On Reset
During powerup, the device is held in a reset state and the /RST pin is driven low until VDD settles above
V
. An additional delay occurs before the device is released from reset; the delay decreases as the V
RST
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to V
times (less than 1 ms), the power-on reset delay (T
PORDelay
) is typically less than 0.3 ms.
). For valid ramp
RST
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be
released from reset before V
reaches the VRST level.
DD
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data mem
ory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
DD
-
VDD
t
2.70
2.55
2.0
1.0
Logic HIGH
Logic LOW
volts
V
RST
D
D
V
/RST
T
PORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 9.2. Power-On and VDD Monitor Reset Timing
9.2. Power-Fail Reset / VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below V
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see
to a level above V
, the CIP-51 will be released from the reset state. Note that even though internal data
RST
Figure 9.2). When VDD returns
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
, the power supply
RST
dropped below
DD
DD
82 Rev. 2.6
C8051F300/1/2/3/4/5
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the V
V
monitor will still be enabled after the reset. The VDD monitor is enabled by writing a ‘1’ to the PORSF
DD
bit in register RSTSRC. See
after a VDD monitor reset. See Table 9.2 for electrical characteristics of the VDD monitor.
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the V
V
monitor is enabled does not cause a system reset.
DD
Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
monitor enabled. Writing a logic ‘1’ to the PORSF flag when the
DD
9.3. External Reset
The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pullup and/or decoupling of the
/RST pin may be necessary to avoid erroneous noise-induced resets. See
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the /RST pin is unaffected by this reset.
monitor is enabled and a software reset is performed, the
DD
Ta bl e 9.2 for complete /RST pin
µs, the one-shot will time out and generate a reset. After a
9.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying
Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by
this reset.
9.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in
page 160; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to ‘1’. The state of the /RST pin is unaffected by this reset.
Section “16.3. Watchdog Timer Mode” on
Rev. 2.6 83
C8051F300/1/2/3/4/5
9.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
• A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
• A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
• A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
Table 9.1. User Code Space Address Limits
Device User Code Space Address Limit
C8051F300/1/2/3 0x1DFF
C8051F304 0x0FFF
C8051F305 0x07FF
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the /RST pin is unaffected
by this reset.
9.8. Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the /RST pin is unaffected by this reset.
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
/RST Output Low Voltage IOL = 8.5 mA, VDD = 2.7 V to 3.6 V 0.6 V
/RST Input High Voltage 0.7 x V
/RST Input Low Voltage 0.3 x V
/RST Input Leakage Current /RST = 0.0 V 25 40 µA
VDD Monitor Threshold (V
Missing Clock Detector Timeout Time from last system clock rising
Reset Time Delay Delay between release of any
Minimum /RST Low Time to
Generate a System Reset
VDD Ramp Time VDD = 0 to V
) 2.40 2.55 2.70 V
RST
edge to reset initiation
reset source and code execution
at location 0x0000
RST
DD
100 220 500 µs
5.0 µs
15 µs
— — 1 ms
V
DD
84 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 9.1. RSTSRC: Reset Source
R R R/W R/W R R/W R/W R Reset Value
— FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(Note: Do not use read-modify-write operations (ORL, ANL) on this register)
Bit7: UNUSED. Read = 0. Write = don’t care.
Bit6: FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
Bit5: C0RSEF: Comparator0 Reset Enable and Flag.
Write
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active-low).
Read
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
Bit4: SWRSF: Software Reset Force and Flag.
Write
0: No Effect.
1: Forces a system reset.
Read
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last was a write to the SWRSF bit.
Bit3: WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
Bit2: MCDRSF: Missing Clock Detector Flag.
Write:
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.
Read:
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
Bit1: PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or
a V
monitor reset. In either case, data memory should be considered indeterminate fol-
DD
lowing the reset. Writing this bit enables/disables the V
Write:
monitor disabled.
0: V
DD
1: V
monitor enabled.
DD
Read:
0: Last reset was not a power-on or V
1: Last reset was a power-on or V
Bit0: PINRSF: HW Pin Reset Flag.
0: Source of last reset was not /RST pin.
1: Source of last reset was /RST pin.
monitor reset.
DD
monitor reset; all other reset flags indeterminate.
DD
monitor.
DD
0xEF
Rev. 2.6 85
C8051F300/1/2/3/4/5
NOTES:
86 Rev. 2.6
C8051F300/1/2/3/4/5
10. Flash Memory
On-chip, reprogrammable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft
ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic
1. Flash bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase
operations are automatically timed by hardware for proper execution; data polling to determine the end of
the write/erase operation is not required. Code execution is stalled during a Flash write/erase operation.
Refer to
10.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initial
ized device. For details on the C2 commands to program Flash memory, see Section “17. C2 Interface”
on page 169.
To ensure the integrity of Flash contents, it is strongly recommended that the on-chip VDD Monitor
be enabled in any system that includes code that writes and/or erases Flash memory from soft
ware.
Ta bl e 10.1 for complete Flash memory electrical characteristics.
-
-
-
10.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function; Flash reads by user
software are unrestricted. The Flash Lock and Key Register (FLKEY) must be written with the correct key
codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The tim
ing does not matter, but the codes must be written in order. If the key codes are written out of order, or the
wrong codes are written, Flash writes and erases will be disabled until the next system reset. Flash writes
and erases will also be disabled if a Flash write or erase is attempted before the key codes have been writ
ten properly. The Flash lock resets after each write or erase; the key codes must be written again before a
following Flash operation can be performed. The FLKEY register is detailed in
SFR Definition 10.2.
10.1.2. Flash Erase Procedure
The Flash memory can be programmed by software using the MOVX instruction with the address and data
byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash
write operations must be enabled by: (1) setting the PSWE Program Store Write Enable bit (PSCTL.0) to
logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key codes in
sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software.
A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash.
A byte location to be programmed should be erased before a new value is written. The 8k
memory is organized in 512-byte pages. The erase operation applies to an entire page (setting all bytes in
the page to 0xFF). To erase an entire 512-byte page, perform the following steps:
Step 1. Disable interrupts (recommended).
Step 2. Set the Program Store Erase Enable bit (PSEE in the PSCTL register).
Step 3. Set the Program Store Write Enable bit (PSWE in the PSCTL register).
Step 4. Write the first key code to FLKEY: 0xA5.
Step 5. Write the second key code to FLKEY: 0xF1.
Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to
be erased.
byte Flash
-
-
Rev. 2.6 87
C8051F300/1/2/3/4/5
10.1.3. Flash Write Procedure
Flash bytes are programmed by software with the following sequence:
Step 1. Disable interrupts (recommended).
Step 2. Erase the 512-byte Flash page containing the target location, as described in Section
10.1.2.
Step 3. Set the PSWE bit in PSCTL.
Step 4. Clear the PSEE bit in PSCTL.
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the 512-
byte sector.
Steps 5–7 must be repeated for each byte to be written. After Flash writes are complete, PSWE should be
cleared so that MOVX instructions do not target program memory. Writing to and erasing the Reserved
area of Flash should be avoided.
Table 10.1. Flash Electrical Characteristics
Parameter Conditions Min Typ Max Units
C8051F300/1/2/3 8192* bytes
Flash Size
Endurance 20k 100 k Erase/Write
Erase Cycle Time 25 MHz System Clock 10 15 20 ms
Write Cycle Time 25 MHz System Clock 40 55 70 µs
SYSCLK Frequency (Flash
writes from application code)
*Note: 512 bytes at location 0x1E00 to 0x1FFF are reserved.
C8051F304 4096 bytes
C8051F305 2048 bytes
100 kHz
10.2. Non-Volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
instruction and read using the MOVC instruction.
10.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A security lock byte stored at the last byte of Flash user space protects the Flash program memory from
being read or altered across the C2 interface. See
Figure 10.1 for a program memory map and the security byte locations for each device.
88 Rev. 2.6
Ta bl e 10.2 for the security byte description; see
C8051F300/1/2/3/4/5
Table 10.2. Security Byte Decoding
Bits Description
7–4 Write Lock: Clearing any of these bits to logic 0 prevents all Flash
memory from being written or page-erased across the C2 interface
3–0 Read/Write Lock: Clearing any of these bits to logic 0 prevents all
Flash memory from being read, written, or page-erased across the
C2 interface.
The lock bits can always be read and cleared to logic 0 regardless of the security settings.
Important note: The only means of removing a lock (write or read/write) once set is to erase the
entire program memory space via a C2 Device Erase command.
C8051F300/1/2/3
Reserved
Lock Byte
FLASH memory
organized in 512-byte
pages
0x1E00
0x1DFF
0x1DFE
0x0000
C8051F304
Reserved
Lock Byte
FLASH memory
organized in 512-byte
pages
0x1000
0x0FFF
0x0FFE
0x0000
C8051F305
Reserved
Lock Byte
FLASH memory
organized in 512-byte
pages
0x0800
0x07FF
0x07FE
0x0000
Figure 10.1. Flash Program Memory Map
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages.
Accessing Flash from the C2 debug interface:
1. Any unlocked page may be read, written, or erased.
2. Locked pages cannot be read, written, or erased.
3. The page containing the Lock Byte may be read, written, or erased if it is unlocked.
4. Reading the contents of the Lock Byte is always permitted only if no pages are locked.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) requires the C2 Device Erase command, which erases all Flash pages including the page containing the Lock Byte and the Lock
Byte itself.
7. The Reserved Area cannot be read, written, or erased.
Rev. 2.6 89
C8051F300/1/2/3/4/5
Accessing Flash from user firmware executing from an unlocked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Locked pages cannot be read, written, or erased. An erase attempt on the page containing the
Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may be read or written only if it is
unlocked. An erase attempt on the page containing the Lock Byte will result in a Flash Error device
reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
Accessing Flash from user firmware executing from a locked page:
1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased.
2. Any locked page except the page containing the Lock Byte may be read, written, or erased. An
erase attempt on the page containing the Lock Byte will result in a Flash Error device reset.
3. The page containing the Lock Byte cannot be erased. It may only be read or written. An erase
attempt on the page containing the Lock Byte will result in a Flash Error device reset.
4. Reading the contents of the Lock Byte is always permitted.
5. Locking additional pages (changing ‘1’s to ‘0’s in the Lock Byte) is not permitted.
6. Unlocking Flash pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted.
7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area,
or any other locked page, will result in a Flash Error device reset.
SFR Definition 10.1. PSCTL: Program Store R/W Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— — — — — — PSEE PSWE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–2: UNUSED: Read = 000000b, Write = don’t care.
Bit1: PSEE: Program Store Erase Enable
Setting this bit (in combination with PSWE) allows an entire page of Flash program memory
to be erased. If this bit is logic 1 and Flash writes are enabled (PSWE is logic 1), a write to
Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter.
0: Flash program memory erasure disabled.
1: Flash program memory erasure enabled.
Bit0: PSWE: Program Store Write Enable
Setting this bit allows writing a byte of data to the Flash program memory using the MOVX
instruction. The Flash location should be erased before writing data.
0: Writes to Flash program memory disabled.
1: Writes to Flash program memory enabled; the MOVX instruction targets Flash memory.
0x8F
90 Rev. 2.6
C8051F300/1/2/3/4/5
SFR Definition 10.2. FLKEY: Flash Lock and Key
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: FLKEY: Flash Lock and Key Register
Write:
This register must be written to before Flash writes or erases can be performed. Flash
remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The
timing of the writes does not matter, as long as the codes are written in order. The key codes
must be written for each Flash write or erase operation. Flash will be locked until the next
system reset if the wrong codes are written or if a Flash operation is attempted before the
codes have been written correctly.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
0xB7
SFR Definition 10.3. FLSCL: Flash Scale
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB6
Bits7: FOSE: Flash One-shot Enable
This bit enables the 50 ns Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
Bits6–0: RESERVED. Read = 0. Must Write 0.
Rev. 2.6 91
C8051F300/1/2/3/4/5
NOTES:
92 Rev. 2.6
C8051F300/1/2/3/4/5
11. Oscillators
C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive
circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL reg
isters, as shown in Figure 11.1. The system clock can be sourced by the external oscillator circuit, the
internal oscillator, or a scaled version of the internal oscillator. The internal oscillator's electrical specifications are given in Tab le 11.1 on page 95.
OSCICL OSCICN
-
Option 3
XTAL2
Option 2
VDD
XTAL2
Option 4
Option 1
XTAL2
10M
EN
Programmable
Internal Clock
Generator
XTAL1
Ω
XTAL2
Input
Circuit
XTLVLD
XOSCMD2
XOSCMD1
XOSCMD0
OSCXCN
OSC
XFCN2
XFCN1
XFCN0
IFRDY
CLKSL
IOSCEN
IFCN1
IFCN0
n
SYSCLK
Figure 11.1. Oscillator Diagram
11.1. Programmable Internal Oscillator
All C8051F300/1/2/3/4/5 devices include a programmable internal oscillator that defaults as the system
clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as
defined by
24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may
vary ±20% from device-to-device.
SFR Definition 11.1. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a
Electrical specifications for the precision internal oscillator are given in Table 11.1 on page 95. The programmed internal oscillator frequency must not exceed 25 MHz. Note that the system clock may be
derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg
-
ister OSCICN. The divide value defaults to 8 following a reset.
Rev. 2.6 93
C8051F300/1/2/3/4/5
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
— Variable
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: UNUSED. Read = 0. Write = don’t care.
Bits 6–0: OSCICL: Internal Oscillator Calibration Register.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the
internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
SFR Definition 11.2. OSCICN: Internal Oscillator Control
R/W R/W R/W R R/W R/W R/W R/W Reset Value
— — — IFRDY CLKSL IOSCEN IFCN1 IFCN0 00010100
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xB3
0xB2
Bits7–5: UNUSED. Read = 000b, Write = don't care.
Bit4: IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
Bit3: CLKSL: System Clock Source Select Bit.
0: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits.
1: SYSCLK derived from the External Oscillator circuit.
Bit2: IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.
Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits.
00: SYSCLK derived from Internal Oscillator divided by 8.
01: SYSCLK derived from Internal Oscillator divided by 4.
10: SYSCLK derived from Internal Oscillator divided by 2.
11: SYSCLK derived from Internal Oscillator divided by 1.
94 Rev. 2.6
Table 11.1. Internal Oscillator Electrical Characteristics
–40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
Calibrated Internal Oscillator
Frequency
Uncalibrated Internal Oscillator
Frequency
C8051F300/1/2/3/4/5
C8051F300/1 devices
–40 to +85 °C
C8051F300/1 devices
0 to +70 °C
C8051F302/3/4/5 devices 16 20 24 MHz
24 24.5 25 MHz
24.3 24.7 25 MHz
Internal Oscillator Supply Current
(from V
DD
)
OSCICN.2 = 1 450 µA
11.2. External Oscillator Drive Circuit
The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A
CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys
tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 11.1. A
10 MΩ resistor also must be wired across the XTAL2 and XTAL1 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as
shown in Option 2, 3, or 4 of
register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 11.3).
Important Note on External Oscillator Usage: Port pins must be configured when using the external
oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins
P0.2 and P0.3 are occupied as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is
enabled in capacitor, RC, or CMOS clock mode, Port pin P0.3 is occupied as XTAL2. The Port I/O Cross
bar should be configured to skip the occupied Port pins; see Section “12.1. Priority Crossbar Decoder”
on page 100 for Crossbar configuration. Additionally, when using the external oscillator circuit in crys-
tal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In
CMOS clock mode, the associated pin should be configured as a digital input. See
I/O Initialization” on page 102 for details on Port input mode selection.
Figure 11. 1. The type of external oscillator must be selected in the OSCXCN
Section “12.2. Port
11.3. System Clock Selection
-
-
The CLKSL bit in register OSCICN selects which oscillator is used as the system clock. CLKSL must be
set to ‘1’ for the system clock to run from the external oscillator; however the external oscillator may still
clock peripherals (timers, PCA) when the internal oscillator is selected as the system clock. The system
clock may be switched on-the-fly between the internal and external oscillator, so long as the selected oscil
lator is enabled and has settled. The internal oscillator requires little start-up time and may be enabled and
selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typi
cally require a start-up time before they are settled and ready for use as the system clock. The Crystal
Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To
avoid reading a false XTLVLD, in crystal mode software should delay at least 1
external oscillator and checking XTLVLD. RC and C modes typically require no start-up time.
Rev. 2.6 95
ms between enabling the
-
-
C8051F300/1/2/3/4/5
SFR Definition 11.3. OSCXCN: External Oscillator Control
R R/W R/W R/W R R/W R/W R/W Reset Value
XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 — XFCN2 XFCN1 XFCN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: XTLVLD: Crystal Oscillator Valid Flag.
(Read only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.
Bits6–4: XOSCMD2-0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode.
011: External CMOS Clock Mode with divide by 2 stage.
100: RC Oscillator Mode with divide by 2 stage.
101: Capacitor Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.
Bit3: RESERVED. Read = 0, Write = don't care.
Bits2–0: XFCN2-0: External Oscillator Frequency Control Bits.
000-111: See table below:
0xB1
XFCN Crystal (XOSCMD = 11x) RC (XOSCMD = 10x) C (XOSCMD = 10x)
000 f ≤ 32 kHz f ≤ 25 kHz K Factor = 0.87
001 32 kHz < f ≤ 84 kHz 25 kHz < f ≤ 50 kHz K Factor = 2.6
010 84 kHz < f ≤ 225 kHz 50 kHz < f ≤ 100 kHz K Factor = 7.7
011 225 kHz < f ≤ 590 kHz 100 kHz < f ≤ 200 kHz K Factor = 22
100 590 kHz < f ≤ 1.5 MHz 200 kHz < f ≤ 400 kHz K Factor = 65
101 1.5 MHz < f ≤ 4 MHz 400 kHz < f ≤ 800 kHz K Factor = 180
110 4 MHz < f ≤ 10 MHz 800 kHz < f ≤ 1.6 MHz K Factor = 664
111 1 0 M H z < f ≤ 30 MHz 1.6 MHz < f ≤ 3.2 MHz K Factor = 1590
CRYSTAL MODE (Circuit from Figure 11.1, Option 1; XOSCMD = 11x)
Choose XFCN value to match crystal frequency.
RC MODE (Circuit from Figure 11.1, Option 2; XOSCMD = 10x)
Choose XFCN value to match frequency range:
f = 1.23(10
f = frequency of oscillation in MHz
C = capacitor value in pF
R = Pull-up resistor value in kΩ
C MODE (Circuit from Figure 11.1, Option 3; XOSCMD = 10x)
Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C x V
f = frequency of oscillation in MHz
C = capacitor value the XTAL2 pin in pF
V
= Power Supply on MCU in volts
DD
3
) / (R x C), where
), where
DD
96 Rev. 2.6
C8051F300/1/2/3/4/5
11.4. External Crystal Example
If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be
configured as shown in
should be chosen from the Crystal colum of the table in SFR Definition 11.3 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the oscillator amplitude detection circuit requires a settling time
to achieve proper bias. Introducing a delay of 1
XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the
external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The rec
ommended procedure is:
Step 1. Force the XTAL1 and XTAL2 pins low by writing 0’s to the port latch.
Step 2. Configure XTAL1 and XTAL2 as analog inputs.
Step 3. Enable the external oscillator.
Step 4. Wait at least 1 ms.
Step 5. Poll for XTLVLD => ‘1’.
Step 6. Switch the system clock to the external oscillator.
Note: Tuning-fork crystals may require additional settling time before XTLVLD returns a valid
result.
Figure 11.1, Option 1. The External Oscillator Frequency Control value (XFCN)
ms between enabling the oscillator and checking the
-
The capacitors shown in the external crystal configuration provide the load capacitance required by the
crystal for correct oscillation. These capacitors are “in series” as seen by the crystal and “in parallel” with
the stray capacitance of the XTAL1 and XTAL2 pins.
Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the
crystal datasheet when completing these calculations.
For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should
use the configuration shown in Figure 12.1, Option 1. The total value of the capacitors and the stray capac
itance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors
yield an equivalent capacitance of 12.5
pF across the crystal, as shown in Figure 11.2.
22 pF
XTAL1
32.768 kHz 10 M
22 pF
Ω
XTAL2
Figure 11.2. 32.768 kHz External Crystal Example
-
Rev. 2.6 97
C8051F300/1/2/3/4/5
11.5. External RC Example
If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as
shown in
capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first
select the RC network value to produce the desired frequency of oscillation. If the frequency desired is
100
f = 1.23( 103 ) / RC = 1.23 ( 103 ) / [ 246 x 50 ] = 0.1 MHz = 100 kHz
Referring to the table in SFR Definition 11.3, the required XFCN setting is 010b.
11.6. External Capacitor Example
If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in
Figure 11.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors,
the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the
required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capaci
tor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and
= 150 kHz:
f
Figure 11. 1, Option 2. The capacitor should be no greater than 100 pF; however for very small
kHz, let R = 246 kΩ and C = 50 pF:
-
f = KF / (C x VDD)
0.150 MHz = KF / (C x 3.0)
Since the frequency of roughly 150 kHz is desired, select the K Factor from the table in SFR Definition 11.3
as KF = 22:
0.150 MHz = 22 / (C x 3.0)
C x 3.0 = 22 / 0.150 MHz
C = 146.6 / 3.0 pF = 48.8 pF
Therefore, the XFCN value to use in this example is 011b and C = 50 pF.
98 Rev. 2.6
C8051F300/1/2/3/4/5
12. Port Input/Output
Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins
can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital
resources as shown in
limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the
use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corre
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(
Figure 12.3 and Figure 12.4). The registers XBR0, XBR1, and XBR2, defined in SFR Definition 12.1, SFR
Definition 12.2, and SFR Definition 12.3 are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 12.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port0 Output Mode register (P0MDOUT). Complete Electrical
Specifications for Port I/O are given in
Figure 12.3. The designer has complete control over which functions are assigned,
Table 12.1 on page 106.
-
Highest
Priority
(Internal Digital Signals)
Lowest
Priority
Figure 12.1. Port I/O Functional Block Diagram
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
UART
SMBus
CP0
Outputs
SYSCLK
PCA
T0, T1
XBR0, XBR1,
XBR2 Registers
Priority
2
2
2
4
2
P0Port Latch
(P0.0-P0.7)
Decoder
Digital
Crossbar
8
P0MDOUT,
P0MDIN Registers
P0
8
I/O
Cells
VDD
VDD
(WEAK)
P0.0
P0.7
PORT
PAD
ANALOG INPUT
PORT-INPUT
Analog Select
GND
Figure 12.2. Port I/O Cell Block Diagram
Rev. 2.6 99
C8051F300/1/2/3/4/5
V
s
12.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the XBR0 register are set. The XBR0 register allows software to skip Port pins that are to
be used for analog input or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding XBR0 bit should be set. This applies to P0.0 if VREF is enabled, P0.3 and/or
P0.2 if the external oscillator circuit is enabled, P0.6 if the ADC is configured to use the external conversion
start signal (CNVSTR), and any selected ADC or Comparator inputs. The Crossbar skips selected pins as
if they were already assigned, and moves to the next unassigned pin.
Decoder priority with no Port pins skipped (XBR0 = 0x00); Figure 12.4 shows the Crossbar Decoder priority with pins 6 and 2 skipped (XBR0 = 0x44).
P0
SF Signal
PIN I/O
TX0
RX0
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
REF x1 x2 CNVSTR
01234567
00000000
XBR0[0:7]
Figure 12.3 shows the Crossbar
Signals Unavailable
Port pin potentially available to peripheral
SF Signals
Special Func tion Signals are not ass igned by the c rossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip t heir corresponding port pins.
Note: x1 refers to the XTA L1 signal; x2 refers to the XTAL2
signal.
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00
100 Rev. 2.6
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