Silicon Laboratories C8051F130, C8051F131, C8051F132, C8051F133 User Guide
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
10 or 12-bit SAR ADC
• ± 1 LSB INL
• Programmable throughput up to 100 ksps
• Up to 8 external inputs; programmable as single-
ended or differential
• Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
• Data-dependent windowed interrupt generator
• Built-in temperature sensor
- 8-bit SAR ADC (‘F12x Only)
• Programmable throughput up to 500 ksps
• 8 external inputs (single-ended or differential)
• Programmable amplifier gain: 4, 2, 1, 0.5
- Two 12-bit DACs (‘F12x Only)
• Can synchronize outputs to timers for jitter-free wave-
form generation
- Two Analog Comparators
- V o ltage Reference
- V
Monitor/Brown-Out Detector
DD
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full-speed, nonintrusive in-circuit/in-system debugging
- Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- IEEE1149.1 compliant boundary scan
- Complete development kit
100-Pin TQFP or 64-Pin TQFP Packaging
-
Temperature Range: –40 to +85 °C
- RoHS Available
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instruction set in 1 or 2 system clocks
- 100 MIPS or 50 MIPS throughput with on-chip PLL
- 2-cycle 16 x 16 MAC engine (C8051F120/1/2/3 and
C8051F130/1/2/3 only)
Memory
-
8448 bytes internal data RAM (8 k + 256)
- 128 or 64 kB Banked Fla s h; in-system programma-
ble in 1024-byte sectors
- External 64 kB data memory interface (programma-
ble multiplexed or non-multiplexed modes)
Digital Peripherals
-
8 byte-wide port I/O (100TQFP); 5 V tolerant
- 4 Byte-wide port I/O (64TQFP); 5 V tolerant
- Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
- Programmable 16-bit counter/timer array with
6 capture/compare modules
- 5 general purpose 16-bit counter/timers
- Dedicated watchdog timer; bi-directional reset pin
Clock Sources
-
Internal precision oscillator: 24.5 MHz
- Flexible PLL technology
- External Oscillator: Crystal, RC, C, or clock
Voltage Supples
-
Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS)
- Power saving sleep and shutdown modes
ANALOG PERIPHERALS
VREF
PGA
AMUX
+
-
VOLTAGE
COMPARATORS
PGA
AMUX
C8051F 12x O nly
+
-
8-bit
500ksps
ADC
10/12-bit
100ksps
ADC
TEMP
SENSOR
12-Bit
D AC
12-Bit
D AC
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
CROSSBAR
Port 4
Port 5
E x te rn a l M em ory In te rfa c e
Port 6
Port 7
100 pin64 pin
Port 0
Port 1
Port 2
Port 3
HIG H-SPEED CO NTROLLER C ORE
8051 CPU
(50 or 100MIPS)
20
INTERRUPTS
128/64 kB
ISP FLASH
DEBUG
CIRCUITRY
8448 B
SRAM
CLOCK / PLL
CIRCUIT
16 x 16 M AC
('F 1 2 0 /1 /2 /3 , 'F 1 3 x )
JTA G
Preliminary Rev. 1.4 12/05 Copyright © 2005 by Silicon Laboratories C8051F12x C8051F13x
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
NOTES:
2 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Ta ble of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 27
1.1.1. Fully 8051 Compatible.............................................................................. 27
1.1.2. Improved Throughput............................................................................... 27
1.1.3. Additional Features .................................................................................. 28
1.2. On-Chip Memory............................................................................................... 29
1.3. JTAG Debug and Boundary Scan..................................................................... 30
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine............................................... 31
1.5. Programmable Digital I/O and Crossbar........................................................... 32
1.6. Programmable Counter Array........................................................................... 33
1.7. Serial Ports ....................................................................................................... 33
1.8. 12 or 10-Bit Analog to Digital Converter ........................................................... 34
1.9. 8-Bit Analog to Digital Converter....................................................................... 35
1.10.12-bit Digital to Analog Converters................................................................... 36
1.11.Analog Comparators......................................................................................... 37
2. Absolute Maximum Ratings .................................................................................. 38
3. Global DC Electrical Characteristics.................................................................... 39
4. Pinout and Package Definitions............................................................................ 41
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)........................................................... 55
5.1. Analog Multiplexer and PGA............................................................................. 55
5.2. ADC Modes of Operation.................................................................................. 57
5.2.1. Starting a Conversion............................................................................... 57
5.2.2. Tracking Modes . ....................................................................................... 58
5.2.3. Settling Time Requirements..................................................................... 59
5.3. ADC0 Programmable Window Detector ........................................................... 66
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)................................ 73
6.1. Analog Multiplexer and PGA............................................................................. 73
6.2. ADC Modes of Operation.................................................................................. 75
6.2.1. Starting a Conversion............................................................................... 75
6.2.2. Tracking Modes . ....................................................................................... 76
6.2.3. Settling Time Requirements..................................................................... 77
6.3. ADC0 Programmable Window Detector ........................................................... 84
7. ADC2 (8-Bit ADC, C8051F12x Only)...................................................................... 91
7.1. Analog Multiplexer and PGA............................................................................. 91
7.2. ADC2 Modes of Operation................................................................................ 92
7.2.1. Starting a Conversion............................................................................... 92
7.2.2. Tracking Modes . ....................................................................................... 92
7.2.3. Settling Time Requirements..................................................................... 94
7.3. ADC2 Programmable Window Detector ......................................................... 100
7.3.1. Window Detector In Single-Ended Mode ............................................... 100
7.3.2. Window Detector In Differential Mode.................................................... 101
Rev. 1.4 3
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C8051F130/1/2/3
8. DACs, 12-Bit Voltage Mode (C8051F12x Only).................................................. 105
8.1. DAC Output Scheduling.................................................................................. 105
8.1.1. Update Output On-Demand ................................................................... 106
8.1.2. Update Output Based on Timer Overflow .............................................. 106
8.2. DAC Output Scaling/Justification.................................................................... 106
9. Voltage Reference................................................................................................ 113
9.1. Reference Configuration on the C8051F120/2/4/6......................................... 113
9.2. Reference Configuration on the C8051F121/3/5/7......................................... 115
9.3. Reference Configuration on the C8051F130/1/2/3......................................... 117
10.Comparators ......................................................................................................... 119
11.CIP-51 Microcontroller ......................................................................................... 127
11.1.Instruction Set................................................................................................. 129
11.1.1.Instruction and CPU Timing................................................................... 129
11.1.2.MOVX Instruction and Program Memory............................................... 129
11.2.Memory Organization..................................................................................... 133
11.2.1.Program Memory ................................................................................... 133
11.2.2.Data Memory.......................................................................................... 135
11.2.3.General Purpose Registers.................................................................... 135
11.2.4.Bit Addressable Locations...................................................................... 135
11.2.5.Stack ..................................................................................................... 135
11.2.6.Special Function Registers .................................................................... 136
11.2.7.Register Descriptions............................................................................. 151
11.3.Interrupt Handler............................................................................................. 154
11.3.1.MCU Interrupt Sources and Vectors...................................................... 154
11.3.2.External Interrupts.................................................................................. 155
11.3.3.Interrupt Priorities................................................................................... 156
11.3.4.Interrupt Latency.................................................................................... 156
11.3.5.Interrupt Register Descriptions............................................................... 157
11.4.Power Management Modes............................................................................ 163
11.4.1.Idle Mode ............................................................................................... 163
11.4.2.Stop Mode.............................................................................................. 164
12.Multiply And Accumulate (MAC0)....................................................................... 165
12.1.Special Function Registers............................................................................. 165
12.2.Integer and Fractional Math............................................................................ 166
12.3.Operating in Multiply and Accumulate Mode.................................................. 167
12.4.Operating in Multiply Only Mode .................................................................... 167
12.5.Accumulator Shift Operations......................................................................... 167
12.6.Rounding and Saturation................................................................................ 168
12.7.Usage Examples ............................................................................................ 168
12.7.1.Multiply and Accumulate Example......................................................... 168
12.7.2.Multiply Only Example............................................................................ 169
12.7.3.MAC0 Accumulator Shift Example......................................................... 169
4 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.Reset Sources....................................................................................................... 177
13.1.Power-on Reset.............................................................................................. 178
13.2.Power-fail Reset............................................................................................. 178
13.3.External Reset................................................................................................ 179
13.4.Missing Clock Detector Reset ........................................................................ 179
13.5.Comparator0 Reset........................................................................................ 179
13.6.External CNVSTR0 Pin Reset........................................................................ 179
13.7.Watchdog Timer Reset................................................................................... 179
13.7.1.Enable/Reset WDT ................................................................................ 180
13.7.2.Disable WDT.......................................................................................... 180
13.7.3.Disable WDT Lockout ............................................................................ 180
13.7.4.Setting WDT Interval.............................................................................. 180
14.Oscillators............................................................................................................. 185
14.1.Internal Calibrated Oscillator.......................................................................... 185
14.2.External Oscillator Drive Circuit...................................................................... 187
14.3.System Clock Selection.................................................................................. 187
14.4.External Crystal Example............................................................................... 190
14.5.External RC Example..................................................................................... 190
14.6.External Capacitor Example........................................................................... 190
14.7.Phase-Locked Loop (PLL).............................................................................. 191
14.7.1.PLL Input Clock and Pre-divider ............................................................ 191
14.7.2.PLL Multiplication and Output Clock...................................................... 191
14.7.3.Powering on and Initializing the PLL...................................................... 192
15.Flash Memory ....................................................................................................... 199
15.1.Programming the Flash Memory.................................................................... 199
15.1.1.Non-volatile Data Storage...................................................................... 200
15.1.2.Erasing Flash Pages From Software ..................................................... 201
15.1.3.Writing Flash Memory From Software.................................................... 202
15.2.Security Options............................................................................................. 203
15.2.1.Summary of Flash Security Options....................................................... 207
16.Branch Target Cache ........................................................................................... 211
16.1.Cache and Prefetch Operation....................................................................... 211
16.2.Cache and Prefetch Optimization................................................................... 212
17.External Data Memory Interface and On-Chip XRAM........................................ 219
17.1.Accessing XRAM............................................................................................ 219
17.1.1.16-Bit MOVX Example........................................................................... 219
17.1.2.8-Bit MOVX Example............................................................................. 219
17.2.Configuring the External Memory Interface.................................................... 219
17.3.Port Selection and Configuration.................................................................... 220
17.4.Multiplexed and Non-multiplexed Selection.................................................... 222
17.4.1.Multiplexed Configuration....................................................................... 222
17.4.2.Non-multiplexed Configuration............................................................... 223
17.5.Memory Mode Selection................................................................................. 224
17.5.1.Internal XRAM Only ............................................................................... 224
17.5.2.Split Mode without Bank Select.............................................................. 224
Rev. 1.4 5
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
17.5.3.Split Mode with Bank Select................................................................... 225
17.5.4.External Only.......................................................................................... 225
17.6.EMIF Timing................................................................................................... 225
17.6.1.Non-multiplexed Mode........................................................................... 227
17.6.2.Multiplexed Mode................................................................................... 230
18.Port Input/Output.................................................................................................. 235
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 238
18.1.1.Crossbar Pin Assignment and Allocation............................................... 238
18.1.2.Configuring the Output Modes of the Port Pins...................................... 239
18.1.3.Configuring Port Pins as Digital Inputs................................................... 240
18.1.4.Weak Pullups.........................................................................................240
18.1.5.Configuring Port 1 Pins as Analog Inputs .............................................. 240
18.1.6.External Memory Interface Pin Assignments......................................... 241
18.1.7.Crossbar Pin Assignment Example........................................................ 243
18.2.Ports 4 through 7 (100-pin TQFP devices only)............................................. 252
18.2.1.Configuring Ports which are not Pinned Out.......................................... 252
18.2.2.Configuring the Output Modes of the Port Pins...................................... 252
18.2.3.Configuring Port Pins as Digital Inputs................................................... 253
18.2.4.Weak Pullups.........................................................................................253
18.2.5.External Memory Interface..................................................................... 253
19.System Management Bus / I2C Bus (SMBus0).................................................. 259
19.1.Supporting Documents................................................................................... 260
19.2.SMBus Protocol.............................................................................................. 260
19.2.1.Arbitration............................................................................................... 261
19.2.2.Clock Low Extension.............................................................................. 261
19.2.3.SCL Low Timeout................................................................................... 261
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 261
19.3.SMBus Transfer Modes.................................................................................. 262
19.3.1.Master Transmitter Mode....................................................................... 262
19.3.2.Master Receiver Mode........................................................................... 262
19.3.3.Slave Transmitter Mode......................................................................... 263
19.3.4.Slave Receiver Mode............................................................................. 263
19.4.SMBus Special Function Registers................................................................ 264
19.4.1.Control Register..................................................................................... 264
19.4.2.Clock Rate Register............................................................................... 267
19.4.3.Data Register......................................................................................... 268
19.4.4.Address Register.................................................................................... 268
19.4.5.Status Register....................................................................................... 269
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 273
20.1.Signal Descriptions......................................................................................... 274
20.1.1.Master Out, Slave In (MOSI).................................................................. 274
20.1.2.Master In, Slave Out (MISO).................................................................. 274
20.1.3.Serial Clock (SCK)................................................................................. 274
20.1.4.Slave Select (NSS) ................................................................................ 274
6 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
20.2.SPI0 Master Mode Operation......................................................................... 275
20.3.SPI0 Slave Mode Operation........................................................................... 277
20.4.SPI0 Interrupt Sources................................................................................... 277
20.5.Serial Clock Timing......................................................................................... 278
20.6.SPI Special Function Registers...................................................................... 280
21.UART0.................................................................................................................... 287
21.1.UART0 Operational Modes ............................................................................ 288
21.1.1.Mode 0: Synchronous Mode.................................................................. 288
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 289
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate.................................................. 291
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 292
21.2.Multiprocessor Communications .................................................................... 293
21.2.1.Configuration of a Masked Address....................................................... 293
21.2.2.Broadcast Addressing............................................................................ 293
21.3.Frame and Transmission Error Detection....................................................... 294
22.UART1.................................................................................................................... 299
22.1.Enhanced Baud Rate Generation................................................................... 300
22.2.Operational Modes......................................................................................... 301
22.2.1.8-Bit UART............................................................................................. 301
22.2.2.9-Bit UART............................................................................................. 302
22.3.Multiprocessor Communications .................................................................... 303
23.Timers.................................................................................................................... 309
23.1.Timer 0 and Timer 1....................................................................................... 309
23.1.1.Mode 0: 13-bit Counter/Timer................................................................ 309
23.1.2.Mode 1: 16-bit Counter/Timer................................................................ 311
23.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 311
23.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 312
23.2.Timer 2, Timer 3, and Timer 4........................................................................ 317
23.2.1.Configuring Timer 2, 3, and 4 to Count Down........................................ 317
23.2.2.Capture Mode ........................................................................................ 318
23.2.3.Auto-Reload Mode................................................................................. 319
23.2.4.Toggle Output Mode (Timer 2 and Timer 4 Only).................................. 320
24.Programmable Counter Array ............................................................................. 325
24.1.PCA Counter/Timer........................................................................................ 326
24.2.Capture/Compare Modules ............................................................................ 328
24.2.1.Edge-triggered Capture Mode................................................................ 329
24.2.2.Software Timer (Compare) Mode........................................................... 330
24.2.3.High Speed Output Mode....................................................................... 331
24.2.4.Frequency Output Mode ........................................................................ 332
24.2.5.8-Bit Pulse Width Modulator Mode......................................................... 333
24.2.6.16-Bit Pulse Width Modulator Mode....................................................... 334
24.3.Register Descriptions for PCA0...................................................................... 335
Rev. 1.4 7
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
25.JTAG (IEEE 1149.1) .............................................................................................. 341
25.1.Boundary Scan............................................................................................... 342
25.1.1.EXTEST Instruction................................................................................ 343
25.1.2.SAMPLE Instruction............................................................................... 343
25.1.3.BYPASS Instruction............................................................................... 343
25.1.4.IDCODE Instruction................................................................................ 343
25.2.Flash Programming Commands..................................................................... 344
25.3.Debug Support ............................................................................................... 347
Document Change List............................................................................................. 349
Contact Information.................................................................................................. 350
8 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
List of Figures
1. System Overview
Figure 1.1. C8051F120/124 Block Diagram............................................................. 21
Figure 1.2. C8051F121/125 Block Diagram............................................................. 22
Figure 1.3. C8051F122/126 Block Diagram............................................................. 23
Figure 1.4. C8051F123/127 Block Diagram............................................................. 24
Figure 1.5. C8051F130/132 Block Diagram............................................................. 25
Figure 1.6. C8051F131/133 Block Diagram............................................................. 26
Figure 1.7. On-Board Clock and Reset.................................................................... 28
Figure 1.8. On-Chip Memory Map............................................................................ 29
Figure 1.9. Development/In-System Debug Diagram............................................... 30
Figure 1.10. MAC0 Block Diagram........................................................................... 31
Figure 1.11. Digital Crossbar Diagram..................................................................... 32
Figure 1.12. PCA Block Diagram.............................................................................. 33
Figure 1.13. 12-Bit ADC Block Diagram................................................................... 34
Figure 1.14. 8-Bit ADC Diagram............................................................................... 35
Figure 1.15. DAC System Block Diagram ................................................................ 36
Figure 1.16. Comparator Block Diagram.................................................................. 37
2. Absolute Maximum Ratings
3. Global DC Electrical Characteristics
4. Pinout and Package Definitions
Figure 4.1. C8051F120/2/4/6 Pinout Diagram (TQFP-100) ..................................... 49
Figure 4.2. C8051F130/2 Pinout Diagram (TQFP-100) ........................................... 50
Figure 4.3. TQFP-100 Package Drawing................................................................. 51
Figure 4.4. C8051F121/3/5/7 Pinout Diagram (TQFP-64) ....................................... 52
Figure 4.5. C8051F131/3 Pinout Diagram (TQFP-64) ............................................. 53
Figure 4.6. TQFP-64 Package Drawing................................................................... 54
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)
Figure 5.1. 12-Bit ADC0 Functional Block Diagram................................................. 55
Figure 5.2. Typical Temperature Sensor Transfer Function..................................... 56
Figure 5.3. ADC0 Track and Conversion Example Timing....................................... 58
Figure 5.4. ADC0 Equivalent Input Circuits.............................................................. 59
Figure 5.5. ADC0 Data Word Example .................................................................... 65
Figure 5.6. 12-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data......................................................... 68
Figure 5.7. 12-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data ............................................................. 69
Figure 5.8. 12-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data ........................................................... 70
Figure 5.9. 12-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data................................................................ 71
Rev. 1.4 9
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)
Figure 6.1. 10-Bit ADC0 Functional Block Diagram................................................. 73
Figure 6.2. Typical Temperature Sensor Transfer Function..................................... 74
Figure 6.3. ADC0 Track and Conversion Example Timing....................................... 76
Figure 6.4. ADC0 Equivalent Input Circuits.............................................................. 77
Figure 6.5. ADC0 Data Word Example .................................................................... 83
Figure 6.6. 10-Bit ADC0 Window Interrupt Example:
Right Justified Single-Ended Data......................................................... 86
Figure 6.7. 10-Bit ADC0 Window Interrupt Example:
Right Justified Differential Data ............................................................. 87
Figure 6.8. 10-Bit ADC0 Window Interrupt Example:
Left Justified Single-Ended Data ........................................................... 88
Figure 6.9. 10-Bit ADC0 Window Interrupt Example:
Left Justified Differential Data................................................................ 89
7. ADC2 (8-Bit ADC, C8051F12x Only)
Figure 7.1. ADC2 Functional Block Diagram............................................................ 91
Figure 7.2. ADC2 Track and Conversion Example Timing....................................... 93
Figure 7.3. ADC2 Equivalent Input Circuit................................................................ 94
Figure 7.4. ADC2 Data Word Example .................................................................... 99
Figure 7.5. ADC2 Window Compare Examples, Single-Ended Mode.................... 100
Figure 7.6. ADC2 Window Compare Examples, Differential Mode........................ 101
8. DACs, 12-Bit Voltage Mode (C8051F12x Only)
Figure 8.1. DAC Functional Block Diagram............................................................ 105
9. Voltage Reference
Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6) ...... 114
Figure 9.2. Voltage Reference Functional Block Diagram (C8051F121/3/5/7) ...... 115
Figure 9.3. Voltage Reference Functional Block Diagram (C8051F130/1/2/3) ...... 117
10.Comparators
Figure 10.1. Comparator Functional Block Diagram.............................................. 119
Figure 10.2. Comparator Hysteresis Plot ............................................................... 121
11.CIP-51 Microcontroller
Figure 11.1. CIP-51 Block Diagram....................................................................... 128
Figure 11.2. Memory Map ...................................................................................... 133
Figure 11.3. Address Memory Map for Instruction Fetches (128 kB Flash Only)... 134
Figure 11.4. SFR Page Stack................................................................................. 137
Figure 11.5. SFR Page Stack While Using SFR Page 0x0F To Access Port 5...... 138
Figure 11.6. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs. 139
Figure 11.7. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR140
Figure 11.8. SFR Page Stack Upon Return From PCA Interrupt........................... 140
Figure 11.9. SFR Page Stack Upon Return From ADC2 Window Interrupt........... 141
12.Multiply And Accumulate (MAC0)
Figure 12.1. MAC0 Block Diagram......................................................................... 165
Figure 12.2. Integer Mode Data Representation.................................................... 166
Figure 12.3. Fractional Mode Data Representation................................................ 166
Figure 12.4. MAC0 Pipeline.................................................................................... 167
10 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
13.Reset Sources
Figure 13.1. Reset Sources.................................................................................... 177
Figure 13.2. Reset Timing ...................................................................................... 178
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 185
Figure 14.2. PLL Block Diagram............................................................................. 191
15.Flash Memory
Figure 15.1. Flash Memory Map for MOVC Read and MOVX Write Operations ... 201
Figure 15.2. 128 kB Flash Memory Map and Security Bytes ................................. 204
Figure 15.3. 64 kB Flash Memory Map and Security Bytes ................................... 205
16.Branch Target Cache
Figure 16.1. Branch Target Cache Data Flow........................................................ 211
Figure 16.2. Branch Target Cache Organiztion...................................................... 212
Figure 16.3. Cache Lock Operation........................................................................ 214
17.External Data Memory Interface and On-Chip XRAM
Figure 17.1. Multiplexed Configuration Example.................................................... 222
Figure 17.2. Non-multiplexed Configuration Example............................................ 223
Figure 17.3. EMIF Operating Modes...................................................................... 224
Figure 17.4. Non-multiplexed 16-bit MOVX Timing................................................ 227
Figure 17.5. Non-multiplexed 8-bi t MOVX without Bank Select Timing ................. 228
Figure 17.6. Non-multiplexed 8-bi t MOVX with Bank Select Timing ...................... 229
Figure 17.7. Multiplexed 16-bit MOVX Timing........................................................ 230
Figure 17.8. Multiplexed 8-bit MOVX without Bank Select Timing......................... 231
Figure 17.9. Multiplexed 8-bit MOVX with Bank Select Timing.............................. 232
18.Port Input/Output
Figure 18.1. Port I/O Cell Block Diagram ............................................................... 235
Figure 18.2. Port I/O Functional Block Diagram..................................................... 237
Figure 18.3. Priority Crossbar Decode Table (EMIFLE = 0; P1MDIN = 0xFF)....... 238
Figure 18.4. Priority Crossbar Decode Table
(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF)................ 241
Figure 18.5. Priority Crossbar Decode Table
(EMIFLE = 1; EMIF in Non-Multiplexed Mode; P1MDIN = 0xFF)........ 242
Figure 18.6. Crossbar Example.............................................................................. 244
19.System Management Bus / I2C Bus (SMBus0)
Figure 19.1. SMBus0 Block Diagram..................................................................... 259
Figure 19.2. Typical SMBus Configuration............................................................. 260
Figure 19.3. SMBus Transaction............................................................................ 261
Figure 19.4. Typical Master Transmitter Sequence................................................ 262
Figure 19.5. Typical Master Receiver Sequence.................................................... 262
Figure 19.6. Typical Slave Transmitter Sequence.................................................. 263
Figure 19.7. Typical Slave Receiver Sequence...................................................... 263
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram............................................................................. 273
Figure 20.2. Multiple-Master Mode Connection Diagram....................................... 276
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 276
Rev. 1.4 11
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram............. 276
Figure 20.5. Master Mode Data/Clock Timing........................................................ 278
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 279
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 279
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 283
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 283
Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 284
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 284
21.UART0
Figure 21.1. UART0 Block Diagram ....................................................................... 287
Figure 21.2. UART0 Mode 0 Timing Diagram........................................................ 288
Figure 21.3. UART0 Mode 0 Interconnect.............................................................. 288
Figure 21.4. UART0 Mode 1 Timing Diagram....................................................... 289
Figure 21.5. UART0 Modes 2 and 3 Timing Diagram............................................ 291
Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram.............................. 292
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram.......................... 294
22.UART1
Figure 22.1. UART1 Block Diagram ....................................................................... 299
Figure 22.2. UART1 Baud Rate Logic.................................................................... 300
Figure 22.3. UART Interconnect Diagram.............................................................. 301
Figure 22.4. 8-Bit UART Timing Diagram.............................................................. 301
Figure 22.5. 9-Bit UART Timing Diagr am............................................................... 302
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram.......................... 303
23.Timers
Figure 23.1. T0 Mode 0 Block Diagram.................................................................. 310
Figure 23.2. T0 Mode 2 Block Diagram.................................................................. 311
Figure 23.3. T0 Mode 3 Block Diagram.................................................................. 312
Figure 23.4. T2, 3, and 4 Capture Mode Block Diagram........................................ 318
Figure 23.5. Tn Auto-reload (T2,3,4) and Toggle Mode (T2,4) Block Diagram..... 319
24.Programmable Counter Array
Figure 24.1. PCA Block Diagram............................................................................ 325
Figure 24.2. PCA Counter/Timer Block Diagram.................................................... 326
Figure 24.3. PCA Interrupt Block Diagram............................................................. 328
Figure 24.4. PCA Capture Mode Diagram.............................................................. 329
Figure 24.5. PCA Software Timer Mode Diagram.................................................. 330
Figure 24.6. PCA High Speed Output Mode Diagram............................................ 331
Figure 24.7. PCA Frequency Output Mode............................................................ 332
Figure 24.8. PCA 8-Bit PWM Mode Diagram......................................................... 333
Figure 24.9. PCA 16-Bit PWM Mode...................................................................... 334
25.JTAG (IEEE 1149.1)
12 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
List Of Ta bles
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 20
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings .................................................................... 38
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
(C8051F120/1/2/3 and C8051F130/1/2/3) ............................................. 39
Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) ....................... 40
4. Pinout and Package Definitions
Table 4.1. Pin Definitions ......................................................................................... 41
5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only)
Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/5) .................... 72
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)
Table 6.1. 10-Bit ADC0 Elec trical Characteristics
(C8051F122/3/6/7 and C8051F13x) ...................................................... 90
7. ADC2 (8-Bit ADC, C8051F12x Only)
Table 7.1. ADC2 Electrical Characteristics ............................................................ 103
8. DACs, 12-Bit Voltage Mode (C8051F12x Only)
Table 8.1. DAC Electrical Characteristics .............................................................. 111
9. Voltage Reference
Table 9.1. Voltage Reference Electrical Characteristics ....................................... 118
10.Comparators
Table 10.1. Comparator Electrical Characteristics ................................................ 126
11.CIP-51 Microcontroller
Table 11.1. CIP-51 Instruction Set Summary ........................................................ 129
Table 11.2. Special Function Register (SFR) Memory Map .................................. 144
Table 11.3. Special Function Registers ................................................................. 146
Table 11.4. Interrupt Summary .............................................................................. 155
12.Multiply And Accumulate (MAC0)
Table 12.1. MAC0 Rounding (MAC0SAT = 0) ....................................................... 168
13.Reset Sources
Table 13.1. Reset Electrical Characteristics .......................................................... 183
14.Oscillators
Table 14.1. Oscillator Electrical Characteristics .................................................... 185
Table 14.2. PLL Frequency Characteristics .......................................................... 195
Table 14.3. PLL Lock Timing Characteristics ........................................................ 196
15.Flash Memory
Table 15.1. Flash Electrical Characteristics .......................................................... 200
16.Branch Target Cache
17.External Data Memory Interface and On-Chip XRAM
Table 17.1. AC Parameters for External Memory Interface ................................... 233
Rev. 1.4 13
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
18.Port Input/Output
Table 18.1. Port I/O DC Electrical Characteristics ................................................. 236
19.System Management Bus / I2C Bus (SMBus0)
Table 19.1. SMB0STA Status Codes and States .................................................. 270
20.Enhanced Serial Peripheral Interface (SPI0)
Table 20.1. SPI Slave Timing Parameters ............................................................ 285
21.UART0
Table 21.1. UART0 Modes .................................................................................... 288
Table 21.2. Oscillator Frequencies for Standard Baud Rates ............................... 295
22.UART1
Table 22.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator ............................................... 305
Table 22.2. Timer Settings for Standard Baud Rates
Using an External 25.0 MHz Oscillator ................................................ 306
Table 22.3. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator .......................................... 306
Table 22.4. Timer Settings for Standard Baud Rates Using the PLL .................... 307
Table 22.5. Timer Settings for Standard Baud Rates Using the PLL .................... 307
23.Timers
24.Programmable Counter Array
Table 24.1. PCA Timebase Input Options ............................................................. 326
Table 24.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 329
25.JTAG (IEEE 1149.1)
Table 25.1. Boundary Data Register Bit Definitions .............................................. 342
14 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
List of Registers
SFR Definition 5.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SFR Definition 5.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . 61
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 5.4. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 5.5. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 5.6. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 66
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 66
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 67
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 67
SFR Definition 6.1. AMX0CF: AMUX0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SFR Definition 6.2. AMX0SL: AMUX0 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 6.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SFR Definition 6.4. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 6.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 84
SFR Definition 6.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 84
SFR Definition 6.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 85
SFR Definition 6.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 85
SFR Definition 7.1. AMX2CF: AMUX2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 7.2. AMX2SL: AMUX2 Channel Select . . . . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 7.3. ADC2CF: ADC2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 7.4. ADC2CN: ADC2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 7.5. ADC2: ADC2 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data Byte . . . . . . . . . . . . . . . . . . 102
SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data Byte . . . . . . . . . . . . . . . . . . . . 102
SFR Definition 8.1. DAC0H: DAC0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.2. DAC0L: DAC0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 8.3. DAC0CN: DAC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 8.4. DAC1H: DAC1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.5. DAC1L: DAC1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 8.6. DAC1CN: DAC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 9.1. REF0CN: Reference Control (C8051F120/2/4/6) . . . . . . . . . . . . 114
SFR Definition 9.2. REF0CN: Reference Control (C8051F121/3/5/7) . . . . . . . . . . . . 116
SFR Definition 9.3. REF0CN: Reference Control (C8051F130/1/2/3) . . . . . . . . . . . . 117
SFR Definition 10.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 10.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . 123
SFR Definition 10.3. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . 124
SFR Definition 10.4. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . 125
SFR Definition 11.1. PSBANK: Program Space Bank Select . . . . . . . . . . . . . . . . . . 134
SFR Definition 11.2. SFRPGCN: SFR Page Control . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 11.3. SFRPAGE: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Rev. 1.4 15
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 11.4. SFRNEXT: SFR Next Register . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 11.5. SFRLAST: SFR Last Register . . . . . . . . . . . . . . . . . . . . . . . . . 143
SFR Definition 11.6. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 11.7. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 11.8. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 11.9. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 11.10. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 11.11. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 11.12. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 11.13. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 11.14. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 11.15. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 11.16. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 11.17. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . 162
SFR Definition 11.18. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SFR Definition 12.1. MAC0CF: MAC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 170
SFR Definition 12.2. MAC0STA: MAC0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 12.3. MAC0AH: MAC0 A High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 171
SFR Definition 12.4. MAC0AL: MAC0 A Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 12.5. MAC0BH: MAC0 B High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 12.6. MAC0BL: MAC0 B Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
SFR Definition 12.7. MAC0ACC3: MAC0 Accumulator Byte 3 . . . . . . . . . . . . . . . . . . 173
SFR Definition 12.8. MAC0ACC2: MAC0 Accumulator Byte 2 . . . . . . . . . . . . . . . . . 173
SFR Definition 12.9. MAC0ACC1: MAC0 Accumulator Byte 1 . . . . . . . . . . . . . . . . . 173
SFR Definition 12.10. MAC0ACC0: MAC0 Accumulator Byte 0 . . . . . . . . . . . . . . . . . 174
SFR Definition 12.11. MAC0OVR: MAC0 Accumulator Overflow . . . . . . . . . . . . . . . . 174
SFR Definition 12.12. MAC0RNDH: MAC0 Rounding Register High Byte . . . . . . . . . 174
SFR Definition 12.13. MAC0RNDL: MAC0 Rounding Register Low Byte . . . . . . . . . 175
SFR Definition 13.1. WDTCN: Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . 181
SFR Definition 13.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SFR Definition 14.1. OSCICL: Internal Oscillator Calibration. . . . . . . . . . . . . . . . . . . 186
SFR Definition 14.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 186
SFR Definition 14.3. CLKSEL: System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . 188
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 189
SFR Definition 14.5. PLL0CN: PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
SFR Definition 14.6. PLL0DIV: PLL Pre-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 14.7. PLL0MUL: PLL Clock Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
SFR Definition 14.8. PLL0FLT: PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
SFR Definition 15.1. FLACL: Flash Access Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
SFR Definition 15.2. FLSCL: Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . 208
SFR Definition 15.3. PSCTL: Program Store Read/Write Control . . . . . . . . . . . . . . . 209
SFR Definition 16.1. CCH0CN: Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
SFR Definition 16.2. CCH0TN: Cache Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 16.3. CCH0LC: Cache Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 16.4. CCH0MA: Cache Miss Accumulator . . . . . . . . . . . . . . . . . . . . . 217
16 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 16.5. FLSTAT: Flash Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
SFR Definition 17.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 220
SFR Definition 17.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 221
SFR Definition 17.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 226
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 245
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 246
SFR Definition 18.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 247
SFR Definition 18.4. P0: Port0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 18.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 18.6. P1: Port1 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 18.7. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 18.8. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 18.9. P2: Port2 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 18.10. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 251
SFR Definition 18.11. P3: Port3 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
SFR Definition 18.12. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 252
SFR Definition 18.13. P4: Port4 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
SFR Definition 18.14. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 254
SFR Definition 18.15. P5: Port5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
SFR Definition 18.16. P5MDOUT: Port5 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 255
SFR Definition 18.17. P6: Port6 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 18.18. P6MDOUT: Port6 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 18.19. P7: Port7 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
SFR Definition 18.20. P7MDOUT: Port7 Output Mode . . . . . . . . . . . . . . . . . . . . . . . 257
SFR Definition 19.1. SMB0CN: SMBus0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SFR Definition 19.2. SMB0CR: SMBus0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . 267
SFR Definition 19.3. SMB0DAT: SMBus0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
SFR Definition 19.4. SMB0ADR: SMBus0 Address . . . . . . . . . . . . . . . . . . . . . . . . . . 269
SFR Definition 19.5. SMB0STA: SMBus0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 280
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
SFR Definition 21.1. SCON0: UART0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
SFR Definition 21.2. SSTA0: UART0 Status and Clock Selection . . . . . . . . . . . . . . . 297
SFR Definition 21.3. SBUF0: UART0 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
SFR Definition 21.4. SADDR0: UART0 Slave Address . . . . . . . . . . . . . . . . . . . . . . . 298
SFR Definition 21.5. SADEN0: UART0 Slave Address Enable . . . . . . . . . . . . . . . . . 298
SFR Definition 22.1. SCON1: Serial Port 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 304
SFR Definition 22.2. SBUF1: Serial (UART1) Port Data Buffer . . . . . . . . . . . . . . . . . 305
SFR Definition 23.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
SFR Definition 23.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
SFR Definition 23.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
SFR Definition 23.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
SFR Definition 23.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Rev. 1.4 17
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 23.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
SFR Definition 23.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
SFR Definition 23.8. TMRnCN: Timer 2, 3, and 4 Control . . . . . . . . . . . . . . . . . . . . . 321
SFR Definition 23.9. TMRnCF: Timer 2, 3, and 4 Configuration . . . . . . . . . . . . . . . . 322
SFR Definition 23.10. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte . . . . . 323
SFR Definition 23.11. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte . . . . 323
SFR Definition 23.12. TMRnL: Timer 2, 3, and 4 Low Byte . . . . . . . . . . . . . . . . . . . . 323
SFR Definition 23.13. TMRnH Timer 2, 3, and 4 High Byte . . . . . . . . . . . . . . . . . . . 324
SFR Definition 24.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
SFR Definition 24.2. PCA0MD: PCA0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
SFR Definition 24.3. PCA0CPMn: PCA0 Capture/Compare Mode . . . . . . . . . . . . . . 337
SFR Definition 24.4. PCA0L: PCA0 Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . 338
SFR Definition 24.5. PCA0H: PCA0 Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 338
SFR Definition 24.6. PCA0CPLn: PCA0 Capture Module Low Byte . . . . . . . . . . . . . . 338
SFR Definition 24.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . 339
JTAG Register Definition 25.1. IR: JTAG Instruction Register . . . . . . . . . . . . . . . . . . 341
JTAG Register Definition 25.2. DEVICEID: JTAG Device ID . . . . . . . . . . . . . . . . . . . 343
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control . . . . . . . . . . . . . . . 345
JTAG Register Definition 25.4. FLASHDAT: JTAG Flash Data . . . . . . . . . . . . . . . . . 346
JTAG Register Definition 25.5. FLASHADR: JTAG Flash Address . . . . . . . . . . . . . . 346
18 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1. System Overview
The C8051F12x and C8051F13x device families are fully integrated mixed-signal System-on-a-Chip
MCUs with 64 digital I/O pins (100-pin TQFP) or 32 digital I/O pins (64-pin TQFP).
Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (100 MIPS or 50 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12 or 10-bit 100 ksps ADC with PGA and 8-channel analog multiplexer
• True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer (C8051F12x Family)
• Two 12-bit DACs with programmable update scheduling (C8051F12x Family)
• 2-cycle 16 by 16 Multiply and Accumulate Engine (C8051F120/1/2/3 and C8051F130/1/2/3)
• 128 or 64 kB of in-system programmable Flash memory
• 8448 (8 k + 256) bytes of on-chip RAM
• External Data Memory Interface with 64 kB address space
• SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with 6 capture/compare modules
• On-chip Watchdog Timer, V
Monitor, and Temperature Sensor
DD
With on-chip V
are truly stand-alone System-on-a-Ch ip solutions. All analog and digital peripherals are enabled/disabled
and configured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing nonvolatile data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and
halt commands. All analog and digital peripherals are fully functional while debugging using JTAG.
Each MCU is specified for operation over the industrial temperature range (–45 to +85 °C). The Port I/O,
RST
, and JTAG pins are tolerant for input signals up to 5 V. The devices are available in 100-pin TQFP or
64-pin TQFP packaging. Table 1.1 lists the specific device features and package offerings for each part
number. Figure 1.1 through Figure 1.6 show functional block diagrams for each device.
monitor, Watchdog Timer, and clock oscillator, the C8051F12x and C8051F13x devices
DD
Rev. 1.4 19
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 1.1. Product Selection Guide
Ordering Part Number
C8051F120 100 128 k 8448
C8051F120-GQ 100 128 k 8448
C8051F121 100 128 k 8448
C8051F121-GQ 100 128 k 8448
C8051F122 100 128 k 8448
C8051F122-GQ 100 128 k 8448
C8051F123 100 128 k 8448
C8051F123-GQ 100 128 k 8448
C8051F124 50 128 k 8448 C8051F124-GQ 50 128 k 8448 C8051F125 50 128 k 8448 C8051F125-GQ 50 128 k 8448 C8051F126 50 128 k 8448 C8051F126-GQ 50 128 k 8448 C8051F127 50 128 k 8448 C8051F127-GQ 50 128 k 8448 C8051F130 100 128 k 8448
C8051F130-GQ 100 128 k 8448
C8051F131 100 128 k 8448
C8051F131-GQ 100 128 k 8448
C8051F132 100 64 k 8448
C8051F132-GQ 100 64 k 8448
C8051F133 100 64 k 8448
C8051F133-GQ 100 64 k 8448
MIPS (Peak)
Flash Memory
RAM
2-cycle 16 by 16 MAC
External Memory Interface
SMBus/I2C
SPI
UARTS
3333
3333
3333
3333
3333
3333
3333
3333
333
333
333
333
333
333
333
333
3333
3333
3333
3333
3333
3333
3333
3333
25364 8 - 8
25364 8 - 8
25332 8 - 8
25332 8 - 8
25364 - 8 8
25364 - 8 8
25332 - 8 8
25332 - 8 8
25364 8 - 8
25364 8 - 8
25332 8 - 8
25332 8 - 8
25364 - 8 8
25364 - 8 8
25332 - 8 8
25332 - 8 8
25364 - 8 25364 - 8 25332 - 8 25332 - 8 25364 - 8 25364 - 8 25332 - 8 25332 - 8 -
Timers (16-bit)
Programmable Counter Array
Digital Port I/O’s
12-bit 100ksps ADC Inputs
10-bit 100ksps ADC Inputs
8-bit 500ksps ADC Inputs
Voltage Reference
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
Analog Comparators
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
Lead-Free (RoHS Compliant)
12 2 2 - 100TQFP
12 2 2
12 2 2 - 64TQFP
12 2 2
12 2 2 - 100TQFP
12 2 2
12 2 2 - 64TQFP
12 2 2
12 2 2 - 100TQFP
12 2 2
12 2 2 - 64TQFP
12 2 2
12 2 2 - 100TQFP
12 2 2
12 2 2 - 64TQFP
12 2 2
- - 2 - 100TQFP
--23100TQFP
- - 2 - 64TQFP
--2364TQFP
- - 2 - 100TQFP
--23100TQFP
- - 2 - 64TQFP
--2364TQFP
3
3
3
3
3
3
3
3
Package
100TQFP
64TQFP
100TQFP
64TQFP
100TQFP
64TQFP
100TQFP
64TQFP
20 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
8
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
External Oscillator
Circuit
Circuitry
Calibrated Internal
Oscillator
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
A
M
U
X
TEMP
SENSOR
CP0
CP1
Prog
Gain
PLL
Debug HW
WDT
System
Clock
100 ksps
(12-Bit)
Reset
ADC
0
5
1
C
o
r
e
256 byte
RAM
8 kB
XRAM
External D a ta
Memory Bus
128 kB
FLASH
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
ADC
500 ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.1. C8051F120/124 Block Diagram
Rev. 1.4 21
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
External Oscillator
Circuit
Circuitry
Calibrated Internal
Oscillator
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
A
M
U
X
TEMP
SENSOR
CP0
CP1
Prog
Gain
PLL
Debug HW
WDT
System
Clock
100 ksps
(12-Bit)
Reset
ADC
8
0
5
1
C
o
r
e
256 byte
RAM
8 kB
XRAM
External Data
Memory Bus
128 kB
FLASH
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
ADC
500 ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
AV+
VREFA
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
Figure 1.2. C8051F121/125 Block Diagram
22 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
8
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
Externa l Oscillator
Circuit
Circuitry
Calibrated Internal
Oscillator
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
A
M
U
X
TEMP
SENSOR
CP0
CP1
Prog
Gain
PLL
Debug HW
WDT
System
Clock
100 ksps
(10-Bit)
Reset
ADC
0
5
1
C
o
r
e
256 byte
RAM
8 kB
XRAM
External D a ta
Memory Bus
128 kB
FLASH
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
ADC
500 ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.3. C8051F122/126 Block Diagram
Rev. 1.4 23
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
External Oscillator
Circuit
Circuitry
Calibrated Internal
Oscillator
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
A
M
U
X
TEMP
SENSOR
CP0
CP1
Prog
Gain
PLL
Debug HW
WDT
System
Clock
100 ksps
(10-Bit)
Reset
ADC
8
0
5
1
C
o
r
e
256 byte
RAM
8 kb
XRAM
External Data
Memory Bus
128 kb
FLASH
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
ADC
500 ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
AV+
VREFA
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
Figure 1.4. C8051F123/127 Block Diagram
24 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
8
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
External Oscillator
Calibrated Inte rn al
Circuit
Circuitry
Oscillator
VREF
WDT
PLL
Debug HW
System
Clock
Reset
0
5
1
C
o
r
e
ADC
100ksps
(10-Bit)
CP0
A
M
U
X
CP1
TEMP
SENSOR
Prog
Gain
256 byte
RAM
8kbyte
XRAM
External D ata
Memory Bus
FLASH
128kbyte
(‘F130)
64kbyte
(‘F132)
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
C
T
L
A
d
d
D
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
Figure 1.5. C8051F130/132 Block Diagram
Rev. 1.4 25
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDO
RST
MONEN
XTAL1
XTAL2
VREF
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Port I/O
Digital Power
SFR Bus
Analog Power
Boundary Scan
TDI
JTAG
Logic
VDD
Monitor
External Oscillator
Circuit
Circuitry
Calibrated Inte rn al
Oscillator
VREF
CP0
A
M
U
X
CP1
TEMP
SENSOR
Prog
Gain
Debug HW
WDT
PLL
System
Clock
100ksps
(10-Bit)
Reset
ADC
8
0
5
1
C
o
r
e
256 byte
RAM
8kbyte
XRAM
External D ata
Memory Bus
FLASH
128kbyte
(‘F131)
64kbyte
(‘F133)
64x4 byte
cache
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
C
T
L
A
d
d
D
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
Figure 1.6. C8051F131/133 Block Diagram
26 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F12x and C8051F13x utilize Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The core has all the periphera l s include d with a standard 8052, including five
16-bit counter/timers, two full-duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 byte-wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute 1 22/333/444/55 8
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 100 MHz, the C8051F120/1/2/3 and C8051F130/1/2/3 have a
peak throughput of 100 MIPS (the C8051F124/5/6/7 have a peak throughput of 50 MIPS).
Rev. 1.4 27
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.1.3. Additional Features
Several key enhancements are implemented in the CIP-51 core and peripherals to improve overall performance and ease of use in end applications.
The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt
driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board V
monitor, a Watchdog Timer, a missing
DD
clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input
pin, and the RST
nally generated POR to be output on the RST
Input pin may be disabled by the user in software; the V
pin. The RST pin is bi-directional, accommodating an external rese t, or allowing the inter-
pin. Each reset source except for the VDD monitor and Reset
monitor is enabled/disabled via th e MONEN
DD
pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after
any reset. If desired, the clock source may be switched on the fly to the external oscillator , which can use a
crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can
be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the 24.5 MH z internal oscillator as needed. Additionally,
an on-chip PLL is provided to achieve higher system clock speeds for increased throughput.
V
DD
(Port I/O)
CP0+
CP0-
XTAL1
XTAL2
Crossbar
Internal
Clock
Generator
PLL
Circuitry
OSC
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
System
Clock
Clock Select
Missing
Clock
Detector
(one-
shot)
EN
Enable
WDT
Enable
MCD
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
EN
WDT
Supply
Monitor
+
-
PRE
WDT
Supply
Reset
Timeout
Strobe
Software Reset
System Reset
(wired-OR)
Reset
Funnel
RST
Figure 1.7. On-Board Clock and Reset
28 Rev. 1.4
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
The devices include an on-chip 8k byte RAM block and an external memory interf ace (EM IF) for acce ssing
off-chip data memory. The on-chip 8k byte block can be addressed over the entire 64k external data memory address range (overlapping 8k boundaries). External data memory address space can be mapped to
on-chip memory only, off-chip memor y only, or a combination of the two (addresses up to 8k directed to onchip, above 8k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed
address/data lines.
On the C8051F12x and C8051F130/1, the MCU’s program memory consists of 128 k bytes of banked
Flash memory. The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved. On the C8051F132/3,
the MCU’s program memory consists of 64 k bytes of Flash memory. This memory may be reprogrammed
in-system in 1024 byte sectors, and requires no special off-chip programming voltage.
On all devices, there are also two 128 byte sectors at addresses 0x20000 to 0x200FF, which may be used
by software for data storage. See Figure 1.8 for the MCU system memory map.
PROGRAM/DATA MEMORY
(FLASH)
C8051F120/1/2/3/4/5/6/7
C8051F130/1
0x200FF
0x20000
0x1FFFF
0x1FC00
0x1FBFF
0x00000
Scrachpad Memory
(DATA only)
RESERVED
FLASH
(In-System
Programmable in 1024
Byte Sectors)
C8051F132/3
0x200FF
0x20000
0x0FFFF
0x00000
Scrachpad Memory
(DATA only)
FLASH
(In-System
Programmable in 1024
Byte Sectors)
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Registers
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Off-chip XRAM space
0x2000
0x1FFF
0x0000
XRAM - 8192 Bytes
(accessable using MOVX
instruction)
0
1
2
3
Up To
256 SFR Pages
Figure 1.8. On-Chip Memory Map
Rev. 1.4 29
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.3. JTAG Debug and Boundary Scan
JTAG boundary scan and debug circuitry is included which provides non-intrusive, full speed, in-circuit
debugging using the production part installed in the end application, via the four-pin JTAG interface. The
JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and
work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the
MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized.
The C8051F120DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F12x or C8051F13x MCUs.
The kit includes a Windows (95 or later) development environment, a serial adapter for connecting to the
JTAG port, and a target application board with a C8051F120 MCU installed. All of the necessary communication cables and a wall-mount power supply are also supplied with the development kit. Silicon Labs’
debug environment is a vastly superior configuration for de veloping and debugging embedd ed applications
compared to standard MCU emulators, which use on-board "ICE Chips" and target cables and require the
MCU in the application board to be socketed. Silicon Labs' debug environment both increases ease of use
and preserves the performance of the precision, on-chip analog peripherals.
WINDOWS 95 OR LATE R
Figure 1.9. Development/In-System Debug Diagram
Silicon Labs Integrated
Development Environment
JTA G (x 4 ), V DD, G ND
Serial
Adapter
TARGET PCB
C8051
F12x/13x
30 Rev. 1.4
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