Silicon Laboratories C8051F020, C8051F021, C8051F022, C8051F023 User Manual
C8051F020/1/2/3
8K ISP FLASH MCU Family
ANALOG PERIPHERALS
- SAR ADC
• 12-Bit (C8051F020/1)
• 10-Bit (C8051F022/3)
• ± 1 LSB INL
• Programmable Throughput up to 100 ksps
• Up to 8 External Inputs; Programmable as Single-Ended or
Differential
• Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
• Data-Dependent Windowed Interrupt Generator
• Built-in Temperature Sensor (± 3°C)
- 8-bit ADC
• Programmable Throughput up to 500 ksps
• 8 External Inputs
• Programmable Amplifier Gain: 4, 2, 1, 0.5
- Two 12-bit DACs
• Can Synchronize Outputs to T im ers for Jitter-Free Wave-
form Generation
- Two Analog Comparators
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
- Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Low-Cost, Complete Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- 22 Vectored Interrupt Sources
MEMORY
- 4352 Bytes Internal Data RAM (4k + 256)
- 64k Bytes FLASH; In-System programmable in 512-byte
Sectors
- External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
DIGITAL PERIPHERALS
- 8 Byte-Wide Port I/O (C8051F020/2); 5V tolerant
- 4 Byte-Wide Port I/O (C8051F021/3); 5V tolerant
- Hardware SMBus™ (I
Two
UART Serial Ports Available Concurrently
2
C™ Compatible), SPI™, and
- Programmable 16-bit Counter/Timer Array with
5
Capture/Compare Modules
- 5 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset Pin
CLOCK SOURCES
- Internal Programmable Oscillator: 2-to-16 MHz
- External Oscillator: Crystal, RC, C, or Clock
- Real-Time Clock Mode using Timer 3 or PCA
SUPPLY VOLTAGE .......................... 2.7V TO 3.6V
- Typical Operating Current: 10 mA @ 20 MHz
- Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP and 64-Pin TQFP Packages Available
Temperature Range: -40°C to +85°C
ANALOG PERIPHERALS
TEMP
AMUX
12-Bit
DAC
12-Bit
DAC
SENSOR
PGA
VREF
AMUX
10/12-bit
100ksps
ADC
PGA
+
-
VOLTAGE
COMPARATORS
500ksps
+
-
8-bit
ADC
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64KB
ISP FLASH
DEBUG
CIRCUITRY
CIRCUIT
DIGITAL I/O
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
4352 B
SRAM
CLOCK
CROSSBAR
64 pin
SANITY
CONTROL
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
External Memory Interface
Port 6
Port 7
100 pin
JTAG
Preliminary Rev. 1.4 12/03 Copyright © 2003 by Silicon Laboratories C8051F020/1/2/3-DS14
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F020/1/2/3
Notes
2 Rev. 1.4
C8051F020/1/2/3
TABLE OF CONTENTS
1. SYSTEM OVERVIEW .........................................................................................................17
1.1. CIP-51™ Microcontroller Core ......................................................................................22
1.1.1. Fully 8051 Compatible ..........................................................................................22
1.1.2. Improved Throughput ............................................................................................22
1.1.3. Additional Features ................................................................................................23
1.2. On-Chip Memory ............................................................................................................24
1.3. JTAG Debug and Boundary Scan ...................................................................................25
1.4. Programmable Digital I/O and Crossbar .........................................................................26
1.5. Programmable Counter Array .........................................................................................27
1.6. Serial Ports.......................................................................................................................27
1.7. 12-Bit Analog to Digital Converter .................................................................................28
1.8. 8-Bit Analog to Digital Converter ...................................................................................29
1.9. Comparators and DACs................................................................................................... 30
2. ABSOLUTE MAXIMUM RATINGS..................................................................................31
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32
4. PINOUT AND PACKAGE DEFINITIONS........................................................................33
5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43
5.1. Analog Multiplexer and PGA.......................................................................................... 43
5.2. ADC Modes of Operation ...............................................................................................44
5.2.1. Starting a Conversion.............................................................................................44
5.2.2. Tracking Modes .....................................................................................................45
5.2.3. Settling Time Requirements ..................................................................................46
5.3. ADC0 Programmable Window Detector.........................................................................53
6. ADC0 (10-BIT ADC, C8051F022/3 ONLY) ........................................................................59
6.1. Analog Multiplexer and PGA.......................................................................................... 59
6.2. ADC Modes of Operation ...............................................................................................60
6.2.1. Starting a Conversion.............................................................................................60
6.2.2. Tracking Modes .....................................................................................................61
6.2.3. Settling Time Requirements ..................................................................................62
6.3. ADC0 Programmable Window Detector.........................................................................69
7. ADC1 (8-BIT ADC) ...............................................................................................................75
7.1. Analog Multiplexer and PGA.......................................................................................... 75
7.2. ADC1 Modes of Operation .............................................................................................76
7.2.1. Starting a Conversion.............................................................................................76
7.2.2. Tracking Modes .....................................................................................................76
7.2.3. Settling Time Requirements ..................................................................................78
8. DACS, 12-BIT VOLTAGE MODE......................................................................................83
8.1. DAC Output Scheduling..................................................................................................83
8.1.1. Update Output On-Demand ...................................................................................84
8.1.2. Update Output Based on Timer Overflow ............................................................. 84
8.2. DAC Output Scaling/Justification ...................................................................................84
9. VOLTAGE REFERENCE (C8051F020/2)..........................................................................91
Rev. 1.4 3
C8051F020/1/2/3
10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93
11. COMPARATORS..................................................................................................................95
12. CIP-51 MICROCONTROLLER........................................................................................101
12.1. Instruction Set ................................................................................................................102
12.1.1. Instruction and CPU Timing ................................................................................102
12.1.2. MOVX Instruction and Program Memory...........................................................102
12.2. Memory Organization ...................................................................................................107
12.2.1. Program Memory ................................................................................................. 107
12.2.2. Data Memory .......................................................................................................108
12.2.3. General Purpose Registers ...................................................................................108
12.2.4. Bit Addressable Locations ...................................................................................108
12.2.5. Stack .................................................................................................................108
12.2.6. Special Function Registers...................................................................................109
12.2.7. Register Descriptions ........................................................................................... 113
12.3. Interrupt Handler ........................................................................................................... 116
12.3.1. MCU Interrupt Sources and Vectors ...................................................................116
12.3.2. External Interrupts ...............................................................................................116
12.3.3. Interrupt Priorities ................................................................................................118
12.3.4. Interrupt Latency..................................................................................................118
12.3.5. Interrupt Register Descriptions ............................................................................119
12.4. Power Management Modes ...........................................................................................125
12.4.1. Idle Mode ............................................................................................................. 125
12.4.2. Stop Mode ............................................................................................................125
13. RESET SOURCES ..............................................................................................................127
13.1. Power-on Reset ..............................................................................................................128
13.2. Power-fail Reset ............................................................................................................128
13.3. External Reset ................................................................................................................129
13.4. Software Forced Reset ...................................................................................................129
13.5. Missing Clock Detector Reset .......................................................................................129
13.6. Comparator0 Reset ........................................................................................................ 129
13.7. External CNVSTR Pin Reset......................................................................................... 129
13.8. Watchdog Timer Reset ..................................................................................................129
13.8.1. Enable/Reset WDT .............................................................................................. 130
13.8.2. Disable WDT .......................................................................................................130
13.8.3. Disable WDT Lockout .........................................................................................130
13.8.4. Setting WDT Interval...........................................................................................130
14. OSCILLATORS...................................................................................................................135
14.1. External Crystal Example ..............................................................................................138
14.2. External RC Example ....................................................................................................138
14.3. External Capacitor Example ..........................................................................................138
15. FLASH MEMORY ..............................................................................................................139
15.1. Programming The FLASH Memory .............................................................................139
15.2. Non-volatile Data Storage ............................................................................................. 140
15.3. Security Options ............................................................................................................ 140
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145
4 Rev. 1.4
C8051F020/1/2/3
16.1. Accessing XRAM ..........................................................................................................145
16.1.1. 16-Bit MOVX Example .......................................................................................145
16.1.2. 8-Bit MOVX Example .........................................................................................145
16.2. Configuring the External Memory Interface ................................................................. 146
16.3. Port Selection and Configuration ..................................................................................146
16.4. Multiplexed and Non-multiplexed Selection.................................................................148
16.4.1. Multiplexed Configuration ..................................................................................148
16.4.2. Non-multiplexed Configuration........................................................................... 149
16.5. Memory Mode Selection ............................................................................................... 150
16.5.1. Internal XRAM Only ...........................................................................................150
16.5.2. Split Mode without Bank Select ..........................................................................150
16.5.3. Split Mode with Bank Select ............................................................................... 151
16.5.4. External Only ....................................................................................................... 151
16.6. Timing .......................................................................................................................151
16.6.1. Non-multiplexed Mode ........................................................................................153
16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................ 153
16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. ........... 154
16.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ..............................155
16.6.2. Multiplexed Mode................................................................................................156
16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’................................ 156
16.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. ........... 157
16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ..............................158
17. PORT INPUT/OUTPUT .....................................................................................................161
17.1. Ports 0 through 3 and the Priority Crossbar Decoder ....................................................163
17.1.1. Crossbar Pin Assignment and Allocation ............................................................163
17.1.2. Configuring the Output Modes of the Port Pins ..................................................164
17.1.3. Configuring Port Pins as Digital Inputs ............................................................... 165
17.1.4. External Interrupts (IE6 and IE7) ........................................................................165
17.1.5. Weak Pull-ups ......................................................................................................165
17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])...................................... 165
17.1.7. External Memory Interface Pin Assignments ......................................................166
17.1.8. Crossbar Pin Assignment Example......................................................................168
17.2. Ports 4 through 7 (C8051F020/2 only) ..........................................................................177
17.2.1. Configuring Ports which are not Pinned Out .......................................................177
17.2.2. Configuring the Output Modes of the Port Pins ..................................................177
17.2.3. Configuring Port Pins as Digital Inputs ............................................................... 178
17.2.4. Weak Pull-ups ......................................................................................................178
17.2.5. External Memory Interface ..................................................................................178
18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183
18.1. Supporting Documents .................................................................................................. 184
18.2. SMBus Protocol.............................................................................................................185
18.2.1. Arbitration............................................................................................................ 185
18.2.2. Clock Low Extension...........................................................................................185
18.2.3. SCL Low Timeout ............................................................................................... 186
18.2.4. SCL High (SMBus Free) Timeout .......................................................................186
Rev. 1.4 5
C8051F020/1/2/3
18.3. SMBus Transfer Modes .................................................................................................187
18.3.1. Master Transmitter Mode ....................................................................................187
18.3.2. Master Receiver Mode .........................................................................................187
18.3.3. Slave Transmitter Mode.......................................................................................188
18.3.4. Slave Receiver Mode ...........................................................................................188
18.4. SMBus Special Function Registers ...............................................................................189
18.4.1. Control Register ................................................................................................... 189
18.4.2. Clock Rate Register .............................................................................................192
18.4.3. Data Register........................................................................................................193
18.4.4. Address Register .................................................................................................. 193
18.4.5. Status Register .....................................................................................................194
19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) ........................................................197
19.1. Signal Descriptions ........................................................................................................198
19.1.1. Master Out, Slave In (MOSI) .............................................................................. 198
19.1.2. Master In, Slave Out (MISO) .............................................................................. 198
19.1.3. Serial Clock (SCK) ..............................................................................................198
19.1.4. Slave Select (NSS) ...............................................................................................198
19.2. SPI0 Operation ..............................................................................................................199
19.3. Serial Clock Timing ......................................................................................................200
19.4. SPI Special Function Registers .....................................................................................201
20. UART0 ..................................................................................................................................205
20.1. UART0 Operational Modes ..........................................................................................206
20.1.1. Mode 0: Synchronous Mode ................................................................................206
20.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................207
20.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................208
20.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................209
20.2. Multiprocessor Communications...................................................................................210
20.3. Frame and Transmission Error Detection...................................................................... 211
21. UART1 ..................................................................................................................................215
21.1. UART1 Operational Modes ..........................................................................................216
21.1.1. Mode 0: Synchronous Mode ................................................................................216
21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................217
21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................218
21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................219
21.2. Multiprocessor Communications...................................................................................220
21.3. Frame and Transmission Error Detection...................................................................... 221
22. TIMERS................................................................................................................................225
22.1. Timer 0 and Timer 1 ......................................................................................................227
22.1.1. Mode 0: 13-bit Counter/Timer............................................................................. 227
22.1.2. Mode 1: 16-bit Counter/Timer............................................................................. 228
22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload ................................................. 229
22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................230
22.2. Timer 2 .......................................................................................................................234
22.2.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................235
22.2.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................236
6 Rev. 1.4
C8051F020/1/2/3
22.2.3. Mode 2: Baud Rate Generator ............................................................................. 237
22.3. Timer 3 .......................................................................................................................240
22.4. Timer 4 .......................................................................................................................243
22.4.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................244
22.4.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................245
22.4.3. Mode 2: Baud Rate Generator ............................................................................. 246
23. PROGRAMMABLE COUNTER ARRAY .......................................................................249
23.1. PCA Counter/Timer....................................................................................................... 250
23.2. Capture/Compare Modules ............................................................................................252
23.2.1. Edge-triggered Capture Mode ............................................................................. 253
23.2.2. Software Timer (Compare) Mode........................................................................254
23.2.3. High Speed Output Mode .................................................................................... 255
23.2.4. Frequency Output Mode ......................................................................................256
23.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................257
23.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................258
23.3. Register Descriptions for PCA0 .................................................................................... 259
24. JTAG (IEEE 1149.1)............................................................................................................265
24.1. Boundary Scan...............................................................................................................266
24.1.1. EXTEST Instruction ............................................................................................ 267
24.1.2. SAMPLE Instruction ...........................................................................................267
24.1.3. BYPASS Instruction ............................................................................................267
24.1.4. IDCODE Instruction ............................................................................................267
24.2. Flash Programming Commands ....................................................................................268
24.3. Debug Support ...............................................................................................................271
Rev. 1.4 7
C8051F020/1/2/3
Notes
8 Rev. 1.4
C8051F020/1/2/3
LIST OF FIGURES AND TABLES
1. SYSTEM OVERVIEW .........................................................................................................17
Table 1.1. Product Selection Guide ...................................................................................... 17
Figure 1.1. C8051F020 Block Diagram................................................................................. 18
Figure 1.2. C8051F021 Block Diagram................................................................................. 19
Figure 1.3. C8051F022 Block Diagram................................................................................. 20
Figure 1.4. C8051F023 Block Diagram................................................................................. 21
Figure 1.5. Comparison of Peak MCU Execution Speeds .....................................................22
Figure 1.6. On-Board Clock and Reset ..................................................................................23
Figure 1.7. On-Chip Memory Map ........................................................................................ 24
Figure 1.8. Development/In-System Debug Diagram ...........................................................25
Figure 1.9. Digital Crossbar Diagram ....................................................................................26
Figure 1.10. PCA Block Diagram............................................................................................ 27
Figure 1.11. 12-Bit ADC Block Diagram ................................................................................28
Figure 1.12. 8-Bit ADC Diagram ............................................................................................29
Figure 1.13. Comparator and DAC Diagram........................................................................... 30
2. ABSOLUTE MAXIMUM RATINGS..................................................................................31
Table 2.1. Absolute Maximum Ratings*.............................................................................. 31
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................32
Table 3.1. Global DC Electrical Characteristics...................................................................32
4. PINOUT AND PACKAGE DEFINITIONS........................................................................33
Table 4.1. Pin Definitions .....................................................................................................33
Figure 4.1. TQFP-100 Pinout Diagram..................................................................................38
Figure 4.2. TQFP-100 Package Drawing...............................................................................39
Figure 4.3. TQFP-64 Pinout Diagram....................................................................................40
Figure 4.4. TQFP-64 Package Drawing.................................................................................41
5. ADC0 (12-BIT ADC, C8051F020/1 ONLY) ........................................................................43
Figure 5.1. 12-Bit ADC0 Functional Block Diagram............................................................ 43
Figure 5.2. Temperature Sensor Transfer Function ............................................................... 44
Figure 5.3. 12-Bit ADC Track and Conversion Example Timing .........................................45
Figure 5.4. ADC0 Equivalent Input Circuits ......................................................................... 46
Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1) .............................47
Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F020/1)............................ 48
Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1) ..................................49
Rev. 1.4 9
C8051F020/1/2/3
Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....55
Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data.... 56
Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data .......57
Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1).....................................58
6. ADC0 (10-BIT ADC, C8051F022/3 ONLY) ........................................................................59
Figure 6.1. 10-Bit ADC0 Functional Block Diagram............................................................ 59
Figure 6.2. Temperature Sensor Transfer Function ............................................................... 60
Figure 6.3. 10-Bit ADC Track and Conversion Example Timing .........................................61
Figure 6.4. ADC0 Equivalent Input Circuits ......................................................................... 62
Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3) .............................63
Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3)............................ 64
Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3) ..................................65
Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3) ...........................................66
Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3) ...............................67
Figure 6.10. ADC0L: ADC0 Data Word LSB Register (C8051F022/3).................................67
Figure 6.11. ADC0 Data Word Example (C8051F022/3) .......................................................68
Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register (C8051F022/3) .....69
Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register (C8051F022/3) ...... 69
Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register (C8051F022/3) .......... 69
Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register (C8051F022/3) ...........69
Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data . 70
Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....71
Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data.... 72
Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data .......73
Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3).....................................74
7. ADC1 (8-BIT ADC) ...............................................................................................................75
Figure 7.1. ADC1 Functional Block Diagram ....................................................................... 75
Figure 7.2. ADC1 Track and Conversion Example Timing ..................................................77
Figure 7.3. ADC1 Equivalent Input Circuit ...........................................................................78
Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3)............................79
Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3) .....................79
Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) .....................................80
Figure 7.7. ADC1: ADC1 Data Word Register .....................................................................81
Figure 7.8. ADC1 Data Word Example .................................................................................81
Table 7.1. ADC1 Electrical Characteristics..........................................................................82
8. DACS, 12-BIT VOLTAGE MODE......................................................................................83
Figure 8.1. DAC Functional Block Diagram ......................................................................... 83
Figure 8.2. DAC0H: DAC0 High Byte Register ...................................................................85
Figure 8.3. DAC0L: DAC0 Low Byte Register ....................................................................85
Figure 8.4. DAC0CN: DAC0 Control Register ..................................................................... 86
Figure 8.5. DAC1H: DAC1 High Byte Register ...................................................................87
Figure 8.6. DAC1L: DAC1 Low Byte Register ....................................................................87
Figure 8.7. DAC1CN: DAC1 Control Register ..................................................................... 88
Table 8.1. DAC Electrical Characteristics............................................................................89
9. VOLTAGE REFERENCE (C8051F020/2)..........................................................................91
10 Rev. 1.4
C8051F020/1/2/3
Figure 9.1. Voltage Reference Functional Block Diagram....................................................91
Figure 9.2. REF0CN: Reference Control Register ................................................................92
Table 9.1. Voltage Reference Electrical Characteristics ......................................................92
10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93
Figure 10.1. Voltage Reference Functional Block Diagram ...................................................93
Figure 10.2. REF0CN: Reference Control Register ................................................................ 94
Table 10.1. Voltage Reference Electrical Characteristics ......................................................94
11. COMPARATORS..................................................................................................................95
Figure 11.1. Comparator Functional Block Diagram .............................................................. 95
Figure 11.2. Comparator Hysteresis Plot .................................................................................96
Figure 11.3. CPT0CN: Comparator0 Control Register ...........................................................97
Figure 11.4. CPT1CN: Comparator1 Control Register ...........................................................98
Table 11.1. Comparator Electrical Characteristics .................................................................99
12. CIP-51 MICROCONTROLLER........................................................................................101
Figure 12.1. CIP-51 Block Diagram ......................................................................................101
Table 12.1. CIP-51 Instruction Set Summary.......................................................................103
Figure 12.2. Memory Map ..................................................................................................... 107
Table 12.2. Special Function Register (SFR) Memory Map ................................................109
Table 12.3. Special Function Registers ................................................................................109
Figure 12.3. SP: Stack Pointer ...............................................................................................113
Figure 12.4. DPL: Data Pointer Low Byte ............................................................................113
Figure 12.5. DPH: Data Pointer High Byte ........................................................................... 113
Figure 12.6. PSW: Program Status Word .............................................................................. 114
Figure 12.7. ACC: Accumulator ............................................................................................115
Figure 12.8. B: B Register ..................................................................................................... 115
Table 12.4. Interrupt Summary.............................................................................................117
Figure 12.9. IE: Interrupt Enable ...........................................................................................119
Figure 12.10. IP: Interrupt Priority ........................................................................................120
Figure 12.11. EIE1: Extended Interrupt Enable 1 ................................................................. 121
Figure 12.12. EIE2: Extended Interrupt Enable 2 ................................................................. 122
Figure 12.13. EIP1: Extended Interrupt Priority 1.................................................................123
Figure 12.14. EIP2: Extended Interrupt Priority 2.................................................................124
Figure 12.15. PCON: Power Control .....................................................................................126
13. RESET SOURCES ..............................................................................................................127
Figure 13.1. Reset Sources .................................................................................................... 127
Figure 13.2. Reset Timing .....................................................................................................128
Figure 13.3. WDTCN: Watchdog Timer Control Register ................................................... 131
Figure 13.4. RSTSRC: Reset Source Register....................................................................... 132
Table 13.1. Reset Electrical Characteristics .........................................................................133
14. OSCILLATORS...................................................................................................................135
Figure 14.1. Oscillator Diagram ............................................................................................ 135
Figure 14.2. OSCICN: Internal Oscillator Control Register ................................................. 136
Table 14.1. Internal Oscillator Electrical Characteristics .....................................................136
Figure 14.3. OSCXCN: External Oscillator Control Register ...............................................137
15. FLASH MEMORY ..............................................................................................................139
Rev. 1.4 11
C8051F020/1/2/3
Table 15.1. FLASH Electrical Characteristics .....................................................................140
Figure 15.1. FLASH Program Memory Map and Security Bytes ......................................... 141
Figure 15.2. FLACL: FLASH Access Limit .........................................................................142
Figure 15.3. FLSCL: FLASH Memory Control .................................................................... 143
Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................145
Figure 16.1. EMI0CN: External Memory Interface Control .................................................147
Figure 16.2. EMI0CF: External Memory Configuration .......................................................147
Figure 16.3. Multiplexed Configuration Example .................................................................148
Figure 16.4. Non-multiplexed Configuration Example .........................................................149
Figure 16.5. EMIF Operating Modes.....................................................................................150
Figure 16.6. EMI0TC: External Memory Timing Control ....................................................152
Figure 16.7. Non-multiplexed 16-bit MOVX Timing ...........................................................153
Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................ 154
Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing .................................155
Figure 16.10. Multiplexed 16-bit MOVX Timing .................................................................156
Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing ................................. 157
Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................158
Table 16.1. AC Parameters for External Memory Interface.................................................159
17. PORT INPUT/OUTPUT .....................................................................................................161
Figure 17.1. Port I/O Cell Block Diagram .............................................................................161
Table 17.1. Port I/O DC Electrical Characteristics .............................................................. 161
Figure 17.2. Lower Port I/O Functional Block Diagram ....................................................... 162
Figure 17.3. Priority Crossbar Decode Table ........................................................................ 163
Figure 17.4. Priority Crossbar Decode Table ........................................................................ 166
Figure 17.5. Priority Crossbar Decode Table ........................................................................ 167
Figure 17.6. Crossbar Example: ............................................................................................ 169
Figure 17.7. XBR0: Port I/O Crossbar Register 0 .................................................................170
Figure 17.8. XBR1: Port I/O Crossbar Register 1 .................................................................171
Figure 17.9. XBR2: Port I/O Crossbar Register 2 .................................................................172
Figure 17.10. P0: Port0 Data Register ...................................................................................173
Figure 17.11. P0MDOUT: Port0 Output Mode Register.......................................................173
Figure 17.12. P1: Port1 Data Register ...................................................................................174
Figure 17.13. P1MDIN: Port1 Input Mode Register ............................................................. 174
Figure 17.14. P1MDOUT: Port1 Output Mode Register.......................................................175
Figure 17.15. P2: Port2 Data Register ...................................................................................175
Figure 17.16. P2MDOUT: Port2 Output Mode Register.......................................................175
Figure 17.17. P3: Port3 Data Register ...................................................................................176
Figure 17.18. P3MDOUT: Port3 Output Mode Register.......................................................176
Figure 17.19. P3IF: Port3 Interrupt Flag Register ................................................................. 177
Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register ...................................................179
Figure 17.21. P4: Port4 Data Register ...................................................................................180
Figure 17.22. P5: Port5 Data Register ...................................................................................180
Figure 17.23. P6: Port6 Data Register ...................................................................................181
Figure 17.24. P7: Port7 Data Register ...................................................................................181
12 Rev. 1.4
C8051F020/1/2/3
18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183
Figure 18.1. SMBus0 Block Diagram ................................................................................... 183
Figure 18.2. Typical SMBus Configuration ..........................................................................184
Figure 18.3. SMBus Transaction ...........................................................................................185
Figure 18.4. Typical Master Transmitter Sequence............................................................... 187
Figure 18.5. Typical Master Receiver Sequence ...................................................................187
Figure 18.6. Typical Slave Transmitter Sequence ................................................................. 188
Figure 18.7. Typical Slave Receiver Sequence .....................................................................188
Figure 18.8. SMB0CN: SMBus0 Control Register ...............................................................191
Figure 18.9. SMB0CR: SMBus0 Clock Rate Register .......................................................... 192
Figure 18.10. SMB0DAT: SMBus0 Data Register ...............................................................193
Figure 18.11. SMB0ADR: SMBus0 Address Register..........................................................193
Figure 18.12. SMB0STA: SMBus0 Status Register ..............................................................194
Table 18.1. SMB0STA Status Codes and States .................................................................. 195
19. SERIAL PERIPHERAL INTERFACE BUS (SPI0) ........................................................197
Figure 19.1. SPI Block Diagram............................................................................................ 197
Figure 19.2. Typical SPI Interconnection ..............................................................................198
Figure 19.3. Full Duplex Operation .......................................................................................199
Figure 19.4. Data/Clock Timing Diagram ............................................................................. 200
Figure 19.5. SPI0CFG: SPI0 Configuration Register ............................................................201
Figure 19.6. SPI0CN: SPI0 Control Register ........................................................................ 202
Figure 19.7. SPI0CKR: SPI0 Clock Rate Register ................................................................203
Figure 19.8. SPI0DAT: SPI0 Data Register .......................................................................... 203
20. UART0 ..................................................................................................................................205
Figure 20.1. UART0 Block Diagram.....................................................................................205
Table 20.1. UART0 Modes ..................................................................................................206
Figure 20.2. UART0 Mode 0 Interconnect ............................................................................206
Figure 20.3. UART0 Mode 0 Timing Diagram .....................................................................206
Figure 20.4. UART0 Mode 1 Timing Diagram .....................................................................207
Figure 20.5. UART Modes 2 and 3 Timing Diagram............................................................ 208
Figure 20.6. UART Modes 1, 2, and 3 Interconnect Diagram .............................................. 209
Figure 20.7. UART Multi-Processor Mode Interconnect Diagram .......................................210
Table 20.2. Oscillator Frequencies for Standard Baud Rates ...............................................212
Figure 20.8. SCON0: UART0 Control Register ....................................................................213
Figure 20.9. SBUF0: UART0 Data Buffer Register.............................................................. 214
Figure 20.10. SADDR0: UART0 Slave Address Register ....................................................214
Figure 20.11. SADEN0: UART0 Slave Address Enable Register ........................................214
21. UART1 ..................................................................................................................................215
Figure 21.1. UART1 Block Diagram.....................................................................................215
Table 21.1. UART1 Modes ..................................................................................................216
Figure 21.2. UART1 Mode 0 Interconnect ............................................................................216
Figure 21.3. UART1 Mode 0 Timing Diagram .....................................................................216
Figure 21.4. UART1 Mode 1 Timing Diagram .....................................................................217
Figure 21.5. UART Modes 2 and 3 Timing Diagram............................................................ 218
Figure 21.6. UART Modes 1, 2, and 3 Interconnect Diagram .............................................. 219
Rev. 1.4 13
C8051F020/1/2/3
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................220
Table 21.2. Oscillator Frequencies for Standard Baud Rates ...............................................222
Figure 21.8. SCON1: UART1 Control Register ....................................................................223
Figure 21.9. SBUF1: UART1 Data Buffer Register.............................................................. 224
Figure 21.10. SADDR1: UART1 Slave Address Register ....................................................224
Figure 21.11. SADEN1: UART1 Slave Address Enable Register ........................................224
22. TIMERS................................................................................................................................225
Figure 22.1. CKCON: Clock Control Register ......................................................................226
Figure 22.2. T0 Mode 0 Block Diagram................................................................................ 228
Figure 22.3. T0 Mode 2 (8-bit Auto-Reload) Block Diagram ...............................................229
Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram ................................................230
Figure 22.5. TCON: Timer Control Register......................................................................... 231
Figure 22.6. TMOD: Timer Mode Register........................................................................... 232
Figure 22.7. TL0: Timer 0 Low Byte ....................................................................................233
Figure 22.8. TL1: Timer 1 Low Byte ....................................................................................233
Figure 22.9. TH0 Timer 0 High Byte ....................................................................................233
Figure 22.10. TH1: Timer 1 High Byte ................................................................................. 233
Figure 22.11. T2 Mode 0 Block Diagram.............................................................................. 235
Figure 22.12. T2 Mode 1 Block Diagram.............................................................................. 236
Figure 22.13. T2 Mode 2 Block Diagram.............................................................................. 237
Figure 22.14. T2CON: Timer 2 Control Register.................................................................. 238
Figure 22.15. RCAP2L: Timer 2 Capture Register Low Byte ..............................................239
Figure 22.16. RCAP2H: Timer 2 Capture Register High Byte ............................................. 239
Figure 22.17. TL2: Timer 2 Low Byte ..................................................................................239
Figure 22.18. TH2 Timer 2 High Byte ..................................................................................239
Figure 22.19. Timer 3 Block Diagram................................................................................... 240
Figure 22.20. TMR3CN: Timer 3 Control Register ..............................................................241
Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte ............................................241
Figure 22.22. TMR3RLH: Timer 3 Reload Register High Byte ........................................... 242
Figure 22.23. TMR3L: Timer 3 Low Byte ............................................................................242
Figure 22.24. TMR3H: Timer 3 High Byte ........................................................................... 242
Figure 22.25. T4 Mode 0 Block Diagram.............................................................................. 244
Figure 22.26. T4 Mode 1 Block Diagram.............................................................................. 245
Figure 22.27. T4 Mode 2 Block Diagram.............................................................................. 246
Figure 22.28. T4CON: Timer 4 Control Register.................................................................. 247
Figure 22.29. RCAP4L: Timer 4 Capture Register Low Byte ..............................................248
Figure 22.30. RCAP4H: Timer 4 Capture Register High Byte ............................................. 248
Figure 22.31. TL4: Timer 4 Low Byte ..................................................................................248
Figure 22.32. TH4 Timer 4 High Byte ..................................................................................248
23. PROGRAMMABLE COUNTER ARRAY .......................................................................249
Figure 23.1. PCA Block Diagram.......................................................................................... 249
Figure 23.2. PCA Counter/Timer Block Diagram .................................................................250
Table 23.1. PCA Timebase Input Options............................................................................250
Figure 23.3. PCA Interrupt Block Diagram........................................................................... 252
Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ..................252
14 Rev. 1.4
C8051F020/1/2/3
Figure 23.4. PCA Capture Mode Diagram ............................................................................ 253
Figure 23.5. PCA Software Timer Mode Diagram................................................................ 254
Figure 23.6. PCA High Speed Output Mode Diagram ..........................................................255
Figure 23.7. PCA Frequency Output Mode ...........................................................................256
Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................................257
Figure 23.9. PCA 16-Bit PWM Mode ...................................................................................258
Figure 23.10. PCA0CN: PCA Control Register .................................................................... 259
Figure 23.11. PCA0MD: PCA0 Mode Register .................................................................... 260
Figure 23.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers ................................. 261
Figure 23.13. PCA0L: PCA0 Counter/Timer Low Byte ....................................................... 262
Figure 23.14. PCA0H: PCA0 Counter/Timer High Byte ......................................................262
Figure 23.15. PCA0CPLn: PCA0 Capture Module Low Byte ..............................................263
Figure 23.16. PCA0CPHn: PCA0 Capture Module High Byte .............................................263
24. JTAG (IEEE 1149.1)............................................................................................................265
Figure 24.1. IR: JTAG Instruction Register .......................................................................... 265
Table 24.1. Boundary Data Register Bit Definitions............................................................266
Figure 24.2. DEVICEID: JTAG Device ID Register ............................................................267
Figure 24.3. FLASHCON: JTAG Flash Control Register .....................................................269
Figure 24.4. FLASHADR: JTAG Flash Address Register ....................................................270
Figure 24.5. FLASHDAT: JTAG Flash Data Register.......................................................... 270
Rev. 1.4 15
C8051F020/1/2/3
Notes
16 Rev. 1.4
C8051F020/1/2/3
1. SYSTEM OVERVIEW
The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCU s with 64 digital I/O pins
(C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to
specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps 8-channel ADC with PGA and analog multiplexer
• True 8-bit ADC 500 ksps 8-channel ADC with PGA and analog multiplexer
• Two 12-bit DACs with programmable update scheduling
• 64k bytes of in-system programmable FLASH memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interface with 64k byte address space
•SPI, SMBus/I2C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with five capture/compare modules
• On-chip Watchdog Timer , VDD Monitor, and T emperature Sensor
With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F020/1/2/3 devices are truly stand-
alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user
firmware. The FLASH memory can be reprogrammed even in-circuit, providin g non-volatile data storage, and also
allowing field upgrades of the 8051 firmware.
Table 1.1 for
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging
using the production MCU installed in the final application. This debug system supports inspection and modificati on
of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional while de bugging using JTAG.
Each MCU is specified for 2.7 V- t o - 3 . 6 V operation over the industrial temperature range (-45° C to +85° C). The
Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5
TQFP package (see block diagrams in
package (see block diagrams in Figure 1.2 and Figure 1.4).
Figure 1.1 and Figure 1.3). The C8051F021/3 are available in a 64-pin TQFP
V. The C8051F020/2 are available in a 100-pin
Tab le 1.1. Product Selection Guide
C
2
MIPS (Peak)
FLASH Memory
RAM
External Memory Interface
SMBus/I
SPI
UARTS
Tim ers (16 -b it)
Programmable Counter Array
Digital Port I/O’s
12-bit 100ksps ADC Inputs
10-bit 100ksps ADC Inputs
8-bit 500ksps ADC Inputs
Vol t a ge Refer e nce
Temperature Sensor
DAC Resolution (bits)
DAC Outputs
C8051F020 25 64k 4352
C8051F021 25 64k 4352
3 3 3
3 3 3
2 5
2 5
3
64 8 - 8
3
32 8 - 8
3 3
3 3
Analog Comparators
12 2 2 100TQFP
12 2 2 64TQFP
Package
C8051F022 25 64k 4352
C8051F023 25 64k 4352
3 3 3
3 3 3
2 5
2 5
3
64 - 8 8
3
32 - 8 8
Rev. 1.4 17
3 3
3 3
12 2 2 100TQFP
12 2 2 64TQFP
C8051F020/1/2/3
Figure 1.1. C8051F020 Block Diagram
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
JTAG
Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
A
M
U
X
CP0
CP1
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
TEMP
SENSOR
Prog
Gain
Boundary Scan
Debug HW
WDT
System
Clock
Reset
ADC
100ksps
(12-Bit)
8
0
5
1
C
o
r
e
SFR Bus
64kbyte
FLASH
256 byte
RAM
4kbyte
RAM
External Data Memory Bus
Port I/O
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Address Bus
Bus Control
Data Bus
ADC
500ksps
(8-Bit)
C
T
L
A
d
d
D
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
VREF1
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
18 Rev. 1.4
Figure 1.2. C8051F021 Block Diagram
C8051F020/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
A
M
U
X
CP0
JTAG
Logic
VREF
(12-Bit)
(12-Bit)
CP1
DAC1
DAC0
Boundary Scan
WDT
Prog
Gain
TEMP
SENSOR
Debug HW
System
Clock
Reset
ADC
100ksps
(12-Bit)
8
0
5
1
C
o
r
e
SFR Bus
64kbyte
FLASH
256 byte
RAM
4kbyte
RAM
External Data Memory Bus
Port I/O
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Address Bus
Bus Control
Data Bus
ADC
500ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
AV+
VREFA
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
Rev. 1.4 19
C8051F020/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AV+
AGND
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
VREFD
DAC1
DAC0
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
JTAG
Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
A
M
U
X
CP0
CP1
VREF
DAC1
(12-Bit)
DAC0
(12-Bit)
TEMP
SENSOR
Prog
Gain
Boundary Scan
Debug HW
WDT
System
Clock
Reset
ADC
100ksps
(10-Bit)
8
0
5
1
C
o
r
e
SFR Bus
64kbyte
FLASH
256 byte
RAM
4kbyte
RAM
Port I/O
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Address Bus
Bus Control
Data Bus
C
T
L
A
d
d
D
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
P0
Drv
P1
Drv
P2
Drv
P3
Drv
8:1
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
20 Rev. 1.4
Figure 1.4. C8051F023 Block Diagram
C8051F020/1/2/3
VDD
VDD
VDD
DGND
DGND
DGND
AV+
AGND
TCK
TMS
TDI
TDO
/RST
MONEN
XTAL1
XTAL2
VREF
DAC1
DAC0
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
CP0+
CP0-
CP1+
CP1-
Digital Power
Analog Power
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
A
M
U
X
CP0
JTAG
Logic
VREF
(12-Bit)
(12-Bit)
CP1
DAC1
DAC0
Boundary Scan
Debug HW
WDT
Prog
Gain
TEMP
SENSOR
System
Clock
Reset
ADC
100ksps
(10-Bit)
8
0
5
1
C
o
r
e
SFR Bus
64kbyte
FLASH
256 byte
RAM
4kbyte
RAM
External Data Memory Bus
Port I/O
Config.
UART0
UART1
SMBus
SPI Bus
PCA
Timers 0,
1, 2, 4
Timer 3/
RTC
P0, P1,
P2, P3
Latches
Crossbar
Config.
Bus Control
Address Bus
Data Bus
ADC
500ksps
(8-Bit)
C
T
L
A
d
d
r
D
a
t
a
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
AV+
VREFA
P0
Drv
P1
Drv
P2
Drv
P3
Drv
A
8:1
M
Prog
Gain
U
X
P4
DRV
P5
DRV
P6
DRV
P7
DRV
P0.0
P0.7
P1.0/AIN1.0
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
Rev. 1.4 21
C8051F020/1/2/3
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F020 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compati-
ble with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full-
duplex UARTs, 256
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24
cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instru ctions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 byte-
system clock cycles to exe-
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a com-
parison of peak throughputs of various 8 -bit microcontroller cores with their maximum system clocks.
Figure 1.5. Comparison of Peak MCU Execution Speeds
25
20
15
MIPS
10
5
Silicon Labs
CIP-51
(25MHz clk)
22 Rev. 1.4
Microchip
PIC17C75x
(33MHz clk)
Philips
80C51
(33MHz clk)
ADuC812
8051
(16MHz clk)
C8051F020/1/2/3
1.1.3. Additional Features
The C8051F020 MCU family includes several key enhancements to the CIP-51 core an d peripherals to improve over-
all performance and ease of use in end applications.
The extended interrupt handler provides 22 interrupt sources into the CIP-51 (as opposed to 7 fo r th e st andard 8051),
allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires
less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when
building multi-tasking, real-time systems.
There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR input pin, and the /RST
pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be
output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the
user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be perma
nently enabled in software after a power-on reset during MCU initialization.
The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If
desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic reso
nator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switch
ing to the fast (up to 16 MHz) internal oscillator as needed.
-
-
-
(Port
I/O)
CP0+
CP0-
XTAL1
XTAL2
Crossbar
Internal
Clock
Generator
OSC
Figure 1.6. On-Board Clock and Reset
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
System
Clock
Clock Select
VDD
Missing
Clock
Detector
(one-
shot)
EN
MCD
WDT
Enable
CIP-51
Microcontroller
Core
WDT
EN
Enable
Supply
Monitor
+
-
PRE
WDT
Supply
Reset
Timeout
Strobe
Software Reset
System Reset
(wired-OR)
Reset
Funnel
/RST
Extended Interrupt
Handler
Rev. 1.4 23
C8051F020/1/2/3
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration . It includes 256 bytes of data RAM, with the
upper 128
addressing accesses the 128
rect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes
can be byte addressable or bit addressable.
The CIP-51 in the C8051F020/1/2/3 MCUs additionally has an on-chip 4k byte RAM block and an external memory
interface (EMIF) for accessing off-chip data memory . The on-chip 4k
external data memory address range (overlapping 4k boundaries). External data memory address space can be
mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 4k directed to
on-chip, above 4k directed to EMIF). The EMIF is also configurable for multiplexed or non-multipl exed address/data
lines.
The MCU’s program memory consists of 64k bytes of FLASH. This memory may be reprogrammed in-system in
512
0xFFFF are reserved for factory use. There is also a single 128
may be useful as a small table for software constants. See
bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indi-
byte block can be addressed over the entire 64k
byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses 0xFE00 to
byte sector at address 0x10000 to 0x1007F, which
Figure 1.7 for the MCU system memory map.
Figure 1.7. On-Chip Memory Map
PROGRAM/DATA MEMORY
(FLASH)
0x1007F
0x10000
0xFFFF
0xFE00
0xFDFF
0x0000
Scrachpad Memory
(DATA only)
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-chip XRAM space
0x1000
0x0FFF
0x0000
24 Rev. 1.4
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
C8051F020/1/2/3
1.3. JTAG Debug and Boundary Scan
The C8051F020 family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed,
in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The
JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes.
Silicon Labs' debugging system supports inspection and m odification of memory and registers, breakpoints, watch-
points, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communicat ion s
channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All
the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a
breakpoint in order to keep them synchronized.
The C8051F020DK development kit provides all the hardware and software necessary to dev elop application code
and perform in-circuit debugging with the C8051F020/1/2/3 MCUs. The kit inclu des software with a developer's stu
dio and debugger, an integrated 8051 assembler, and an RS-232 to JTAG serial adapter . It also has a tar get application
board with the associated MCU installed, plus the RS-232 and JTAG cables, and wall-mount power supply. The
Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port. As shown
in
Figure 1.8, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial
Adapter to the user's application board, picking up the four JTAG pins and VDD and GND. The Serial Adapter takes
its power from the application board; it requires roughly 20
ficient power available from the target system, the provided power supply can be connected directly to the Serial
Adapter.
mA at 2.7-3.6 V. For applications where there is not suf-
-
Silicon Labs’ debug environment is a vastly superior con figuration for developing and debugging embedded applica-
tions compared to standard MCU emulators, which use on-board "ICE Chips" and target cables and require the MCU
in the application board to be socketed. Silicon Labs' debug environment both increases ease of use and preserves the
performance of the precision analog peripherals.
Figure 1.8. Development/In-System Debug Diagram
Silicon Labs Integrated
Development Environment
WINDOWS 95/98/NT/ME/2000
RS-232
Serial
Adapter
JTAG (x4), VDD, GND
C8051
F020
TARGET PCB
VDD GND
Rev. 1.4 25
C8051F020/1/2/3
1.4. Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F020/2 have 4 additional ports (4, 5,
6, and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the stand ard 8051 with a few enhance
ments.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported .
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparat or outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Con
trol registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for
the particular application.
Figure 1.9)
-
-
Highest
Priority
Lowest
Priority
Port
Latches
(Internal Digital Signals)
UART0
SPI
SMBus
UART1
PCA
Comptr.
Outputs
T0, T1,
T2, T2EX,
T4,T4EX
/INT0,
/INT1
/SYSCLK
CNVSTR
P0
P1
P2
P3
2
4
2
2
6
2
8
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7)
Figure 1.9. Digital Crossbar Diagram
XBR0, XBR1,
XBR2, P1MDIN
Registers
Priority
Decoder
Digital
Crossbar
To External
Memory
Interface
(EMIF)
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
8
8
8
8
P0
I/O
Cells
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
To
ADC1
Input
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority
26 Rev. 1.4
C8051F020/1/2/3
1.5. Programmable Counter Array
The C8051F020 MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five
16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 5 pro
grammable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by
12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the
external oscillator source divided by 8.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software
Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. The
PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port I/O via the Digital Cross
bar.
Figure 1.10. PCA Block Diagram
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
-
-
Capture/Compare
Module 1
CEX1
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4
CEX4
ECI
Capture/Compare
Module 0
CEX0
Crossbar
Port I/O
1.6. Serial Ports
The C8051F020 MCU Family includes two Enhanced Full-Duplex UARTs, SPI Bus, and SMBus/I2C. Each of the
serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very
little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any
or all of the serial buses may be used together with any other.
Rev. 1.4 27
C8051F020/1/2/3
1.7. 12-Bit Analog to Digital Converter
The C8051F020/1 has an on-chip 12-bit SAR ADC (ADC0) with a 9-chann el input multiplexer and programmable
gain amplifier. W ith a maximum throughput of 100
C8051F022/3 devices include a 10-bit SAR ADC with similar specifications and configuration options. The ADC0
voltage reference is selected between the DAC0 output and an external VREF pin. O n C8051F0 20/2 devices, AD C0
has its own dedicated VREF0 input pin; on C8051F021/3 devices, the ADC0 shares the VREFA input pin with the 8-
bit ADC1. The on-chip 15
ppm/°C voltage reference may generate the voltage reference for other system components
or the on-chip ADCs via the VREF output p in.
The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers. One input
channel is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of
the eight external input channels can be configured as either two single-ended inputs or a single differential input.
The system controller can also put the ADC into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in
powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input
voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in differential mode, a DAC
could be used to provide the DC offset).
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of Timer 3, or an
external signal input. This flexibility allows the start of c onversion to be triggered by software events, external HW
signals, or a periodic timer overflow signal. Conversion completions are indicated by a status bit and an interrupt (i f
enabled). The resulting 10 or 12-bit data word is latched into two SFRs upon com pletion of a conversion. The data
can be right or left justified in these registers under software control.
ksps, the ADC offers true 12-bit accuracy with an INL of ±1LSB.
Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within
or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not inter
rupt the controller unless the converted data is within the specified window.
Figure 1.11. 12-Bit ADC Block Diagram
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
Analog Multiplexer
TEMP
SENSOR
AGND
+
-
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
Configuration, Control, and Data
Programmable Gain
Amplifie r
AV+
+
X
-
External VREF
DAC0 Output
Registers
Pin
12-Bit
SAR
ADC
VREF
Start
Conversion
Window Compare
Logic
12
Write to AD0BUSY
Timer 3 Overflow
CNVSTR
Timer 2 Overflow
Compare
ADC Data
Registers
Conversion
Complete
Window
Interrupt
Interrupt
-
28 Rev. 1.4
C8051F020/1/2/3
1.8. 8-Bit Analog to Digital Converter
The C8051F020/1/2/3 has an on-board 8-bit SAR ADC (ADC1) with an 8-channel input multiplexer and program ma-
ble gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit accuracy with an INL of
±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microco ntroller
via the Special Function Registers. The ADC1 voltage reference is selected between the analog power supply (AV+)
and an external VREF pin. On C8051F020/2 devices, ADC1 has its o wn dedicated VREF1 input pin; on
C8051F021/3 devices, ADC1 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC1
into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when differ-
ent ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal
with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set
in software to 0.5, 1, 2, or 4.
A flexible conversion scheduling system allows ADC1 conversi ons to be initiated by software commands, timer
overflows, or an external input signal. ADC1 conversions may also be synchronized with ADC0 software-com
manded conversions. Conversion completions are indicated by a status bit and an interrupt (i f enabled), and the
resulting 8-bit data word is latched into an SFR upon completion.
Figure 1.12. 8-Bit ADC Diagram
-
AIN1.0
AIN1.1
AIN1.2
AIN1.3
AIN1.4
AIN1.5
AIN1.6
AIN1.7
Analog Multiplexer
8-to-1
AMUX
Configuration, Control, and Data Registers
Programmable Gain
Amplifier
AV+
+
X
-
External VREF
AV+
Pin
8-Bit
SAR
ADC
Start Conversion
VREF
Conversion
Complete
8
ADC Data
Register
Interrupt
Write to AD1BUSY
Timer 3 Overflow
CNVSTR Input
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Rev. 1.4 29
C8051F020/1/2/3
1.9. Comparators and DACs
Each C8051F020/1/2/3 MCU has two 12-bit DACs and two comparators on chip. The MCU data and control inter-
face to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator
in low power shutdown mode.
The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising
edge, falling edge, or both; these interrupts are capable of waking up the MCU from sleep mode. The comparators'
output state can also be polled in software. The comparator outputs can be programmed to appear on the Port I/O pins
via the Crossbar.
The DACs are voltage output mode, and include a flexible output scheduling mechanism. This scheduling mecha-
nism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage
reference is supplied via the dedicated VREFD input pin on C8051F020/2 devices or via the internal voltage refer
ence on C8051F021/3 devices. The DACs are especially useful as references for the comparators or offsets for the
differential inputs of the ADC.
Figure 1.13. Comparator and DAC Diagram
-
(Port I/O)
(Port I/O)
CP0+
CP0-
CP1+
CP1-
DAC0
DAC1
CP0
CP1
+
CP0
-
+
CP1
-
REF
DAC0
REF
DAC1
CROSSBAR
CP0
CP1
SFR's
(Data
and
Cntrl)
CIP-51
and
Interrupt
Handler
30 Rev. 1.4
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