Silicon Laboratories C8051F010 User Manual

C8051F000/1/2/5/6/7

a
ANALOG PERIPHERALS

- SAR ADC

 12-Bit (C8051F000/1/2, C8051F005/6/7)
 10-bit (C8051F010/1/2, C8051F015/6/7)
 ±1LSB INL; No Missing Codes
 Programmable Throughput up to 100ksps
 Up to 8 External Inputs; Programmable as Single-

- Two 12-bit DACs

- Two Analog Comparators

- Voltage Reference

- Precision VDD Monitor/Brown-out Detector

ON-CHIP JTAG DEBUG & BOUNDARY SCAN

- On-Chip Debug Circuitry Facilitates Full Speed, Non-

- Provides Breakpoints, Single Stepping, Watchpoints, Stack

- Inspect/Modify Memory and Registers

- Superior Performance to Emulation Systems Using ICE-

- IEEE1149.1 Compliant Boundary Scan

- Low Cost Development Kit

Ended or Differential

 Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
 Data Dependent Windowed Interrupt Generator
 Built-in Temperature Sensor (± 3°C)

 Programmable Hysteresis Values
 Configurable to Generate Interrupts or Reset

 2.4V; 15 ppm/°C
 Available on External Pin

Intrusive In-System Debug (No Emulator Required!)

Monitor

Chips, Target Pods, and Sockets

Mixed-Signal 32KB ISP FLASH MCU Family

C8051F010/1/2/5/6/7

HIGH SPEED 8051 µC CORE

- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks

- Up to 25MIPS Throughput with 25MHz Clock

- 21 Vectored Interrupt Sources

MEMORY

- 256 Bytes Internal Data RAM (F000/01/02/10/11/12)

- 2304 Bytes Internal Data RAM (F005/06/07/15/16/17)

- 32k Bytes FLASH; In-System Programmable in 512 byte

Sectors

DIGITAL PERIPHERALS

- 4 Byte-Wide Port I/O; All are 5V tolerant

- Hardware SMBus

Serial Ports Available Concurrently

- Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules

- Four General Purpose 16-bit Counter/Timers

- Dedicated Watch-Dog Timer

- Bi-directional Reset

CLOCK SOURCES

- Internal Programmable Oscillator: 2-to-16MHz

- External Oscillator: Crystal, RC,C, or Clock

- Can Switch Between Clock Sources on-the-fly; Useful in

Power Saving Modes

SUPPLY VOLTAGE ........................2.7V to 3.6V

- Typical Operating Current: 12.5mA @ 25MHz

- Multiple Power Saving Sleep and Shutdown Modes

64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40°C to +85°C

TM

(I2CTM Compatible), SPITM, and UART

ANALOG PERIPHERALS

TEMP

SENSOR

PGA

AMUX

VREF

SAR

ADC

12-Bit

DAC

12-Bit

DAC

+

-

COMPARATORS

+

-

VOLTAGE

DIGITAL I/O

PCA

SMBus

SPI Bus

UART

Timer 0

Timer 1

Timer 2

Timer 3

CROSSBAR

Port 0Port 1

Port 2Port 3

HIGH-SPEED CONTROLLER CORE

8051 CPU

(25MIPS)

32KB

ISP FLASH

CLOCK

CIRCUIT

256/2304 B

SRAM

JTAG

21

INTERRUPTS

DEBUG

CIRCUITRY

SANITY

CONTROL

Rev. 1.7 11/03 Copyright © 2003 by Silicon Laboratories

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

TABLE OF CONTENTS

1. SYSTEM OVERVIEW........................................................................................................8

Table 1.1. Product Selection Guide ...................................................................................................................8

Figure 1.1. C8051F000/05/10/15 Block Diagram .............................................................................................9

Figure 1.2. C8051F001/06/11/16 Block Diagram ...........................................................................................10

Figure 1.3. C8051F002/07/12/17 Block Diagram ...........................................................................................11

1.1. CIP-51TM CPU .......................................................................................................................................12

Figure 1.4. Comparison of Peak MCU Execution Speeds...............................................................................12

Figure 1.5. On-Board Clock and Reset............................................................................................................13

1.2. On-Board Memory.................................................................................................................................14

Figure 1.6. On-Board Memory Map................................................................................................................14

1.3. JTAG Debug and Boundary Scan..........................................................................................................15

Figure 1.7. Debug Environment Diagram .......................................................................................................15

1.4. Programmable Digital I/O and Crossbar ...............................................................................................16

Figure 1.8. Digital Crossbar Diagram..............................................................................................................16

1.5. Programmable Counter Array................................................................................................................17

Figure 1.9. PCA Block Diagram .....................................................................................................................17

1.6. Serial Ports.............................................................................................................................................17

1.7. Analog to Digital Converter ..................................................................................................................18

Figure 1.10. ADC Diagram .............................................................................................................................18

1.8. Comparators and DACs.........................................................................................................................19

Figure 1.11. Comparator and DAC Diagram...................................................................................................19

2. ABSOLUTE MAXIMUM RATINGS*.............................................................................20

3. GLOBAL DC ELECTRICAL CHARACTERISTICS...................................................20

4. PINOUT AND PACKAGE DEFINITIONS ....................................................................21

Table 4.1. Pin Definitions................................................................................................................................21

Figure 4.1. TQFP-64 Pinout Diagram .............................................................................................................23

Figure 4.2. TQFP-64 Package Drawing ..........................................................................................................24

Figure 4.3. TQFP-48 Pinout Diagram .............................................................................................................25

Figure 4.4. TQFP-48 Package Drawing ..........................................................................................................26

Figure 4.5. LQFP-32 Pinout Diagram .............................................................................................................27

Figure 4.6. LQFP-32 Package Drawing ..........................................................................................................28

5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only).........................................................................29

Figure 5.1. 12-Bit ADC Functional Block Diagram........................................................................................29

5.1. Analog Multiplexer and PGA................................................................................................................29

5.2. ADC Modes of Operation......................................................................................................................30

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing...................................................................30

Figure 5.3. Temperature Sensor Transfer Function.........................................................................................31

Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) ............................................................31

Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)...........................................................32

Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x).................................................................33

Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) ..........................................................................34

Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) .............................................................35

Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)...............................................................35

5.3. ADC Programmable Window Detector.................................................................................................36

Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x) ..................................36

Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x) ...................................36

Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x) .......................................36

Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x).........................................36

Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data.................................................37

Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................37

Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................38

Rev. 1.7 2

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................38

Table 5.1. 12-Bit ADC Electrical Characteristics............................................................................................39

6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only).........................................................................40

Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................40

6.1. Analog Multiplexer and PGA................................................................................................................40

6.2. ADC Modes of Operation......................................................................................................................41

Figure 6.2. 10-Bit ADC Track and Conversion Example Timing...................................................................41

Figure 6.3. Temperature Sensor Transfer Function.........................................................................................42

Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) ............................................................42

Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)...........................................................43

Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x).................................................................44

Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) ..........................................................................45

Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) .............................................................46

Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)...............................................................46

6.3. ADC Programmable Window Detector.................................................................................................47

Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x) ..................................47

Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x) ...................................47

Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x) .......................................47

Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x).........................................47

Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data.................................................48

Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................48

Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ...................................................49

Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................49

Table 6.1. 10-Bit ADC Electrical Characteristics............................................................................................50

7. DACs, 12 BIT VOLTAGE MODE....................................................................................51

Figure 7.1. DAC Functional Block Diagram....................................................................................................51

Figure 7.2. DAC0H: DAC0 High Byte Register .............................................................................................52

Figure 7.3. DAC0L: DAC0 Low Byte Register ..............................................................................................52

Figure 7.4. DAC0CN: DAC0 Control Register...............................................................................................52

Figure 7.5. DAC1H: DAC1 High Byte Register .............................................................................................53

Figure 7.6. DAC1L: DAC1 Low Byte Register ..............................................................................................53

Figure 7.7. DAC1CN: DAC1 Control Register...............................................................................................53

Table 7.1. DAC Electrical Characteristics.......................................................................................................54

8. COMPARATORS ..............................................................................................................55

Figure 8.1. Comparator Functional Block Diagram ........................................................................................55

Figure 8.2. Comparator Hysteresis Plot...........................................................................................................56

Figure 8.3. CPT0CN: Comparator 0 Control Register ....................................................................................57

Figure 8.4. CPT1CN: Comparator 1 Control Register ....................................................................................58

Table 8.1. Comparator Electrical Characteristics ............................................................................................59

9. VOLTAGE REFERENCE ................................................................................................60

Figure 9.1. Voltage Reference Functional Block Diagram .............................................................................60

Figure 9.2. REF0CN: Reference Control Register ..........................................................................................61

Table 9.1. Reference Electrical Characteristics ...............................................................................................61

10. CIP-51 CPU.........................................................................................................................62

Figure 10.1. CIP-51 Block Diagram................................................................................................................62

10.1. INSTRUCTION SET.........................................................................................................................63

Table 10.1. CIP-51 Instruction Set Summary..................................................................................................65

10.2. MEMORY ORGANIZATION..........................................................................................................68

Figure 10.2. Memory Map...............................................................................................................................69

10.3. SPECIAL FUNCTION REGISTERS................................................................................................70

Table 10.2. Special Function Register Memory Map......................................................................................70

Table 10.3. Special Function Registers ...........................................................................................................70

Figure 10.3. SP: Stack Pointer.........................................................................................................................74

Figure 10.4. DPL: Data Pointer Low Byte ......................................................................................................74

3 Rev. 1.7

C8051F000/1/2/5/6/7

Figure 10.5. DPH: Data Pointer High Byte .....................................................................................................74

Figure 10.6. PSW: Program Status Word........................................................................................................75

Figure 10.7. ACC: Accumulator......................................................................................................................76

Figure 10.8. B: B Register ...............................................................................................................................76

10.4. INTERRUPT HANDLER .................................................................................................................77

Table 10.4. Interrupt Summary........................................................................................................................78

Figure 10.9. IE: Interrupt Enable.....................................................................................................................79

Figure 10.10. IP: Interrupt Priority..................................................................................................................80

Figure 10.11. EIE1: Extended Interrupt Enable 1 ...........................................................................................81

Figure 10.12. EIE2: Extended Interrupt Enable 2 ...........................................................................................82

Figure 10.13. EIP1: Extended Interrupt Priority 1 ..........................................................................................83

Figure 10.14. EIP2: Extended Interrupt Priority 2 ..........................................................................................84

10.5. Power Management Modes ...............................................................................................................85

Figure 10.15. PCON: Power Control Register ................................................................................................86

C8051F010/1/2/5/6/7

11. FLASH MEMORY.............................................................................................................87

11.1. Programming The Flash Memory......................................................................................................87

Table 11.1. FLASH Memory Electrical Characteristics..................................................................................87

11.2. Non-volatile Data Storage .................................................................................................................88

11.3. Security Options ................................................................................................................................88

Figure 11.1. PSCTL: Program Store RW Control...........................................................................................88

Figure 11.2. Flash Program Memory Security Bytes .......................................................................................89

Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) ...............................................90

Figure 11.4. FLSCL: Flash Memory Timing Prescaler ...................................................................................91

12. EXTERNAL RAM (C8051F005/06/07/15/16/17).............................................................92

Figure 12.1. EMI0CN: External Memory Interface Control ...........................................................................92

13. RESET SOURCES .............................................................................................................93

Figure 13.1. Reset Sources Diagram ...............................................................................................................93

13.1. Power-on Reset..................................................................................................................................94

13.2. Software Forced Reset.......................................................................................................................94

Figure 13.2. VDD Monitor Timing Diagram ..................................................................................................94

13.3. Power-fail Reset.................................................................................................................................94

13.4. External Reset....................................................................................................................................95

13.5. Missing Clock Detector Reset ...........................................................................................................95

13.6. Comparator 0 Reset ...........................................................................................................................95

13.7. External CNVSTR Pin Reset.............................................................................................................95

13.8. Watchdog Timer Reset ......................................................................................................................95

Figure 13.3. WDTCN: Watchdog Timer Control Register .............................................................................96

Figure 13.4. RSTSRC: Reset Source Register.................................................................................................97

Table 13.1. Reset Electrical Characteristics ....................................................................................................98

14. OSCILLATOR ...................................................................................................................99

Figure 14.1. Oscillator Diagram ......................................................................................................................99

Figure 14.2. OSCICN: Internal Oscillator Control Register .........................................................................100

Table 14.1. Internal Oscillator Electrical Characteristics ..............................................................................100

Figure 14.3. OSCXCN: External Oscillator Control Register.......................................................................101

14.1. External Crystal Example ................................................................................................................102

14.2. External RC Example ......................................................................................................................102

14.3. External Capacitor Example ............................................................................................................102

15. PORT INPUT/OUTPUT..................................................................................................103

15.1. Priority Cross Bar Decoder..............................................................................................................103

15.2. Port I/O Initialization.......................................................................................................................103

Figure 15.1. Port I/O Functional Block Diagram ..........................................................................................104

Figure 15.2. Port I/O Cell Block Diagram.....................................................................................................104

Table 15.1. Crossbar Priority Decode ...........................................................................................................105

Figure 15.3. XBR0: Port I/O CrossBar Register 0 ........................................................................................106

Rev. 1.7 4

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 15.4. XBR1: Port I/O CrossBar Register 1 ........................................................................................107

Figure 15.5. XBR2: Port I/O CrossBar Register 2 ........................................................................................108

15.3. General Purpose Port I/O.................................................................................................................109

15.4. Configuring Ports Which are not Pinned Out..................................................................................109

Figure 15.6. P0: Port0 Register .....................................................................................................................109

Figure 15.7. PRT0CF: Port0 Configuration Register ....................................................................................109

Figure 15.8. P1: Port1 Register .....................................................................................................................110

Figure 15.9. PRT1CF: Port1 Configuration Register ....................................................................................110

Figure 15.10. PRT1IF: Port1 Interrupt Flag Register....................................................................................110

Figure 15.11. P2: Port2 Register ...................................................................................................................111

Figure 15.12. PRT2CF: Port2 Configuration Register ..................................................................................111

Figure 15.13. P3: Port3 Register ...................................................................................................................112

Figure 15.14. PRT3CF: Port3 Configuration Register ..................................................................................112

Table 15.2. Port I/O DC Electrical Characteristics........................................................................................112

16. SMBus / I2C Bus...............................................................................................................113

Figure 16.1. SMBus Block Diagram .............................................................................................................113

Figure 16.2. Typical SMBus Configuration ..................................................................................................114

16.1. Supporting Documents ....................................................................................................................114

16.2. Operation .........................................................................................................................................115

Figure 16.3. SMBus Transaction...................................................................................................................115

16.3. Arbitration .......................................................................................................................................116

16.4. Clock Low Extension ......................................................................................................................116

16.5. Timeouts ..........................................................................................................................................116

16.6. SMBus Special Function Registers..................................................................................................116

Figure 16.4. SMB0CN: SMBus Control Register ..........................................................................................118

Figure 16.5. SMB0CR: SMBus Clock Rate Register....................................................................................119

Figure 16.6. SMB0DAT: SMBus Data Register ...........................................................................................120

Figure 16.7. SMB0ADR: SMBus Address Register .....................................................................................120

Figure 16.8. SMB0STA: SMBus Status Register..........................................................................................121

Table 16.1. SMBus Status Codes ..................................................................................................................122

17. SERIAL PERIPHERAL INTERFACE BUS.................................................................123

Figure 17.1. SPI Block Diagram ...................................................................................................................123

Figure 17.2. Typical SPI Interconnection......................................................................................................124

17.1. Signal Descriptions..........................................................................................................................124

17.2. Operation .........................................................................................................................................125

Figure 17.3. Full Duplex Operation...............................................................................................................125

17.3. Serial Clock Timing.........................................................................................................................126

Figure 17.4. Data/Clock Timing Diagram.....................................................................................................126

17.4. SPI Special Function Registers........................................................................................................127

Figure 17.5. SPI0CFG: SPI Configuration Register......................................................................................127

Figure 17.6. SPI0CN: SPI Control Register ..................................................................................................128

Figure 17.7. SPI0CKR: SPI Clock Rate Register..........................................................................................129

Figure 17.8. SPI0DAT: SPI Data Register ....................................................................................................129

18. UART.................................................................................................................................130

Figure 18.1. UART Block Diagram ..............................................................................................................130

18.1. UART Operational Modes...............................................................................................................131

Table 18.1. UART Modes .............................................................................................................................131

Figure 18.2. UART Mode 0 Interconnect......................................................................................................131

Figure 18.3. UART Mode 0 Timing Diagram...............................................................................................131

Figure 18.4. UART Mode 1 Timing Diagram...............................................................................................132

Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ......................................................................133

Figure 18.6. UART Modes 2 and 3 Timing Diagram....................................................................................134

18.2. Multiprocessor Communications.....................................................................................................135

Figure 18.7. UART Multi-Processor Mode Interconnect Diagram ...............................................................135

5 Rev. 1.7

C8051F000/1/2/5/6/7

Table 18.2. Oscillator Frequencies for Standard Baud Rates ........................................................................136

Figure 18.8. SBUF: Serial (UART) Data Buffer Register.............................................................................136

Figure 18.9. SCON: Serial Port Control Register..........................................................................................137

C8051F010/1/2/5/6/7

19. TIMERS ............................................................................................................................138

19.1. Timer 0 and Timer 1........................................................................................................................138

Figure 19.1. T0 Mode 0 Block Diagram........................................................................................................139

Figure 19.2. T0 Mode 2 Block Diagram........................................................................................................140

Figure 19.3. T0 Mode 3 Block Diagram........................................................................................................141

Figure 19.4. TCON: Timer Control Register.................................................................................................142

Figure 19.5. TMOD: Timer Mode Register...................................................................................................143

Figure 19.6. CKCON: Clock Control Register..............................................................................................144

Figure 19.7. TL0: Timer 0 Low Byte ............................................................................................................145

Figure 19.8. TL1: Timer 1 Low Byte ............................................................................................................145

Figure 19.9. TH0: Timer 0 High Byte ...........................................................................................................145

Figure 19.10. TH1: Timer 1 High Byte .........................................................................................................145

19.2. Timer 2 ............................................................................................................................................146

Figure 19.11. T2 Mode 0 Block Diagram......................................................................................................147

Figure 19.12. T2 Mode 1 Block Diagram......................................................................................................148

Figure 19.13. T2 Mode 2 Block Diagram......................................................................................................149

Figure 19.14. T2CON: Timer 2 Control Register..........................................................................................150

Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte ......................................................................151

Figure 19.16. RCAP2H: Timer 2 Capture Register High Byte .....................................................................151

Figure 19.17. TL2: Timer 2 Low Byte ..........................................................................................................151

Figure 19.18. TH2: Timer 2 High Byte .........................................................................................................151

19.3. Timer 3 ............................................................................................................................................152

Figure 19.19. Timer 3 Block Diagram...........................................................................................................152

Figure 19.20. TMR3CN: Timer 3 Control Register ......................................................................................152

Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte ....................................................................153

Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ...................................................................153

Figure 19.23. TMR3L: Timer 3 Low Byte ....................................................................................................153

Figure 19.24. TMR3H: Timer 3 High Byte...................................................................................................153

20. PROGRAMMABLE COUNTER ARRAY....................................................................154

Figure 20.1. PCA Block Diagram .................................................................................................................154

20.1. Capture/Compare Modules..............................................................................................................155

Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules ...........................................155

Figure 20.2. PCA Interrupt Block Diagram...................................................................................................155

Figure 20.3. PCA Capture Mode Diagram ....................................................................................................156

Figure 20.4. PCA Software Timer Mode Diagram........................................................................................157

Figure 20.5. PCA High Speed Output Mode Diagram..................................................................................157

Figure 20.6. PCA PWM Mode Diagram .......................................................................................................158

20.2. PCA Counter/Timer.........................................................................................................................159

Table 20.2. PCA Timebase Input Options.....................................................................................................159

Figure 20.7. PCA Counter/Timer Block Diagram.........................................................................................159

20.3. Register Descriptions for PCA ........................................................................................................160

Figure 20.8. PCA0CN: PCA Control Register ...............................................................................................160

Figure 20.9. PCA0MD: PCA Mode Register ................................................................................................161

Figure 20.10. PCA0CPMn: PCA Capture/Compare Registers......................................................................162

Figure 20.11. PCA0L: PCA Counter/Timer Low Byte .................................................................................163

Figure 20.12. PCA0H: PCA Counter/Timer High Byte ................................................................................163

Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte........................................................................163

Figure 20.14. PCA0CPHn: PCA Capture Module High Byte.......................................................................163

21. JTAG (IEEE 1149.1) ........................................................................................................164

Figure 21.1. IR: JTAG Instruction Register ..................................................................................................164

21.1. Boundary Scan.................................................................................................................................165

Rev. 1.7 6

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Table 21.1. Boundary Data Register Bit Definitions.....................................................................................165

Figure 21.2. DEVICEID: JTAG Device ID Register ....................................................................................166

21.2. Flash Programming Commands.......................................................................................................167

Figure 21.3. FLASHCON: JTAG Flash Control Register.............................................................................168

Figure 21.4. FLASHADR: JTAG Flash Address Register............................................................................168

Figure 21.5. FLASHDAT: JTAG Flash Data Register..................................................................................169

Figure 21.6. FLASHSCL: JTAG Flash Scale Register .................................................................................169

21.3. Debug Support.................................................................................................................................170

7 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1. SYSTEM OVERVIEW

The C8051F000 family are fully integrated mixed-signal System on a Chip MCUs with a true 12-bit multi-channel
ADC (F000/01/02/05/06/07), or a true 10-bit multi-channel ADC (F010/11/12/15/16/17). See the Product Selection
Guide in Table 1.1 for a quick reference of each MCUs’ feature set. Each has a programmable gain pre-amplifier,
two 12-bit DACs, two voltage comparators (except for the F002/07/12/17, which have one), a voltage reference,
and an 8051-compatible microcontroller core with 32kbytes of FLASH memory. There are also I2C/SMBus,
UART, and SPI serial interfaces implemented in hardware (not “bit-banged” in user software) as well as a
Programmable Counter/Timer Array (PCA) with five capture/compare modules. There are also 4 general-purpose
16-bit timers and 4 byte-wide general-purpose digital Port I/O. The C8051F000/01/02/10/11/12 have 256 bytes of
RAM and execute up to 20MIPS, while the C8051F005/06/07/15/16/17 have 2304 bytes of RAM and execute up to
25MIPS.

With an on-board VDD monitor, WDT, and clock oscillator, the MCUs are truly stand-alone System-on-a-Chip
solutions. Each MCU effectively configures and manages the analog and digital peripherals. The FLASH memory
can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the
8051 firmware. Each MCU can also individually shut down any or all of the peripherals to conserve power.

On-board JTAG debug support allows non-intrusive (uses no on-chip resources), full speed, in-circuit debug using
the production MCU installed in the final application. This debug system supports inspection and modification of
memory and registers, setting breakpoints, watchpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional when using JTAG debug.

Each MCU is specified for 2.7V-to-3.6V operation over the industrial temperature range (-45C to +85C). The Port
I/Os, /RST, and JTAG pins are tolerant for input signals up to 5V. The C8051F000/05/10/15 are available in the
64-pin TQFP (see block diagram in Figure 1.1). The C8051F001/06/11/16 are available in the 48-pin TQFP (see
block diagram in Figure 1.2). The C8051F002/07/12/17 are available in the 32-pin LQFP (see block diagram in
Figure 1.3).

Table 1.1. Product Selection Guide

C8051F000 20 32k 256

C8051F001 20 32k 256

C8051F002 20 32k 256

C8051F005 25 32k 2304

C8051F006 25 32k 2304

C8051F007 25 32k 2304

C8051F010 20 32k 256

C8051F011 20 32k 256

C8051F012 20 32k 256

C8051F015 25 32k 2304

C8051F016 25 32k 2304

C8051F017 25 32k 2304

MIPS (Peak)

FLASH Memory

RAM

SMBus/I2C

SPI

√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √
√ √ √

UART

4

4

4

4

4

4

4

4

4

4

4

4

Timers (16-bit)

Programmable Counter Array

Digital Port I/O’s

ADC Resolution (bits)

ADC Max Speed (ksps)

ADC Inputs

Voltage Reference

Temperature Sensor

DAC Resolution

DAC Outputs

Voltage Comparators

Package

32 12 100 8

√

16 12 100 8

√

8 12 100 4

√

32 12 100 8

√

16 12 100 8

√

8 12 100 4

√

32 10 100 8

√

16 10 100 8

√

8 10 100 4

√

32 10 100 8

√

16 10 100 8

√

8 10 100 4

√

√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √
√ √

12 2 2 64TQFP

12 2 2 48TQFP

12 2 1 32LQFP

12 2 2 64TQFP

12 2 2 48TQFP

12 2 1 32LQFP

12 2 2 64TQFP

12 2 2 48TQFP

12 2 1 32LQFP

12 2 2 64TQFP

12 2 2 48TQFP

12 2 1 32LQFP

Rev. 1.7 8

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 1.1. C8051F000/05/10/15 Block Diagram

VDD
VDD

VDD
DGND
DGND
DGND

AV+

AV+
AGND
AGND

TCK

TMS

TDI

TDO

/RST

XTAL1
XTAL2

VREF

DAC0

DAC1

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

CP0+

CP0-

CP1+

CP1-

Digital Power

Analog Power

VREF

JTAG
Logic

VDD

Monitor

External

Oscillator

Circuit

Internal

Oscillator

DAC0

(12-Bit)

DAC1

(12-Bit)

Boundary Scan

Debug HW

WDT

System Clock

Reset

8

0

5

1

C

o

r

e

32kbyte

FLASH

256 byte

RAM

2048 byte

XRAM

(F005/15 only)

SFR Bus

UART

SMBus

SPI Bus

PCA

Timers

0,1,2

Timer 3

Port 0
Latch

Port 1
Latch

Port 2
Latch

Port 3
Latch

C

R

O

S

S

B

A

R

S

W

I

T

C

H

A
M
U
X

CP0

CP1

Prog
Gain

TEMP

ADC

100ksps

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P
3

D

r

v

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

9 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 1.2. C8051F001/06/11/16 Block Diagram

VDD

VDD

DGND
DGND
DGND
DGND

AV+

AV+

AGND
AGND

TCK

TMS

TDI

TDO

/RST

XTAL1
XTAL2

VREF

DAC0

DAC1

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

CP0+

CP0-

CP1+

CP1-

Digital Power

Analog Power

VREF

JTAG
Logic

VDD

Monitor

External

Oscillator

Circuit

Internal

Oscillator

DAC0

(12-Bit)

DAC1

(12-Bit)

Boundary Scan

Debug HW

WDT

Reset

System Clock

8

0

5

1

C

o

r

e

32kbyte

FLASH

256 byte

RAM

2048 byte

XRAM

(F006/16 only)

SFR Bus

UART

SMBus

SPI Bus

PCA

Timers

0,1,2

Timer 3

Port 0

Latch

Port 1

Latch

Port 2

Latch

Port 3

Latch

C

R

O

S

S

B

A

R

S

W

I

T

C

H

A
M
U
X

CP0

CP1

Prog
Gain

TEMP

ADC

100ksps

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P
3

D

r

v

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

Rev. 1.7 10

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 1.3. C8051F002/07/12/17 Block Diagram

VDD

VDD

DGND
DGND

AV+

AV+

AGND
AGND

TCK

TMS

TDI

TDO

/RST

XTAL1
XTAL2

VREF

DAC0

DAC1

AIN0
AIN1
AIN2
AIN3

CP0+

CP0-

Digital Power

Analog Power

VREF

A
M
U
X

JTAG
Logic

VDD

Monitor

External

Oscillator

Circuit

Internal

Oscillator

DAC0

(12-Bit)

DAC1

(12-Bit)

Prog
Gain

CP0

CP1

Boundary Scan

Debug HW

WDT

TEMP

System Clock

ADC

100ksps

Reset

8

0

5

1

C

o

r

e

32kbyte

FLASH

256 byte

RAM

2048 byte

XRAM

(F007/17 only)

SFR Bus

UART

SMBus

SPI Bus

PCA

Timers

0,1,2

Timer 3

Port 0

Latch

Port 1

Latch

Port 2

Latch

Port 3

Latch

C

R

O

S

S

B

A

R

S

W

I

T

C

H

P
0

D

r
v

P
1

D

r
v

P
2

D

r
v

P
3

D

r
v

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

11 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.1. CIP-51TM CPU

1.1.1. Fully 8051 Compatible

The C8051F000 family utilizes Silicon Laboratories’ proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51
develop software. The core has all the peripherals included with a standard 8052, including four 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR)
address space, and four byte-wide I/O Ports.

1.1.2. Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz. By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.

The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:

Instructions

Clocks to Execute

With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.

TM

instruction set. Standard 803x/805x assemblers and compilers can be used to

26 50 5 14 7 3 1 2 1

1 2 2/3 3 3/4 4 4/5 5 8

Figure 1.4. Comparison of Peak MCU Execution Speeds

25

20

15

MIPS

10

5

Silicon Labs

CIP-51

(25MHz clk)

Microchip

PIC17C75x

(33MHz clk)

Philips

80C51

(33MHz clk)

ADuC812

8051

(16MHz clk)

Rev. 1.7 12

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.1.3. Additional Features

The C8051F000 MCU family has several key enhancements both inside and outside the CIP-51 core to improve its
overall performance and ease of use in the end applications.

The extended interrupt handler provides 21 interrupt sources into the CIP-51 (as opposed to 7 for the standard

8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system
requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very
useful when building multi-tasking, real-time systems.

There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator 0, a forced software reset, the CNVSTR pin, and the /RST pin.
The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be
output on the /RST pin. Each reset source except for the VDD monitor and Reset Input Pin may be disabled by the
user in software. The WDT may be permanently enabled in software after a power-on reset during MCU
initialization.

The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset.
If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic
resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low
power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically
switching to the fast (up to 16MHz) internal oscillator as needed.

Figure 1.5. On-Board Clock and Reset

(Port

I/O)

Crossbar

CP0+

CP0-

CNVSTR

(CNVSTR

reset

enable)

Comparator 0

+

-

(CP0

reset

enable)

Missing

Detector

Internal

Clock

XTAL1

XTAL2

Generator

OSC

System
Clock

Clock Select

VDD

WDT

WDT

EN

Enable

Clock

(one-

shot)

EN

MCD

Enable

CIP-51

Microcontroller

Core

Supply
Monitor

+

-

PRE

WDT

Supply

Reset

Timeout

Strobe

Software Reset

System Reset

(wired-OR)

Reset
Funnel

/RST

Extended Interrupt

Handler

13 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.2. On-Board Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with
the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and
direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct
and indirect addressing. The first 32 bytes are addressable as four banks of general-purpose registers, and the next
16 bytes can be byte addressable or bit addressable.

The CIP-51 in the C8051F005/06/07/15/16/17 MCUs additionally has a 2048 byte RAM block in the external data
memory address space. This 2048 byte block can be addressed over the entire 64k external data memory address
range (see Figure 1.6).

The MCU’s program memory consists of 32k + 128 bytes of FLASH. This memory may be reprogrammed in­system in 512 byte sectors, and requires no special off-chip programming voltage. The 512 bytes from addresses
0x7E00 to 0x7FFF are reserved for factory use. There is also a single 128-byte sector at address 0x8000 to 0x807F,
which may be useful as a small table for software constants or as additional program space. See Figure 1.6 for the
MCU system memory map.

Figure 1.6. On-Board Memory Map

0x807F

0x8000

0x7FFF

0x7E00

0x7DFF

0x0000

PROGRAM MEMORY

128 Byte ISP FLASH

RESERVED

FLASH

(In-System

Programmable in 512

Byte Sectors)

0xFF

0x80
0x7F

0x30

0x2F

0x20

0x1F

0x00

DATA MEMORY

INTERNAL DATA ADDRESS SPACE

Upper 128 RAM

(Indirect Addressing

Only)

(Direct and Indirect

Addressing)

Bit Addressable

General Purpose

Registers

Special Function

Register's

(Direct Addressing Only)

Lower 128 RAM
(Direct and Indirect
Addressing)

EXTERNAL DATA ADDRESS SPACE

0xFFFF

0xF800

0x17FF

0x1000

0x0FFF

0x0800

0x07FF

0x0000

(same 2048 byte RAM block )

(same 2048 byte RAM block )

(same 2048 byte RAM block )

RAM - 2048 Bytes

(accessable using MOVX

instruction)

The same 2048 byte RAM
block can be addressed on
2k boundaries throughout
the 64k External Data
Memory space.

Rev. 1.7 14

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.3. JTAG Debug and Boundary Scan

The C8051F000 family has on-chip JTAG and debug circuitry that provide non-intrusive, full speed, in-circuit
debug using the production part installed in the end application using the four-pin JTAG I/F. The JTAG port is

fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing purposes.

Silicon Labs’ debug system supports inspection and modification of memory and registers, breakpoints,
watchpoints, a stack monitor, and single stepping. No additional target RAM, program memory, timers, or
communications channels are required. All the digital and analog peripherals are functional and work correctly
while debugging. All the peripherals (except for the ADC) are stalled when the MCU is halted, during single
stepping, or at a breakpoint in order to keep them in sync.

The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the
hardware and software necessary to develop application code and perform in-circuit debug with the C8051F000/1/2,
F005/6/7, F010/1/2, and F015/6/7 MCUs respectively. The kit includes software with a developer’s studio and
debugger, an integrated 8051 assembler, and an RS-232 to JTAG protocol translator module referred to as the EC.
It also has a target application board with the associated MCU installed and a large prototyping area, plus the RS­232 and JTAG cables, and wall-mount power supply. The Development Kit requires a Windows
95/98/NT/2000/XP computer with one available RS-232 serial port. As shown in Figure 1.7, the PC is connected
via RS-232 to the EC. A six-inch ribbon cable connects the EC to the user’s application board, picking up the four
JTAG pins and VDD and GND. The EC takes its power from the application board. It requires roughly 20mA at

2.7-3.6V. For applications where there is not sufficient power available from the target board, the provided power
supply can be connected directly to the EC.

This is a vastly superior configuration for developing and debugging embedded applications compared to standard
MCU Emulators, which use on-board “ICE Chips” and target cables and require the MCU in the application board
to be socketed. Silicon Labs’ debug environment both increases ease of use and preserves the performance of the
precision analog peripherals.

Figure 1.7. Debug Environment Diagram

TARGET PCB

C8051F000/1/2/5/6/7

C8051F000/1/2/5/6/7

1.4. Programmable Digital I/O and Crossbar

The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. All four ports are pinned out on the
F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and onl

C8051F010/1/2/5/6/7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.5. Programmable Counter Array

The C8051F000 MCU family has an on-board Programmable Counter/Timer Array (PCA) in addition to the four
16-bit general-purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer timebase with 5
programmable capture/compare modules. The timebase gets its clock from one of four sources: the system clock
divided by 12, the system clock divided by 4, Timer 0 overflow, or an External Clock Input (ECI).

Each capture/compare module can be configured to operate in one of four modes: Edge-Triggered Capture,
Software Timer, High Speed Output, or Pulse Width Modulator. The PCA Capture/Compare Module I/O and
External Clock Input are routed to the MCU Port I/O via the Digital Crossbar.

Figure 1.9. PCA Block Diagram

System

Clock

T0 Overflow

/4

/12

16-Bit Counter/Timer

Capture/Compare

Module 0

Capture/Compare

Module 1

Capture/Compare

Module 2

Capture/Compare

Module 3

Capture/Compare

Module 4

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

Crossbar

Port I/O

1.6. Serial Ports

The C8051F000 MCU Family includes a Full-Duplex UART, SPI Bus, and I2C/SMBus. Each of the serial buses is
fully implemented in hardware and makes extensive use of the CIP-51’s interrupts, thus requiring very little
intervention by the CPU. The serial buses do not “share” resources such as timers, interrupts, or Port I/O, so any or
all of the serial buses may be used together.

17 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.7. Analog to Digital Converter

The C8051F000/1/2/5/6/7 has an on-chip 12-bit SAR ADC with a 9-channel input multiplexer and programmable
gain amplifier. With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of
±1LSB. The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum
throughput of 100ksps. Each ADC has an INL of ±1LSB, offering true 12-bit accuracy with the C8051F00x, and
true 10-bit accuracy with the C8051F01x. There is also an on-board 15ppm voltage reference, or an external
reference may be used via the VREF pin.

The ADC is under full control of the CIP-51 microcontroller via the Special Function Registers. One input channel
is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of the
eight external input channels can be configured as either two single-ended inputs or a single differential input. The
system controller can also put the ADC into shutdown to save power.

A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in
powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input
voltage signals, or when it is necessary to “zoom in” on a signal with a large DC offset (in differential mode, a DAC
could be used to provide the DC offset).

Conversions can be started in four ways; a software command, an overflow on Timer 2, an overflow on Timer 3, or
an external signal input. This flexibility allows the start of conversion to be triggered by software events, external
HW signals, or convert continuously. A completed conversion causes an interrupt, or a status bit can be polled in
software to determine the end of conversion. The resulting 10 or 12-bit data word is latched into two SFRs upon
completion of a conversion. The data can be right or left justified in these registers under software control.

Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within a
specified window. The ADC can monitor a key voltage continuously in background mode, but not interrupt the
controller unless the converted data is within the specified window.

Figure 1.10. ADC Diagram

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

(not bonded out on
F002, F007, F012,
and F017

+

-

+

-

+

-

+

-

9-to-1
AMUX
(SE or

DIFF)

SENSOR

TEMP

Programmable

Gain Amp

+

X

-

Control & Data

SFR's

REF

100ksps

SAR

ADC

SFR Bus

VREF

Rev. 1.7 18

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

1.8. Comparators and DACs

The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is
not bonded out on the F002, F007, F012, and F017). The MCU data and control interface to each comparator and
DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown
mode.

The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising
edge, falling edge, or both. The comparators’ output state can also be polled in software. These interrupts are
capable of waking up the MCU from idle mode. The comparator outputs can be programmed to appear on the Port
I/O pins via the Crossbar.

The DACs are voltage output mode and use the same voltage reference as the ADC. They are especially useful as
references for the comparators or offsets for the differential inputs of the ADC.

Figure 1.11. Comparator and DAC Diagram

(Port I/O)

(Port I/O)

CP0

CP1

CROSSBAR

CP0+

CP0-

CP1+

CP1-

DAC0

REF

DAC0

CP0

CP1

SFR's

(Data

and

Cntrl)

CIP-51

and

Interrupt

Handler

DAC1

REF

DAC1

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

2. ABSOLUTE MAXIMUM RATINGS*

Ambient temperature under bias................................................................................................................. -55 to 125°C

Storage Temperature .................................................................................................................................. -65 to 150°C

Voltage on any Pin (except VDD and Port I/O) with respect to DGND...................................-0.3V to (VDD + 0.3V)

Voltage on any Port I/O Pin or /RST with respect to DGND....................................................................-0.3V to 5.8V

Voltage on VDD with respect to DGND...................................................................................................-0.3V to 4.2V

Maximum Total current through VDD, AV+, DGND and AGND.....................................................................800mA

Maximum output current sunk by any Port pin...................................................................................................100mA

Maximum output current sunk by any other I/O pin.............................................................................................25mA

Maximum output current sourced by any Port pin ..............................................................................................100mA

Maximum output current sourced by any other I/O pin ........................................................................................ 25mA

*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the devices at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

3. GLOBAL DC ELECTRICAL CHARACTERISTICS

-40°C to +85°C unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Analog Supply Voltage (Note 1) 2.7 3.0 3.6 V
Analog Supply Current Internal REF, ADC, DAC, Comparators

all active
Analog Supply Current with
analog sub-systems inactive
Analog-to-Digital Supply
Delta ( | VDD – AV+ | )
Digital Supply Voltage 2.7 3.0 3.6 V
Digital Supply Current with
CPU active

Digital Supply Current
(shutdown)
Digital Supply RAM Data
Retention Voltage
Specified Operating
Temperature Range
SYSCLK (System Clock
Frequency)
SYSCLK (System Clock
Frequency)
Tsysl (SYSCLK Low Time) 18 ns
Tsysh (SYSCLK High Time) 18 ns

Note 1: Analog Supply AV+ must be greater than 1V for VDD monitor to operate.
Note 2: SYSCLK must be at least 32 kHz to enable debugging.

Internal REF, ADC, DAC, Comparators

all disabled, oscillator disabled

0.5 V

VDD = 2.7V, Clock=25MHz

VDD = 2.7V, Clock=1MHz

VDD = 2.7V, Clock=32kHz

Oscillator not running 5

1.5 V

-40 +85

C8051F005/6/7, C8051F015/6/7

(Note 2)

C8051F000/1/2, C8051F010/1/2

(Note 2)

1 2 mA

5 20

12.5

0.5
10

0 25 MHz

0 20 MHz

mA

µA

mA

µA
µA

°C

Rev. 1.7 20

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

4. PINOUT AND PACKAGE DEFINITIONS

Table 4.1. Pin Definitions

Pin Numbers

F000

F001

Name

VDD

DGND

AV+

AGND

TCK

TMS

TDI

TDO

XTAL1

XTAL2

/RST

VREF

CP0+

CP0-

CP1+

CP1-

DAC0

DAC1

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

F005
F010
F015

31,
40,

62
30,
41,

61

16,

17

5,
15
22 18 14
21 17 13
28 20 15

29 21 16

18 14 10

19 15 11

20 16 12

6 3 3

4 2 2
3 1 1
2 45
1 46

64 48 32

63 47 31

7 4 4

8 5 5

9 6 6

10 7 7

11 8

12 9

F006
F011
F016

23,

32

22,
33,
27,

19

13,

43

44,

12

F002
F007
F012
F017

18,

20

17,

21

9,

29

8,

30

Type Description

D In

D In

D In

D Out

A In

A Out

D I/O

A I/O

A In

A In

A In

A In

A Out

A Out

A In

A In

A In

A In

A In

A In

Digital Voltage Supply.

Digital Ground.

Positive Analog Voltage Supply.

Analog Ground.

JTAG Test Clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of

TCK.
JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on
the falling edge of TCK. TDO output is a tri-state driver.
Crystal Input. This pin is the return for the internal oscillator circuit for a
crystal or ceramic resonator. For a precision internal clock, connect a crystal
or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external
CMOS clock, this becomes the system clock.
Crystal Output. This pin is the excitation driver for a crystal or ceramic
resonator.
Chip Reset. Open-drain output of internal Voltage Supply monitor. Is driven
low when VDD is < 2.7V. An external source can force a system reset by
driving this pin low.
Voltage Reference. When configured as an input, this pin is the voltage
reference for the MCU. Otherwise, the internal reference drives this pin.
Comparator 0 Non-Inverting Input.

Comparator 0 Inverting Input.
Comparator 1 Non-Inverting Input.
Comparator 1 Inverting Input.
Digital to Analog Converter Output 0. The DAC0 voltage output. (See

Section 7 DAC Specification for complete description).
Digital to Analog Converter Output 1. The DAC1 voltage output. (See
Section 7 DAC Specification for complete description).
Analog Mux Channel Input 0. (See ADC Specification for complete
description).
Analog Mux Channel Input 1. (See ADC Specification for complete
description).
Analog Mux Channel Input 2. (See ADC Specification for complete
description).
Analog Mux Channel Input 3. (See ADC Specification for complete
description).
Analog Mux Channel Input 4. (See ADC Specification for complete
description).
Analog Mux Channel Input 5. (See ADC Specification for complete
description).

21 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Pin Numbers

F000

F001

Name

AIN6

AIN7

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

F005
F010
F015

13 10

14 11

39 31 19
42 34 22
47 35 23
48 36 24
49 37 25
50 38 26
55 39 27
56 40 28
38 30
37 29
36 28
35 26
34 25
32 24
60 42
59 41
33
27
54
53
52
51
44
43
26
25
24
23
58
57
46
45

F006
F011
F016

F002
F007
F012
F017

Type Description

A In

A In

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

D I/O

Analog Mux Channel Input 6. (See ADC Specification for complete
description).
Analog Mux Channel Input 7. (See ADC Specification for complete
description).
Port0 Bit0. (See the Port I/O Sub-System section for complete description).

Port0 Bit1. (See the Port I/O Sub-System section for complete description).
Port0 Bit2. (See the Port I/O Sub-System section for complete description).
Port0 Bit3. (See the Port I/O Sub-System section for complete description).
Port0 Bit4. (See the Port I/O Sub-System section for complete description).
Port0 Bit5. (See the Port I/O Sub-System section for complete description).
Port0 Bit6. (See the Port I/O Sub-System section for complete description).
Port0 Bit7. (See the Port I/O Sub-System section for complete description).
Port1 Bit0. (See the Port I/O Sub-System section for complete description).
Port1 Bit1. (See the Port I/O Sub-System section for complete description).
Port1 Bit2. (See the Port I/O Sub-System section for complete description).
Port1 Bit3. (See the Port I/O Sub-System section for complete description).
Port1 Bit4. (See the Port I/O Sub-System section for complete description).
Port1 Bit5. (See the Port I/O Sub-System section for complete description).
Port1 Bit6. (See the Port I/O Sub-System section for complete description).
Port1 Bit7. (See the Port I/O Sub-System section for complete description).
Port2 Bit0. (See the Port I/O Sub-System section for complete description).
Port2 Bit1. (See the Port I/O Sub-System section for complete description).
Port2 Bit2. (See the Port I/O Sub-System section for complete description).
Port2 Bit3. (See the Port I/O Sub-System section for complete description).
Port2 Bit4. (See the Port I/O Sub-System section for complete description).
Port2 Bit5. (See the Port I/O Sub-System section for complete description).
Port2 Bit6. (See the Port I/O Sub-System section for complete description).
Port2 Bit7. (See the Port I/O Sub-System section for complete description).
Port3 Bit0. (See the Port I/O Sub-System section for complete description).
Port3 Bit1. (See the Port I/O Sub-System section for complete description).
Port3 Bit2. (See the Port I/O Sub-System section for complete description).
Port3 Bit3. (See the Port I/O Sub-System section for complete description).
Port3 Bit4. (See the Port I/O Sub-System section for complete description).
Port3 Bit5. (See the Port I/O Sub-System section for complete description).
Port3 Bit6. (See the Port I/O Sub-System section for complete description).
Port3 Bit7. (See the Port I/O Sub-System section for complete description).

Rev. 1.7 22

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.1. TQFP-64 Pinout Diagram

CP1-

CP1+

CP0-

CP0+

AGND

VREF

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AGND

AV+

10

11

15

16

1

2

3

4

5

6

7

8

9

12

13

14

DAC0

64

17

DAC1

63

AV+

VDD

62

18

19

XTAL1

XTAL2

P3.5

P3.4

57

P0.7

56

DGND

61

60

P1.6

P1.7

59

58

C8051F000
C8051F005
C8051F010
C8051F015

20

21

22

23

24

25

TCK

TMS

/RST

P3.3

P3.1

P3.2

P0.6

55

26

P2.2

P2.3

53

54

27

P3.0

P2.1

28

TDI

P2.4

52

29

TDO

P2.5

51

30

DGND

P0.5

50

31

P0.4

49

VDD

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

P1.5

P0.3

P0.2
P3.6

P3.7

P2.6

P2.7

P0.1

DGND

VDD

P0.0

P1.0

P1.1

P1.2

P1.3

P1.4

P2.0

23 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.2. TQFP-64 Package Drawing

64

PIN 1

DESIGNATOR

1

A2

D

D1

MIN

NOM

MAX

(mm)

(mm)

(mm)

A

-

-

1.20

A1

0.05

E1

E

e

A

b

A1

A2

b

D

D1

e

E

E1

0.95

0.17

-

0.15

-

1.05

0.22

0.27

-

12.00

-

10.00

-

0.50

-

12.00

-

10.00

-

-

-

-

-

Rev. 1.7 24

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.3. TQFP-48 Pinout Diagram

AGND

CP0-

CP0+

VREF

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

DAC0

48

1

2

3

4

5

6

7

8

9

10

11

12

13

AV+

CP1-

DAC1

47

46

14

15

XTAL2

XTAL1

CP1+

45

AGND

44

AV+

43

P1.6

42

P1.7

41

C8051F001
C8051F006
C8051F011
C8051F016

16

17

18

19

20

/RST

TMS

TCK

TDI

DGND

P0.7

40

21

TDO

P0.5

P0.6

39

38

22

23

VDD

DGND

P0.4

37

36

35

34

33

32

31

30

29

28

27

26

25

24

P1.5

P0.3

P0.2

P0.1

DGND

VDD

P0.0

P1.0

P1.1

P1.2

DGND

P1.3

P1.4

25 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.4. TQFP-48 Package Drawing

48

PIN 1

IDENTIFIER

A2

1

D

D1

E1

E

e

A

A1

b

A

A1

A2

b

D

D1

e

E

E1

MIN

(mm)

-

0.05

0.95

0.17

-

-

-

-

-

NOM

(mm)

-

-

1.00

0.22

9.00

7.00

0.50

9.00

7.00

MAX

(mm)

1.20

0.15

1.05

0.27

-

-

-

-

-

Rev. 1.7 26

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.5. LQFP-32 Pinout Diagram

AGND

CP0-

CP0+

VREF

AIN0

AIN1

AIN2

AIN3

DAC0

32

DAC1

31

AGND

30

AV+

29

P0.7

28

1

2

3

4

5

6

C8051F002
C8051F007
C8051F012
C8051F017

7

8

9

10

11

12

13

AV+

XTAL1

XTAL2

/RST

TMS

P0.6

27

14

TCK

P0.5

26

15

TDI

P0.4

25

16

TDO

24

23

22

21

20

19

18

17

P0.3

P0.2

P0.1

DGND

VDD

P0.0

VDD

DGND

27 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

Figure 4.6. LQFP-32 Package Drawing

IDENTIFIER

32

PIN 1

1

A2

D

D1

A1

eb

MIN

NOM

(mm)

A

A1

0.05

E1

E

A2

b

1.35

0.30

D

D1

e

A

E

E1

(mm)

-

1.40

0.37

-

9.00

-

7.00

-

0.80

-

9.00

-

7.00

MAX

(mm)

-

-

1.60

0.15

1.45

0.45

-

-

-

-

-

Rev. 1.7 28

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only)

The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 5.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.

Figure 5.1. 12-Bit ADC Functional Block Diagram

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

+

-

+

-

+

-

+

-

9-to-1

AMUX

(SE or

DIFF)

X

+

-

ADCEN

AV+

AGND

12-Bit

SAR

ADC0LTLADC0LTHADC0GTLADC0GTH

AV+

ADC

SYSCLK

REF

12

24

COMB
LOGIC

12

ADC0LADC0H

Conversion Start

ADWINT

TEMP

SENSOR

AGND

M

T

T

CNV

D

A

R
2

B

3
O

STR

U

O
V

SY(

V

w

)

AMX0CF

AIN01IC

AIN23IC

AIN45IC

AIN67IC

AMX0SL

AMXAD1

AMXAD2

AMXAD3

AMXAD0

ADCSC0

ADCSC1

ADCSC2

ADC0CF

AMPGN2

AMPGN1

AMPGN0

ADCEN

ADCTM

ADCINT

ADC0CN

ADSTM0

ADSTM1

ADBUSY

ADWINT

ADLJST

5.1. Analog Multiplexer and PGA

Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 5.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.5),
and the Configuration register AMX0CF (Figure 5.4). The table in Figure 5.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 5.6). The PGA can be software­programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.

29 Rev. 1.7

C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7

5.2. ADC Modes of Operation

The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before
performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC
conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or
16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate
different system clock speeds.

A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:

1. Writing a 1 to the ADBUSY bit of ADC0CN;

2. A Timer 3 overflow (i.e. timed continuous conversions);

3. A rising edge detected on the external ADC convert start signal, CNVSTR;

4. A Timer 2 overflow (i.e. timed continuous conversions).

Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag. Note: When conversions are

performed “on-demand”, the ADCINT flag, not ADBUSY, should be polled to determine when the
conversion has completed. Converted data is available in the ADC data word MSB and LSB registers, ADC0H,

ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 5.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.

The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different
low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):

1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;

2. Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;

3. Tracking is active only when the CNVSTR input is low;

4. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.

Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the
ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In
this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also
be disabled (shutdown) when the entire chip is in low power standby or sleep modes.

Figure 5.2. 12-Bit ADC Track and Conversion Example Timing

(ADSTM[1:0]=10)

Timer2, Timer3 Overflow;

Write 1 to ADBUSY

(ADSTM[1:0]=00, 01, 11)

A. ADC Timing for External Trigger Source

CNVSTR

SAR Clocks

ADCTM=1

ADCTM=0

SAR Clocks

ADCTM=1

SAR Clocks

ADCTM=0

Low Power or

Convert

Track Or Convert

B. ADC Timing for Internal Trigger Sources

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Low Power or

Convert

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Track or Convert

1 2 3 4 5 6 7 8 9 1011 1213141516

Track

Track

Convert Track

Convert

Convert

Convert

Low Power Mode

Track

17 18 19

Low Power Mode

Rev. 1.7 30