Silicon Laboratories C8051F005 User Manual

C8051F005

25 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU

Analog Peripherals

12-Bit ADC

- ±1 LSB INL; no missing codes

- Programmable throughput up to 100 ksps

- 8 external inputs; programmable as single-ended or differential

- Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5

- Data-dependent windowed interrupt generator

- Built-in temperature sensor (±3 °C)

Two 12-Bit DACs

- Voltage output

- 10 µsec settling time

Two Comparators

- 16 programmable hysteresis values

- Configurable to generate interrupts or reset

Internal Voltage Reference
VDD Monitor/Brown-out Detector

On-Chip JTAG Debug

- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit

emulation

- Supports breakpoints, single stepping, watchpoints, inspect/modify

memory, and registers

- Superior performance to emulation systems using ICE-chips, target

pods, and sockets

- Fully compliant with IEEE 1149.1 specification

High-Speed 8051 µC Core

- Pipelined instruction architecture; executes 70% of Instructions in 1 or 2

system clocks

- Up to 25 MIPS throughput with 25 MHz clock

- Expanded interrupt handler; up to 21 interrupt sources

Memory

- 2304 bytes data RAM

- 32 kB Flash; in-system programmable in 512-byte sectors (512 bytes

are reserved)

Digital Peripherals

- 32 port I/O; all are 5 V tolerant

- Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports

available concurrently

- Programmable 16-bit counter/timer array with five capture/compare

modules

- 4 general-purpose 16-bit counter/timers

- Dedicated watchdog timer; bidirectional reset

Clock Sources

- Internal programmable oscillator: 2–16 MHz

- External oscillator: Crystal, RC, C, or Clock

- Can switch between clock sources on-the-fly

Supply Voltage: 2.7 to 3.6 V

- Typical operating current: 12.5 mA at 25 MHz

- Multiple power saving sleep and shutdown modes

64-Pin TQFP
Temperature Range: –40 to +85 °C

VDD
VDD

VDD
DGND
DGND
DGND

AV+

AV+
AGND
AGND

TCK

TMS

TDI

TDO

RST

XTAL1
XTAL2

VREF

DAC1

DAC0

AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7

CP0+

CP0-

CP1+

CP1-

Digital Power

Analog Power

JTAG
Logic

Monitor

External

Oscillator

Circuit

Internal

Oscillator

VREF

A
M
U
X

CP0

CP1

VDD

DAC1

(12-Bit)

DAC0

(12-Bit)

SENSOR

TEMP

Boundary Scan

Debug HW

WDT

Prog
Gain

Reset

System Clock

ADC

100 ksps

(12-Bit)

8
0
5
1

C
o

r

e

32 kB

FLASH

256 Byte

RAM

2048 Byte

XRAM

SFR Bus

UART

SMBus

SPI Bus

5-Chnl

PCA

Timers

0,1,2

Timer 3

Port 0

Latch

Port 1

Latch

Port 2

Latch

Port 3

Latch

C
R
O
S
S
B
A
R

S
W

I
T
C
H

P
0

D

r

v

P
1

D

r

v

P
2

D

r

v

P
3

D

r

v

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004

25 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCU

Selected Electrical Specifications

(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GLOBAL CH ARACTERI STICS

Analog Supply Voltage 2.7 3.6 V
Analog Supply Current Internal REF, ADC, DAC, Comparators all

Analog Supply Current with
analog sub-systems inactive
Digital Supply Voltage 2.7 3.6 V
Digital Supply Current with
CPU active

Digital Supply Current
(shutdown mode)
VDD Data Retention Voltage RAM remains valid 1.5 V

CPU & DIGITAL I/O

Clock Frequency Range DC 25 MHz
Port Output High Voltage IOH = –3 mA, Port I/O push-pull VDD – 0.7 V
Port Output Low Voltage IOL = 8.5 mA 0.6 V
Input High Voltage 0.8 x VDD V
Input Low Voltage 0.2 x VDD V
SMBus SCL Frequency SYSCLK = MCU system clock SYSCLK/8 MHz
SPI Bus Clock Frequency SYSCLK = MCU system clock SYSCLK/2 MHz

A/D CONVERTER

Resolution 12 bits
Integral Nonlinearity
Differential Nonlinearity Guaranteed Monotonic
Throughput Rate 100 ksps
Input Voltage Range 0 V

D/A CONVERTERS

Resolution 12 bits
Integral Nonlinearity Specified from Data Word 014h to FEBh
Differential Nonlinearity Guaranteed Monotonic
Offset Error Data Word = 014h
Output Settling Time To ½ LSB of full-scale 10 µs
Output Voltage Swing 0 V

COMPARATO RS

Supply Current (each Comparator) 1.5 µA
Response Time | (CP+) – (CP-) | = 100 mV 4 µs
Input Voltage Range –0.25 (AV+) +0.25 V
Input Bias Current –5 0.001 +5 nA
Input Offset Voltage –10 +10 mV

active
Internal REF, ADC, DAC, Comparators all
disabled

Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz
Oscillator not running 2 µA

C8051F005

0.8 mA

5 µA

12

0.5
20

±4

±3

mA

1

±
±1

REF

LSB
1

±

LSB

–1 LSB V

REF

mA

µA

LSB
LSB

V

LSB

64

PIN 1

DESIGNATOR

A2

Package Information

D

D1

1

e

b

A1

C8051F005DK Development Kit

MIN

NOM

(mm)

A

A1

E1

E

A

0.05

A2

0.95

b

0.17

D

D1

e

E

E1

MAX

(mm)

(mm)

-

-

1.20

-

0.15

-

1.05

0.22

0.27

-

12.00

-

-

10.00

-

-

0.50

-

-

12.00

-

-

10.00

-

Precision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004

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