Silicon Laboratories C8051F Service Manual

SOFTWARE UART EXAMPLES

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Relevant Devices

This application note applies to the following devices:

C8051F000, C8051F001, C8051F002, C8051F005, C8051F006, C8051F010, C8051F011, C8051F012, C8051F012, C8051F015, C8051F016, C8051F017, C8051F220, C8051F221, C8051F226, C8051F230, C8051F231, C8051F236.

Introduction

This application note presents a discussion about software UART implementation on C8051Fxxx devices. Two complete examples are given: a C program using the PCA as the baud rate source, and an assembly program using Timer 0 as the baud rate source.

Implementation Options

The essential trade-off to consider when implementing a software UART (SW UART) is between hardware usage and speed/efficiency. Designs that utilize more hardware are likely to consume less CPU bandwidth and allow higher bit rates. This trade-off is discussed below.

Baud Rate Sources

An interrupt must be generated for each bit that is transferred; at a full-duplex 115.2 kbps, that’s an interrupt every 4.3 µs. The method of generating these interrupts (baud rate source) determines to a large extent how much overhead the implementation consumes. Available options include: 8-bit timers, 16-bit timers, and the Programmable Counter Array (PCA). Note that for full-duplex operation, two baud rate sources are required (one each for transmit and receive).

Key Features

The two software examples were designed to closely mimic the hardware UART while still preserving hardware resources and CPU bandwidth. The following is a list of key features found in both examples:

• An interface similar to the hardware UART, with user-level transmit and receive interrupts.

• Interrupt or polled mode access support.

• Full-duplex communication up to 57.6 kbps using an 18.432 MHz clock source.

• State-based, interrupt-driven implementation, requiring minimal CPU overhead.

• Minimal hardware usage:

- ‘C’ example uses two PCA modules.

- Assembly example uses Timer 0 in Mode 3.

The use of 8-bit timers allows one of the 16-bit hardware timers to be used for both transmit and receive baud rate generation. Timer 0 offers this capability in Mode 3. Note that when Timer 0 is in this mode, Timer 1 functionality is reduced; however, Timer 1 may still provide baud rate generation for the hardware UART (HW UART). Using 8-bit timers preserves hardware resources, but does introduce some overhead and latency issues. These issues are discussed in Example 2.

An alternative to the above solution is the use of 16-bit auto-reload timers. In this case two of the 16 bit hardware timers are occupied by the SW UART-

-one for transmit and one for receive. Any of the available timers will suffice, but the auto-reload feature on Timer 2 and Timer 3 reduces overhead, and eliminates any interrupt latency issues. Additionally, 16-bit timers support a wider range of baud rates.

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The Programmable Counter Array (PCA) also provides an excellent solution for the SW UART, as demonstrated in the provided ‘C’ example. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each of these modules may be configured to trigger an interrupt when the PCA counter matches the associated compare module’s contents. Since the PCA counter runs uninterrupted, this solution avoids the problem of accumulated interrupt latency. The PCA implementation is not available on C8051F2xx devices.

Additional Considerations

Each of the above timer sources may be clocked by SYSCLK or an external signal. In the provided examples, baud rate sources are clocked by SYSCLK, which is derived from an external

18.432 MHz crystal. Any baud rate/crystal fre-

quency combination is allowed, though software overhead limits the maximum baud rate-toSYSCLK ratio.

START bit detection is also a concern for the SW UART receiver. C8051F00x and C8051F01x devices offer many external interrupt sources, several of which can be configured to detect falling edges. Both example programs utilize external interrupts for START detection.

Program Structure

In software timer mode, the PCA can generate an interrupt when the PCA counter matches a value in of one of the compare modules. Since the PCA counter runs uninterrupted, the modules can be updated each bit time to accurately produce the next bit time. In addition, the PCA offers a capture function that is useful in START bit detection.

The PCA modules may be routed via the crossbar to external signals. These signals (called CEXn for module n) can be used to trigger PCA counter captures. This feature is exploited in the SW UART receiver. START bit recognition is accomplished with module 0 configured to capture the PCA counter contents upon a falling edge on the RX pin. This function offers two benefits: (1) START bit detection is easily accomplished; and (2) since the capture is performed immediately as the edge is detected, the bit sample timing is immune to interrupt latency.

Implementation

The transmit and receive operations for Example 1 are implemented as two independent state

Example 1: Programmable Counter Array Implementation

Example 1 uses two PCA modules to generate the receive and transmit baud rates (modules 0 and 1, respectively). The modules are configured in software timer mode to generate baud rate interrupts. An introduction to the PCA can be found in AN007.

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Figure 1. T ransmit and Receive State Machines

State 0

: Transmit START bit.

- Drop TX pin as START condition.

- Update Baud Rate source for next bit time.

- Increment state variable.

State 1-9

:Transmit Bit.

- Shift LSB of Transmit Data onto TX pin.

- Shift STOP bit into MSB of Transmit Data.

- Update Baud Rate source for next bit time.

- Increment state variable.

State 10

: STOP bit transmitted.

- Indicate Transmit complete.

- Trigger user-level interrupt if enabled.

- Reset Transmitter to Idle state.

Transmit State Machine

Interrupt Sources

State 0

: Start bit detected.

- Load Baud Rate source f or 3/2 bit time.

- Increment state variable.

State 1-8

: Bit Received.

- Shift value of RX pin into RX shift register.

- Update Baud Rate source for next bit time.

- Increment state variable.

State 9

: Capture STOP bit.

- Indicate Receive complete.

- Trigger user-level interrupt if enabled.

- Reset Receiver to Idle state.

Receive State Machine

Interrupt Sources

1) User (begin TX)

2) Bit Time Generator

1) START detection

2) Bit Time Generator

Figure 2. SW UART Bit Timing

D1D0 D2 D3 D4 D5 D6 D7

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

3/2 Bit-Time 1 Bit-Time

machines in the PCA ISR. The state machines are illustrated in Figure 1.

Receive State Machine

When the SW UART is initialized, the PCA module 0 is configured for negative-edge capture mode. Its input, CEX0, is routed via the crossbar to a GPIO pin (P0.2, SW_RX). With the state machine in State 0, an interrupt is generated when a falling edge is detected on SW_RX. Since the module is in capture mode, the contents of the PCA counter are loaded into the module 0 capture registers. Note that this value is independent of interrupt latency. Module 0 is switched to software timer

mode after the START bit is detected, and 3/2 bittime is added to the module 0 capture register. The extra 1/2 bit-time is used only after the start bit is detected, so that sampling will occur during the middle of the next bit period (see Figure 2). When the PCA counter reaches the value held in the module 0 capture registers, the first bit-sampling interrupt (LSB in this case) occurs.

States 1-8 execute on module match interrupts. In each state, bits are sampled from SW_RX and shifted into the RXSHIFT variable. The PCA module 0 contents are updated in each state to provide the next bit-time interrupt (1 bit time is added

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1) Read RDR.

2) Clear SRI

SRI

To Receive

STXBSY

1) Write data to TDR.

2) Set CCF1 to initiate transmit.

3) Set STXBSY

STI

To Transmit

Done?

End RX

Yes

Done?

NoYes

End TX

Initialization

1) Define SYSCLK and desired BAUD_RATE.

2) Call SW_UART_INIT.

3) Set SES if user-level interrupt support is desired.

4) Set SREN to enable th e SW UART receiver.

5) Call SW_UART_ENABLE.

1) Clear STI

Figure 3. Example 1 User-Level Polled

Mode Interface

to the compare registers). The state variable is also incremented.

State 9 captures the STOP bit, posts SRI, and returns the receiver to Idle state.

Transmit State Machine

A user initiates a transmit by forcing a PCA module 1 interrupt (setting CCF1=1). In State 0, the TX pin is forced low to generate the START condition. The PCA counter is read, and this value plus one bit-time is loaded into to the module 1 capture registers. Note that a few SYSCLKs will pass between the time the START bit is generated and when the PCA counter is read. This is the only instance in Example 1 where interrupt latency affects the bit time. The effect is negligible (worst case ~ 1/16 bit-time for 57.6 kbps and an

18.432 MHz SYSCLK).

States 1-9 are executed on module match interrupts. In each state, a bit is shifted out of the LSB of TDR, and a ‘1’ shifted in the MSB of TDR to represent the STOP bit. One bit time is added to the PCA module 1 capture registers to generate the next bit time. After 9 shifts, the data byte + STOP bit have been transmitted. The Transmit Complete indicator (STI) is set, the Transmit Busy indicator (STXBSY) is cleared, and the TX state variable is reset.

procedure for Example 1 is shown in Figure 3.

Program Interface

The SW UART supports both polled and interruptdriven interfacing. Polled support is configured by disabling user-level interrupts (SES=0). The transmit and receive indicators (STI and SRI, respectively) can then be polled for transfer completions. The initialization and polled mode programming

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The initialization routine, SW_UART_INIT, configures the PCA, interrupts, and state variables for

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Figure 4. Example 1 User-Level

Interrupt Mode Interface

Exit ISR

STI || SRI 1) Re-trigger IE7

1) Read RDR.

2) Clear SRI

SRI

IE7 Interrupt

STI

1) Clear STI

2) Write new data to TDR

3) Set CCF1 to initate transmit.

4) Set STXBSY

Clear IE7 Interrupt

Flag

Figure 5. Example 1 Test

Configuration

P0.0 (HW_TX)

P0.3 (SW_RX)

P0.1 (HW_RX)

P0.2 (SW_TX)

use in the SW UART. The SW_UART_ENABLE routine enables the SW UART. The SREN bit must be set to enable the receiver. Note that the TIME_COUNT constant is calculated by the software from the BAUD_RATE and SYSCLK constants.

If user-level interrupt support is enabled (SES=1), an IE7 interrupt is generated each time a transmit or receive is completed. As with the hardware UART, user software must check the transmit/ receive complete flags to determine the source of the interrupt. In the event that a transmit and receive are completed simultaneously, the user software will receive only one interrupt. The IE7 ISR must be capable of handling this situation. T w o options are available: (1) service both transmit and receive in the same ISR execution, or (2) service one (STI or SRI) and force an interrupt so that the ISR is called again to service the other. The second option is recommended to minimize ISR execution time.

Test code is provided to interface the SW UART with the HW UART. Connect jumper wires as shown in Figure 5.

To use the software in interrupt mode, set SES=1. The programming procedure for interrupt mode is shown in Figure 4.

The test code routines configure and enable the HW UART in Mode 1 using Timer 1 as the baud rate source. Timer 1 is also configured. Different baud rates and crystals may be tested by changing the BAUD_RATE and SYSCLK constants. Both HW and SW UART baud rate counts are calculated by the software from these constants. The testing routines transmit 15 characters in both directions.

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T o test the SW UART in polled mode, comment the line

; INTERRUPT_TEST();

and uncomment the line

POLLED_TEST();

Reverse the above steps to test the SW UART in interrupt mode. Uncomment the line

INTERRUPT_TEST();

And comment the line

; POLLED_TEST();

The longest states in Example 2 require 113 SYSCLKs (TX States 1-9). For an 18.432 MHz crystal, a SW UART transmit or receive operation will require a worst case 6 µs per bit transferred (113*T

bandwidth for a transmit or receive (70% for fullduplex). For the Example 1 software compiled with the Keil compiler, the full-duplex overhead may be approximated by the following equation:

FD Overhead(%) ~ = BAUD_RATE/81,000

SYSCLK

). At 57.6 kbps, that’s ~35% of CPU

With Timer 0 in Mode 3, Timer 1 may not set the TF1 flag, generate an interrupt, or be clocked by external signals. However, Timer 1 may still operate as a baud rate generator for the HW UART if configured in Mode 2 (8-bit timer w/auto-reload). While Timer 0 is in Mode 3, Timer 1 may be enabled/disabled through its mode settings. Timer 1 is disabled in Mode 3, and enabled in all other modes.

With Timer 1 as the HW UART baud rate source, this solution is perhaps the most efficient use of hardware resources. The downside is increased software overhead (relative to the 16-bit timer solution). Timer 0 Mode 3 does not offer auto-reload capabilities; the manual timer reload requires a 16bit move in each interrupt service routine (ISR) iteration. In addition, interrupt latency will affect the bit-time accuracy. A correction constant can be factored into the timer preload values to compensate for typical interrupt latency, but variations in interrupt latency are unaccounted for.

Slower baud rates may require more than 8-bits of timer counts for each bit time. With SYSCLK at

18.432 MHz and Timer 0 in SYSCLK/1 mode, baud rates below 72 kbps require more than 256 timer counts. Available options include:

Per the above equation, baud rates above 80 kbps are not supported for full duplex operation. The overhead penalty is only incurred while the SW UART is performing a transfer. The code listing begins on page 10.

Example 2: 8-Bit Timer Implementation

In Example1 the SW UART uses Timer0 in Mode 3. In this mode, Timer 0 is split into two 8bit timers: one is used for transmitting and one for receiving. TL0 is used as the receive timer; TH0 is used as the transmit timer.

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1) Use Timer 0 in SYSCLK/12 mode. Slower baud rates may be achieved with 8 bits, but standard baud rate/SYSCLK combinations are more difficult to obtain.

2) Use Timer 0 in SYSCLK/1 mode, and keep an upper timer byte manually in the timer ISR. Note that this method will generate an interrupt every 256 SYSCLKs for each transmit and receive, regardless of the baud rate (an interrupt each time the lower 8-bits overflow). The Example 2 software demonstrates option #2.