Silicon Laboratories AN0021 User manual

AN0021: Analog to Digital Converter
(ADC)

This application note describes how to use the Analog to Digital
Converter (ADC) of EFM32 Gecko Series 0 and 1 devices to con­vert

an analog input voltage to a digital value. Many aspects of
the ADC, including inputs, references, and the different operating
modes are described. Calibration routines for offset and gain are
also included.

The provided software examples show how to use the different operating modes of the
ADC. The example projects are configured for the EFM32 Gecko Series 0 and 1 devi­ces, but can easily be ported to other EZR32 Wireless MCU and EFR32 Wireless
Gecko devices by changing the project settings.

For simplicity, EFM32 Wonder Gecko, Gecko, Giant Gecko, Leopard Gecko, Tiny
Gecko, Zero Gecko, and Happy Gecko are a part of the EFM32 Gecko Series 0.

EZR32 Wonder Gecko, Leopard Gecko, and Happy Gecko are a part of the EZR32
Wireless MCU Series 0.

EFM32 Pearl Gecko and Jade Gecko (and future devices) are a part of the EFM32
Gecko Series 1.

EFR32 Blue Gecko, Flex Gecko, and Mighty Gecko are a part of the EFR32 Wireless
Gecko Series 1.

KEY POINTS

• There are new ADC features in EFM32
Gecko Series 1 devices.

• This document discusses ADC operation
and advanced features.

• The ADC supports offset and gain
calibration.

• This application note includes:

• This PDF document

• Source files

• Example C-code

• Multiple IDE projects

+

ADC

...0101110...

-

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AN0021: Analog to Digital Converter (ADC)

Analog to Digital Converter

1. Analog to Digital Converter

1.1 Introduction

The EFM32 Gecko ADC is a Successive Approximation Register (SAR) architecture. The maximum resolution is 12 bits, which can
achieve one million samples per second (Msps). The integrated input MUX can select the ADC input from external pins or internal sig­nals. With PRS and DMA, the ADC can operate without CPU intervention, minimizing current consumption or allowing the core to do
other work. The ADC can be clocked at different speeds and run using different warm-up modes to reduce the energy consumption
even further.

This application note discusses general operation and usage of the ADC. In addition, advanced features and power saving techniques
are described. Software examples of ADC operation both with DMA and PRS are included. Offset and Gain Calibration of the ADC is
also described and included in the software examples.

For extremely low power periodic ADC sampling, a software example that enters Energy Mode 2 (EM2) between each ADC sample is
also included. This is the best way to do low power ADC sampling for sampling frequencies below a couple of kHz.

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1.2 Overview

AN0021: Analog to Digital Converter (ADC)

Analog to Digital Converter

The Figure

1.1 ADC Overview of EFM32 Giant Gecko on page 2 and Figure 1.2 ADC Overview of EFM32 Pearl Gecko on page 3

illustrate the internal connections of the inputs, reference selection, and registers.

ADCn_CTRL

ADCn_CMD

ADCn_SINGLECTRL

ADCn_SCANCTRL

3

Sequencer

+

-

ADCn

ADCn_STATUS

Prescaler

ADCn_CH0
ADCn_CH1
ADCn_CH2
ADCn_CH3
ADCn_CH4
ADCn_CH5
ADCn_CH6
ADCn_CH7

ADC_CLKHFPERCLK

DAC0
DAC1

Temp

V

DD

V
V

V

ref

/

DD

SS

/2

ADCn_SINGLEDATA

ADCn_SCANDATA

Oversampling

filter

Result

buffer

Control

SAR

V

DD

1.25 V

2.5 V

5 V differential

2x(VDD-VSS)

Figure 1.1. ADC Overview of EFM32 Giant Gecko

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HFPERCLK

ASYNCCLK

ADCn

ADCn

ADCCLKMODE

ADC_CLK

ADCn_STATUS

Conversion clock

Prescaler

(adc_clk_sar)

ADC_CLK

ADCn_BIASPROG

ADCn_CMPTHR

ADCn_CTRL

ADCn_CMD

ADCn_SINGLECTRL

ADCn_SINGLECTRLX

ADCn_SCANCTRL

ADCn_SCANCTRLX

Sequencer

AN0021: Analog to Digital Converter (ADC)

Analog to Digital Converter

ADCn_SINGLEDATA ADCn_SCANDATA

SCAN

INPUTID

SINGLESAMPLE

FIFO

SCAN SAMPLE

FIFO

APORT0X

APORT0Y

AVDD
DVDD

DECOUPLE

IOVDD

APORT1X
APORT2X
APORT3X
APORT4X

APORT1Y
APORT2Y
APORT3Y
APORT4Y

DAC0OUT0
DAC0OUT1

vdd_mux

TEMP

VSS

INP_MUX

Control

+

Oversampling

filter

-

INN_MUX

VSS

ADCn_EXTP ADCn_EXTN

Figure 1.2. ADC Overview of EFM32 Pearl Gecko

Some new ADC features (see the list below) are added in the EFM32 Gecko Series 1 and EFR32 Wireless Gecko Series 1 devices.

•

Externally controllable conversion start time using PRS in TIMED mode

• Can be run during EM2 and EM3, waking up the system upon various enabled interrupts

• Can be run during EM2 and EM3 with DMA enabled to pull data from the FIFOs without waking up the system

• Automated clock gating to save power when not converting

• Supports up to 144 external input channels and 11 internal inputs

• Includes temperature sensor and random number generator function

• Programmable scan sequence

• Up to 32 configurable samples in scan sequence

• Four deep FIFOs to store conversion data along with a channel ID and an option to overwrite old data when full

• Programmable watermark (DVL) to generate a SCAN interrupt

• Supports window compare function

• Programmable single-channel conversion

• Four deep FIFOs to store conversion data along with an option to overwrite old data when full

• Programmable watermark (DVL) to generate a SINGLE interrupt

• Supports window compare function

• Programmable and preset input full scale (peak-to-peak) range (VFS) with selectable reference sources

• User-programmable dividers for flexible VFS options from internal, external, or supply voltage reference sources

• Interrupt generation and/or a DMA request when

• Programmable number of converted data available in the single FIFO (also generates DMA request)

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AN0021: Analog to Digital Converter (ADC)

• Programmable number of converted data available in the scan FIFO (also generates DMA request)

Single FIFO overflow or underflow

•

• Scan FIFO overflow or underflow

• Latest Single conversion tripped compare logic

• Latest Scan conversion tripped compare logic

• Analog over-voltage interrupt

• Programming Error interrupt due to APORT Bus Request conflict or NEGSEL programming error

Analog to Digital Converter

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AN0021: Analog to Digital Converter (ADC)

General Operation

2. General Operation

2.1 Clock Selection

The ADC has an internal pre-scaler which can divide the selected ADC conversion clock source. Any factor between 1 and 128 can be
chosen by writing a value between 0 and 127 to the PRESC bit field in the ADCn_CTRL register.

The symbols for different clock sources can be found in Figure 1.1 ADC Overview of EFM32 Giant Gecko on page 2 and Figure

1.2 ADC Overview of EFM32 Pearl Gecko on page 3.

Table 2.1. ADC Clock Selection

Item EFM32 Gecko Series 0 and EZR32

Series 0

ADC peripheral clock source (register in-

HFPERCLK HFPERCLK

EFM32 Gecko Series 1 and EFR32 Wireless
Gecko Series 1

terface)

ADC conversion clock source HFPERCLK The ADC_CLK is selected by ADCCLKMODE bit

field in the ADCn_CTRL register

•

HFPERCLK (ADCCLKMODE = 0)

• ASYNCCLK (ADCCLKMODE = 1)

ASYNCCLK source — Selected by ADC0CLKSEL bit field in the

CMU_ADCCTRL register

•

Disabled (ADC0CLKSEL = 0)

• AUXHFRCO (ADC0CLKSEL = 1)

• HFXO (ADC0CLKSEL = 2)

• HFSRCCLK (ADC0CLKSEL = 3)

ADC conversion clock frequency ADC_CLK = HFPERCLK / (1 to 128)

Range is from 32 kHz to 13 MHz

Clock source for ADC operation in EM2

— AUXHFRCO (ASYNCCLK) is the only available

and EM3

adc_clk_sar = ADC_CLK / (1 to 128)
Range is from 32 kHz to 16 MHz

option during EM2 or EM3

2.2 Input Selection

The

external inputs can either be selected as single-ended inputs or combined to allow for differential inputs (see 3.6 Analog Port

(APORT) for ADC). The DIFF bit field in the ADCn_SINGLECTRL or ADCn_SCANCTRL register enables differential mode.

The ADC input signals are shielded fairly well against other noisy signals within the EFM32 Gecko. If high ADC accuracy is needed, it is
advisable not to use any of the unused ADC input pins for noise-inducing activities, such as serial communication.

2.2.1 Single-Ended Mode

In single-ended mode the input signal is measured with ground as the negative input. The voltage span between 0 V and the selected
reference is divided in small steps according to the selected resolution.

The result is an unsigned number between 0 and 2

resolution

- 1, indicating where the input voltage is located in the span between ground

and the reference voltage.

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.2.2 Differential Mode

differential mode the measured value is the difference between two inputs. Since one input is defined as the positive input and the

In
other is defined as the negative input, the difference can be positive or negative depending on which input is higher. As a result, the
conversion result is a signed number represented in two's complement form. If the negative input is higher than the positive input, the
converted value is negative (see 4.3 Differential Inputs and 5.3 Single and Scan Conversion with Differential Inputs). Note that the ADC
cannot convert negative voltages in reference to ground.

Table 2.2. ADC Input Selection

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wireless

Gecko Series 1

External inputs for Single-

Up to 8, fix on pins PD0 – PD7 Up to 144 through APORT

Ended mode

External inputs for Differential
mode

Up to 8, fix on pins PD0 – PD7

•

Two neighboring inputs are used in differential

Up to 72 through APORT

mode, for instance channel 0 and channel 1 is
one differential pair, channel 2 and channel 3
another

• The lowest channel number is the positive dif­ferential input

Internal inputs 6 Up to 11

Input filtering Low pass RC filter or an internal decoupling ca-

—

pacitor

Temperature sensor Set INPUTSEL bit field in the ADCn_SIN-

GLECTRL register to TEMP

Offset calibration Set INPUTSEL bit field in the ADCn_SIN-

GLECTRL register to DIFF0 (short between posi-

Set POSSEL bit field in the ADCn_SINGLECTRL
register to TEMP

Set POSSEL and NEGSEL bit fields in the
ADCn_SINGLECTRL register to VSS

tive and negative inputs)

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.3 Reference Selection

convert an analog voltage to a digital value, the ADC needs a reference voltage to which it compares the incoming analog voltage.

To
Since the ADC cannot measure voltages larger than the reference voltage, the reference voltage should be above the maximum expec­ted measured voltage.

The selected reference source is combined with internal circuitry to produce the full-scale voltage (VFS) for the converter. VFS is the
full input range of the converter, from the lowest possible input voltage to the highest. For single-ended conversions, the input range on
the selected positive input is from 0 to VFS. For differential conversions, the input to the converter is the difference between the positive
and negative input selections. The ADC conversion result ranges from -VFS/2 to +VFS/2.

The maximum and minimum input voltage which the ADC can recognize at any external pin is limited to the supply voltages. If VFS is
configured to be larger than the supply range (for example, VFS configured to 5 V when operating on a 3.3 V supply), the full ADC
range is not available.

The ADC cannot measure negative voltages or voltages larger than the reference voltage. As a result, it is important to keep both in­puts within the electrical limits of the device.

Table 2.3. ADC Reference Selection

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wireless

Gecko Series 1

Internal bandgap reference • 1.25 V

•

2.5 V (supply voltage > 2.5 V)

• 5 V differential (supply voltage > 2.75 V)

Internal reference • VDD

•

Unbuffered 2 x VDD

External single-ended refer-

Pin PD6 as input Use ADCn_EXTP pin as input

ence

External differential reference • Use pin PD6 as positive input

•

Use pin PD7 as negative input

• Reference = 2 x (PD6 – PD7)

GPBIASACC bit field of the

— • Set to 0 (HIGHACC) when an internal bandgap

ADCn_BIASPROG register

• 1.25 V

•

2.5 V

• 5 V differential

• AVDD

• 2 x AVDD

• Use ADCn_EXTP pin as positive input

•

Use ADCn_EXTN pin as negative input

• Reference = 2 x (ADCn_EXTP – ADCn_EXTN)

reference source is used

•

Set to 1 (LOWACC) when AVDD or an external
pin reference is used

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.4 Conversions

conversion consists of acquisition and approximation phases. The input is sampled in the acquisition phase before it is converted to

A
digital representation during the approximation phase. The acquisition time can be configured independently for scan sequence and
single channel conversions by setting AT bit field in the ADCn_SINGLECTRL or ADCn_SCANCTRL register.

The symbols for different clock sources can be found in Figure 1.1 ADC Overview of EFM32 Giant Gecko on page 2 and Figure

1.2 ADC Overview of EFM32 Pearl Gecko on page 3.

Table 2.4. ADC Conversions

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wireless

Gecko Series 1

ADC_CLK Pre-scaled HFPERCLK HFPERCLK or ASYNCCLK

adc_clk_sar — Pre-scaled ADC_CLK

Acquisition time (AT) 1 to 256 (integer power of 2) ADC_CLK cycles 1 to 256 (integer power of 2) adc_clk_sar cycles

Minimum acquisition time for

2 µs —

VDD/3

Minimum acquisition time for
the internal temperature sensor

2 µs AT bit field of the ADCn_SINGLECTRL or

ADCn_SCANCTRL register should be set to a
value of 9 (256 adc_clk_sar cycles)

ADC warm-up time Based on HFPERCLK Based on ADC_CLK

ADC total conversion time per

In ADC_CLK cycles

In adc_clk_sar cycles

output

•

Tacq equals the number of

Tconv = (Tacq + N) x OVSRSEL

Tconv = (Tacq + (N + 1)) x OVSRSEL

acquisition cycles

• N is the resolution in bits

• OVSRSEL is the oversam­pling ratio when oversam­pling is enabled

2.5 ADC Modes

The ADC contains two separate programmable modes: single channel mode and scan mode. Both modes have separate configuration
and result registers. Both modes may be set up to run only once per trigger or to automatically repeat after each operation. The scan
mode has priority over single channel mode.

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.5.1 Single Channel Mode

single channel mode, the ADC converts one input either one time or continuously if the REP bit field in the ADCn_SINGLECTRL

In
register is set (see 4.1 Single Conversion and 5.1 Single and Scan Conversion). The DIFF bit field in the ADCn_SINGLECTRL register
selects whether differential or single-ended inputs are used.

Table 2.5. ADC Single Channel Mode

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wireless

Gecko Series 1

Input selection The input for single conversion is defined by the

bit field INPUTSEL in the ADCn_SINGLECTRL
register

The POSSEL and NEGSEL bit fields in the
ADCn_SINGLECTRL register select the input sig­nals

FIFO for conversion results — 4 x 32 bit

Programmable FIFO water­mark (DVL) to generate SIN­GLE interrupt

— The DVL bit field of the ADCn_SINGLECTRLX

register controls the FIFO watermark crossing
which sets the SINGLEDV bit in the ADCn_STA­TUS register

SINGLEDV bit in the
ADCn_STATUS register is set

SINGLEOF bit in ADCn_IF reg­ister is set

ADCn_SINGLEFIFOCOUNT

Valid data in the ADCn_SINGLEDATA register (DVL+1) number of single channel conversion re-

sults are available in single FIFO

Result is not read before the next result is ready,
the first result is overwritten

Signals that a result from a single channel FIFO
has been overwritten before being read

— Number of unread data available in single FIFO

register

ADCn_SINGLEFIFOCLEAR

— Clear single FIFO content

register

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.5.2 Scan Mode

scan mode, the ADC can be configured to convert a sequence of different inputs, either one time or continuously if the REP bit field

In
in the ADCn_SCANCTRL register is set (see 4.2 Scan Conversion with DMA Transfer and 5.1 Single and Scan Conversion). The DIFF
bit field in the ADCn_SCANCTRL register selects whether differential or single-ended inputs are used. DMA can be used to transfer
results to RAM after each conversion. All the results can then be read from RAM after the sequence has finished.

Table 2.6. ADC Scan Mode

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wire-

less Gecko Series 1

Input selection The inputs included in the scan sequence are

defined by the bit field INPUTMASK in
ADCn_SCANCTRL register

The inputs included in the scan sequence
are defined by the ADCn_SCANMASK,
ADCn_SCANINPUTSEL and
ADCn_SCANNEGSEL registers

FIFO for conversion results — 4 x 32 bit

Programmable FIFO watermark (DVL)
to generate SCAN interrupt

— The DVL field of the ADCn_SCANCTRLX

register controls the FIFO watermark cross­ing which sets the SCANDV bit in the
ADCn_STATUS register

SCANDV bit in the ADCn_STATUS
register is set

SCANOF bit in ADCn_IF register is
set

Valid data in the ADCn_SCANDATA register (DVL+1) number of scan conversion results

are available in scan FIFO

Result is not read before the next result is ready,
the first result is overwritten

Signals that a result from a scan FIFO has
been overwritten before being read

ADCn_SCANDATAX register — The FIFO data is tagged with SCANINPU-

TID and can be read along with the scan
data using this register

ADCn_SCANFIFOCOUNT register — Number of unread data available in scan

FIFO

ADCn_SCANFIFOCLEAR register — Clear scan FIFO content

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AN0021: Analog to Digital Converter (ADC)

General Operation

2.6 Warm-Up Modes

power-on, the ADC requires some time for internal bias currents and references to settle prior to starting a conversion. This time

After
period is called the warm-up time and is performed by hardware. Firmware must program the number of clock cycles required to count
at least 1 µs in the TIMEBASE bit field of the ADCn_CTRL register.

Normally, the ADC is warmed up only when samples are requested and is shut off when there are no more samples waiting. However,
if lower latency is needed, configuring the WARMUPMODE bit field in the ADCn_CTRL allows the ADC and/or reference to stay warm
between samples, reducing the warm-up time or eliminating it altogether. Note that keeping the ADC and/or reference enabled between
samples increases the energy consumption of the ADC.

Note: Only the reference selected for scan mode is kept warm. To avoid warm-up time in single conversion mode, the single conver­sion reference needs to be the same as the scan conversion reference.

Table 2.7. ADC Warm-up Mode of EFM32 Gecko Series 0

Warmup Mode EFM32 Gecko Series 0 and EZR32 Series 0

NORMAL • ADC and references are shut off when there are no samples waiting

•

When entering Energy Mode 2 or 3, the ADC must be stopped and WARMUPMODE must be set
to NORMAL

• Total time = Bandgap reference warm-up time (5 µs) + ADC warm-up time (1 µs) + ADC conver­sion time

FASTBG • Bandgap warm-up is eliminated, but with reduced reference accuracy

•

Total time = ADC warm-up time (1 µs) + ADC conversion time

KEEPSCANREFWARM • The reference selected for scan mode is kept warm. The ADC will still need to be warmed up

before conversion

Total time = ADC warm-up time (1 µs) + ADC conversion time

•

KEEPADCWARM • The ADC and the reference selected for scan mode are kept warm

Total time = ADC conversion time

•

Table 2.8. ADC Warm-up Mode of EFM32 Gecko Series 1

Warmup Mode EFM32 Gecko Series 0 and EZR32 Series 1

NORMAL • ADC and references are shut off when there are no samples waiting

Total time = ADC warm-up time (5 µs) + ADC conversion time

•

KEEPINSTANDBY • The reference selected for scan mode is kept warm, but the ADC is powered down

The ADC will initiate a 1 us warm-up period before a conversion begins

•

• Total time = ADC warm-up time (1 µs) + ADC conversion time

KEEPINSLOWACC • It is similar to KEEPINSTANDBY, but continuously tracks the input, keeping the input multiplexer

connected to the analog bus

•

Total time = ADC warm-up time (1 µs) + ADC conversion time

KEEPADCWARM • The ADC and the reference selected for scan mode are kept warm

Total time = ADC conversion time

•

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AN0021: Analog to Digital Converter (ADC)

Advanced Features

3. Advanced Features

3.1 Bias Current Programming

The current consumption of the ADC can be adjusted through the ADCn_BIASPROG register. Adjusting this bitfield also affects the
performance and bandwidth of the ADC. The default register values should be used to ensure correct operation of the ADC within the
specified clock speed range and with all configurations. The bias current settings should only be changed while the ADC is disabled
(i.e., in NORMAL warm-up mode and no conversion in progress).

Table 3.1. ADC Bias Current Programming

Item EFM32 Gecko Series 0 and EZR32 Series 0 EFM32 Gecko Series 1 and EFR32 Wireless

Gecko Series 1

BIASPROG and HALFBIAS
bit fields of the ADCn_BIA­SPROG register

COMPBIAS bit field of the
ADCn_BIASPROG register

ADCBIASPROG bit field of
the ADCn_BIASPROG regis­ter

Scale the bias current of the bandgap reference —

Scale the bias current of the ADC comparator —

— • Scale the internal bias of the ADC

•

For proper operation, the ADC conversion
speed must be scaled accordingly

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AN0021: Analog to Digital Converter (ADC)

Advanced Features

3.2 Oversampling

higher than 12-bit accuracy is needed, the ADC can automatically sample and average the result in hardware. The number of sam-

If
ples for each averaged result can be selected as 2n for n = [1..12]. If oversampling is enabled, the ADC result is not ready until all the

samples are converted and averaged (see 4.4 Oversampling and 5.2 Single and Scan Conversion with Oversampling).

The result is averaged by accumulating samples and right shifting the result. For 2x, 4x, 8x and 16x oversampling the result is not right
shifted. Instead, the result consists of more than 12 bits. See Table 3.2 Oversampling Result Shifting and Resolution on page 13 for
oversampling result representation.

Table 3.2. Oversampling Result Shifting and Resolution

Oversampling Setting Number of Right Shifts Result Resolution (# bits)

2x 0 13

4x 0 14

8x 0 15

16x 0 16

32x 1 16

64x 2 16

128x 3 16

256x 4 16

512x 5 16

1024x 6 16

2048x 7 16

4096x 8 16

If the samples of the measured signal are affected by uncorrelated random noise added to each sample, oversampling and averaging

be used to increase the signal-to-noise ratio. The number of additional samples needed to get n additional bits of meaningful data

can
in the result is given by the following equation.

Note: samples = 2

2n

Note that an accurate result requires more time to sample the signal. For example, this equation can be used to get a 16 bit accuracy at
the expense of using more time per sample because the signal must be sampled many times. To get 4 additional bits of meaningful

data for the 12-bit ADC in the EFM32 Gecko, the number of samples needed equals 2

2*4

which is 256 samples.

3.3 Peripheral Reflex System

The ADC can be configured as both a consumer and a producer of PRS signals. Both scan and single conversions can be triggered by
a PRS signal and PRS signals can also be produced when a conversion is finished.

Often the ADC samples a voltage with fixed intervals and, preferably, without the CPU intervention. Periodic measurements can be
achieved by using the Peripheral Reflex System and a timer (producer) that runs continuously and sends a PRS pulse to the ADC (con­sumer) with specific intervals. When the ADC receives a PRS pulse, it triggers a conversion start. A conversion-finished interrupt can
then handle the result (see 4.5 PRS Triggered Sampling and 5.4 Single Conversion Interrupt (EM1)). The conversion result can also be
directly transferred to RAM using DMA.

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