SIGE SE4100L-R Datasheet

SE4100L

PointCharger™ GPS Receiver IC

Preliminary Information

Applications

 Mobile phone & PDA accessories  Portable navigation  Personal security  Security systems  Asset tracking  Telematics equipment

Features

 30 mW power consumption  4x4mm 24 pin LPCC package  Single conversion radio with integrated IF filters  On-chip, Gain switchable LNA  Low LNA noise figure, 1.3dB typ.  On chip crystal oscillator can be powered up

independently

 Fully integrated VCO, VCO tank circuit and PLL.  Remote antenna current detection

Ordering Information

Type Package Remark

SE4100L-R 24 Pin LPCC Shipped in

Tape & Reel

Functional Block Diagram

Product Description

The SE4100 is an integrated GPS receiver designed to receive the L1 signal at 1575.42MHz. The receiver has a low IF architecture, and integrates all of the amplifier, oscillator, mixer and demodulation functions.

The external component count is low, requiring just a

16.368MHz crystal and 11 passive components in its minimum configuration. This and the 24 pin LPCC package result in a very small circuit footprint, which is complemented by just 30mW operating power.

Two digitally controlled shutdown modes enable either to part to be powered down entirely or for just the 16 MHz clock supply to the baseband processor to be maintained.

A switchable gain LNA enables the SE4100 to be used with a local passive antenna or with a remote active antenna without changing the circuit configuration. The on-chip VCO and PLL generates the required LO frequency from the external 16.368MHz crystal. All of the VCO and LO chain is integrated. An image reject mixer downconverts the RF signal to a 4.092MHz IF. The integrated IF filter feeds a combiner, limiter and output latch. The output signal is a 1-bit quantized

4.092 MHz digital IF at CMOS levels.

SE4100 Block Diagram

Det.

Vtune

MixIn

RF Amp

÷96

IF FilterMixers

Quadrature

÷2

VCO

RxEnb

Phase

Shift /

Combiner

ClkOut

+45° / -45°

D-type

DataOut

QClk

LNAOut

LowGain

LNAIn

AntOK

AntDetP

AntDetN

Xtal1

LNA

Ant current

monitor

Phase

Xtal2

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Xtal

Oscillator

OscEnb

Pin Out Diagram

SE4100L

PointCharger™ GPS Receiver IC

Preliminary Information

VccLNA

AntDetP

AntDetN

LNAIn

LowGain

AntOK

MixIn

Vss2

LNAOut

242123

7108

DataOut

VccRF

SE4100L

Top View

RxEnb

ClkOut

Vss1

MixIn

VccVCO

OscEnb

Vtune

Xtal1

Xtal2

OscEnb

Vtune

Xtal1

Xtal2

VccVCO

Vss1

212322

SE4100L

Bottom View

VccRF

Die Pad

RxEnb

Vss2

LNAOut

VccLNA

AntDetP

AntDetN

LNAIn

LowGain

AntOK

ClkOut

DataOut

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PointCharger™ GPS Receiver IC

Pin Out Description

Pin No. Name Description

1 VccLNA Power supply connection for LNA

2 AntDetP Connection to battery side of antenna current sensing resistor

3 AntDetN Connection to antenna feed side of antenna current sensing resistor

4 LNAIn LNA Input

5 LowGain LNA Gain control, High = low gain

6 AntOK Antenna OK output flag (high = antenna current OK)

7 DataOut Data Output

8 ClkOut Buffered version of Xtal Osc output / D-type clock

9 RxEnb

10 R0 Reserved internal connection, must be tied to VDD for normal operation

Enable control for Receiver (all circuits except Reference oscillator and Data Registers), active high input

SE4100L

Preliminary Information

11 R1 Reserved internal connection, must be tied to VDD for normal operation

12 R2 Reserved internal connection, must be tied to VDD for normal operation

13 R3 Reserved internal connection, must be tied to VDD for normal operation

14 Xtal2 Connection to crystal

15 Xtal1 Connection to crystal

16 VDD Power supply for digital circuits (Xtal Oscillator, Data Registers and Bias circuits)

17 Vtune Charge pump output / VCO control voltage input

18 OscEnb Enable control for Reference oscillator, active high input

19 VCCVCO Decoupling connection for VCO power supply

20 MixIn

21 VSS1 Ground

22 VCCRF Power supply connection for all RF circuits except the LNA

23 VSS2 Ground

24 LNAOut

Die Pad Gnd Ground connection for all circuits via die pad

Mixer input signal, 50Ω single ended

LNA Output, 50Ω single ended

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SE4100L

PointCharger™ GPS Receiver IC

Preliminary Information

Functional Description

LNA

The internal LNA consists of two transistors cascaded. The biasing, gain switching circuit and

output matching to 50Ω is contained on the IC. A

conceptual diagram of the internal circuit is shown below.

Vbias2

Vbias1

LNAIn

The input match to 50Ω requires three external

components, two capacitors and an inductor. The inductor should be a high Q type, e.g. wirewound or microstrip; otherwise the low noise figure of the LNA will not be obtained.

The output match is optimized to allow for a short length of narrow track between the IC package and a filter. Exact lengths and track widths will depend on the board material and thickness.

The gain of the amplifier is switched between high and low settings by the CMOS level compatible LowGain input pin. Internally, this reduces the gain of the second stage only in the low gain setting, which maintains a low noise figure for the amplifier.

The power supply for the amplifier is provided through the VccLNA pin. Care should be taken with the PCB layout to ensure that the power supply cannot act as a bypass around any filter between the LNA output and the mixer input.

Antenna Current Monitor

VccLNA

LNAOut

Gain Control

The state of the logic output on the AntOK pin is dependent on the voltage drop between AntDetP and AntDetN pins, AntDetP being the higher dc voltage. The current setting this voltage is adjusted by changing the value of the external current sense resistor between these pins.

Voltage

between

Logic Output

AntOK

AntDetP and

AntDetN (∆V

ANT

)

<0.125 Low

0.25>∆V>0.5

High

>0.75 Low

The AntOK pin is a CMOS output designed to interface directly to the LowGain input pin, so that in the event the supply to the external active antenna is either shorted or open circuited, the internal LNA gain is switched to the high gain setting.

The external current sense resistor should be chosen according to the typical current of the external antenna I

, using the formula:

ANT

0.375

R =

EXT

ANT

Mixer RF Input

The mixer RF input pin, MixIn, is a single ended 50Ω

input, designed to either interface to the LNAOut pin or to the output of an external filter using only a dc blocking capacitor, and without additional matching components.

The input is a common base configuration providing a

wideband 50Ω termination. A conceptual diagram of

the input circuit is shown below:

Vbias1

0.5mA

MixIn

Ω

800

The antenna current monitor is a window comparator designed to operate with common mode input voltages above the chip V the supply current to an external active antenna and provide a logic output indicating if the current is within

. It is designed to monitor

the desired range.

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SE4100L

PointCharger™ GPS Receiver IC

Preliminary Information

The filter type chosen should require a termination

impedance of 50+j0Ω. Examples of suitable types are

shown on the application schematic diagram.

The PCB layout should keep the track from the filter to the MixIn pin as short as possible to minimize

pickup and mismatch (if the track is not 50Ω). A dc

blocking capacitor should be used, even if the filter does not present a dc path, as the MixIn pin has 0.4V dc present which may be detrimental to the filter.

A filter will improve the performance of the receiver in the presence of out of band blocking signals, but is not essential if operation in the presence of such signals is not critical. If the filter is not fitted, the LNAOut pin should be connected to the MixIn pin via a coupling capacitor.

PLL and Loop Filter

The entire phase-locked loop generating the local oscillator for the mixer is contained on-chip, with the exception of the loop filter.

Values provided on the application circuit should be used, as these will provide optimum performance under all conditions.

The capacitors may be ceramic dielectric types, with either COG/NP0 or X7R dielectric. Higher capacitance per unit volume dielectrics should be avoided as the absolute tolerance and temperature stability may compromise system performance.

The PCB layout should keep the track from the Vtune pin to the loop filter as short as possible to minimize noise pickup.

Crystal Oscillator

The crystal oscillator is a Pierce configuration, as shown in the diagram below. The application circuit is designed to work with parallel resonant crystals with a load capacitance of 12pF.

Xtal1

Xtal2

The PCB layout should minimize the lengths of the tracks to Xtal1 and Xtal2 pins. The capacitors at each terminal of the crystal should be mounted adjacent to the crystal and have a low impedance connection to the ground plane.

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