SIGE SE1030W Datasheet

Ω 50

Ω

R

LightCharger™ 2.5 Gb/s Transimpedance Amplifier

Applications

§ SONET/SDH-based transmission systems, test
equipment and modules

§ OC-48 fibre optic modules and line termination

§ ATM optical receivers

§ Gigabit Ethernet

§ Fibre Channel

Features

§ Single +3.3 V power supply

§ Input noise current = 360 nA rms when used with

a 0.5 pF detector

§ Transimpedance gain = 2.3 kΩ into a 50 Ω load
(differential)

§ On-chip automatic gain control gives input
current overload of 2.6 mA pk and max output
voltage swing of 300 mV pk-pk

§ Differential 50 Ω outputs

§ Bandwidth (-3 dB) = 2.4 GHz

§ Wide data rate range = 50 Mb/s to 2.5 Gb/s

§ Constant photodiode reverse bias voltage = 1.5 V

(anode to input, cathode to VCC)

§ Minimal external components, supply decoupling

only

§ Operating junction temperature range = -40°C to

+125°C

§ Equivalent to Nortel Networks AB89-A2A

Ordering Information

SE1030W

Final

Product Description

SiGe Semiconductor offers a portfolio of optical
networking ICs for use in high-performance optical
transmitter and receiver functions, from 155 Mb/s up
to 12.5 Gb/s.

SiGe Semiconductor’s SE1030W is a fully integrated,
silicon bipolar transimpedance amplifier; providing
wideband, low noise preamplification of signal current
from a photodetector. It features differential outputs,
and incorporates an automatic gain control
mechanism to increase dynamic range, allowing input
signals up to 2.6 mA peak. A decoupling capacitor on
the supply is the only external circuitry required. A
system block diagram is shown after the functional
description, on page 3.

Noise performance is optimized for 2.5 Gb/s
operation, with a calculated rms noise based

sensitivity of –26 dBm for 10
using a detector with 0.5 pF capacitance and a
responsivity of 0.9 A/W, with an infinite extinction ratio
source.

-10

bit error rate, achieved

Type Package Remark

SE1030W Bare Die Shipped in

Waffle Pack

Functional Block Diagram

VCC or +ve supply

Input

Current

TZ_IN

SE1030
TzAmp

2.5 Gb/s

f

Tz Amp

Bandgap
Reference

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Automatic Gain Control

Integrator Rectifier

Output
Driver

50

OUTP

OUTN

Bondpad Diagram

SE1030W

LightCharger™ 2.5 Gb/s Transimpedance Amplifier

Final

VCC

1

2 DNC

Top

View

TZ_IN

3

7 6 5 4

Bondpad Description

Pad No. Name Description

11

VCC

10

OUTP

9

OUTN

8

VCC VEE2 VEE1 VEE1 VEE1

1 VCC
2 DNC Do not connect.

3 TZ_IN Input pad (connect to photodetector anode).
4 VEE2

5 VEE1
6 VEE1
7 VEE1
8 VCC
9 OUTN Negative differential voltage output.

10 OUTP Positive differential voltage output.
11 VCC

Positive supply (+3.3 V), pads 1, 8 & 11 are connected on chip. Only one pad needs
to be bonded.

Negative supply (0V) – Note this is separate ground for the input stage, which is AC
coupled on chip. There is no DC current through this pad.
Negative supply (0V), pads 5, 6 & 7 are connected on chip. Only one pad needs to be
bonded.
Negative supply (0V), pads 5, 6 & 7 are connected on chip. Only one pad needs to be
bonded.
Negative supply (0V), pads 5, 6 & 7 are connected on chip. Only one pad needs to be
bonded.
Positive supply (+3.3 V), pads 1, 8 & 11 are connected on chip. Only one pad needs
to be bonded.

Positive supply (+3.3 V), pads 1, 8 & 11 are connected on chip. Only one pad needs
to be bonded.

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2 2

TZ

LightCharger™ 2.5 Gb/s Transimpedance Amplifier

Functional Description
Amplifier Front-End

The transimpedance front-end amplifies an input
current from a photodetector, at pin TZ_IN, to produce
a differentia l output voltage with the feedback resistor
Rf determining the level of amplification (see the
functional block diagram on page 1). An automatic
gain control loop varies this resistor, to ensure that
the output from the front-end does not saturate the
output driver stage that follows. This gain control
allows input signals of up to 2.6 mA peak.

The input pin TZ_IN is biased at 1.5 V below the
supply voltage VCC, allowing a photodetector to have
a constant reverse bias by connecting the cathode to

3.3 V. This enables full single rail operation.

The front-end stage has its own supply ground
connection (VEE2) to achieve optimum noise
performance and maintain integrity of the high-speed
signal path. The front-end shares the VCC (+3.3 V)

System Block Diagram

SE1030W

Final

connection with the rem ainder of the circuitry, which has
a separate ground (VEE1).

Output driver stage

The output driver acts as a buffer stage, capable of
swinging up to 300 mVpk-pk differential into a 100 Ω
load. The small output swings allow ease of use with

low voltage post amplifiers (e.g. 3.3 V parts).
Increasing optical input level gives a positive-going
output signal on the OUTP pin.

Automatic Gain Control (AGC)

The AGC circuit monitors the voltages from the output
driver and compares them to an internal reference
level produced via the on-chip bandgap reference
circuit. When this level is exceeded, the gain of the
front-end is reduced by controlling the feedback
resistor Rf.

A long time-constant integrator is used within the
control loop of the AGC with a typical low frequency
cut-off of 5 kHz.

Receiver Module

AGC

Amplifier

2.5 GHz

2.5 Gb/s

Clock

Data

Clock & Data

Recovery

2

SE1230

LOS

2

SE1030W

Amplifier

PIN

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