SIGE SE1020W Datasheet

Applications



Gigabit-Ethernet systems, test equipment
and modules



OC-24 fibre optic modules and line
termination

Fibre Channel optical systems



Features

 Single +3.3 V power supply
 Power dissipation = 110 mW (typ)
 Input noise current = 180 nA rms when used

with a 0.7 pF detector

 Transimpedance gain = 4.0 kΩ into a 50 Ω

load (differential)

 On-chip automatic gain control gives input

current overload of 2.6 mA pk and max
output voltage swing of 300 mV pk-pk

 Differential 50 Ω outputs

 Bandwidth (-3 dB) = 1.2 GHz
 Wide data rate range = 50 Mb/s to 1.25 Gb/s
 Constant photodiode reverse bias voltage =

1.5 V (anode to input, cathode to VCC)

 Minimal external components, supply

decoupling only

 Operating junction temperature range =

-40°C to +125°C

Ordering Information

SE1020W

1.25 Gb/s Transimpedance Amplifier
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Product Description

SiGe Semiconductor offers a portfolio of optical
networking ICs for use in high-performance
optical transmitter and receiver functions, from
155 Mb/s up to 12.5 Gb/s.

SiGe Semiconductor’s SE1020W is a fully
integrated, silicon bipolar transimpedance
amplifier; providing wideband, low noise
preamplification of signal current from a
photodetector. It features differential outputs and
incorporates an automatic gain control
mechanism to increase dynamic range, allowing
input signals up to 2.6 mA peak. A decoupling
capacitor on the supply is the only external
circuitry required. A system block diagram is
shown after the functional description, on page 3.

Type Package Remark

SE1020W Bare Die None

Functional Block Diagram

VCC or +ve suppl y

Input

Current

TZ_IN

SE1020
TzAmp

1.25 Gb/s

R

f

Tz Amp

Bandgap
Reference

Automatic Gain Control

Integr ator

42-DST-01  Rev 1.3  May 27/02 Confidential 1 of 7

Rectifi er

Output
Driver

Ω

50

Ω

50

OUTP

OUTN

Bondpad Diagram

SE1020W

1.25 Gb/s Transimpedance Amplifier
Product Preview

VCC

1

Top

View

TZ_IN

2

6 5 4 3

Bondpad Description

Pad No. Name Description

1 VCC

2 TZ_IN Input pad (connect to photodetector anode).

3 VEE2

4 VEE1

5 VEE1

6 VEE1

7 VCC

8 OUTN Negative differential voltage output.

Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one
pad needs to be bonded.

Negative supply (0V) – Note this is separate ground for the input stage,
which is AC coupled on chip. There is no DC current through this pad.
Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad
needs to be bonded.
Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad
needs to be bonded.
Negative supply (0V), pads 4, 5 & 6 are connected on chip. Only one pad
needs to be bonded.
Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one
pad needs to be bonded.

10

VCC

9

OUTP

8

OUTN

7

VCC VEE2 VEE1 VEE1 VEE1

9 OUTP Positive differential voltage output.

10 VCC

Positive supply (+3.3 V), pads 1, 7 & 10 are connected on chip. Only one
pad needs to be bonded.

42-DST-01  Rev 1.3  May 27/02 Confidential 2 of 7

Functional Description

Amplifier front-end

The transimpedance front-end amplifies an input
current from a photodetector, at pin TZ_IN, to
produce an output voltage with the feedback
resistor Rf determining the level of amplification
(see the functional block diagram on page 1). An
automatic gain control loop varies this resistor, to
ensure that the output from the front-end does
not saturate the output driver stage that follows.
This gain control allows input signals of up to

2.6 mA peak.

The input pin TZ_IN is biased at 1.5 V below the
supply voltage VCC, allowing a photodetector to
have a constant reverse bias by connecting the
cathode to 3.3 V. This enables full single rail
operation.

The front-end stage has its own supply ground
connection (VEE2) to achieve optimum noise
performance and maintain integrity of the high­speed signal path. The front-end shares the VCC

System Block Diagram

1.25 GHz

1.25 Gb/s

2

Clock

Clock & Data

Recovery

2

Data

Amplifier

2

AGC

SE1230

LOS

SE1020W

1.25 Gb/s Transimpedance Amplifier
Product Preview

(+3.3 V) connection with the remainder of the
circuitry, which has a separate ground (VEE1).

Output driver stage

The output driver acts as a buffer stage, capable
of swinging up to 300 mVpk-pk differential into a

100 Ω load. The small output swings allow ease

of use with low voltage post amplifiers (e.g. 3.3 V
parts). Increasing optical input level gives a
positive-going output signal on the OUTP pin.

Automatic Gain Control (AGC)

The AGC circuit monitors the voltages from the
output driver and compares them to an internal
reference level produced via the on-chip bandgap
reference circuit. When this level is exceeded, the
gain of the front-end is reduced by controlling the
feedback resistor Rf.

A long time-constant integrator is used within the
control loop of the AGC with a typical low
frequency cut-off of 10 kHz.

Receiver Module

2

SE1020W

TZ

Amplifier

PIN

42-DST-01  Rev 1.3  May 27/02 Confidential 3 of 7