r
Product Technical Specification and
Customer Design Guidelines
®
Wireless Microprocesso
WMP100/
Open AT® Software Suite v1.0
Reference: WM_DEV_WUP_PTS_005
Revision: 002
Date: March 19, 2007
®
WMP100/Open AT
Software
Suite v1.0
Product Technical Specification &
Customer Design Guidelines
Reference: WM_DEV_WUP_PTS_005
Revision:
Date:
002
March 19, 2007
®
Powered by the Wavecom Open AT
Software Suite
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confidential ©
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Document Information
Level Date History of the evolution
001 19/10/2006 Creation (Preliminary version)
002 19/03/2007 Updates
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Overview
This document defines and specifies the WMP100/Open AT® Software Suite
v1.0 available in a GSM/GPRS Class 10 quad-band version.
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Table of Contents
Document Information......................................................................... 2
Overview ............................................................................................. 3
Table of Contents................................................................................ 4
Table of Figures................................................................................. 10
Cautions ............................................................................................ 12
Trademarks ....................................................................................... 12
Copyright .......................................................................................... 12
1 References................................................................................ 13
1.1 Reference documents............................................................................13
1.1.1 WAVECOM reference documentation ............................................13
1.1.2 General reference documentation ..................................................13
1.2 List of abbreviations ..............................................................................14
2 General description................................................................... 17
2.1 General information...............................................................................17
2.1.1 Overall dimensions ........................................................................17
2.1.2 Environment and mechanics..........................................................17
2.1.3 GSM/GPRS Features ......................................................................17
2.1.4 Interfaces.......................................................................................18
2.1.5 Operating system ..........................................................................18
2.2 Functional description ...........................................................................19
2.2.1 RF functionalities ...........................................................................20
2.2.2 Baseband functionalities................................................................20
2.3 Software description .............................................................................20
3 Interfaces ................................................................................. 21
3.1 General Interfaces .................................................................................21
3.2 Power supply ........................................................................................22
3.2.1 Power supply description ..............................................................22
3.2.2 Power supply constraints on VBATT-RF ........................................22
3.2.3 Power supply constraints on VBATT-BB........................................23
3.2.4 Electrical characteristics ................................................................23
3.2.5 Pin description...............................................................................23
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Application ....................................................................................24
3.2.6
3.3 Power consumption ..............................................................................25
3.3.1.1 Power consumption without Open AT® processing .................26
3.3.1.2 Power consumption with a Dhrystone Open AT® application...27
3.3.1.3 Consumption waveform samples.............................................28
3.3.1.3.1 Connected mode current waveform .......................................28
3.3.1.3.2 Slow Idle mode current waveform .........................................29
3.3.1.3.3 Fast Idle mode current waveform ..........................................30
3.3.1.3.4 Transfer mode Class 10 current waveform ............................31
3.4 Electrical information for digital I/O........................................................32
3.5 SPI Bus .................................................................................................34
3.5.1 Features ........................................................................................34
3.5.1.1 Characteristics .........................................................................34
3.5.1.2 SPI configuration .....................................................................34
3.5.1.3 SPI waveforms ........................................................................35
3.5.2 Pin description...............................................................................36
3.5.3 Application ....................................................................................36
3.5.3.1 4-wire interface .......................................................................36
3.5.3.2 3-wire interface .......................................................................37
3.6 I2C bus..................................................................................................38
3.6.1 Features ........................................................................................38
3.6.1.1 Characteristics .........................................................................38
3.6.1.2 I²C waveforms .........................................................................38
3.6.2 Pin description...............................................................................39
3.6.3 Application ....................................................................................39
3.7 Keyboard interface.................................................................................40
3.7.1 Features ........................................................................................40
3.7.2 Pin description...............................................................................41
3.7.3 Application ....................................................................................42
3.8 Main serial link (UART1)........................................................................42
3.8.1 Features ........................................................................................42
3.8.2 Pin description...............................................................................43
3.8.3 First download ..............................................................................45
3.8.4 Application ....................................................................................46
3.9 Auxiliary serial link (UART2) ..................................................................50
3.9.1 Features ........................................................................................50
3.9.2 Pin description...............................................................................51
3.9.3 Application ....................................................................................51
3.10 SIM Interface.........................................................................................52
3.10.1 Features ........................................................................................52
3.10.2 Pin description...............................................................................54
3.10.3 Application ....................................................................................54
3.11 General Purpose Input/Output ...............................................................56
3.11.1 Features ........................................................................................56
3.11.2 Pin description...............................................................................56
3.12 Analog to Digital Converter....................................................................58
3.12.1 Features ........................................................................................58
3.12.2 Pin description...............................................................................58
3.12.3 Application ....................................................................................59
3.13 Digital to Analog Converter....................................................................60
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3.13.1
Features ........................................................................................60
3.13.2 Pin description...............................................................................60
3.14 Analogue audio interface.......................................................................61
3.14.1 Microphone Features .....................................................................61
3.14.1.1 Electrical characteristics...........................................................61
3.14.1.1.1 MIC1 Microphone Inputs ...................................................61
3.14.1.1.2 MIC2 Microphone Inputs ...................................................62
3.14.2 Speaker Features ...........................................................................64
3.14.2.1 Speakers Outputs Power .........................................................64
3.14.2.1.1 SPK1 Speaker Outputs.......................................................64
3.14.2.1.2 SPK2 Speaker Outputs......................................................66
3.14.3 Pin description...............................................................................67
3.14.4 Application ....................................................................................67
3.14.4.1 Microphone .............................................................................67
3.14.4.1.1 MIC2 Differential connection example................................67
3.14.4.1.2 MIC2 single-ended connection example ............................69
3.14.4.1.3 MIC1 Differential connection example................................70
3.14.4.1.4 MIC1 Single-ended connection example ............................72
3.14.4.2 Speaker ...................................................................................73
3.14.4.2.1 SPK2 Differential connection..............................................73
3.14.4.2.2 SPKx Single-ended connection ..........................................74
3.14.5 Design recommendation ................................................................74
3.14.5.1 General ....................................................................................74
3.14.5.2 Recommended microphone characteristics..............................74
3.14.5.3 Recommended speaker characteristics ....................................75
3.14.5.4 Recommended filtering components........................................75
3.14.5.5 Audio track and PCB layout recommendation ..........................77
3.15 PWM / Buzzer Output ...........................................................................78
3.15.1 Features ........................................................................................78
3.15.2 Pin description...............................................................................78
3.15.3 Application ....................................................................................79
3.16 Battery charging interface .....................................................................80
3.16.1 Feature ..........................................................................................80
3.16.1.1 Pre-Charging ...........................................................................81
3.16.1.2 Temperature monitoring ..........................................................81
3.16.2 Pin description...............................................................................82
3.16.3 Application ....................................................................................82
3.17 ON / ~OFF signal...................................................................................84
3.17.1 Features ........................................................................................84
3.17.2 Pin description...............................................................................84
3.17.3 Application ....................................................................................84
3.17.3.1 Power ON ................................................................................85
3.17.3.2 Power OFF...............................................................................87
3.18 BOOT signal ..........................................................................................88
3.18.1 Features ........................................................................................88
3.18.2 Pin description...............................................................................88
3.18.3 Application ....................................................................................88
3.19 Reset signals .........................................................................................89
3.19.1 Features ........................................................................................89
3.19.2 Pin description...............................................................................92
3.19.3 Application ....................................................................................93
3.20 External Interrupt ..................................................................................94
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3.20.1
Features ........................................................................................94
3.20.2 Pin description...............................................................................94
3.20.3 Application ....................................................................................95
3.21 VCC_2V8 and VCC_1V8 output ..............................................................96
3.21.1 Features ........................................................................................96
3.21.2 Pin description...............................................................................96
3.21.3 Application ....................................................................................96
3.22 Real Time Clock.....................................................................................97
3.22.1 Features ........................................................................................97
3.22.2 Pin description...............................................................................97
3.22.3 Application ....................................................................................98
3.22.4 Design recommendation ................................................................98
3.23 BAT-RTC (Backup Battery) ....................................................................99
3.23.1 Features ........................................................................................99
3.23.2 Pin description.............................................................................100
3.23.3 Application ..................................................................................100
3.23.3.1 Super Capacitor .....................................................................100
3.23.3.2 Non Rechargeable battery......................................................101
3.23.3.3 Rechargeable battery cell .......................................................101
3.24 FLASH-LED signal ...............................................................................102
3.24.1 Features ......................................................................................102
3.24.2 Pin description.............................................................................103
3.24.3 Application ..................................................................................104
3.25 Digital audio interface (PCM) ...............................................................104
3.25.1 Features ......................................................................................104
3.25.2 Pin description.............................................................................107
3.25.3 Application TBD...........................................................................107
3.26 USB 2.0 interface ................................................................................107
3.26.1 Features ......................................................................................107
3.26.2 Pin description.............................................................................108
3.26.3 Application ..................................................................................109
3.27 Memory interface ................................................................................110
3.27.1 Features ......................................................................................111
3.27.1.1 Generic Description................................................................111
3.27.1.2 Case of ST 32/8 (M36W0R5030T0ZAQF) ..............................112
3.27.1.3 Access bus Waveform ...........................................................113
3.27.1.4 Flash space............................................................................116
3.27.1.5 RAM space ............................................................................116
3.27.1.6 16-bit wide data bus User Space ...........................................117
3.27.2 Electrical characteristics of the signals.........................................117
3.27.3 Pin description.............................................................................117
3.27.4 Application ..................................................................................120
3.27.5 Constraints ..................................................................................121
3.28 RF interface .........................................................................................124
3.28.1 RF connection..............................................................................124
3.28.2 RF performances .........................................................................124
3.28.3 Antenna specifications ................................................................125
3.28.4 Antenna.......................................................................................125
4 Consumption measurement procedure ................................... 127
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged
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Hardware configuration.......................................................................127
4.1
4.1.1 Equipment ...................................................................................127
4.1.2 Wireless Microprocessor motherboard ........................................129
4.1.3 SIM cards used ...........................................................................130
4.2 Software configurations ......................................................................130
4.2.1 Wireless Microprocessor configuration ........................................130
4.2.2 Equipment configuration .............................................................131
4.3 Template .............................................................................................132
5 Technical specifications ......................................................... 133
5.1 Ball Grid Array pin out .........................................................................133
5.2 Environmental Specifications...............................................................139
5.3 MSL level ............................................................................................140
5.4 Mechanical specifications....................................................................140
5.4.1 Physical characteristics................................................................140
5.4.2 Mechanical drawings ..................................................................140
5.4.3 Mechanical constraints................................................................143
5.5 PCB specifications...............................................................................143
6 Peripheral devices references ................................................. 143
6.1 SIM Card Reader .................................................................................143
6.2 Microphone.........................................................................................143
6.3 Speaker ...............................................................................................143
6.4 Antenna Cable.....................................................................................144
6.5 GSM antenna ......................................................................................144
7 Noises and design................................................................... 145
7.1 EMC recommendations .......................................................................145
7.2 Power Supply......................................................................................145
8 Appendix................................................................................. 146
8.1 Standards and Recommendations.......................................................146
8.2 Safety recommendations (for information only) ...................................150
8.2.1 RF safety .....................................................................................150
8.2.1.1 General ..................................................................................150
8.2.1.2 Exposure to RF energy...........................................................150
8.2.1.3 Efficient terminal operation ....................................................150
8.2.1.4 Antenna care and replacement ..............................................151
8.2.2 General safety..............................................................................151
8.2.2.1 Driving...................................................................................151
8.2.2.2 Electronic devices ..................................................................151
8.2.2.3 Vehicle electronic equipment .................................................151
8.2.2.4 Medical electronic equipment ................................................151
8.2.2.5 Aircraft ..................................................................................152
8.2.2.6 Children .................................................................................152
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8.2.2.7
Blasting areas ........................................................................152
8.2.2.8 Potentially explosive atmospheres .........................................152
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Table of Figures
Figure 1 : Functional architecture ................................................................... 19
Figure 2 : Power supply during burst emission ..............................................22
Figure 3 : Reject filter diagram........................................................................ 24
Figure 4: SPI Timing diagrams, Mode 0, Master, 4 wires ............................... 35
Figure 5: Example of 4-wire SPI bus application............................................. 36
Figure 6: Example of 3-wire SPI bus application............................................. 37
Figure 7: I²C Timing diagrams, Master ........................................................... 38
Figure 8: First example of I²C bus application................................................. 39
Figure 9: Second example of I²C bus application ............................................ 40
Figure 10: Example of keyboard implementation ............................................ 42
Figure 11: Example of UART1 connection for download with another device on
the link...................................................................................................... 45
Figure 12: Example of RS-232 level shifter implementation for UART1........... 46
Figure 13: Example of V24/CMOS serial link implementation for UART1 ........ 48
Figure 14: Example of full modem V24/CMOS serial link implementation for
UART1 ...................................................................................................... 49
Figure 15: Example of RS-232 level shifter implementation for UART2........... 51
Figure 16: Example of SIM Socket implementation......................................... 54
Figure 17: Example of MIC2 input differential connection with LC filter.......... 67
Figure 18: Example of MIC2 input differential connection without LC filter..... 68
Figure 19: Example of MIC2 input single-ended connection with LC filter ...... 69
Figure 20: Example of MIC2 input single-ended connection without LC filter . 69
Figure 21: Example of MIC1 input differential connection with LC filter.......... 70
Figure 22: Example of MIC1 input differential connection without LC filter..... 71
Figure 23: Example of MIC1 input single-ended connection with LC filter ...... 72
Figure 24: Example of MIC1 input single-ended connection without LC filter . 72
Figure 25: Example of Speaker differential connection.................................... 73
Figure 26: Example of Speaker single-ended connection ................................ 74
Figure 27: Microphone ................................................................................... 75
Figure 28: Audio track design......................................................................... 77
Figure 29: Example of buzzer implementation ................................................ 79
Figure 30: Example of LED driven by the BUZZ-OUT output........................... 79
Figure 31: Charging block diagram................................................................. 80
Figure 32: Charging schematic for Li-Ion ........................................................ 82
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Figure 33: Example of ON/~OFF pin connection ............................................. 84
Figure 34 : Power-ON sequence (no PIN code activated) ................................ 85
Figure 35 : Power-OFF sequence ................................................................... 87
Figure 36: Example of BOOT pin implementation ........................................... 88
Figure 37 : Reset functional block................................................................... 89
Figure 38 : Reset waveform events ................................................................ 90
Figure 39 : Reset sequence waveform............................................................ 91
Figure 40 : BOOT sequence waveform .......................................................... 92
Figure 41: Example of ~RESET pin connection with push button configuration
................................................................................................................. 93
Figure 42: Example of ~RESET pin connection with transistor configuration.. 93
Figure 43: Example of INTx driving example with open collector.................... 95
Figure 44: Example of INTx driving example with open collector.................... 95
Figure 45 : PCB lay out for the crystal MS2V-T1S .......................................... 98
Figure 46 : Real Time Clock power supply...................................................... 99
Figure 47: RTC supplied by a gold capacitor................................................. 100
Figure 48: RTC supplied by a non rechargeable battery................................ 101
Figure 49: RTC supplied by a rechargeable battery cell ................................ 101
Figure 50 : FLASH-LED state during RESET and Initialization time ............... 103
Figure 51: Example of GSM activity status implementation.......................... 104
Figure 52 : PCM Frame waveform................................................................ 106
Figure 53 : PCM Sampling waveform........................................................... 106
Figure 54: Example of USB implementation.................................................. 109
Figure 55: Memory bus ................................................................................ 110
Figure 56: Read synchronous timing ............................................................ 113
Figure 57: Write synchronous timing ...........................................................114
Figure 58: Read / Write Asynchronous timing .............................................. 115
Figure 59: Memory connection schematic .................................................... 120
Figure 60: Memory PCB ............................................................................... 123
Figure 61: Antenna and ground balls placement .......................................... 126
Figure 62: RF 50 ohms embedded line ......................................................... 126
Figure 63: Antenna connection point keep away area ..................................126
Figure 64: RF connector and ESD protection example .................................. 127
Figure 65: Typical hardware configuration ................................................... 128
Figure 66 : Environmental classes ................................................................ 139
Figure 67 : Mechanical drawing ................................................................... 141
Figure 68 : Mechanical drawing ................................................................... 142
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Cautions
This platform contains a modular transmitter. This device is used for wireless
applications. Note that all electronics parts and elements are ESD sensitive.
Information provided herein by WAVECOM is accurate and reliable. However
no responsibility is assumed for its use and any of such WAVECOM
information is herein provided “as is” without any warranty of any kind,
whether express or implied.
General information about WAVECOM and its range of products is available at
the following internet address:
http://www.wavecom.com
Trademarks
®, WAVECOM®, WISMO®, Open AT®, Wireless Microprocessor®, Wireless
®
, and certain other trademarks and logos appearing on this document, are
CPU
filed or registered trademarks of Wavecom S.A. in France or in other countries.
All other company and/or product names mentioned may be filed or registered
trademarks of their respective owners.
Copyright
This manual is copyrighted by WAVECOM with all rights reserved. No part of
this manual may be reproduced in any form without the prior written
permission of WAVECOM. No patent liability is assumed with respect to the
use of their respective owners.
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged
confidential ©
without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à
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1 References
1.1 Reference documents
For more details, several documents are referenced in this specification. The
WAVECOM documents references herein are provided in the WAVECOM
documentation package; the general reference documents which are not
WAVECOM owned are not provided in the documentation package.
1.1.1 WAVECOM reference documentation
®
[1] Wireless Microprocessor
Reference: WM_DEV_WUP_PTS_004
[2] WMP100 Development Kit User Guide
Reference: WM_DEV_WUP_UGD_001
WMP100 Technical Specification
®
[3] AT Command Interface Guide for Open AT
Firmware v6.5
Reference: WM_DEV_OAT_UGD_035
1.1.2 General reference documentation
[4] “I²C Bus Specification”, Version 2.0, Philips Semiconductor 1998
[5] ISO 7816-3 Standard
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1.2 List of abbreviations
Abbreviation Definition
AC Alternative Current
ADC Analog to Digital Converter
A/D Analog to Digital conversion
AF Audio-Frequency
AT ATtention (prefix for modem commands)
AUX AUXiliary
CAN Controller Area Network
CB Cell Broadcast
CEP Circular Error Probable
CLK CLocK
CMOS Complementary Metal Oxide Semiconductor
CS Coding Scheme
CTS Clear To Send
DAC Digital to Analogue Converter
dB Decibel
DC Direct Current
DCD Data Carrier Detect
DCE Data Communication Equipment
DCS Digital Cellular System
DR Dynamic Range
DSR Data Set Ready
DTE Data Terminal Equipment
DTR Data Terminal Ready
EFR Enhanced Full Rate
E-GSM Extended GSM
EMC ElectroMagnetic Compatibility
EMI ElectroMagnetic Interference
EMS Enhanced Message Service
EN ENable
ESD ElectroStatic Discharges
FIFO First In First Out
FR Full Rate
FTA Full Type Approval
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Abbreviation
Definition
GND GrouND
GPI General Purpose Input
GPC General Purpose Connector
GPIO General Purpose Input Output
GPO General Purpose Output
GPRS General Packet Radio Service
GPS Global Positioning System
GSM Global System for Mobile communications
HR Half Rate
I/O Input / Output
LED Light Emitting Diode
LNA Low Noise Amplifier
MAX MAXimum
MIC MICrophone
MIN MINimum
MMS Multimedia Message Service
MO Mobile Originated
MT Mobile Terminated
na Not Applicable
NF Noise Factor
NMEA National Marine Electronics Association
NOM NOMinal
NTC Négative Temperature Coefficient
PA Power Amplifier
Pa Pascal (for speaker sound pressure measurements)
PBCCH Packet Broadcast Control CHannel
PC Personal Computer
PCB Printed Circuit Board
PDA Personal Digital Assistant
PFM Power Frequency Modulation
PSM Phase Shift Modulation
PWM Pulse Width Modulation
RAM Random Access Memory
RF Radio Frequency
RFI Radio Frequency Interference
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Abbreviation
Definition
RHCP Right Hand Circular Polarization
RI Ring Indicator
RST ReSeT
RTC Real Time Clock
RTCM Radio Technical Commission for Maritime services
RTS Request To Send
RX Receive
SCL Serial CLock
SDA Serial DAta
SIM Subscriber Identification Module
SMS Short Message Service
SPI Serial Peripheral Interface
SPL Sound Pressure Level
SPK SPeaKer
SRAM Static RAM
TBC To Be Confirmed
TDMA Time Division Multiple Access
TP Test Point
TVS Transient Voltage Suppressor
TX Transmit
TYP TYPical
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus
USSD Unstructured Supplementary Services Data
VSWR Voltage Standing Wave Ratio
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2 General description
2.1 General information
The WMP100 Wireless Microprocessor® is a self-contained E-GSM/GPRS
900/1800 and 850/1900 quad-band processor, including the characteristics
listed in the subsection below.
2.1.1 Overall dimensions
• Length: 25 mm
• Width: 25 mm
• Thickness: 3.65 mm
• Weight: 4.25 g
• Package: WMBGA576 / ball Ø 0,6 mm @ pitch 1mm
2.1.2 Environment and mechanics
• Green policy: Restriction of Hazardous Substances in Electrical and
Electronic Equipment (RoHS) compliant
• Complete shielding
The WMP100 is compliant with RoHS Directive 2002/95/EC which sets limits
for the use of certain restricted hazardous substances. This directive states
that “from 1st July 2006, new electrical and electronic equipment put on the
market does not contain lead, mercury, cadmium, hexavalent chromium,
polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE)”.
2.1.3 GSM/GPRS Features
• 2 Watts EGSM 900/GSM 850 radio section running under 3.6 Volts
• 1 Watt GSM1800/1900 radio section running under 3.6 Volts
• Hardware GPRS class 10 capable
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2.1.4 Interfaces
• Digital section running under 2.8 Volts and 1.8Volts.
• 3V/1V8 SIM interface
• 1.8V Parallel interface for devices (memories, LCD…)
• Power supply
• Watchdog
• Serial links (UART)
• Analogue audio
• ADC / DAC
• PCM digital audio
• Keyboard
• USB 2.0 slave
• Serial buses (I2C,SPI)
• PWM
• GPIOs
2.1.5 Operating system
• Real Time Clock with calendar
• Echo Cancellation + noise reduction (quadri codec)
• Full GSM or GSM/GPRS Operating System stack
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2.2 Functional description
The global architecture of WMP100 is described below:
WMP100
32768
kHz
Analog Interfaces
AUDIO
CH1 & CH2
DAC
ADCs
Control &
Power
power
supplys
reset
RTC
Charging
DSP
core
ARM 946
32bit
core
AHB bus
Radio
GSM / GPRS
Digital Interfaces
UART
1,2
SPI
1,2
PCM
SIM
I²C
ITs
USB 2.0
KEYPAD
GPIOs
PWM
Extended Memory Bridge
ControlDataAddress
Figure 1 : Functional architecture
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2.2.1 RF functionalities
The Radio Frequency (RF) range complies with the Phase II EGSM 900/DCS
1800 and GSM 850/PCS 1900 recommendation. The frequencies are listed in
the table below.
Transmit band (Tx) Receive band (Rx)
GSM 850 824 to 849 MHz 869 to 894 MHz
E-GSM 900 880 to 915 MHz 925 to 960 MHz
DCS 1800 1710 to 1785 MHz 1805 to 1880 MHz
PCS 1900 1850 to 1910 MHz 1930 to 1990 MHz
The RF part is based on a specific quad band chip including:
• a Digital low-IF receiver
• a Quad-band LNAs (Low Noise Amplifier)
• an Offset PLL (Phase Locked Loop) transmitter
• a Frequency synthesizer
• a Digitally controlled crystal oscillator (DCXO)
• a Tx/Rx FEM (Front-End Wireless Microprocessor
®
) for quad-band
GSM/GPRS
2.2.2 Baseband functionalities
The Baseband is composed of an ARM9, a DSP and an analog element (with
audio signals, I/Q signals, ADC, DAC).
The core power supply is to 1.8 volts. The analog power supply is to 2.8v
2.3 Software description
The Open AT® Software Suite v1.0 is the software package that supports
WMP100. It consists of:
®
• An Open AT
command interface over a serial port or USB.
• An Open AT
applications (telemetry, multimedia, automotive…)
• An Open AT
and debugs applications over the Open AT
• Several Open AT
that are able to run over the Open AT
Firmware v6.5 which drives the WMP100 thanks to an AT
®
Operating System (OS) v5.0 which runs various types of
®
Integrated Development Environment (IDE) which builds
®
plug-ins which are software provided by Wavecom
®
Operating System
®
Operating System
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3 Interfaces
3.1 General Interfaces
The WMP100 is provided with a “Development Kit Wireless Microprocessor®”
containing an access to the all interfaces.
The available interfaces are described in the table below.
chapter Name Driven by
18.5.1 SPI Bus X X
18.5.2 I2C Bus X X
11 Keyboard Interface X X
12.2 Main Serial Link X X
13.2 Auxiliary Serial Link X X
14 SIM Interface X X
3 General Purpose IO X X
18.3 Analog to Digital
Converter
18.4 Digital to Analog
Converter
16 Analog audio Interface
9 PWM / Buzzer Output X X
18.3.1 Battery charging
interface
18.7 External Interruption X X
18.1 VCC_2V8 and
VCC_1V8
17 Real Time Clock X X
18.2 BAT-RTC (Backup
Battery)
8 FLASH-LED signal X X
18.6 Digital Audio Interface
(PCM)
15 USB 2.0 Interface X X
4 Memory interface
(on parallel interface)
Open AT®
Firmware
v6.5
X X
X X
X X
X X
X X
X X
X X
X X
Not
driven by
Open AT®
Firmware
v6.5
Driven by
Open AT®
OS v5.0
Not
driven by
Open AT®
OS v5.0
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3.2 Power supply
3.2.1 Power supply description
The power supply is one of the key elements in the design of a GSM terminal.
The WMP100 is powered by a single power supply VBATT. This power supply
feeds two inputs to the supply, VBATT-BB and VBATT-RF.
VBATT-RF powers all the radio components of the WMP100. It has to be
carefully designed because most of the current is transmitted through this
input. The VBATT-RF current is bursted due to the GSM / GPRS transmission
protocol.
VBATT-BB supplies the digital part of the WMP100. VBATT-BB is directly
connected to the internal power management unit of the WMP100. This unit
controls the VBATT-BB voltage and provides the power supplies like VCC_1V8
and VCC_2V8.
Note: The VBATT-BB input generates noise, so the VBATT must be filtered by a
band reject filter.
3.2.2 Power supply constraints on VBATT-RF
Due to the bursted emission in GSM / GPRS, the power supply must be able to
deliver high current peaks in a short time. During the peaks the ripple (U
the supply voltage must not exceed a certain limit (see
voltage
for details).
Table 1 Power supply
ripp
) on
• In communication mode, a GSM/GPRS class 2 terminal emits 577μs
radio bursts every 4.615ms. (See
VBATT-RFT
t = 577 μs
Uripp
T = 4,615 ms
Figure 2 below.)
Uripp
Figure 2 : Power supply during burst emission
• In communication mode, a GPRS class 10 terminal emits 1154μs radio
bursts every 4.615ms.
VBATT-RF:
• supplies the RF components with 3.6 V directly. It is essential to keep a
minimum voltage ripple at this connection in order to avoid any phase
error.
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The RF Power Amplifier current (1.5 A peak in GSM /GPRS mode) flows
with a ratio of:
o 1/8 of the time (around 577μs every 4.615ms for GSM /GPRS cl. 2)
and
o 2/8 of the time (around 1154μs every 4.615ms for GSM /GPRS cl.
10).
The rising time is around 10μs.
3.2.3 Power supply constraints on VBATT-BB
The VBATT-BB input is used as well to supply the WMP100 core as well to
monitor the level voltage of VBATT.
VBATT-BB is internally connected to several regulators and to a switching
regulator which provides the VCC_1V8 voltage internally. Because the
switching regulator generates perturbation on the VBATT signal, it is
mandatory to add an external reject filter between VBATT and VBATT-BB.
3.2.4 Electrical characteristics
Input power Supply Voltage
V
V
MIN
NOM
V
I
MAX
Ripple max (U
MAX
ripp
)
VBATT-BB 3.2 3.6 4.8 0.3 A (TBC) (TBD)
VBATT-RF
1,2
3.2 3.6 4.8 1.5 A (TBC) 10mV(TBC)
Table 1 Power supply voltage
(1): This value has to be guaranteed during the burst (with 1.5A Peak in GSM
or GPRS mode)
(2): Maximum operating Voltage Stationary Wave Ratio (VSWR) 2:1
When powering the WMP100 with a battery, the total impedance
(battery+protections+PCB) should be <150 mOhms.
3.2.5 Pin description
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Signal Pin number
VBATT-BB
VBATT-RF
AC1,AC2,AD1,AD2
A12,A13,A14,B12,B13,B14
3.2.6 Application
The reject filter must be connected between VBATT and VBATT-BB.
VBATT-RF
VBATT
Filter
C1 C2
L1
VBATT-BB
WMP100
Figure 3 : Reject filter diagram
Recommended components:
C1, C2: 10μF +/-20%
o GRM21BR60J106KE19L from MURATA
o CM21X5R106M06AT from KYOCERA
o JMK212BJ106MG-T from TAYO YUDEN
o C2012X5R0J106MT from TDK
L1: 220nH +/-5%
o 0805CS-221XJLC from COILCRAFT
o 0805G221J E from STETCO
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3.3 Power consumption
Power consumption depends on the configuration used. It is for this reason
that the following consumption values are given for each mode, RF band and
type of software used (with or without an Open AT
Note: All of the following information is given assuming a 50 Ω RF output.
The following consumption values were obtained by performing measurements
on WMP100 samples at a temperature of 25° C.
®
application).
Three VBATT values are used to measure the consumption, VBATT
VBATT
(4.8V) and VBATT
MAX
(3.6V).
TYP
(3.2V),
MIN
The average current is given for the three VBATT values and the peak current
given is the maximum current peak measured with the three VBATT voltages.
For a more detailed description of the operating modes, (refer to the document
[3] AT Command Interface Guide for Open AT® Firmware v6.5).
For more information about the consumption measurement procedure, refer to
§ 4.
All following consumption measurement values have to be confirmed.
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®
3.3.1.1 Power consumption without Open AT
processing
The following measurement results are relevant when:
®
¾ There is no Open AT
®
¾ The Open AT
application is disabled
¾ No processing is required by the Open AT
application
®
application
Power consumption without Open AT® processing
I
Operating mode Parameters
MIN
average
VBATT=4,8V
I
NOM
average
VBATT=3,6V
I
MAX
average
VBATT=3,2V
I
MAX
peak
unit
Alarm Mode
Fast Idle Mode
Slow Idle Mode 1
Fast Standby Mode
Slow Standby Mode
Connected Mode
Transfer Mode
class 8 (4Rx/1Tx)
Transfer Mode
class 10 (3Rx/2Tx)
21
Paging 9 (Rx burst occurrence ~2s) 15
Paging 2 (Rx burst occurrence ~0,5s) 17
Paging 9 (Rx burst occurrence ~2s)
Paging 2 (Rx burst occurrence ~0,5s)
1.5
(1.5 to 1.75)
4
(4 to 4.3)
30
1.4
850/900 MHz
PCL5 (TX power 33dBm) 210
PCL19 (TX power 5dBm) 81
PCL0 (TX power 30dBm) 145
1800/1900 MHz
PCL15 (TX power 0dBm) 77
850/900 MHz
gam. 3(TX power 33dBm) 201
gam.17(TX power 5dBm) 78
gam.3(TX power 30dBm) 138
1800/1900 MHz
gam.18(TX power 0dBm) 74
850/900 MHz
gam.3 (TX power 33dBm) 364
gam.17 (TX power 5dBm) 112
gam.3 (TX power 30dBm) 237
1800/1900 MHz
gam.18 (TX power 0dBm) 104
16
17
18
1.6
(1.6 to 1.9)
4.4
(4.4 to 4.75)
36
1.4
218
89
153
85
209
85
146
81
372
120
245
111
15 µA
18 160 RX mA
19 160 RX mA
1.7
(1.7 to 2.05)
4.6
(4.6 to 4.95)
160
160
RX
RX
39 mA
1.5 mA
222 1450 TX mA
92 270 TX mA
157 850 TX mA
88 250
TX
213 1450 TX mA
88 270
TX
149 850 TX mA
84 250
TX
378 1450 TX mA
123 270 TX mA
248 850 TX mA
115 250
TX
mA
mA
mA
mA
mA
mA
means that the current peak is the RF transmission burst (Tx burst)
TX
means that the current peak is the RF reception burst (Rx burst)
RX
1
Slow Idle Mode consumption depends on the SIM card used. Some SIM cards
respond faster than others, in which case the longer the response time is, the
higher the consumption is. These measurements were performed with a large
number of 3V SIM cards, the results in brackets are the minimum and
maximum currents measured from among all the SIMs used.
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®
3.3.1.2 Power consumption with a Dhrystone Open AT
®
The Open AT
application used is the Dhrystone application. The following
application
consumption results are measured during the run of the Dhrystone application.
Power consumption with Dhrystone Open AT® application
I
Operating mode Parameters
MIN
average
VBATT=4,8V
I
NOM
average
VBATT=3,6V
I
MAX
average
VBATT=3,2V
I
MAX
peak
unit
Alarm Mode
Fast Idle Mode
Slow Idle Mode
Fast Standby Mode
Slow Standby Mode
Connected Mode
Transfer Mode
class 8 (4Rx/1Tx)
Transfer Mode
class 10 (3Rx/2Tx)
N/A
Paging 9 (Rx burst occurrence ~2s) 31
Paging 2 (Rx burst occurrence ~0,5s) 32
Paging 9 (Rx burst occurrence ~2s) N/A
Paging 2 (Rx burst occurrence ~0,5s) N/A
31
N/A
850/900 MHz
PCL5 (TX power 33dBm) 211
PCL19 (TX power 5dBm) 82
PCL0 (TX power 30dBm) 146
1800/1900 MHz
PCL15 (TX power 0dBm) 78
850/900 MHz
gam. 3(TX power 33dBm) 202
gam.17(TX power 5dBm) 78
gam.3(TX power 30dBm) 140
1800/1900 MHz
gam.18(TX power 0dBm) 75
850/900 MHz
gam.3 (TX power 33dBm) 365
gam.17 (TX power 5dBm) 113
gam.3 (TX power 30dBm) 239
1800/1900 MHz
gam.18 (TX power 0dBm) 105
N/A
38
39
N/A
N/A
38
N/A
219
90
154
85
210
86
148
82
373
121
247
113
N/A µA
41 160 RX mA
42 160
mA
RX
N/A 160 RX mA
N/A 160 RX mA
41 mA
N/A mA
223 1450 TX mA
93 270
mA
TX
159 850 TX mA
89 250
mA
TX
214 1450 TX mA
89 270
mA
TX
151 850 TX mA
85 250 TX mA
379 1450 TX mA
125 270
mA
TX
250 850 TX mA
117 250
mA
TX
means that the current peak is the RF transmission burst (Tx burst)
TX
means that the current peak is the RF reception burst (Rx burst)
RX
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3.3.1.3 Consumption waveform samples
The consumption waveforms presented below are for an EGSM900 network
configuration without the Open AT
®
Software Suite running on the WMP100.
The typical VBATT voltage is 3.6V.
Four significant operating mode consumption waveforms are described:
¾ Connected Mode (PCL5: Tx power 33dBm)
¾ Slow Idle mode (Paging 9)
¾ Fast idle mode (Paging 9)
¾ Transfer mode (GPRS class 10, gam.3: Tx power 33dBm )
The following waveform shows only the form of the current.
3.3.1.3.1 Connected mode current waveform
Connected mode 33dBm
Current(A) / Time (s)
1.6
TX PEAK
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0
.
0
0
2
0
.
0
0
4
0
.
0
0
6
0
.0
0
8
0
.0
1
0
.
0
1
2
0
.
0
1
4
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3.3.1.3.2 Slow Idle mode current waveform
Slow Idle mode Paging ~2s
Current(A) / Time (s)
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
-0.02
RX PEAK
0
0
1
2
3
4
5
6
7
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3.3.1.3.3 Fast Idle mode current waveform
Fast Idle mode Paging ~2s
Current(A) / Time (s)
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
RX PEAK
0
0
1
2
3
4
5
6
7
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3.3.1.3.4 Transfer mode Class 10 current waveform
Transfer mode Class 10 33dBm
Current(A) / Time (s)
1.6
TX PEAK
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0
.
0
0
2
0
.
0
0
4
0
.
0
0
6
0
.
0
0
8
0
.
0
1
0
.
0
1
2
0
.
0
1
4
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3.4 Electrical information for digital I/O
There are three types of digital I/O on the WMP100: 2.8Volt CMOS, 1.8Volt
CMOS and Open drain.
The I/O concerned are all interfaces like GPIOs, SPIs, Keypad, etc.
The three types are described below.
Electrical characteristics of digital I/O
2.8 Volts type (2V8 )
Parameter I/O type Minim. Typ Maxim. Condition
Internal 2.8V power supply
Input / Output pin
VIL
VIH
VOL
VOH
IOH
IOL
*Absolute maximum ratings
VCC_2V8
CMOS
CMOS
CMOS
CMOS
1.8 Volts type (1V8)
Parameter I/O type Minim. Typ Maxim. Condition
Internal 1V8 power supply VCC_1V8
Input / Output pin
VIL CMOS -0.5V* 0.54V
VIH CMOS 1.33V 2.2V*
2.74V 2.8V 2.86V
-0.5V* 0.84V
1.96V 3.2V*
0.4V IOL = - 4 mA
2.4V IOH = 4 mA
4mA
- 4mA
1.76V 1.8V 1.94V
VOL CMOS 0.4V IOL = - 4 mA
VOH CMOS 1.4V IOH = 4 mA
IOH
IOL
*Absolute maximum ratings
confidential ©
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4mA
- 4mA
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Open drain outputs type
Signal name Parameter I/O type Minimum Typ Maximum Condition
FLASH-LED
SDA /
GPIO27
and
SCL /
VOL Open Drain
IOL Open Drain
VOL Open Drain
I
Open Drain
OL
V
Open Drain
TOL
VIH Open Drain
VIL Open Drain
0.4V
8mA
0.4V BUZZ-OUT
100mA
3.3V Tolerated
2V
0.8V
voltage
GPIO26
VOL Open Drain
Open Drain
I
OL
0.4V
3mA
The reset states of each I/O are given in their corresponding interface’s chapter
descriptions. The states definitions are defined below:
Reset state definition
Parameter Definition
0
1
Pull down
Set to GND
Set to supply 1V8 or 2V8 depending of I/O type
Internal pull down with ~60K resistor.
Pull up Internal pull up with ~60K resistor to supply 1V8 or 2V8
depending of I/O type.
Z High impedance
Undefined Be careful, undefined mustn’t be used in your application if
a special state at reset is needed. Those pins can be a
toggling signal during reset.
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3.5 SPI Bus
The WMP100 provides two SPI bus (i.e. for LCD, memories…).
3.5.1 Features
• a CLK signal
• an I/O signal
• an I signal
• a CS signal complying with standard SPI bus.
3.5.1.1 Characteristics
• Master mode operation
• The Hardware CS is usable only for word handling mode. In normal
mode the CS can be any GPIO.
• The SPI speed is from 102 Kbit/s up to 13 Mbit/s in master mode
operation
• 3 or 4-wire interface
• SPI-mode configuration: 0 to 3 (for more details, refer to document
AT Command Interface Guide for Open AT® Firmware v6.5).
• 1 to 16 bits data length
3.5.1.2 SPI configuration
Operation Maximum
Speed
Master 13 Mb/s 0,1,2,3
For the 4-wire configuration, SPIx-I/O is used as output only, SPIx-I is used as input only.
For the 3-wire configuration, SPIx-I/O is used as input and output.
SPI-
Mode
Duplex
3-wire type 4-wire type
Half SPIx-CLK; SPIx-
IO; ~SPIx-CS
SPIx-CLK; SPIx-IO;
SPIx-I; ~SPIx-CS
[3]
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3.5.1.3 SPI waveforms
Waveform for SPI transfer with 4-wire configuration in master mode 0 (chip
select is not represented).
CLK-cycle
SPIx-CLK
Data-OUTdelay
SPIx-IO
Data valid
Data-IN-setup
SPIx-I
Data-IN-hold
Data valid
Figure 4: SPI Timing diagrams, Mode 0, Master, 4 wires
AC characteristics
Signal Description Minimum Typ Maximum Unit
CLK-cycle SPI clock frequency 0.1015 13 MHz
Data-OUT delay Data out ready delay time 10 ns
Data-IN-setup Data in setup time 2 ns
Data-OUT-hold Data out hold time 2 ns
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3.5.2 Pin description
Signal Pin
number
I/O I/O
type
Reset
state
Description Multiplexed
with
SPI1-CLK U15 O 2V8 Z SPI Serial Clock GPIO28
SPI1-IO
SPI1-I
~SPI1-CS
V12
R13
M14
I/O 2V8 Z SPI Serial input/output GPIO29
I 2V8 Z SPI Serial input GPIO30
O 2V8 Z SPI Enable GPIO31 /
INT5
Signal Pin
number
SPI2-CLK
SPI2-IO
SP2-I
~SPI2-CS
R15
M13
U16
T18
I/O I/O
type
Reset
state
Description Multiplexed
with
O 2V8 Z SPI Serial Clock GPIO32
I/O 2V8 Z SPI Serial input/output GPIO33
I 2V8 Z SPI Serial input GPIO34
O 2V8 Z SPI Enable GPIO35 /
INT4
See chapter
characteristics and for Reset state definition.
3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
3.5.3 Application
3.5.3.1 4-wire interface
The particularity of the 4-wire serial interface (SPI bus) is that the input and the
output data lines are dissociated. The SPIx-IO signal is used only for data
output and the SPIx-I signal is used only for data input.
SPIx-CLK
SPIx-IO
WMP100
SPIx-I
VCC_2 V8
R1
~SPIx -CS
Customer
application
Figure 5: Example of 4-wire SPI bus application
One pull up resistor R is needed to set the SPIx-CS level during the reset state.
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Except for R, no external component is needed if the electrical specification of
the customer application complies with the WMP100 SPIx interface electrical
specification.
3.5.3.2 3-wire interface
When used in 3-wire interface (SPI bus), only the line SPIx-IO is used for
output and input data.
SPIx-CLK
SPIx-IO
WMP100
SPIx-I
~SPIx -CS
VCC_2 V8
R1
Customer
application
Figure 6: Example of 3-wire SPI bus application
The SPIx-I line is not used in 3-wire configuration. This line can be left opened
or used as GPIO for a different application functionality.
One pull up resistor R is needed to set the SPIx-CS level during the reset state.
Except for R, no external component is needed if the electrical specification of
the customer application complies with the WMP100 SPIx interface electrical
specification.
The SPIx interface voltage range is 2.8V. It can be powered by the VCC_2V8
(ball R1) of the WMP100 or by another power supply.
R value depends on the peripheral plugged on the SPIx interface.
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3.6 I2C bus
3.6.1 Features
The I2C interface includes a clock signal (SCL) and a data signal (SDA)
complying with a 100Kbit/s-standard interface (standard mode: s-mode).
3.6.1.1 Characteristics
The I²C bus is always master.
The maximum speed transfer range is 400Kbit/s (Fast mode: f-mode).
For more information on the bus, see document
Version 2.0, Philips Semiconductor 1998
.
3.6.1.2 I²C waveforms
I²C bus waveform in master mode configuration:
SCL-freq
T-high
SCL
T-data-
setup
Data valid
SDA
T-free
T-start
Data valid
T-data-
hold
[4] “I²C Bus Specification”,
T-stop
Figure 7: I²C Timing diagrams, Master
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AC characteristics
Signal Description Minimum Typ Maximum Unit
SCL-freq I²C clock frequency 100 400 KHz
T-start Hold time START condition 0.6 μs
T-stop Setup time STOP condition 0.6 μs
T-free Bus free time, STOP to START
1.3 μs
T-high High period for clock 0.6 μs
T-data-hold Data hold time 0 0.9 μs
T-data-setup Data setup time 100 ns
3.6.2 Pin description
Signal Pin
number
SCL
SDA
See chapter 3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
characteristics and for Reset state definition.
AA15
AA16
I/O I/O type Reset
state
Description Multiplexed
with
O Open drain Z Serial Clock GPIO26
I/O Open drain Z Serial Data GPIO27
3.6.3 Application
The two lines need to be pull up to the V
I²C voltage. The VI²C voltage is
dependent on the customer application component connected on the I²C bus.
Nevertheless, the VI²C must complying with the WMP100 electrical
specification (3.3V Max).
The VCC_2V8 (ball R1) of the WMP100 can be used to connect the pull up
resistors, if the I²C bus voltage is 2.8 V.
VI²C
1K 1K
WMP100
SCL
SDA
Customer
application
Figure 8: First example of I²C bus application
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The I²C bus is complying with the Standard mode (baud rate 100Kbit/s) and
the Fast mode (baud rate 400Kbit/s). The pull up resistor value choice depends
on the mode used. For the Fast mode, it is recommended to use 1K ohm
resistor to ensure the compliance with the I²C specification. For the Standard
mode, higher values of resistors can be used to save power consumption.
R1
WMP100
VCC_2V8
SCL
SDA
Figure 9: Second example of I²C bus application
3.7 Keyboard interface
3.7.1 Features
This interface provides 10 connections:
1K 1K
Customer
application
5 rows (ROW0 to ROW4),
5 columns (COL0 to COL4).
The scanning is a digital one, and the debouncing is done in the WMP100. No
discrete components like resistors or capacitors are needed.
The keyboard scanner is equipped with:
• internal pull-down resistors for the rows
• pull-up resistors for the columns.
Current only flows from the column pins to the row pins. This allows a
transistor to be used in place of the switch for power-on functions.
No discrete components like R, C (Resistor, Capacitor) are needed.
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3.7.2 Pin description
Signal Pin
number
ROW0
ROW1
ROW2
ROW3
ROW4
COL0
COL1
COL2
COL3
COL4
See chapter
characteristics and for Reset state definition.
AC23
AD22
AD21
AC22
AD23
AD19
AD20
AC20
AC19
AC21
3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
I/O I/O
type
I/O 1V8 0 Row scan GPIO9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
1V8
Reset
state
Description Multiplexed
with
0 Row scan GPIO10
0 Row scan GPIO11
0 Row scan GPIO12
0 Row scan GPIO13
Pull up Column scan GPIO4
Pull up Column scan GPIO5
Pull up Column scan GPIO6
Pull up Column scan GPIO7
Pull up Column scan GPIO8
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3.7.3 Application
Keypad matrix application allows for up to 25 keys.
0
l
o
C
1
l
o
C
2
l
o
C
3
l
o
C
4
l
o
C
Row 0
Row 1
Row 2
Row 3
Row 4
Figure 10: Example of keyboard implementation
3.8 Main serial link (UART1)
A flexible 8-wire serial interface is available complying with V24 protocol
signaling but not with V28 (electrical interface) due to a 2.8 Volts interface.
3.8.1 Features
The maximum baud rate of the UART1 is 460 Kbit/s.
The signals are the follows:
• TX data (CT103/TX)
• RX data (CT104/RX)
• Request To Send (~CT105/RTS)
• Clear To Send (~CT106/CTS)
• Data Terminal Ready (~CT108-2/DTR)
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• Data Set Ready (~CT107/DSR)
• Data Carrier Detect (~CT109/DCD)
• Ring Indicator (~CT125/RI).
3.8.2 Pin description
Signal Pin
CT103/TXD1*
CT104/RXD1*
~CT105/RTS1*
~CT106/CTS1*
~CT107/DSR1*
~CT108-
number
R17
T13
Y18
N15
T12
M16
I/O I/O
type
I 2V8 Z Transmit serial
2V8
O
2V8
I
2V8
O
2V8
O
2V8
I
2/DTR1*
~CT109/DCD1 *
~CT125/RI1 *
CT102/GND*
See chapter
characteristics and for Reset state definition.
*According to PC view
3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
AB16
AA18
AA19
2V8
O
2V8
O
GND Ground
Reset
state
Description Multiplexed
with
GPIO36
data
1 Receive serial
GPIO37
data
Z Request To
GPIO38
Send
Z Clear To Send GPIO39
Z Data Set Ready GPIO40
Z Data Terminal
GPIO41
Ready
Undefined Data Carrier
GPIO43
Detect
Undefined Ring Indicator GPIO42
The rising time and falling time of the reception signals (mainly CT103) have to
be less than 300 ns.
Recommendation:
The WMP100 is designed to operate using all the serial interface signals. In
particular, it is mandatory to use RTS and CTS for hardware flow control in
order to avoid data corruption during transmission.
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For the use case with 5-wire serial interface
• Signal: CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*
• The signal ~CT108-2/DTR1* must be managed following the V24
protocol signalling if we want to use the slow idle mode
• The other signals and their multiplexed are not available
• Please refer to the document
®
Firmware v6.5 for more information.
AT
[3] AT Command Interface Guide for Open
For the use case with 4-wire serial interface
• CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*
• The signal ~CT108-2/DTR1* must be configured at the low level
• The other signals and their multiplexed are not available
• Please refer to the document
®
Firmware v6.5 for more information.
AT
[3] AT Command Interface Guide for Open
For the use case with 2-wire serial interface
• This case is possible for connected external chip but not recommended
(and forbidden for AT command or modem use)
• The external chip must be a flow control
• CT103/TXD1*, CT104/RXD1*
• The signal ~CT108-2/DTR1* must be configured at the low level
• The signals ~CT105/RTS1*, ~CT106/CTS1* are not used, please
configure the AT command (AT+IFC=0,0 see document
Command Interface Guide for Open AT
®
Firmware v6.5).
[3] AT
• The signal ~CT105/RTS1* must be configured at the low level
• The other signals and their multiplexed are not available
• Please refer to the document
®
Firmware v6.5 for more information.
AT
[3] AT Command Interface Guide for Open
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3.8.3 First download
The first download of the Flash (when Flash is blank) of the WMP100 must be
done through the UART1 serial interface. That’s mandatory that the UART1 is
available for the first download, so it’s necessary to be careful about the
connectivity of the UART1 with others devices used in the application.
If no device is connected and there are no conflicts, the computer can be
directly connected on the WMP100 through a RS232 level shifter.
When a device is used on UART1, allowing for the ability to unselect the device
during the download is recommended (via the enable signal).
Figure 11: Example of UART1 connection for download with another device
on the link
The Download connector is directly connected on the four UART1 signals,
which may create conflicts with the Device lines. For this reason an enable
must be available on the device to set the device output signals at High
impedance.
NOTE:
• In this configuration (4-wire), the signal ~CT108-2/DTR1 (ball M16)
must be configured at the low level.
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At the same time, to run the first download, the BOOT signal of the WMP100
must be driven. The switch S2 must be closed. After the download started S2
can be open. See the BOOT signal chapter (§ 3.18) for more information.
If the WMP100 is power ON (VBATT present), S1 must be closed for enable
the WMP100.
Start the specific PC software tool provided by WAVECOM.
S3 must be closed* (a pulse to 0L during at least 200μs) for start the
download. See RESET signals chapter (§3.19) for more information.
* S3 can be not use if the condition on S1 and S2 are respected before than the
power supply is applied.(There is in this case an automatic internal reset).
If a computer is used for the first download, a RS232 level shifter must be used
(See the application with the ADM3307EACP in this chapter).
Note: XMODEM download can be launched through UART1 and UART2, but
first download has to be launched with a specific PC software tool provided by
WAVECOM only through UART1.
3.8.4 Application
The level shifter must be a 2.8V with V28 electrical signal compliant.
Figure 12: Example of RS-232 level shifter implementation for UART1
U1 chip also protects the WMP100 against ESD at 15KV. (Air Discharge)
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Recommended components:
R1, R2 : 15Kohm
C1, C2, C3, C4, C5 : 1uF
C6 : 100nF
C7 : 6.8uF TANTAL 10V CP32136 AVX
U1 : ADM3307EACP ANALOG DEVICES
J1 : SUB-D9 female
R1 and R2 are necessary only during Reset state to forced ~CT1125-RI1 and
~CT109-DCD1 signal to high level.
The ADM3307EACP chip is able to speed up to 921Kb/s*. If others level
shifters are used, ensured that their speed are compliant with the UART1
speed useful.
*: For this baud rate the power supply must be provided by an external
regulator at 3.0 V.
The ADM3307EACP can be powered by the VCC_2V8 (ball R1) of the WMP100
or by an external regulator at 2.8 V (the baud rate will be limited up to
720kbps).
If the UART1 interface is connected directly to a host processor, it is not
necessary to used level shifters. The interface can be connected as shown
below:
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V24/CMOS possible design
:
ON / ~OFF
~RESET
CT103-TXD1 / GPIO36
CT104-RXD1 / GPIO37
~CT105-RTS1 / GPIO38
~CT106-CTS1 / GOPI39
Tx
Customer application
Rx
RTS
CTS
GND
( DTE )
WMP100
( DCE )
U5
V6
R17
T13
Y18
N15
M16
GND
Figure 13: Example of V24/CMOS serial link implementation for UART1
The design shown in the above figure is a basic design.
However, a more flexible design to access this serial link with all modem
signals is shown below
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ON / ~OFF
~RESET
2.8Volt
2x 15K
~CT109-DCD1 / GPIO43
~CT125-RI1 / GPIO42
CT103-TXD1 / GPIO36
CT104-RXD1 / G PIO37
~CT105-RTS1 / GPIO38
~CT106-CTS1 / GOPI39
~CT107-DSR1 / GPIO40
~CT108-2-DTR1 / GPIO41
GND
DCD
Customer
RI
application
Tx
Rx
RTS
CTS
DSR
DTR
GND
( DTE )
WMP100
( DCE )
U5
V6
AB16
AA18
R17
T13
Y18
N15
T12
M16
GND
Figure 14: Example of full modem V24/CMOS serial link implementation for
UART1
It is recommended to add a 15K-ohm pull-up resistor on ~CT125-RI1 and
~CT109-DCD1 to set high level during reset state.
The UART1 interface is 2.8 Volt type, but is 3 Volt tolerant.
The WMP100 UART1 is designed to operate using all the serial interface
signals. In particular, it is mandatory to use RTS and CTS for hardware flow
control in order to avoid data corruption during transmission.
Warning: If you want to activate Power Down mode (Wavecom 32K mode) in
your Open AT® application, you need to wire the DTR ball to a GPIO. Please
refer to the document
(see the “Appendixes”) for more information on Wavecom 32K mode
v6.5
[3] AT Command Interface Guide for Open AT® Firmware
activation using the Open AT® Software Suite.
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3.9 Auxiliary serial link (UART2)
An auxiliary serial interface (UART2) is available on WMP100. This interface
may be used to connect a Bluetooth or a GPS chip controlled by an Open AT
®
Plug-in.
3.9.1 Features
Maximum baud rate of the UART2 is 460 Kbit/s.
The signals are the follows:
• TX data (CT103/TX)
• RX data (CT104/RX)
• Request To Send (~CT105/RTS)
• Clear To Send (~CT106/CTS)
The WMP100 is designed to operate using all the serial interface signals. In
particular, it is mandatory to use RTS and CTS for hardware flow control in
order to avoid data corruption during transmission.
For the use case with 2-wire serial interface
• This case is possible for connected external chip but not recommended
(and forbidden for AT command or modem use)
• The external chip must be a flow control
• CT103/TXD2*, CT104/RXD2*
• The signals ~CT105/RTS2*, ~CT106/CTS2* are not used, please
configure the AT command (AT+IFC=0,0. Please refer to the document
[3] AT Command Interface Guide for Open AT® Firmware v6.5.
• The signal ~CT105/RTS2* must be configured at the low level
• The other signal and their multiplexed are not available
• Please refer to the document
®
Firmware v6.5 (see the “Appendixes”).
AT
[3] AT Command Interface Guide for Open
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3.9.2 Pin description
Signal Pin
number
CT103 /
T16
TXD2*
CT104 /
U17
I/O I/O type Reset
state
Description Multiplexed
with
I 1V8 Z Transmit serial data GPIO14 /
INT6
O
1V8
Z Receive serial data GPIO15
RXD2*
~CT106 /
W17
O
1V8
Z Clear To Send GPIO16
CTS2*
~CT105 /
V13
I
RTS2*
CT102/GND*
* According to PC view
See chapter
characteristics and for Reset state definition.
V15
3.4, “Electrical information for digital I/O” Open drain, 2V8 and 1V8 voltage
GND Ground
1V8
Z Request To Send GPIO17 /
INT7
3.9.3 Application
The voltage level shifter must be a 1.8V with V28 electrical signal compliant.
Figure 15: Example of RS-232 level shifter implementation for UART2
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Recommended components:
Capacitors
C1 : 220nF
C2, C3, C4 : 1μF
Inductor
L1 : 10μH
RS-232 Transceiver
®
U1 : LINEAR TECHNOLOGY LTC
2804IGN
J1 : SUB-D9 female
The LTC2804 can be powered by the VCC_1V8 (ball AD5) of the WMP100 or
by an external regulator at 1.8 V.
The UART2 interface can be connected directly to others components if the
voltage interface is 1.8 V.
3.10 SIM Interface
The Subscriber Identification Module can be directly connected to the
WMP100 through this dedicated interface.
3.10.1 Features
The SIM interface controls 1.8V and 3V SIM card.
It is recommended to add Transient Voltage Suppressor diodes (TVS) on the
signal connected to the SIM socket in order to prevent any Electrostatics
Discharge.
TVS diodes with low capacitance (less than 10 pF) have to be connected on
SIM-CLK and SIM-IO signals to avoid any disturbance of the rising and falling
edge.
These types of diodes are mandatory for the Full Type Approval. They shall be
placed as close as possible to the SIM socket.
The following references can be used: DALC208SC6 from ST Microelectronics.
5 signals exist:
• SIM-VCC: SIM power supply.
• ~SIM-RST: reset.
• SIM-CLK: clock.
• SIM-IO: I/O port.
• SIMPRES: SIM card detect.
The SIM interface controls a 3V / 1V8 SIM. This interface is fully compliant
with GSM 11.11 recommendations concerning SIM functions.
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Electrical Characteristics of SIM interface
Parameter Conditions Minim. Typ Maxim. Unit
SIM-IO VIH
SIM-IO VIL I
~SIM-RST, SIM-CLK
V
OH
SIM-IO VOH
~SIM-RST, SIM-IO,
SIM-CLK
V
OL
Voltage
SIM-VCC current
SIM-CLK Rise/Fall
= ± 20μA
I
IH
= 1mA
IL
Source current = 20μA
Source current = 20μA
Sink current =
-200μA
SIMVCC = 2.9V
I
VCC= 1mA
SIMVCC = 1.8V
I
VCC= 1mA
VBATT = 3.6V
Loaded with 30pF
Time
~SIM-RST, Rise/Fall
Loaded with 30pF
Time
0.7xSIMVCC
V
0.4 V
0.9xSIMVCC
0.8xSIMVCC
V
0.4 V
2.84 2.9 2.96
1.74 1.8 1.86
10
20 ns
20 ns
V SIM-VCC Output
V
mA
SIM-IO Rise/Fall
Time
SIM-CLK Frequency
Loaded with 30pF
Loaded with 30pF
0.7 1 μs
3.25 MH
z
Note:
When SIMPRES is used, a low to high transition means that the SIM card is
inserted and a high to low transition means that the SIM card is removed.
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3.10.2 Pin description
Signal Pin
I/O I/O type Reset
number
SIM-CLK
~SIM-RST
SIM-IO
SIM-VCC
SIMPRES
*SIM-IO pull up is about 10K ohm
See chapter
1V8 voltage characteristics and for Reset state definition.
3.4, “Electrical information for digital I/O” on page 32 for Open drain, 2V8 and
Y2
Y1
W1
W2
Y3
O 2V9 / 1V8 0 SIM Clock Not mux
I
2V9 / 1V8
2V9 / 1V8
2V9 / 1V8
1V8
*Pull up SIM Data
O
I/O
O
3.10.3 Application
Description Multiplexed
state
0 SIM Reset
SIM Power
Supply
Z SIM Card
Detect
with
Not mux
Not mux
Not mux
GPIO18 /
INT8
Figure 16: Example of SIM Socket implementation
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Recommended components:
• R1 : 100K ohm
• C1 : 470pF
• C2 : 100nF
• D1 : ESDA6V1SC6 from ST
• D2 : DALC208SC6 from SGS-THOMSON
• J1 : ITT CANNON CCM03 series (See chapter 9.2 for more information)
The capacitor (C2) placed on the SIM-VCC line must not exceed 330 nF.
SIM socket connection:
Pin description of the SIM socket
Signal Pin number Description
VCC 1 SIM-VCC
RST 2 ~SIM-RST
CLK 3 SIM-CLK
CC4 4
SIMPRES with 100 kΩ
pull down resistor and
470 pF capacitor
GND 5 GROUND
VPP 6 Not connected
I/O 7 SIM-IO
CC8 8 VCC_1V8 of WMP100 (ball AD5 )
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3.11 General Purpose Input/Output
The Wireless Microprocessor® provides up to 49 General Purpose I/O. They are
used to control any external device such as a LCD or a Keyboard backlight...
3.11.1 Features
Reset State:
0 : Set to GND
1: Set to supply 1V8 or 2V8 depending of I/O type.
Pull down: Internal pull down with ~60K resistor.
Pull up: Internal pull up with ~60K resistor to supply 1V8 or 2V8
depending of I/O type.
Z: High impedance.
Undefined: Be careful, undefined mustn’t be used in your application if
a special state at reset is needed. Those pins can be toggling signals.
3.11.2 Pin description
Signal
Pin
number
I/O I/O type
Reset state
Multiplexed with
GPIO0 W15 I/O 1V8 0 Not mux
GPIO1 R18
GPIO2
GPIO3
U22
V16 I/O 1V8
I/O
I/O
1V8 Z CS2 / A25
1V8
Z
Z
A24
INT0 / A26
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
AD19 I/O 1V8
AD20 I/O 1V8
AC20 I/O 1V8
AC19 I/O 1V8
AC21 I/O 1V8
AC23 I/O 1V8
AD22 I/O 1V8
AD21 I/O 1V8
AC22 I/O 1V8
AD23 I/O 1V8
Pull up
Pull up
Pull up
Pull up
Pull up
0
0
0
0
0
COL0
COL1
COL2
COL3
COL4
ROW0
ROW1
ROW2
ROW3
ROW4
GPIO14 T16 I/O 1V8 Z CT103-TXD2 / INT6
GPIO15 U17 I/O 1V8 Z CT104-RXD2
GPIO16 W17 I/O 1V8 Z ~CT106-CTS2
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Signal
Pin
number
I/O I/O type
Reset state
Multiplexed with
GPIO17 V13 I/O 1V8 Z ~CT105-RTS2 /
INT7
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
Y3 I/O 1V8
AA17 I/O 2V8
Y13 I/O 2V8
AA13 I/O 2V8
M15 I/O 2V8
V17 I/O 2V8
N16 I/O 2V8
Y19 I/O 2V8
AA15 I/O
AA16 I/O
Open
drain
Open
drain
Z SIMPRES / INT8
Z Not mux
Undefined
Undefined
Z
Not mux
Not mux
Not mux
Z Not mux
Z Not mux
Z
Z
Z
INT1
SCL
SDA
GPIO28 U15 I/O 2V8 Z SPI1-CLK
GPIO29 V12 I/O 2V8 Z SPI1-IO
GPIO30 R13 I/O 2V8 Z SP1-I
GPIO31 M14 I/O 2V8 Z ~SPI1-CS / INT5
GPIO32 R15 I/O 2V8 Z SPI2-CLK
GPIO33 M13 I/O 2V8 Z SPI2-IO
GPIO34 U16 I/O 2V8 Z SP2-I
GPIO35 T18 I/O 2V8 Z ~SPI2-CS / INT4
GPIO36 R17 I/O 2V8 Z CT103-TXD1
GPIO37 T13 I/O 2V8 1 CT104-RXD1
GPIO38 Y18 I/O 2V8 Z ~CT105-RTS1
GPIO39 N15 I/O 2V8 Z ~CT106-CTS1
GPIO40 T12 I/O 2V8 Z ~CT107-DSR1
GPIO41 M16 I/O 2V8 Z ~CT108-2-DTR1
GPIO42 AA18 I/O 2V8 Undefined ~CT125-RI1
GPIO43 AB16 I/O 2V8 Undefined ~CT109-DCD1
GPIO44 AB13 I/O 2V8 Undefined 32kHz buffered
output clock
GPIO45 Y17 I/O 1V8 Z INT2
GPIO46 V18 I/O 2V8 Z INT3
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Signal
Pin
number
I/O I/O type
Reset state
Multiplexed with
GPIO47 Y15 I/O 1V8 0 Not mux
GPIO48 Y16 I/O 1V8 0 Not mux
See chapter
characteristics and for Reset state definition.
3.4, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage
3.12 Analog to Digital Converter
Three Analog to Digital Converters inputs are provided by the WMP100. Those
converters are 10 bits resolution, ranging from 0 to 2V.
3.12.1 Features
BAT-TEMP / AUX-ADC2 input can be used, typically, to monitor external
temperature, useful for safety power off in case of application over heating (for
Li-Ion battery).
AUX-ADC0 and AUX-ADC1 input can be used for customer application
Electrical Characteristics of ADC
Parameter Min Typ Max Unit
Resolution 10 bits
Sampling rate 216 S/s
Input signal range 0 2 V
ADC Reference Accuracy TBD %
Integral Accuracy 15 mV
Differential Accuracy 2.5 mV
Input
impedance
BAT-TEMP /
AUX-ADC2
AUX-ADC0
AUX-ADC1
1M
1M
1M
Ω
Ω
Ω
3.12.2 Pin description
Signal Pin number I/O I/O type Description
BAT-TEMP / AUX-
confidential ©
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N18
I Analog A/D converter
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ADC2*
AUX-ADC0
AUX-ADC1
*This input can be used for battery charging temperature sensor,
see chapter “
3.16 Battery Charging interface “.
N17
M17
I Analog A/D converter
I Analog A/D converter
3.12.3 Application
The BAT-TEMP / AUX-ADC2 input is used for battery monitoring during
charging of battery. All information is provided in the “Battery Charging” (see
chapter 3.16).
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3.13 Digital to Analog Converter
One Digital to Analog Converter (DAC) input is provided by the Wireless
Microprocessor
®
.
3.13.1 Features
The converter is 8-bit resolution, guaranteed monotonic with a ranges from 0V
to 2.3V.
This output assumes a typical external load of 2kΩ and 50pF in parallel to GND.
Electrical Characteristics of the DAC
Parameter Min Typ Max Unit
Resolution - 8 - bits
Maximum Output voltage 2.1 2.2 2.3 V
Minimum Output voltage 0 - 40 mV
Output voltage after reset - 1.147 - V
Integral Accuracy -5 - +5 LSB
Differential Accuracy -1 - +1 LSB
Full scale settling time
- 40 - μs
(load: 50pF // 2kΩ to GND)
One LSB settling time
- 8 - μs
(load: 50pF // 2kΩ to GND
)
3.13.2 Pin description
Pin description of the DAC
Signal Pin number I/O I/O type Description
AUX-DAC0 V14 O Analog D/A converter
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3.14 Analogue audio interface
Two different microphone inputs and two different speaker outputs are
supported. The WMP100 also includes an echo cancellation feature which
allows hands free function.
In some cases, ESD protection must be added on the audio interface lines.
3.14.1 Microphone Features
The connection can be either differential or single-ended but using a differential
connection in order to reject common mode noise and TDMA noise is strongly
recommended. When using a single-ended connection, be sure to have a very
good ground plane, a very good filtering as well as shielding in order to avoid
any disturbance on the audio path.
The gain of MIC inputs is internally adjusted and can be tuned using an AT
command.
Both can be configured in differential or single ended.
The MIC2 inputs already include the biasing for an electret microphone
allowing an easy connection.
3.14.1.1 Electrical characteristics
3.14.1.1.1 MIC1 Microphone Inputs
By default, the MIC1 inputs are single-ended but it can be configured in
differential.
The MIC1 inputs do not include an internal bias . The MIC1 input needs to
have an external biasing if an electret micro is used.
®
AC coupling is already embedded in the Wireless Microprocessor
.
Equivalent circuits of MIC1
DC equivalent circuit AC equivalent circuit
MIC1P
MIC1N
DC
Blocked
MIC1P
MIC1N
Z1
Z1
GND
Electrical Characteristics of MIC1
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Parameters Min Typ Max Unit
DC Characteristics N/A V
AC Characteristics
Z1 70 120 160
KΩ
200 Hz<F<4 kHz
Maximum working
voltage
( MIC1P-MIC1N)
AT+VGT*=2 13.8 mVrms
AT+VGT*=1 77.5
AT+VGT*=0 346
Positive +7.35 V Maximum rating
voltage
(MIC1P or MIC1N)
Negative
-
0.9
• *The input voltage depends of the input micro gain set by AT command. Please refer to the
document
3.14.1.1.2 MIC2 Microphone Inputs
[3] AT Command Interface Guide for Open AT® Firmware v6.5.
By default, the MIC2 inputs are differential ones, but it can be configured in
single ended. They already include the convenient biasing for an electret
microphone. The electret microphone can be directly connected on those
inputs, thus allowing easy connection to a handset.
®
AC coupling is already embedded in the Wireless Microprocessor
.
Equivalent circuits of MIC2
DC equivalent circuit AC equivalent circuit
MIC2P
MIC2N
R
R
GND
MIC2+
MIC2P
MIC2N
Z2
Z2
GND
Electrical Characteristics of MIC2
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Parameters Min Typ Max Unit
Internal biasing
DC Characteristics
AC Characteristics
200 Hz<F<4 kHz
Maximum working
voltage
( MIC2P-MIC2N)
voltage
(MIC2P or MIC2N)
MIC2+ 2 2.1 2.2 V
Output current 0.5 1.5
R2 1650 1900 2150
mA
Ω
Z2 MIC2P
(MIC2N=Open)
1.1 1.3 1.6
Z2 MIC2N
(MIC2P=Open)
Z2 MIC2P
(MIC2N=GND)
0.9 1.1 1.4
KΩ
Z2 MIC2N
(MIC2P=GND)
Impedance
between
MIC2P and
1.3 1.6 2
MIC2N
AT+VGT*=2 13.8
AT+VGT*=1 77.5
mVrms
AT+VGT*=0 346
Positive +7.35** Maximum rating
V
Negative -0.9
• *The input voltage depends of the input micro gain set by AT command. Please refer to the
document
• **Because MIC2P is internally biased, it is necessary to use a coupling capacitor to
connect an audio signal provided by an active generator. Only a passive microphone can
be directly connected to the MIC2P and MIC2N inputs.
[3] AT Command Interface Guide for Open AT® Firmware v6.5
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Ω
March 19, 2007
3.14.2 Speaker Features
The connection is single-ended on SPK1 and is differential or single-ended on
SPK2. Using a differential connection to reject common mode noise and TDMA
noise is strongly recommended. Moreover in single-ended mode, ½ of the
power is lost. When using a single-ended connection, be sure to have a very
good ground plane, a very good filtering as well as shielding in order to avoid
any disturbance on the audio path.
Parameter Typ Unit Connection
Z (SPK1P, SPK1N) 16 or 32
Z (SPK2P, SPK2N) 4
Z (SPK2P, SPK2N) 8
Ω
Ω
Ω
single-ended mode
single-ended mode
Differential mode
3.14.2.1 Speakers Outputs Power
The both speakers maximum power output are not similar, that is due to the
different configuration between the Speaker1 which is only single ended and
the speaker2 which can be differential, so speaker2 can provides more power.
The maximal specifications given below are available with the maximum
power output configuration values set by an AT command. The typical values
are recommanded.
3.14.2.1.1 SPK1 Speaker Outputs
With the SPK1 interface, only single ended speaker connection is allowed
Equivalent circuits of SPK1
WMP100
1Ω
SPK1N
1
SPK1P
Electrical Characteristics of SPK1
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Parameters Min Typ Max Unit
Biasing
- 1.30 V
voltage
Output
swing
voltage
RL=16Ω: AT+VGR=6; singleended
RL=32Ω; AT+VGR=6; singleended
RL Load resistance 14.5 32 -
IOUT Output current;
single-ended; peak
value
POUT
RL=16Ω; AT+VGR*=6
RL=16Ω
RL=32Ω
RL=32Ω; AT+VGR*=6
RPD Output pull-down resistance at
- 1.7 - Vpp
- 1.9 2.75
Vpp
Ω
- 40 85 mA
- 22 - mA
- 25 mW
- 16 27 mW
28 40 52
KΩ
power-down
*The output voltage depends of the output speaker gain set by AT command. Please refer to
the document
[3] AT Command Interface Guide for Open AT® Firmware v6.5.
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Ω
March 19, 2007
3.14.2.1.2 SPK2 Speaker Outputs
The SPK2 interface allows differential and single ended speaker connection
Equivalent circuits of SPK2
WMP100
+
SPK
1Ω
1
SPK2N
SPK2P
Electrical Characteristics of SPK2
Parameters Min Typ Max Unit
Biasing
SPK2P and SPK2N 1.30 V
voltage
Output
swing
voltage
RL=8Ω: AT+VGR=6*; single ended
RL=8Ω: AT+VGR=6*; differential
RL=32Ω: AT+VGR=6*; single
- - 2 Vpp
- - 4 Vpp
- - 2.5 Vpp
ended
RL=32Ω: AT+VGR=6*; differential
- - 5 Vpp
RL Load resistance 6 8 -
IOUT
POUT
Output current; peak value; RL=8Ω
RL=8Ω; AT+VGR=6*;
RPD Output pull-down resistance at
- - 180 mA
- - 250 mW
28 40 52
Ω
KΩ
power-down
VPD Output DC voltage at power-down - - 100 mV
*The output voltage depends of the output speaker gain set by AT command. Please refer to the
document
[3] AT Command Interface Guide for Open AT® Firmware v6.5.
If a singled ended solution is used with the speaker2 output, only one of the
both SPK2 has to be chosen. The result is a maximal output power divided by
2.
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3.14.3 Pin description
Signal Pin
I/O I/O type Description
number
MIC1P
MIC1N
MIC2P
MIC2N
SPK1P
SPK1N
SPK2P
SPK2N
AC10
AB10
AC9
AB9
AC8
AB8
AC7
AB7
I Analog Microphone 1 positive input
I Analog Microphone 1 negative input
I Analog Microphone 2 positive input
I Analog Microphone 2 negative input
O Analog Speaker 1 positive output
O Analog Speaker 1 negative output
O Analog Speaker 2 positive output
O Analog Speaker 2 negative output
3.14.4 Application
3.14.4.1 Microphone
3.14.4.1.1 MIC2 Differential connection example
Figure 17: Example of MIC2 input differential connection with LC filter
*:Z2 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.2.
Note: Audio quality can be very good without L1, L2, C2, C3, C4 depending on
the design. But if there is EMI perturbation, this filter can reduce the
TDMA noise. This filter (L1, L2, C2, C3, C4) is not mandatory. If not
used, the capacitor must be removed and coil replaced by 0 Ohm
resistors as the shown in the following schematic.
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Figure 18: Example of MIC2 input differential connection without LC filter
*:Z2 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.2.
The capacitor C1 is highly recommended to eliminate the TDMA noise. C1
must be close to the microphone.
Recommended components:
• C1 : 12pF to 33pF (depending of the design ,needs to be tuned)
• C2, C3, C4 : 47pF (need to be tuned depending on the design)
• L1, L2 : 100nH (need to be tuned depending on the design)
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3.14.4.1.2 MIC2 single-ended connection example
WMP100
2.1V typ
Z2*= 1100
L1
C1MIC
C2
AC9
AB9
MIC2P
MIC2N
typ
100nF
100nF
Figure 19: Example of MIC2 input single-ended connection with LC filter
*:Z2 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.2.
Audio
ADC
Internal input impedance value becomes 1100 ohms, due to the connection of
MIC2N to ground.
The single ended design is not recommended for improve TDMA rejection
noise. Usually, it’s difficult to eliminate TDMA noise from a single ended
design.
It is recommended to add L1 and C2 footprint to add a LC filter to try to
eliminate the TDMA noise.
When not used, the filter can be removed by replacing L1 by a 0 Ohm resistor
and by disconnecting C2, as the following schematic.
Figure 20: Example of MIC2 input single-ended connection without LC filter
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*:Z2 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.2.
The capacitor C1 is highly recommended to eliminate the TDMA noise. C1
must be close to the microphone.
Recommended components:
C1: 12pF to 33pF (depending of the design ,needs to be tuned )
C2: Must be tuned depending of the design.
L1: Must be tuned depending of the design.
3.14.4.1.3 MIC1 Differential connection example
VCC_2V8
R1
R2
MIC
C5
L1
C1
L2
C2
C3
C4
R3
AC10
AB10
MIC1P
MIC1N
Z1*=120k Ohm
typ
100nF
100nF
Z1*=120k Ohm
typ
WMP100
Audio
ADC
R4
Figure 21: Example of MIC1 input differential connection with LC filter
*:Z1 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.1.
Note : Audio quality can be very good without L1, L2, C2, C3, C4 depending on
the design. But if there is EMI perturbation, this filter can reduce the
TDMA noise. This filter (L1, L2, C2, C3, C4) is not mandatory. When not
used, the capacitor must be removed and coil replaced by 0 Ohm
resistors as shown in the following schematic.
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VCC_2V8
WMP100
R1
R2
MIC1P
AC10
C5
C1MIC
R3
R4
AB10
MIC1N
Z1*=120k Ohm
typ
100nF
100nF
Z1*=120k Ohm
typ
Audio
ADC
Figure 22: Example of MIC1 input differential connection without LC filter
*:Z1 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.1.
The capacitor C1 is highly recommended to eliminate the TDMA noise. C1
must be close to the microphone.
Vbias can be VCC_2V8 of the WMP100 (ball R1) but it is possible to use
another 2V to 3V supply voltage depending of the micro characteristics.
Be careful, if VCC_2V8 is used TDMA noise can degrade quality.
Recommended components:
R1 : 4.7K ohm ( for Vbias equal to 2.8V )
R2, R3 : 820 ohm
R4 : 1K ohm
C1 : 12pF to 33pF (depending of the design ,needs to be tuned )
C2, C3, C4 : 47pF (need to be tuned depending on the design)
C5 : 2.2uF +/- 10%
L1, L2 : 100nH (need to be tuned depending on the design)
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3.14.4.1.4 MIC1 Single-ended connection example
VCC_2V8
WMP100
R1
R2
L1
C5
MIC
C1
C2
AC10
AB10
MIC1P
MIC1N
Z1*=120k Ohm
typ
100nF
100nF
Z1*=120k Ohm
typ
Audio
ADC
Figure 23: Example of MIC1 input single-ended connection with LC filter
*:Z1 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.1.
The single ended design is not recommended for improve TDMA rejection
noise. Usually, it’s difficult to eliminate TDMA noise from a single ended
design.
It is recommended to add L1 and C2 footprint to add a LC EMI filter to try to
eliminate the TDMA noise.
When not used, the filter can be removed by replacing L1 by a 0 Ohm resistor
and by disconnecting C2, as the following schematic.
VCC_2V8
WMP100
R1
R2
MIC1P
AC10
C5
C1MIC
AB10
MIC1N
Z1*=120k Ohm
typ
100nF
100nF
Z1*=120k Ohm
typ
Audio
ADC
Figure 24: Example of MIC1 input single-ended connection without LC filter
*:Z1 is from 200Hz to 4kHz. For more characteristics refer to the chapter
3.14.1.1.1.
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Recommended components:
R1: 4K7 ohm ( for Vbias equal to 2.8V )
R2: 820 ohm
C1: 12pF to 33pF (depending of the design ,needs to be tuned)
C2: Must be tuned depending of the design.
C5 : 2.2uF +/- 10%
L1: Must be tuned depending of the design.
Vbias must be very “clean” to avoid bad performance in case of single-ended
implementation. That is the reason why Vbias could be another 2 V to 3V
power supply instead of VCC_2V8 which is available on the ball R1.
CAUTION: If VCC_2V8 is used TDMA noise can degrade quality.
The capacitor C1 is highly recommended to eliminate the TDMA noise. C1
must be close to the microphone.
3.14.4.2 Speaker
3.14.4.2.1 SPK2 Differential connection
SPK2P
SPK2N
Figure 25: Example of Speaker differential connection
Impedance of the speaker amplifier output in differential mode is:
R ≤ 2Ω +/-10 %.
The connection between the WMP100 pins and the speaker must be designed
to keep the serial impedance lower than 3 Ω in differential mode.
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3.14.4.2.2 SPKx Single-ended connection
Typical implementation
:
Figure 26: Example of Speaker single-ended connection
4.7 μF < C1 < 47 μF (depending on speaker characteristics and output power).
Using a single-ended connection includes losing of the output power (- 6 dB)
compared to a differential connection.
The connection between the WMP100 pins and the speaker must be designed
to keep the serial impedance lower than 1.5 Ω in single ended mode.
If SPKxP channel is used, SPKxN can be left opened.
If SPKxN channel is used, SPKxP can be left opened.
3.14.5 Design recommendation
3.14.5.1 General
When speakers and microphones are exposed to the external environment, it is
recommended to add ESD protection as closed as possible to the speaker or
microphone, connected between the audio lines and a good ground.
The microphone connections may be either differential or single-ended, but
using a differential connection to reject common mode noise and TDMA noise
is strongly recommended.
While using a single-ended connection, ensure to have a good ground plane, a
good filtering as well as shielding, in order to avoid any disturbance on the
audio path.
It is important to select an appropriate microphone, speaker and filtering
components to avoid TDMA noise
3.14.5.2 Recommended microphone characteristics
The impedance of the microphone has to be around 2 kΩ.
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Sensitivity from -40dB to –50 dB.
SNR > 50 dB.
Frequency response compatible with the GSM specifications.
To suppress TDMA noise, it is highly recommended to use microphones with
two internal decoupling capacitors:
-CM1=56pF (0402 package) for the TDMA noise coming from the
demodulation of the GSM 850 and GSM900 frequency signal.
-CM2=15pF (0402 package) for the TDMA noise coming from the
demodulation of the DCS/PCS frequency signal.
The capacitors have to be soldered in parallel of the microphone
CM
Figure 27: Microphone
3.14.5.3 Recommended speaker characteristics
Type of speakers: Electro-magnetic /10mW
Impedance: 8Ω for hands-free (SPK2)
Impedance: 32Ω for heads kit (SPK1)
Sensitivity: 110dB SPL min
Receiver frequency response compatible with the GSM specifications.
3.14.5.4 Recommended filtering components
When designing a GSM application, it is important to select the right audio
filtering components.
The strongest noise, called TDMA, is mainly due to the demodulation of the
GSM850/GSM900/DCS1800 and PCS1900 signal: A burst being produced
every 4.615ms; the frequency of the TDMA signal is equal to 216.7Hz plus
harmonics.
The TDMA noise can be suppress by filtering the RF signal using the right
decoupling components.
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The types of filtering components are:
-RF decoupling inductors
-RF decoupling capacitors
A good “Chip S-Parameter” simulator is proposed by Murata, the following link
help to find it:
http://www.murata.com/designlib/mcsil.html
Using different Murata components, we could see that the value, the package
and the current rating can have different decoupling effects.
The table below shows some examples with different Murata components:
Package 0402
Filtered band GSM900 GSM 850/900 DCS/PCS
Value 100nH 56pF 15pF
Types Inductor Capacitor Capacitor
Position Serial Shunt Shunt
Manufacturer Murata Murata Murata
Rated 150mA 50V 50V
Reference LQG15HSR10J02
or
LQG15HNR10J02
GRM1555C1H560JZ01 GRM1555C1H150JZ01
or
GRM1555C1H150JB01
Package 0603
Filtered band GSM900 GSM 850/900 DCS/PCS
Value 100nH 47pF 10pF
Types Inductor Capacitor Capacitor
Position Serial Shunt Shunt
Manufacturer Murata Murata Murata
Rated 300mA 50V 50V
Reference LQG18HNR10J00 GRM1885C1H470JA01
or
GRM1885C1H470JB01
GRM1885C1H150JA01
or
GQM1885C1H150JB01
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3.14.5.5 Audio track and PCB layout recommendation
To avoid TDMA noise, it is recommended to surround the audio tracks by
ground:
1mm
0.2mm min
Differential Audio line
Ground Ground
WMP100
Ground
Plane
0.15mm max
1mm
Differential
Audio line
always in
parallel
Figure 28: Audio track design
Remark:
Avoid digital tracks crossing under and over the audio tracks.
Application
board
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3.15 PWM / Buzzer Output
This output is controlled by a PWM controller and can be used as buzzer or as
PWM.
3.15.1 Features
The BUZZ-OUT is an open drain one. A buzzer can be directly connected
between this output and VBATT. The maximum current is 100 mA (PEAK).
Electrical Characteristics
Parameter Condition Minimum Maximum Unit
VOL Iol = 100mA 0.4
I
VBATT = VBATTmax
PEAK
Frequency TBD TBD
Duty cycle TBD TBD
3.15.2 Pin description
Signal Pin
I/O I/O type Reset state
number
BUZZ-OUT U4 O Open
drain
See chapter
voltage characteristics and for Reset state definition.
3.4, “Electrical information for digital I/O” on page 32 for Open drain, 2V8 and 1V8
V
100
mA
Hz
%
Description
Z PWM / Buzzer output
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3.15.3 Application
The maximum peak current is 100 mA and the maximum average current is 40
mA. A diode against transient peak voltage must be added as described below.
VBATT
R1
D1
C1
WMP100
BUZZ-OUT
Figure 29: Example of buzzer implementation
Where:
R1 must be chosen in order to limit the current at I
PEAK
max
C1 = 0 to 100 nF (depending on the buzzer type)
D1 = BAS16 (for example)
Recommended characteristics for the buzzer:
electro-magnetic type
Impedance: 7 to 30 Ω
Sensitivity: 90 dB SPL min @ 10 cm
Current: 60 to 90 mA
The BUZZ-OUT output can also be used to drive a LED as shown in the Figure
below:
« BUZZER »
BUZZ-OUT
R1
470 Ω
1
2
D1
VBATT
Figure 30: Example of LED driven by the BUZZ-OUT output
R1 value can be accorded depending of the LED (D1) characteristics.
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3.16 Battery charging interface
The WMP100 charging interface is able to drive the charging of different
batteries technologies by combing hardware and software controls.
3.16.1 Feature
The charging architecture of WMP100 supports 3 batteries technologies:
¾ Ni-Cd (Nickel-Cadmium)
¾ Ni-Mh (Nickel-Metal Hydride)
¾ Li-Ion (Lithium-Ion)
WMP100
CHARGER
DC output
V2/V3
CHG-IN
CHG-GATE
V4
AC1/AC2/
BATTERY
NTC
TEMPERATURE
SENSOR
AD1/AD2
N18
R1
VBATT-BB
VCC_2V8
BAT-TEMP
ALGORITHM
CONTROL
INTERFACE
Figure 31: Charging block diagram
The software algorithm controls a switch (by CHG-GATE signal), which
connects the CHG-IN signal to the VBATT-BB signal. The algorithm controls
the frequency and the connected time of the switching. During the charging
procedure the battery charging level is controlled by the VBATT-BB
measurement. When the battery is full, the algorithm stopped the charging
procedure.
When Li-Ion battery is used, the battery temperature is monitoring through the
BAT-TEMP ADC input.
One more charging mode is provided by the WMP100. It’s called “Precharging” mode, but it’s a special charging mode because it is activated only
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when the WMP100 is OFF. So the control is only performed by the hardware.
The goal of this charging mode is to prevent the battery to be damaged by
preventing the discharged under the minimum battery level.
3.16.1.1 Pre-Charging
When a charger DC power supply is connected to the CHG-IN signal and if the
voltage battery is between 2.8v and 3.2v, a constant current of 50mA is
provided to the battery.
®
When the battery is able to supply the WMP100/Open AT
Software Suite
v1.0, the WMP100 is automatically powered on and the software algorithm is
activated to finish the charge.
Note: When pre-charging is launched, the FLASH-LED output blinks
automatically.
3.16.1.2 Temperature monitoring
The monitoring of the temperature is only available for the Li-Ion battery. The
BAT-TEMP / AUX-ADC2 (N18) ADC input must be used to sample the
temperature analog signal provided by a NTC temperature sensor which is
placed close to the battery cellular. The minimum and maximum temperature
range can be set by software command.
Electrical Characteristics of battery charging interface
Parameter Minimum Typ Maximum Unit
Charging Operating temperature 0 50 °C
BAT-TEMP / AUX-
resolution 10
ADC2
sampling rate 216 S/s
Input Impedance ( R )
Input signal range 0 2 V
Voltage (for I=Imax) 4.6* V CHG-IN
Voltage (for I=0) 6* V
CHG-GATE Switch control by
current
*To be parameterized as per battery manufacturer
bits
1M
Ω
30 40 50 mA
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3.16.2 Pin description
Pin description of battery charging interface
Signal Pin number I/O I/O type Description
CHG-IN V2 / V3 I Analog Current source input
CHG-GATE V4 O Analog Current source to drive
PNP transistor
BAT-TEMP /
AUX-ADC2
3.16.3 Application
DC
Charger
N18 I Analog A/D converter
WMP100
CHG-IN
T1
R1
CHG-GATE
VBATT-BB
VCC_2V8
BAT-TEMP /
AUX-ADC2
OUT
R3
Battery cells
+ NTC
NTC out
NTC
GND
R2
Figure 32: Charging schematic for Li-Ion
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The charging schematic needs a transistor to switch the current from the
Charger DC source power supply to the battery. The control of the transistor is
performed by the WMP100 through the CHG-GATE signal.
It is important that the Charger DC power supply has a limited output current
to not damage the transistor T1.
The R1 and R2 resistors are needed only when the temperature is monitored,
typically for Li-Ion battery. The R1 is necessary to bias the NTC resistor of the
battery. The VCC_2V8 output power voltage of the WMP100 can be used to
power the bridge R1/ R2 / NTC. The R1 and R2 values have to be calculated to
have a maximum of 2volt at the BAT-TEMP / AUX-ADC2 input on the
WMP100.
The R3 resistor must be added to improve the performances of the charge.
Pre-Charging mode doesn’t use the T1 transistor, when Pre-charging is
activated, the current provided by the Charger DC power supply crosses the
WMP100 by the CHG-IN signal to the VBATT-BB to charge the battery. The
current limitation is controlled inside the WMP100.
Recommended components:
o T1 : NSL12AW from On Semiconductor
o R1 = 100K
o R2 = 270K
o R3= 5.6K (package 0402, 1/16W, +-5% is sufficient)
o NTC = 100K @ 25°C NTH4G42B104F01 from MURATA
Note:
o In this example, the transistor T1 has a maximal continuous current of
2A, so the Charger DC power supply must have an output current
limited to 2A.
o The maximum Charger output current, provided to the battery, must be
accorded to the battery electrical characteristics.
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3.17 ON / ~OFF signal
This input is used to switch ON or OFF the Wireless Microprocessor.
A high level signal has to be provided on the pin ON/~OFF to switch ON the
Wireless Microprocessor.. The voltage of this signal has to be maintained at
0.8 x VBATT during a minimum of 4000ms. This signal can be left at high level
until switch off.
To switch OFF the Wireless Microprocessor the pin ON/OFF has to be
released. The Wireless Microprocessor can be switched off through the
Operating System.
) Warning:
All external signals must be inactive when the Wireless Microprocessor is OFF
to avoid any damage when starting and allow Wireless Microprocessor to start
and stop correctly.
3.17.1 Features
Electrical Characteristics of the signal
Parameter I/O type Minimum Maximum Unit
VIL CMOS VBATT x 0.2 V
VIH CMOS VBATT x 0.8 VBATT V
3.17.2 Pin description
Signal Pin number I/O I/O type Description
ON/∼OFF
U5 I CMOS WMP100 Power ON
3.17.3 Application
VBATT
Figure 33: Example of ON/~OFF pin connection
Switch
1
3
2
ON/~OFF
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Y
F
K
»
Y
T
March 19, 2007
3.17.3.1 Power ON
®
Once WMP100/Open AT
set the ON/OFF signal to high to start the WMP100/Open AT
Software Suite v1.0 is powered, the application must
®
Software Suite
v1.0 power ON sequence. The ON/OFF signal must be held high during a
minimum delay of T
power-ON. After this delay, an internal mechanism maintains the
WMP100/Open AT
on/off-hold
®
Software Suite v1.0 in power ON condition.
(Minimum hold delay on the ON/~OFF signal) to
During the power ON sequence, an internal reset is automatically performed by
the WMP100/Open AT
®
Software Suite v1.0 for 40ms (typically). During this
phase, any external reset should be avoided during this phase.
POWER SUPPL
ON/OF
INTERNAL RS
Module OFF
I
STATE OF THE MODULE
I
= overall current consumption (Base Band + RF part)
BB+RF
BB+RF
< 22μA
T
on/off-ho ld
(2000ms min)
T
rst
(40ms typ)
RESET mode
I
=20 to 40mA
BB+RF
SIM and Network dependent
Module ON
I
<120mA
BB+RF
(no loc. update)
AT answers « O
Module READ
Figure 34 : Power-ON sequence (no PIN code activated)
The duration of the firmware power-up sequence depends on:
• the need to perform a recovery sequence if the power has been lost
during a flash memory modification.
Other factors have a minor influence
• the number of parameters stored in EEPROM by the AT commands
received so far
• the ageing of the hardware components, especially the flash memory
• the temperature conditions
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recommended
The
way to de-assert the ON/~OFF signal is to use either an AT
command or WIND indicators: the application has to detect the end of the
power-up initialization and de-assert ON/~OFF afterwards.
• Send an “AT” command and wait for the “OK” answer: once the
initialization is complete the AT interface answers « OK » to “AT” message
• Wait for the “+WIND: 3” message: after initialization, the WMP100/Open
®
Software Suite v1.0, if configured to do so, will return an unsolicited
AT
1
.
“+WIND: 3” message. The generation of this message is enabled or
disabled via an AT command.
Note:
• Please refer to the document
®
Firmware v6.5 for more information on these commands.
AT
[3] AT Command Interface Guide for Open
Proceeding thus – by software detection - will always prevent the application
from de-asserting the ON/~OFF signal too early.
If WIND indicators are disabled or AT commands unavailable or not used, it is
still possible to de-assert ON/~OFF after a delay long enough (T
on/off-hold
) to
ensure that the firmware has already completed its power-up initialization.
The table below gives the minimum values of T
T
on/off-hold
Open AT® Firmware
minimum values
Safe evaluations of the firmware
on/off-hold
T
on/off-hold
:
power-up time
6.65 & above 8 s
The above figure take the worst cases into account: power-loss recovery
operations, slow flash memory operations in high temperature conditions, and
so on. But they are safe because they are large enough to ensure that ON/~OFF
is not de-asserted too early.
Additional notes:
1. Typical power-up initialization time figures for best cases conditions
(no power-loss recovery, fast and new flash memory…) approximate
3.5 seconds in every firmware version. But releasing ON/~OFF after
this delay does not guarantee that the application will actually start-up
if for example the power plug has been pulled off during a flash
memory operation, like a phone book entry update or an AT&W
command…
2. The ON/~OFF signal can be left at a high level until switch OFF. But
this is not recommended as it will prevent the AT+CPOF command
from performing a clean power-off. (see also <<<NOTE IN POWER OFF
CHAPTER>>> for an alternate usage)
1
If the application manages hardware flow control, the AT command can be sent during the
initialisation phase.
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3. When using a battery as power source, it is not recommended to let
this signal high:
If the battery voltage is too low and the ON/~OFF signal at low level,
an internal mechanism switches OFF the WMP100/Open AT
®
Software
Suite v1.0. This automatic process prevents the battery to be over
discharged and optimize its life span.
4. During the power-ON sequence, an internal reset is automatically
performed by the WMP100/Open AT
®
Software Suite v1.0 for 40 ms
(typically). Any external reset should be avoided during this phase.
5. Connecting a charger on the WMP100/Open AT® Software Suite v1.0
as exactly the same effect than setting the ON/~OFF signal. In
particular the WMP100/Open AT
®
Software Suite v1.0 will not
POWER-OFF after the AT+CPOF command, unless the Charger is
disconnected.
3.17.3.2 Power OFF
®
To properly power OFF the WMP100/Open AT
Software Suite v1.0 the
application must reset the ON/OFF signal and then send the AT+CPOF
command to deregister from the network and switch off the WMP100/Open
®
Software Suite v1.0.
AT
®
Once the « OK » response is issued by the WMP100/Open AT
Software Suite
v1.0, the power supply can be switched off.
POWER SUPPLY
ON/OFF
AT COMMAND
STATE OF THE MODULE
I
= overall current consumption (Base Band + RF part)
BB+RF
Module
READY
AT+CPOF
Network dependent
OK response
Module OFF
I
<22µA
BB+RF
Figure 35 : Power-OFF sequence
Note:
• If the ON/~OFF pin is maintained to ON (High Level) then the module
can’t be switched OFF.
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3.18 BOOT signal
A specific control pin BOOT is available to download the WMP100 only if the
standard XMODEM download, controlled with AT command, is not possible.
Specific PC software, provided by WAVECOM, is needed to perform this
download, specifically for the first download of the Flash memory.
3.18.1 Features
The BOOT pin must be connected to the VCC_1V8 for this specific download.
BOOT Operating mode Comment
Leave open Normal use No download
Leave open Download XMODEM AT command for Download
AT+WDWL
1 Download specific Need WAVECOM PC software
For more information, see chapter 3.8.3.
This BOOT pin must be left open for normal use or XMODEM download.
However, in order to make development and maintenance phases easier, it is
highly recommended to set a test point, either a jumper or a switch to
VCC_1V8 (ball AD5) power supply.
3.18.2 Pin description
Signal Pin number I/O I/O type Description
BOOT W18 I 1V8 Download mode selection
3.18.3 Application
VCC_1V8
Switch
1
3
2
BOOT
Figure 36: Example of BOOT pin implementation
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3.19 Reset signals
The WMP100 have two reset signals. The main is ~RESET which is the input
reset of the processor. The second is ~EXT-RESET which is derived from the
main reset.
3.19.1 Features
WMP100
to processor
Processor control
internal reset
~RESET
Watchdog
Power supply
~EXT-RESET
Power
management
Figure 37 : Reset functional block
The ~RESET signal is an input/output signal. It is controlled as well by the user
as well by an internal voltage supervisor. This ~RESET signal drive the reset of
the processor through the watchdog unit.
The ~EXT-RESET is an output signal and is the result of the combination of the
~RESET and the watchdog reset. This signal is used to provide a reset to all
the microprocessor’s system components. Typically, the ~EXT-RESET is used
to reset the NOR Flash memories state machine.
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Figure 38 : Reset waveform events
Three different reset events can occur:
o Power on reset:
The power on reset is automatically controlled by the internal power
management unit. It resets the ~RESET signal as long as the power
supply voltage VCC_1V8 is under 1.60 V typ.
The ~RESET is always reset when the VCC_1V8 is high, after what a
cancellation time is launched (ta).
The ~EXT-RESET is always reset when the ~RESET signal is high,
after what a cancellation time is launched (tb).
o External reset (~RESET):
The external reset is managed by the user or by an external event of
the WMP100. This is the asynchronous reset of the processor. The
external reset must be generated on the ~RESET signal.
The ~Reset signal must be held low during the time (tc) to reset the
microprocessor. .
o Internal reset (~EXT-RESET):
The internal reset is launched by the watchdog unit, controlled by the
processor. This reset affects only the ~EXT-RESET signal (td).
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A
March 19, 2007
Electrical Characteristics of the signals
~RESET
Parameter Minimum
Input Impedance ( R )*
Input Impedance ( C )
~Reset time (tc)
Cancellation time (ta)
100K
10n
200
20 40 100
Typ Maximum Unit
at power up only
0.57
0 0.57
1.33
300
34 35
122
~EXT-
RESET
VH**
VIL
V
IH
Watchdog reset (td)
Cancellation time (tb)
Delay after a ~RESET
active (te)
17
200
20
~CS0
First access time (tf)
Total boot
time (tg)
BOOT = 1
BOOT =
Leave open
***
* internal pull up
**V
Hysterisis Voltage
H :
*** Normal configuration. Refer to the chapter 3.18 for further details on the BOOT signal.
Ω
F
μs
ms
V
V
V
μs
ms
μs
μs
ms
Sequence after an external reset event (~RESET)::
To activate the « emergency » reset sequence, the ~RESET signal has to be set
to low for 200μs minimum for example by a push button . As soon as the reset
is complete, the interface answers « OK » to the application.
~RESET
~EXT-RESET
STATE OF
THE
MODULE
Module
READY
RESET mode
I
tc = Min:200μs
=20 to 40mA
BB+RF
tb = Typ:34ms
Module ON
I
<120mA without
BB+RF
loc update
SIM and network
dependent
T answers “OK”
Module
READY
Figure 39 : Reset sequence waveform
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At power up, the ~RESET time (ta), is performed after switching ON the
Wireless Microprocessor
®
. It is generated by the internal WMP100 voltage
supervisor.
The ~RESET time is provided by the internal RC component. To keep the same
time, it’s not recommended to plug another R or C component into the ~RESET
signal. Only a switch or an open drain gate is recommended.
®
The (tb) time is the cancellation time needed for the WMP100/Open AT
Software Suite v1.0 initialization. (tb) time is automatically done by the
WMP100/Open AT
®
Software Suite v1.0 itself, after a hardware reset.
The firsts access on
~CS0 after an internal reset event (~EXT-RESET):
After an internal reset (like a Watchdog reset) the delay of the active ~CS0
signal (chip select 0 for access to the external FLASH) depend of the BOOT
signal state. Refer to the chapter 3.18 for further details on the BOOT signal.
Figure 40 : BOOT sequence waveform
3.19.2 Pin description
Signal Pin
I/O I/O type Description
number
~RESET V6 I/O Open
1V8 WMP100 Reset
Drain*
~EXT-RESET AB14 O Push Drain 1V8 External Reset
* internal pull up. See the characteristics in the table §3.19.1.
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3.19.3 Application
If used (emergency reset), it has to be driven by an open collector or an open
drain output (due to the internal pull-up resistor embedded into the Wireless
Microprocessor
®
) as shown in the diagram hereunder.
Push button
1
3
GND
2
~RESET
Figure 41: Example of ~RESET pin connection with push button
configuration
~RESET
Reset
command
GND
T1
Rohm DTC144EE
Figure 42: Example of ~RESET pin connection with transistor configuration
Open collector or open drain transistor can be used. If an open collector is
chosen, T1 can be a Rohm DTC144EE.
Reset command ~RESET Operating mode
1 0 Reset activated
0 1 Reset inactive
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3.20 External Interrupt
The WMP100 provides up to 9 external interrupts inputs in two voltages
ranges (in 1.8V and 2.8V).
3.20.1 Features
Those interrupt inputs can be activated on:
• high to low edge
• low to high edge
• low to high and high to low edge
• low level
• high level
When used, interruptions input must not be left opened.
If not used, they have to be configured as GPIO.
Electrical characteristics of the signals
Parameter Minimum Maximum Unit
VIL 0.54
Interrupt pin at 1V8
VIH 1.33
VIL 0.84
Interrupt pin at 2V8
1.96 V
V
IH
3.20.2 Pin description
Signal Pin
number
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
V16
Y19
Y17
V18
T18
M14
T16
V13
I/O I/O type Reset
state
I 1V8 Z External Interrupt 0 GPIO3 / A26
I 2V8 Z External Interrupt 1 GPIO25
I 1V8 Z External Interrupt 2 GPIO45
I 2V8 Z External Interrupt 3 GPIO46
I 2V8 Z External Interrupt 4 GPIO35 /
I 2V8 Z External Interrupt 5 GPIO31 /
I 1V8 Z External Interrupt 6 GPIO14 /
I 1V8 Z External Interrupt 7 GPIO17 /
V
V
V
Description Multiplexed
with
~SPI2-CS
~SPI1-CS
CT103-TXD2
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Signal Pin
number
I/O I/O type Reset
state
Description Multiplexed
with
~CT105-
RTS2
INT8
Y3
I 1V8 Z External Interrupt 8 GPIO18 /
SIMPRES
See chapter 3.4, “Electrical information for digital I/O” on page 32 for Open drain, 2V8 and 1V8
voltage characteristics and for Reset state definition.
3.20.3 Application
INTx are high impedance input type, so it is important to set the interrupt input
signal with pull up or pull down resistor if they are driven by an open drain,
open collector or by a switch. If they are driven by a push-pull transistor, no
pull up or pull down resistor is necessary.
VCC_1V8
R1
INTx
Intx
command
T1
Rohm DTC144EE
GND
Figure 43: Example of INTx driving example with open collector
VCC_2V8
R1
INTx
Intx
command
GND
T1
Rohm DTC144EE
Figure 44: Example of INTx driving example with open collector
Where:
R1 value can be 47K Ohm.
T1 can be a Rohm DTC144EE open collector transistor.
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3.21 VCC_2V8 and VCC_1V8 output
VCC_2V8 output can be used only for pull-up resistor and can be used as a
reference supply.
VCC_1V8 is used to supply the Flash and Ram memories; it can be used as
well for pull-up resistors.
Those voltages supplies are available when the WMP100 is on.
3.21.1 Features
Electrical characteristics of the signals
Parameter Minimum Typ Maximum Unit
Output voltage
1.76 1.8 1.94 V
VCC_1V8
Output Current
Output voltage
80 (TBC) mA
2.74 2.8 2.86 V
VCC_2V8
Output Current
15 mA
3.21.2 Pin description
Signal Pin number I/O I/O type Description
VCC_1V8
VCC_2V8
AD5
R1
O Supply Digital supply
O Supply Digital supply
3.21.3 Application
Those digital power supplies are mainly used to:
o VCC_1V8 is used to supply Flash and Ram memory devices
o pull-up signals such as I/O
o supply the digital transistors driving LEDs
o supply the SIMPRES signal
o act as a voltage reference for ADC interface AUX-ADC (only for VCC_2V8)
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3.22 Real Time Clock
The Real Time Clock of the WMP100 need to be feeds by a 32768Hz
frequency. An internal oscillator is available to drive a crystal at the frequency
of 32768Hz.
3.22.1 Features
Those two pins are used to connect a crystal which is mandatory to setup and
to run the WMP100.
It is possible to access to the 32768 Hz signal (buffered output) on the GPIO44
(ball AB13). Refer to the chapter 3.11.
Electrical characteristics of the signal
Parameter Minimu
oscillator input
cycle time
XIN_32K
oscillator input
high time
oscillator input
Start time 32kHz
oscillator start
GPIO44 Delay time
with respect to
3.22.2 Pin description
32kHz
32kHz
32kHz
low time
time
XIN_32K
Typ Maximum Unit
m
- 1/3276
- μs
8
5 - - μs
5 - - μs
- - 2 s
- - 20 ns
Signal Pin number I/O I/O type Description
XIN_32K AC24 I analog Oscillator input
XOUT_32K AB24 O analog Oscillator output
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3.22.3 Application
XOUT_32K
XIN_32K
R1
X1
C1 C2
The R1 resistor is mandatory if the crystal maximum power dissipation is
under 1μW.
The value of the components R1, C1 and C2 are tuned with the crystal MS2VT1S.
It is important to place the crystal close to the WMP100, to reduce as a
minimum the length of the nets.
Recommended components:
C1, C2 : 22pF
R1 : 100Kohm
X1: 32768Hz crystal. MS2V-T1S (+/- 20ppm @25°C) Microcrystal
3.22.4 Design recommendation
Exemple with the
Layer 1:
crystal. MS2V-T1S
-Good ground under the crystal.
-Good ground connection of the crystal legs and the load capacitance of the
crystal.
-Crystal as close as possible to the WMP100 in order to decreases as
maximum as possible the parasite capacitance brought by the design of the
layout
0.2mm
width
Figure 45 : PCB lay out for the crystal MS2V-T1S
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Layer 2:
A complete layer of ground
3.23 BAT-RTC (Backup Battery)
The WMP100 provides an input / output to connect a Real Time Clock power
supply.
3.23.1 Features
This pin is used as a back-up power supply for the internal Real Time Clock.
The RTC is supported by the WMP100 when VBATT is available but a back-up
power supply is needed to save date and hour when the VBATT is switched
off.
WMP100
from VBATT
to RTC
2.5V
regulator
1.8V
regulator
BAT-RTC
Figure 46 : Real Time Clock power supply
If the RTC is not used this pin can be left open.
If the VBATT is available, the back-up battery can be charged by the internal
2.5V power supply regulator.
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