Sierra Wireless Q2686 Installation guide

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Product Technical Specification

Q2686 Wireless CPU

Reference: WM_PRJ_Q2686_PTS_001

Revision: 010

Date: June 30, 2009

Q2686 Wireless CPU®

Q2686 Wireless CPU

Product Technical Specification

Reference: WM_PRJ_Q2686_PTS_001

Revision:

Date:

010 June 30, 2009

Supports Open AT

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.

WM_PRJ_Q2686_PTS_001-010 June 30, 2009

embedded ANSI C applications

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Q2686 Wireless CPU®

Document History

Level Date List of revisions

001 01/17/2005 Creation (Preliminary version)

002 06/01/2005 Pin-out modification (see chapter 3.1)

003 15/09/2005

Update Functional architecture Pin-out modification (see chapter 4.1) Add RESET state of all IOs of all interfaces Update power supply range (see chapter 3.2) Update electrical information for digital IO (see chapter 3.2) Update SPI bus configuration (see chapter 3.4) Remove 3 GPIO (see chapter 3.9) Change MIC1 biasing voltage configuration (see chapter 3.11) Change SPK1 definition to only single-ended (see chapter 3.11) Update ON/ÕFF operating sequence (see chapter 3.14) Update BOOT definition (see chapter 3.15) Update ~RESET operating sequence and electrical characteristics (see chapter 3.14) Update Interrupt activation (see chapter 3.17) Update RTC electrical characteristics (see chapter 3.19) Update PCM description and add waveform (see chapter 3.21)

004 November 22,

2005

005 February 2006 Update “PCM interface” waveform (see chapter 3.21)

Update Q2686 version “Overview” section Update “Cautions”, “Trademarks” and “Copyright” Update “Electrical information for digital I/O” (see chapter 3.3) Update SPI max frequency (see chapter 3.4) Update available GPIO (see chapter 3.9) Add “OFF state“ voltage caution (see chapter 3.2) Update “Battery charging interface” (see chapter 3.13) Update “Analog audio interface” (see chapter 3.11) Update ”Environmental Specifications” (see chapter 4.2) Update “General Purpose Connector pin-out description” (see chapter 4.1)

Update “Electrical information for digital IO” absolute maximum rating (see chapter 3.3) Update “General purpose connector” (see chapter 3.1) Update “SPI bus” speed (see chapter 3.4.1) Update “I²C bus” (see chapter 3.4.2) Update “Main serial link UART 1” maximum speed (see chapter 3.6) Update “Auxiliary serial link UART 2” maximum speed (see chapter 3.7) Update “SIM” General description (see chapter 3.8.1) Update “USB 2.0 interface” features (see chapter 3.22) Update “Operating system upgrade” (see chapter 6.3) Update “General purpose input/output” signals description (see chapter 3.9) Update “General purpose connector pin-out description” signal description (see chapter 4.1) Update “Battery charging interface” (see chapter 3.13) Update “Analog to μDigital Converter” (see chapter 3.10) Update “FLASH-LED signal” (see chapter 3.20)

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Q2686 Wireless CPU®

Level Date List of revisions

Update ‘Analog Audio interface” (see chapter 3.11)

006 March 2006

007 March 2007

008 June 2008

009 May 14, 2009

010 June 30, 2009

Update “Power consumption” (see chapter 3.3.2) Update “ON/~OFF signal” (see chapter 3.14) Update “BAT-RTC” (see chapter 3.19) Update “Electrical information for digital IO” absolute maximum rating (see chapter 3.3) Update “Buzzer output”, remove PWM features ( see chapter 3.12 ) Update “EMC recommendation” add ESD recommendations (see chapter 6.1.1 ) Update “SPI bus” add waveforms ( see chapter 3.4.1 ) Update “I²C bus” add waveforms ( see chapter 3.4.2 ) Update “Analog to Digital Converter“ sampling rate (see chapter 3.10)

Modification of the ON/ ~OFF paragraph Add ATEX 94/9/CE directive information in section Update reference documents Update section Other minor corrections Software update : Open AT Consumption modifications: ( see chapter 3.22) Modification in analog audio interface ( see chapter 3.11 ). Update of Temperature Class B (-30 °C + 85°C ) ( see chapter 4.3 ) New chapter for correspondences of labelling between Q2686 with Open AT ADC modifications: ( see chapter 3.10) SPI modification: ( see chapter 3.4 ) BUZZER modifications : ( see chapter 3.12 ) LED0 : new designation : ( see chapter 3.20 and 4.2) GPIO44:new designation: ( see chapter 4.2 ) Reset signal: modification on input impedance (see chapter 3.16) Current start up definition ( see chapter 3.2.2 ) Charger interface updated ( see chapter 3.13 ) RTC interface : Maximum input voltage updated (see chapter

3.19.1)

Update Storage temperature in section Updates to contents of section Updated to antenna gain information in section 7.1.

3.6 “Main serial link (UART1)”

Software Suite v2

Software Suite v2 ( see chapter 4.2 )

7.1.

4.3.

4.4

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Q2686 Wireless CPU®

Overview

This document defines and specifies the Q2686 Wireless CPU®, available in a GSM/GPRS Class 10 quad-band version:

• Q2686H: EGSM/GPRS 900/1800/850/1900 MHz version with 32 Mb of Bursted Flash memory and 8 Mb of SRAM (32/8).

• Q2686G: EGSM/GPRS 900/1800/850/1900 MHz version with 64 Mb of Bursted Flash memory and 16 Mb of SRAM (64/16).

The Q2686 Wireless CPU

). Open AT® is the world’s most comprehensive cellular development

AT environment, which allows embedded standard ANSI C applications to be natively executed directly on the Wireless CPU

This Product Technical Specification document covers the Wireless CPU and does not include the programmable capabilities provided via the use of Open AT

Software Suites.

supports a powerful open software platform (Open

alone

For detailed software programming guides, refer to the documents shown in the

WM_PRJ_Q2686_PTS_001” section.

“

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Q2686 Wireless CPU®

Cautions

This platform contains a modular transmitter. This device is used for wireless applications. Note that all electronics parts and elements are ESD sensitive.

Information provided herein by WAVECOM is accurate and reliable. However, no responsibility is assumed for its use and any of such WAVECOM information is herein provided “as is” without any warranty of any kind, whether express or implied.

Trademarks

WIRELESS” Open AT are filed or registered trademarks of Wavecom S.A. in France and/or in other countries. All other company and/or product names mentioned may be filed or registered trademarks of their respective owners.

, WAVECOM®, WISMO®, Wireless Microprocessor®, Wireless CPU®,

and certain other trademarks and logos appearing on this document,

, ,

, inSIM®, “YOU MAKE IT, WE MAKE IT

This manual is copyrighted by WAVECOM with all rights reserved. No part of this manual may be reproduced, modified or disclosed to third parties in any form without the prior written permission of WAVECOM.

No Warranty/No Liability

This document is provided “as is”. Wavecom makes no warranties of any kind, either expressed or implied, including any implied warranties of merchantability, fitness for a particular purpose, or noninfringement. The recipient of the documentation shall endorse all risks arising from its use. In no event shall Wavecom be liable for any incidental, direct, indirect, consequential, or punitive damages arising from the use or inadequacy of the documentation, even if Wavecom has been advised of the possibility of such damages and to the extent permitted by law.

This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.

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Web Site Support

Q2686 Wireless CPU®

General information about Wavecom and its

www.wavecom.com

range of products:

Specific support about the Q2686 Wireless

CPU

www.wavecom.com/Q2686

Carrier/Operator approvals: www.wavecom.com/approvals

Open AT® Introduction: www.wavecom.com/OpenAT

Developer support for software and hardware: www.wavecom.com/forum

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Q2686 Wireless CPU®

Table of Contents

1 References................................................................................ 13

1.1 Reference Documents........................................................................... 13

1.1.1 Open AT® Software Documentation............................................... 13

1.1.2 AT Software Documentation......................................................... 13

1.1.3 Hardware Documents ................................................................... 13

1.1.4 Other Wavecom Documents ......................................................... 13

1.1.5 General Reference Documents ...................................................... 13

1.2 List of Abbreviations ............................................................................. 14

2 General Description .................................................................. 17

2.1 General Information .............................................................................. 17

2.1.1 Overall Dimensions ....................................................................... 17

2.1.2 Environment and Mechanics......................................................... 17

2.1.3 GSM/GPRS Features ..................................................................... 17

2.1.4 Interfaces ...................................................................................... 17

2.1.5 Operating System ......................................................................... 18

2.1.6 Connection Interfaces ................................................................... 18

2.2 Functional Architecture......................................................................... 19

2.2.1 RF Functionalities ......................................................................... 20

2.2.2 Baseband Functionalities .............................................................. 20

2.3 Operating System ................................................................................. 20

3 Interfaces ................................................................................. 21

3.1 General Purpose Connector (GPC)......................................................... 21

3.2 Power Supply ....................................................................................... 22

3.2.1 Power Supply Description............................................................. 22

3.2.2 Power Consumption ..................................................................... 23

3.2.2.1 Start-up Current...................................................................... 24

3.2.2.2 Power Consumption without Open AT® Processing ................ 25

3.2.2.3 Power Consumption with Open AT® Software ........................ 26

3.2.2.4 Consumption Waveform Samples ........................................... 28

3.2.2.5 Power Supply Pin-out ............................................................. 30

3.3 Electrical Information for Digital I/O....................................................... 31

3.4 Serial interface...................................................................................... 33

3.4.1 SPI Bus ......................................................................................... 33

3.4.1.1 Characteristics ........................................................................ 33

3.4.1.2 SPI configuration..................................................................... 33

3.4.1.3 SPI waveforms........................................................................ 34

3.4.1.4 SPI1 Bus: Pins description ...................................................... 35

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Q2686 Wireless CPU®

3.4.1.5 SPI2 Bus: Pins description ...................................................... 35

3.4.2 I2C Bus ......................................................................................... 36

3.4.2.1 I²C Waveforms ........................................................................ 36

3.4.2.2 I²C Bus Pin-out ....................................................................... 37

3.5 Keyboard Interface................................................................................ 37

3.6 Main Serial Link (UART1)...................................................................... 38

3.7 Auxiliary Serial Link (UART2) ................................................................ 40

3.8 SIM Interface ........................................................................................ 41

3.8.1 General Description....................................................................... 41

3.9 General Purpose Input/Output .............................................................. 43

3.10 Analog to Digital Converter................................................................... 45

3.11 Analog Audio Interface ......................................................................... 46

3.11.1 Microphone Features .................................................................... 46

3.11.1.1 MIC1 Microphone Inputs ........................................................ 46

3.11.1.2 MIC2 Microphone Inputs ........................................................ 47

3.11.2 Speaker Features .......................................................................... 49

3.11.2.1 Speakers Outputs Power......................................................... 49

3.11.3 Pin description .............................................................................. 51

3.12 Buzzer Output ...................................................................................... 52

3.13 Battery Charging Interface .................................................................... 53

3.13.1 Ni-Cd / Ni-Mh Charging Algorithm ................................................ 53

3.13.2 Li-Ion Charging Algorithm............................................................. 55

3.13.3 Pre-charging ................................................................................. 56

3.13.4 Temperature Monitoring ............................................................... 56

3.14 ON / ~OFF signal .................................................................................. 58

3.14.1 Operating Sequences.................................................................... 58

3.14.1.1 Power-ON ............................................................................... 58

3.14.1.2 Power-OFF.............................................................................. 61

3.15 BOOT Signal......................................................................................... 62

3.16 Reset Signal (~RESET).......................................................................... 63

3.17 External Interrupt.................................................................................. 65

3.18 VCC_2V8 and VCC_1V8 Output............................................................. 66

3.19 BAT-RTC (Backup Battery).................................................................... 67

3.19.1 Interface Description ..................................................................... 67

3.20 LED0 Signal.......................................................................................... 69

3.21 Digital Audio Interface (PCM)................................................................ 72

3.21.1 Description ................................................................................... 72

3.22 USB 2.0 Interface.................................................................................. 75

3.23 RF Interface .......................................................................................... 76

3.23.1 RF Connections............................................................................. 76

3.23.2 RF Performance ............................................................................ 76

3.23.3 Antenna Specifications ................................................................. 77

4 Technical Specifications ........................................................... 78

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Q2686 Wireless CPU®

4.1 General Purpose Connector Pin-out Description.................................... 78

4.2 Labeling Correspondence between Q2686 and Open AT® Software Suite v2

4.3 Environmental Specifications ................................................................ 82

4.4 Conformance with ATEX 94/9/CE directive............................................ 83

4.5 Mechanical Specifications..................................................................... 83

4.5.1 Physical Characteristics ................................................................ 83

4.5.2 Mechanical Drawings ................................................................... 83

5 Connector and Peripheral Device References............................ 85

5.1 General Purpose Connector .................................................................. 85

5.2 SIM Card Reader .................................................................................. 85

5.3 Microphone .......................................................................................... 85

5.4 Speaker ................................................................................................ 86

5.5 Antenna Cable ...................................................................................... 86

5.6 RF Board-to-board Connector ............................................................... 86

5.7 GSM Antenna....................................................................................... 86

6 Design Guidelines ..................................................................... 87

6.1 HARDWARE and RF.............................................................................. 87

6.1.1 EMC Recommendations................................................................ 87

6.1.2 Power Supply ............................................................................... 88

6.1.3 Layout Requirement...................................................................... 89

6.1.4 Antenna ........................................................................................ 90

6.2 Mechanical Integration ......................................................................... 90

6.3 Operating System Upgrade................................................................... 90

7 Appendix................................................................................... 91

7.1 Standards and Recommendations ........................................................ 91

7.2 Safety Recommendations (for information only).................................... 95

7.2.1 RF Safety ...................................................................................... 95

7.2.1.1 General ................................................................................... 95

7.2.1.2 Exposure to RF Energy ............................................................ 95

7.2.1.3 Efficient Terminal Operation .................................................... 95

7.2.1.4 Antenna Care and Replacement .............................................. 96

7.2.2 General Safety............................................................................... 96

7.2.2.1 Driving .................................................................................... 96

7.2.2.2 Electronic Devices ................................................................... 96

7.2.2.3 Vehicle Electronic Equipment .................................................. 96

7.2.2.4 Medical Electronic Equipment ................................................. 96

7.2.2.5 Aircraft.................................................................................... 97

7.2.2.6 Children .................................................................................. 97

7.2.2.7 Blasting Areas......................................................................... 97

7.2.2.8 Potentially Explosive Atmospheres.......................................... 97

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Q2686 Wireless CPU®

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Q2686 Wireless CPU®

ADC

Table of Figures

2 6 8 6

B O A R D

T O

B O A R D

N T E R

F A C E

C O N N E C T O R

CHARGER

AUDIO FILTER

USB detection

SUPPLY INTERFACE

POWER

AUDIO

KEYPAD

PCM

UART2

UART1

USB

SIM 1.8V/3V

RTC

MEMORY

FLASH / SRAM

INTERFACE

EXT_IT

SPI1

SPI2

I2C

GPIO

DAC

EBI

TRANSCEIVER

FRONT END

ANTENNA

COAX

UFL

IMP

Figure 1: Functional architecture................................................................. 19

Figure 2: Power supply during burst emission.................................................. 22

Figure 3: Start-up current waveform................................................................. 24

Figure 4: SPI Timing diagrams,Mode 0,Master,4 wires .................................... 34

Figure 5: SPI Timing diagrams with LOAD signal, Mode 0, Master, 4 wires..... 35

Figure 6: I²C Timing diagrams, Master .............................................................36

Figure 7: Ni-Cd / Ni-Mh charging waveform .....................................................53

Figure 8: Li-Ion full charging waveform ............................................................55

Figure 9: Power-ON sequence (no PIN code activated) ..................................... 59

Figure 10: Power-OFF sequence....................................................................... 61

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WM_PRJ_Q2686_PTS_001-010 June 30, 2009

Q2686 Wireless CPU®

Figure 11: Reset sequence waveform ............................................................... 63

Figure 12: Real Time Clock power supply ......................................................... 67

Figure 13: LED0 state during RESET and Initialization time............................... 71

Figure 14: PCM frame waveform ...................................................................... 73

Figure 15: PCM sampling waveform................................................................. 73

Figure 16: Environmental classes .....................................................................82

Figure 17: Mechanical drawing ........................................................................ 84

Figure 18: Layout requirement.......................................................................... 89

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Q2686 Wireless CPU®

1 References

1.1 Reference Documents

For more details, several reference documents may be consulted. The Wavecom reference documents are provided in the Wavecom document package, contrary to the general reference documents which are not authored by Wavecom.

Please check the web site for the latest documentation available. Note that the last software version available for Q2686 is Open AT

1.1.1 Open AT

[1] Getting started with Open AT [2] Tutorial for Open AT [3] Tools Manual for Open AT [4] Basic Development Guide for Open AT [5] ADL User Guide for Open AT [6] Open AT

Software Documentation

Release Note

Software Suite v2.0.

1.1.2 AT Software Documentation

[7] AT commands interface Guide V7.1 [8] AT Commands Interface Guide (Bluetooth) [9] Open AT

firmware Release Note

1.1.3 Hardware Documents

[10] Q2686 Wireless CPU

(Ref. WM_PRJ_Q2686_PTS_003)

[11] Q2686 Wireless CPU

Customer Design Guidelines

Process Customer Guidelines

(Ref.WM_PRJ_Q2686_PTS_004)

1.1.4 Other Wavecom Documents

[12] Automotive Environmental Control Plan for Q2686 Wireless CPU

(Ref. WM_T&D_Q2686_DCP_001)

1.1.5 General Reference Documents

[13] “I²C Bus Specification”, Version 2.0, Philips Semiconductor 1998 [14] ISO 7816-3 Standard

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1.2 List of Abbreviations

Abbreviation Definition

AC Alternating Current ADC Analog to Digital Converter A/D Analog to Digital conversion AF Audio-Frequency AT ATtention (prefix for modem commands) AUX AUXiliary CAN Controller Area Network CB Cell Broadcast CEP Circular Error Probable CLK CLocK CMOS Complementary Metal Oxide Semiconductor

Q2686 Wireless CPU®

CS Coding Scheme CTS Clear To Send DAC Digital to Analog Converter dB Decibel DC Direct Current DCD Data Carrier Detect DCE Data Communication Equipment DCS Digital Cellular System DR Dynamic R

ange DSR Data Set Ready DTE Data Terminal Equipment DTR Data Terminal Ready EFR Enhanced Full Rate E-GSM Extended GSM EMC ElectroMagnetic Compatibility EMI ElectroMagnetic Interference EMS Enhanced Message Service EN ENable ESD ElectroStatic Discharges FIFO First In First Out FR Full Rate

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Abbreviation

Definition

FTA Full Type Approval GND GrouND GPI General Purpose Input GPC General Purpose Connector GPIO General Purpose Input Output GPO General Purpose Output GPRS General Packet Radio Service GPS Global Positioning System GSM Global System for Mobile communications HR Half Rate I/O Input / Output LED Light Emitting Diode LNA Low Noise Amplifier MAX MAXimum

Q2686 Wireless CPU®

MIC MICrophone MIN MINimum MMS Multimedia Message Service MO Mobile Originated MT Mobile Terminated na Not Applicable NF Noise Factor NMEA National Marine Electronics Association NOM NOMinal NTC Negative Temperature Coefficient PA Power Amplifier Pa Pascal (for speaker sound pressure measurements) PBCCH Packet Broadcast Control CHannel PC Personal Computer PCB Printed Circuit Board PDA Personal Digital Assistant PFM Power Frequency Modulation PSM Phase Shift Modulation PWM Pulse Width Modulation RAM Random Access Memory

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Q2686 Wireless CPU®

Abbreviation

Definition

RF Radio Frequency RFI Radio Frequency Interference RHCP Right Hand Circular Polarization RI Ring Indicator RST ReSeT RTC Real Time Clock RTCM Radio Technical Commission for Maritime services RTS Request To Send RX Receive SCL Serial CLock SDA Serial DAta SIM Subscriber Identification Module SMS Short Message Service SPI Serial Peripheral Interface SPL Sound Pressure Level SPK SPeaKer SRAM Static RAM TBC To Be Confirmed TDMA Time Division Multiple Access TP Test Point TVS Transient Voltage Suppressor TX Transmit TYP TYPical UART Universal Asynchronous Receiver-Transmitter USB Universal Serial Bus USSD Unstructured Supplementary Services Data VSWR Voltage Standing Wave Ratio

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2 General Description

2.1 General Information

Q2686 Wireless CPU®

The Q2686 series is a self-contained E-GSM/GPRS 900/1800 and 850/1900 quad-band Wireless CPU

with the following characteristics:

2.1.1 Overall Dimensions

• Length: 40 mm

• Width: 32.2 mm

• Thickness: 4 mm

2.1.2 Environment and Mechanics

• Green policy: RoHS compliant

• Complete shielding

The Q2686 Wireless CPU

is compliant with RoHS (Restriction of Hazardous Substances in Electrical and Electronic Equipment) Directive 2002/95/EC which sets limits for the use of certain restricted hazardous substances. This directive states that “from 1st July 2006, new electrical and electronic equipment put on the market does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenyl ethers (PBDE)”.

The Wireless CPU

s which are compliant with this

directive are identified by the RoHs logo on their label.

2.1.3 GSM/GPRS Features

• 2-Watt EGSM 900/GSM 850 radio section running under 3.6 volts

• 1-Watt GSM1800/1900 radio section running under 3.6 volts

• Hardware GPRS class 10 capable

2.1.4 Interfaces

• Digital section running under 2.8 volts and 1.8V.

• 3V/1V8 SIM interface

• Complete interfacing:

o Power supply o Serial link o Analog audio o PCM digital audio o SIM card o Keyboard o USB 2.0 slave

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o Serial LCD (not available with AT commands)

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2.1.5 Operating System

• Real Time Clock (RTC) with calendar

• Battery charger

• Echo cancellation + noise reduction (quadri codec)

• Full GSM or GSM/GPRS Operating System stack

2.1.6 Connection Interfaces

The Q2686 Wireless CPU

has four external connections:

• Three for RF circuit:

o UFL connector o Soldered connection o IMP connection

• One for baseband signals:

o 100 pin I/O connector.

Q2686 Wireless CPU®

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Q2686 Wireless CPU®

ADC

2.2 Functional Architecture

The global architecture of the Q2686 Wireless CPU® is displayed below:

2 6 8 6

B O A R D

T O

B O A R D

I N T E R

F A C E

C O N N E C T O R

CHARGER

AUDIO FILTER

USB detection

SUPPLY INTERFACE

POWER

AUDIO

KEYPAD

PCM

UART2

UART1

USB

SIM 1.8V/3V

RTC

MEMORY

FLASH / SRAM

INTERFACE

EXT_IT

SPI1

SPI2

I2C

GPIO

DAC

EBI

TRANSCEIVER

FRONT END

ANTENNA

COAX

UFL

IMP

Figure 1: Functional architecture

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Q2686 Wireless CPU®

2.2.1 RF Functionalities

The Radio Frequency (RF) range complies with the Phase II EGSM 900/DCS 1800 and GSM 850/PCS 1900 recommendations. The frequencies are:

Transmit band (Tx) Receive band (Rx)

GSM 850 824 to 849 MHz 869 to 894 MHz

E-GSM 900 880 to 915 MHz 925 to 960 MHz

DCS 1800 1710 to 1785 MHz 1805 to 1880 MHz

PCS 1900 1850 to 1910 MHz 1930 to 1990 MHz

The Radio Frequency (RF) part is based on a specific quad-band chip with a:

• Digital low-IF receiver

• Quad-band LNA (Low Noise Amplifier)

• Offset PLL (Phase Locked Loop) transmitter

• Frequency synthesizer

• Digitally controlled crystal oscillator (DCXO)

• Tx/Rx FEM ( Front-End Wireless CPU

) for quad-band GSM/GPRS

2.2.2 Baseband Functionalities

The digital part of the Q2686 Wireless CPU

is composed of a PCF5212 PHILIPS chip. This chipset uses a 0.18 μm CMOS mixed technology, which allows massive integration as well as low current consumption.

2.3 Operating System

The Q2686 Wireless CPU® is designed to integrate various types of specific process applications such as vertical applications (telemetry, multimedia, automotive).

The Operating System offers a set of AT commands to control the Wireless

. With this standard Operating System, some interfaces of the Wireless

CPU

CPU® are not available because they are dependent on the peripheral devices

connected to the Wireless CPU The Operating System is Open AT

compliant.

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3 Interfaces

3.1 General Purpose Connector (GPC)

Q2686 Wireless CPU®

A 100-pin connector is provided to interface the Q2686 Wireless CPU® with a board containing either a serial LCD Wireless CPU

, a keyboard, a SIM

connector, or a battery connection. The available interfaces on the GPC are described below:

Chapter Name

3.4 Serial Interface X

3.5 Keyboard Interface X X

3.6 Main Serial Link X X

3.7 Auxiliary Serial Link X X

3.8 SIM Interface X X

3.9 General Purpose IO X X

3.10 Analog to Digital Converter

3.11 Analog Audio

Interface

3.12 Buzzer Output X X

3.13 Battery Charging

Interface

3.17 External Interruption X X

3.18 VCC_2V8 and

VCC_1V8

3.19 BAT-RTC (Backup

Battery)

3.20 LED0 signal X X

3.21 Digital Audio Interface

(PCM)

3.22 USB 2.0 Interface X X

Driven by

commands

X X

Driven by

Open AT®

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Q2686 Wireless CPU®

3.2 Power Supply

3.2.1 Power Supply Description

The power supply is one of the key issues in the design of a GSM terminal. Due to the burst emission mode used in GSM/GPRS, the power supply must be

able to deliver high current peaks in a short time. During the peaks, the ripple

) on the supply voltage must not exceed a certain limit (see Table 1 Power

ripp

supply voltage ).

• In communication mode, a GSM/GPRS class 2 terminal emits 577μs radio bursts every 4.615ms (see

VBATTT

Figure 2).

Uripp

t = 577 μs

T = 4,615 ms

Uripp

Figure 2: Power supply during burst emission

• In communication mode, a GPRS class 10 terminal emits 1154μs radio bursts every 4.615ms.

Only the VBATT input is necessary to supply the Q2686 Wireless CPU

VBATT:

• Directly supplies the RF components with 3.6 V. It is essential to keep a minimum voltage ripple at this connection in order to avoid any phase error.

The RF Power Amplifier current (1.5 A peak in GSM /GPRS mode) flows with a ratio of:

o 1/8 of the time (around 577μs every 4.615ms for GSM /GPRS cl. 2)

and

o 2/8 of the time (around 1154μs every 4.615ms for GSM /GPRS

cl. 10).

The rising time is around 10μs.

• Is internally used to provide, via several regulators, the VCC_2V8 and VCC_1V8 power supply required for the baseband signals.

The Q2686 Wireless CPU

shielding case is the grounding. The ground must

be connected to the motherboard through a complete layer on the PCB.

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Q2686 Wireless CPU®

VBATT

1,2

3.2 3.6 4.8

MIN

NOM

MAX

Table 1 Power supply voltage

(1): This value must be guarantied during the burst (with 1.5A Peak in GSM or GPRS mode) (2): Max operating Voltage Stationary Wave Ratio (VSWR) 2:1

When the Wireless CPU

is supplied with a battery, the total impedance

(battery + protections + PCB) should be < 150 mΩ. As the radio power amplifier is directly connected to VBATT, the Wireless CPU

is sensitive to any Alternative Current on lines. When a DC/DC converter is used, Wavecom recommends setting the converter frequency in such a way that the resulting voltage does not exceed the values in following table.

Freq. (kHz)

Max

ripp

(mVpp)

<10 300

10 ≤ f ≤ 200

> 200 10

Table 2 Maximum voltage ripple (Uripp) vs Frequency

When the Wireless CPU any pin of the 100-pin connector, except on Vbatt (pins 1 to 4) ,BAT-RTC (pin

7) for RTC operation or ON/~OFF (pin 19) to power-ON the Wireless CPU

is in Alarm/Off mode, no voltage has to be applied on

3.2.2 Power Consumption

Power consumption is dependent on the configuration used. It is for this reason that the following consumption values are given for each mode, RF band and type of software used (AT or Open AT

All the following information is given assuming a 50 Ω RF output. The following consumption values were obtained by performing measurements

on the Wireless CPU Three VBATT values are used to measure the consumption, VBATT

VBATT

(4.8V) and VBATT

MAX

samples at a temperature of 25° C.

(3.6V).

TYP

(3.2V),

MIN

The average current is given for the three VBATT values and the peak current given is the maximum current peak measured with the three VBATT voltages.

For a more detailed description of the operating modes, see the appendix of the AT Command User Guide

For more information on the consumption measurement procedure, see Q2686 Wireless CPU

Customer Design Guidelines [10].

[7].

First let’s define start-up current in view to avoid start issues.

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Q2686 Wireless CPU®

3.2.2.1 Start-up Current

The start-up current is defined as follow: During the first second following the Power on, a peak of current appears :

This peak of current is called “I

current “ and has a duration of about 161

startup

ms (Typical) . Figure 3 shows the waveform of current and localizes the peak considered as

the start-up current.

Figure 3: Start-up current waveform

In this condition, we can consider the following results:

25°C 3.2 V 3.6 V 4.8 V

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WM_PRJ_Q2686_PTS_001-010 June 30, 2009

88 mA 80 mA 64 mA

Start-up

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Q2686 Wireless CPU®

3.2.2.2 Power Consumption without Open AT

The following measurement results are relevant when:

• there is no Open AT

• Open AT

application is disabled

application

• no processing is required by the Open AT

Power consumption without Open AT® processing

Operating mode Parameters

Alarm Mode

Fast Idle Mode

Paging 9 (Rx burst occurrence ~2s) 32.6 39.7 43.2 154 RX mA

Paging 2 (Rx burst occurrence ~0,5s) 33.6 40.7 44.2 156

Paging 9 (Rx burst occurrence ~2s) 1.9 2.1 2.3 155 RX mA

Slow Idle Mode 1

Paging 2 (Rx burst occurrence ~0,5s) 5 5.7 6 158

Fast Standby Mode

Slow Standby Mode

average

VBATT=4,8V

Processing

application

NOM

average

VBATT=3,6V

NOM

average

VBATT=3,2V

MAX

peak

unit

21 16 15 µA

33.5 40.8 44.1 51 mA

0.37 0.38 0.43 49.9 mA

850/900 MHz

Connected Mode

PCL5 (TX power 33dBm) 209 217 222 1462 TX mA

PCL19 (TX power 5dBm) 85.6 93.8 98 257 TX mA

PCL0 (TX power 30dBm) 153 162 166 894 TX mA

1800/1900 MHz

PCL15 (TX power 0dBm) 82 89 94 225

850/900 MHz

Transfer Mode

class 8 (4Rx/1Tx)

gam. 3(TX power 33dBm) 198.2 206.5 211.5 1428 TX mA

gam.17(TX power 5dBm) 80 88 91 226

gam.3(TX power 30dBm) 145 153 158 870TX mA

1800/1900 MHz

gam.18(TX power 0dBm) 77 85 88 206

850/900 MHz

Transfer Mode

class 10 (3Rx/2Tx)

gam.3 (TX power 33dBm) 357 366.5 373 1426 TX mA

gam.17 (TX power 5dBm) 114 123 125 248

gam.3 (TX power 30dBm) 248 257 263 878TX mA

1800/1900 MHz

gam.18 (TX power 0dBm) 108 117 121 229

means that the current peak is the RF transmission burst (Tx burst)

means that the current peak is the RF reception burst (Rx burst)

Slow Idle Mode consumption is dependent on the SIM card used. Some SIM cards respond faster than others, the longer the response time, the higher the consumption. The measurements were performed with a large number of 3V SIM cards, the results in brackets are the minimum and

maximum currents measured from among all the SIMs used

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Q2686 Wireless CPU®

3.2.2.3 Power Consumption with Open AT

Software

The Open AT™ software used is the Full CPU Load application, the following consumption results are measured during the run of the Full CPU Load application.

The two tables are respectively for the CPU clock programmed at 26 MHz and 104 MHz.

Power consumption with Full CPU load Open AT® application CPU@26MHz

Working mode Parameters

NOM

average

VBATT=4,8V

NOM

average

VBATT=3,6V

NOM

average

VBATT=3,2V

MAX

peak

unit

Alarm Mode

Fast Idle Mode

Slow Idle Mode

Fast Standby Mode

Slow Standby Mode

Connected Mode

Transfer Mode class 8 (4Rx/1Tx)

GPRS

Transfer Mode class 10 (3Rx/2Tx)

N/A* N/A* N/A* N/A*

Paging 9 (Rx burst occurrence ~2s)

32 38 43 194

Paging 2 (Rx burst occurrence ~0,5s) 33 39 44 196

Paging 9 (Rx burst occurrence ~2s) N/A* N/A* N/A* N/A*

Paging 2 (Rx burst occurrence ~0,5s) N/A* N/A* N/A* N/A*

33 38 44 50 mA

N/A* N/A* N/A* N/A*

850/900 MHz

1800/1900 MHz

850/900 MHz

PCL5 (TX power 33dBm) 210 220 223 1390

PCL19 (TX power 5dBm) 86 92 95 270

PCL0 (TX power 30dBm) 154 162 167 888

PCL15 (TX power 0dBm) 80 88 92 241

Gam.3 (TX power

33dBm)

Gam.17 (TX power

5dBm)

Gam.3 (TX power

30dBm)

199 207 212 1450

80 88 92 249

147 152 159 860

1800/1900 MHz

850/900 MHz

Gam.18 (TX power

0dBm)

Gam.3 (TX power

33dBm)

Gam.17 (TX power

5dBm)

Gam.3 (TX power

30dBm)

77 85 89 221

357 367 374 1462

115 123 127 275

252 260 266 870

1800/1900 MHz

Gam.18 (TX power

0dBm)

109 117 121 249

means that the current peak is the RF transmission burst (Tx burst)

means that the current peak is the RF reception burst (Rx burst)

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Q2686 Wireless CPU®

* N/A: That doesn’t mean that no Open AT® application is possible in this specific mode. That means that the specific Full CPU load Open AT a worst case for the consumption measurement).

application can’t allow this specific mode. (This is

Power consumption with Full CPU load Open AT® application CPU@104MHz

Working mode Parameters

NOM

average

VBATT=4,8V

NOM

average

VBATT=3,6V

NOM

average

VBATT=3,2V

MAX

peak

unit

Alarm Mode

Fast Idle Mode

Slow Idle Mode

Fast Standby Mode

Slow Standby Mode

Connected Mode

Transfer Mode class 8 (4Rx/1Tx)

GPRS

Transfer Mode class 10 (3Rx/2Tx)

N/A* N/A* N/A* N/A*

Paging 9 (Rx burst occurrence ~2s)

51 62 68 220

Paging 2 (Rx burst occurrence ~0,5s) 52 63 69 220

Paging 9 (Rx burst occurrence ~2s) N/A* N/A* N/A* N/A*

Paging 2 (Rx burst occurrence ~0,5s) N/A* N/A* N/A* N/A*

49 63 69 150 mA

N/A* N/A* N/A* N/A*

850/900 MHz

1800/1900 MHz

850/900 MHz

PCL5 (TX power 33dBm) 210 220 230 1385

PCL19 (TX power 5dBm) 84 94 104 290

PCL0 (TX power 30dBm) 155 163 169 880

PCL15 (TX power 0dBm) 89 102 109 270

Gam.3 (TX power

33dBm)

Gam.17 (TX power

5dBm)

Gam.3 (TX power

30dBm)

225 243 252 1509

107 126 133 306

175 190 198 912

1800/1900 MHz

850/900 MHz

Gam.18 (TX power

0dBm)

Gam.3 (TX power

33dBm)

Gam.17 (TX power

5dBm)

Gam.3 (TX power

30dBm)

104 120 129 284

385 403 414 1532

142 159 167 385

271 288 301 949

1800/1900 MHz

Gam.18 (TX power

0dBm)

136 153 161 341

means that the current peak is the RF transmission burst (Tx burst)

means that the current peak is the RF reception burst (Rx burst)

* N/A: That doesn’t mean that no Open AT means that the specific Full CPU load Open AT a worst case for the consumption measurement).

application is possible in this specific mode. That

application can’t allow this specific mode. (This is

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3.2.2.4 Consumption Waveform Samples

Q2686 Wireless CPU®

The consumption waveforms are given for a EGSM900 network configuration with AT software running on the Q2686 Wireless CPU

/Open AT® Software

Suite v2. The VBATT voltage is at the typical value of 3.6V. Four significant operating mode consumption waveforms are described:

• Connected Mode (PCL5: Tx power 33dBm)

• Slow Idle mode (Paging 9)

• Fast idle mode (Paging 9)

• Transfer mode (GPRS class 10, PCL3: Tx power 33dBm )

The following waveform shows only the form of the current, for correct current values, see sections

3.2.2.4.1 Connected Mode Current Waveform

3.2.2.2 and 3.2.2.3.

Connected mode 33dBm

Current(A) / Time (s)

1.6

TX PEAK

1.4

1.2

0.8

0.6

0.4

0.2

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3.2.2.4.2 Slow Idle Mode Current Waveform

Slow Idle mode Paging ~2s

Current(A) / Time (s)

Q2686 Wireless CPU®

0.16

RX PEAK

0.14

0.12

0.1

0.08

0.06

0.04

0.02

-0.02

3.2.2.4.3 Fast Idle Mode Current Waveform

Fast Idle mode Paging ~2s

Current(A) / Time (s)

0.16

RX PEAK

0.14

0.12

0.1

0.08

0.06

0.04

0.02

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3.2.2.4.4 Transfer Mode Class 10 Current Waveform

Transfer mode Class 10 33dBm

Current(A) / Time (s)

1.6

TX PEAK

1.4

1.2

0.8

0.6

0.4

0.2

Q2686 Wireless CPU®

3.2.2.5 Power Supply Pin-out

The grounding connection is made through the shielding; the four leads must

be soldered to the ground plane.

Signal Pin number

VBATT

GND

Power supply pin-out

1,2,3,4

Shielding

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Q2686 Wireless CPU®

3.3 Electrical Information for Digital I/O

The three types of digital I/O on the Q2686 Wireless CPU® are: 2.8 volt CMOS,

1.8 volt CMOS and Open drain. The three types are described below:

Electrical characteristics of digital I/O

2.8 volt type (2V8 )

Parameter I/O type Minim. Typ Maxim. Condition

Internal 2.8V power supply

Input / Output pin

VIL

VIH

VOL

VOH

IOH

IOL

*Absolute maximum ratings

VCC_2V8

CMOS

2.74V 2.8V 2.86V

-0.5V* 0.84V

1.96V 3.2V*

0.4V IOL = - 4 mA

2.4V IOH = 4 mA

4mA

- 4mA

All 2.8V I/O pins do not accept input signal voltage above the maximum voltage specified above, except for the UART1 interface, which is 3.3V tolerant.

1.8 volt type (1V8)

Parameter I/O type Minim. Typ Maxim. Condition

Internal 1V8 power supply VCC_1V8

Input / Output pin

VIL CMOS -0.5V* 0.54V

VIH CMOS 1.33V 2.2V*

1.76V 1.8V 1.94V

VOL CMOS 0.4V IOL = - 4 mA

VOH CMOS 1.4V IOH = 4 mA

IOH

IOL

*Absolute maximum ratings

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4mA

- 4mA

Page: 31 / 97

Q2686 Wireless CPU®

Open drain output type

Signal name Parameter I/O type Minimum Typ Maximum Condition

LED0

SDA1 /

GPIO27

and

SCL1 /

VOL Open Drain

Open Drain

VOL Open Drain

Open Drain

TOL

VIH Open Drain

VIL Open Drain

0.4V

8mA

0.4V BUZZER0

100mA

3.3V Tolerated

0.8V

voltage

GPIO26

VOL Open Drain

Open Drain

0.4V

3mA

The reset states of the I/Os are given in each interface description chapter. Definitions of these states are given below:

Reset state definition

Parameter Definition

Pull-down

Set to GND

Set to supply 1V8 or 2V8 depending on I/O type

Internal pull-down with ~60kΩ resistor.

Pull-up Internal pull-up with ~60kΩ resistor to supply 1V8 or 2V8

depending on I/O type.

Z High impedance

Undefined Caution: undefined must not be used in your application if a

special state is required at reset. These pins may be a toggling signal during reset.

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Q2686 Wireless CPU®

3.4 Serial interface

The Q2686 Wireless CPU® provide two SPI bus (i.e. for LCD, memories…). or an I²C 2-wire interface..

3.4.1 SPI Bus

Both SPI bus interfaces include:

• A CLK signal

• An I/O signal

• An I signal

• A CS (Chip Select) signal complying with the standard SPI bus (any

GPIO).

• An optional Load signal (only the SPIx-LOAD signal)

3.4.1.1 Characteristics

• Master mode operation

• The CS signal must be any GPIO

• The LOAD signal (optional) is used for the word handling mode (only the

SPIx-LOAD signal)

• SPI speed is from 102 kbit/s to 13 Mbit/s in master mode operation

• 3 or 4-wire interface(5-wire possible with the optional SPIx-LOAD signal)

• SPI-mode configuration: 0 to 3 (for more details, refer to document.

• 1 to 16 bits data length

3.4.1.2 SPI configuration

Operation Maximum

Speed

Master 13 Mb/s 0,1,2,3 Half

For the 3-wire configuration, SPIx-I/O is used as input and output.

SPI-

Mode

Duplex 3-wire

type

SPIx-CLK; SPIx-IO;

GPIOx as CS

4-wire

type

SPIxCLK; SPIx-IO; SPIx-I; GPIOx as CS

5-wire type

SPIx-CLK; SPIxIO; SPIx-I; GPIOx as CS; SPIxLOAD (not muxed in GPIO);

For the 4-wire configuration, SPIx-I/O is used as output only, SPIx-I is used as input only.

For the 5-wire configuration, SPIx-I/O is used as output only, SPIx-I is used as input only. And the dedicated SPIx-LOAD signal is used. It is an additional signal in more than a Chip Select (any other GPIOx)

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Q2686 Wireless CPU®

3.4.1.3 SPI waveforms

Waveform for SPI transfer with 4-wire configuration in master mode 0 .

Figure 4: SPI Timing diagrams,Mode 0,Master,4 wires

AC characteristics

Signal Description Minimum Typ Maximum Unit

CLK-cycle SPI clock frequency 0.102 13 MHz

Data-OUT delay Data out ready delay time

10 ns

Data-IN-setup Data in setup time 2 ns

Data-OUT-hold Data out hold time 2 ns

Waveform for SPI transfer with the LOAD signal configuration in master mode

0.(chip select is not represented)

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CLK-cycle

Q2686 Wireless CPU®

D1 D0

Tload_lead

Tload_high Tload_lag

Figure 5: SPI Timing diagrams with LOAD signal, Mode 0, Master, 4 wires

3.4.1.4 SPI1 Bus: Pins description

Pins description

Signal Pin

number

I/O I/O

type

Reset

state

Description Multiplexed

with

SPI1-CLK 23 O 2V8 Z SPI Serial Clock GPIO28 SPI1-IO 25 I/O 2V8 Z SPI Serial input/output GPIO29 SPI1-I 24 I 2V8 Z SPI Serial input GPIO30 SPI1-LOAD 22 O 2V8 Z SPI load GPIO31

For Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition, refer to Chapter

3.3, "Electrical information for digital I/O".

3.4.1.5 SPI2 Bus: Pins description

Pins description

Signal Pin

number

I/O I/O

type

Reset

state

Description Multiplexed

with

SPI2-CLK 26 O 2V8 Z SPI Serial Clock GPIO32

SPI2-IO 27 I/O 2V8 Z SPI Serial input/output GPIO33

SP2-I 29 I 2V8 Z SPI Serial input GPIO34

SPI2-LOAD 28 O 2V8 Z SPI Load GPIO35

See Chapter 3.3 “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

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Q2686 Wireless CPU®

3.4.2 I2C Bus

The I2C interface includes a clock signal (SCL1) and data signal (SDA1) complying with a 100kbit/s-standard interface (standard mode: s-mode).

The I²C bus is always master. The maximum speed transfer range is 400kbit/s (fast mode: f-mode). For more information on the bus, see the “I²C Bus Specification Version 2.0”

from PHILIPS

[13].

3.4.2.1 I²C Waveforms

I²C bus waveform in master mode configuration:

Figure 6: I²C Timing diagrams, Master

AC characteristics

Signal Description Minimum Typ Maximum Unit

SCL1-freq I²C clock frequency 100 400 kHz

T-start Hold time START condition 0.6 μs

T-stop Setup time STOP condition 0.6 μs

T-free Bus free time, STOP to START

1.3 μs

T-high High period for clock 0.6 μs

T-data-hold Data hold time 0 0.9 μs

T-data-setup Data setup time 100 ns

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3.4.2.2 I²C Bus Pin-out

Pin description

Q2686 Wireless CPU®

Signal Pin

number

I/O I/O type Reset

state

Description Multiplexed

with

SCL1 44 O Open drain Z Serial Clock GPIO26

SDA1 46 I/O Open drain Z Serial Data GPIO27

See Chapter 3.3, "Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

3.5 Keyboard Interface

This interface provides 10 connections:

• 5 rows (ROW0 to ROW4) and

• 5 columns (COL0 to COL4).

The scanning is a digital one and debouncing is performed in the Q2686 Wireless CPU

No discrete components such as Rs, Cs (Resistors, Capacitors) are needed.

Signal Pin

number

Keyboard interface pin description

I/O I/O

type

Reset

state

Description Multiplexed

with

ROW0 68 I/O 1V8 0 Row scan GPIO9

ROW1 67 I/O

ROW2 66 I/O

ROW3 65 I/O

ROW4 64 I/O

COL0 59 I/O

COL1 60 I/O

COL2 61 I/O

COL3 62 I/O

COL4 63 I/O

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and for Reset state definition.

1V8

0 Row scan GPIO10

0 Row scan GPIO11

0 Row scan GPIO12

0 Row scan GPIO13

Pull-up Column scan GPIO4

Pull-up Column scan GPIO5

Pull-up Column scan GPIO6

Pull-up Column scan GPIO7

Pull-up Column scan GPIO8

With the Open AT® Software Suite v2 when the keyboard service is used the whole multiplexed signals become unavailable for other purposes. In the same way if one or more GPIOs ( of this table) are allocated the keyboard service is unavailable.

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Q2686 Wireless CPU®

3.6 Main Serial Link (UART1)

A flexible 8-wire serial interface is available, complying with V24 protocol signalling, but not with V28 (electrical interface) due to a 2.8 volts interface.

The signals are:

• TX data (CT103/TX)

• RX data (CT104/RX)

• Request To Send (~CT105/RTS)

• Clear To Send (~CT106/CTS)

• Data Terminal Ready (~CT108-2/DTR)

• Data Set Ready (~CT107/DSR).

• Data Carrier Detect (~CT109/DCD)

• Ring Indicator (CT125/RI).

UART1 interface pin description

Signal Pin

number

CT103/TXD1* 71 I 2V8 Z Transmit serial

I/O I/O

type

Reset

state

Description Multiplexed

with

GPIO36

data

CT104/RXD1* 73 O

2V8

1 Receive serial

GPIO37

data

~CT105/RTS1* 72 I

2V8

Z Request To

GPIO38

Send

~CT106/CTS1* 75 O

~CT107/DSR1* 74 O

~CT108-

76 I

2/DTR1*

~CT109/DCD1 * 70 O

2V8

Z Clear To Send GPIO39

Z Data Set Ready GPIO40

Z Data Terminal

Ready

Undefined Data Carrier

GPIO41

GPIO43

Detect

~CT125/RI1 * 69 O

CT102/GND* Shielding

2V8

Undefined Ring Indicator GPIO42

GND Ground

leads

See Chapter “3.3 Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and for Reset state definition.

*According to PC view

With the Open AT® Software Suite v2, when the UART1 service is used, the whole multiplexed signals become unavailable for other purposes. In the same way if one or more GPIOs (of this table) are allocated the UART1 service is unavailable.

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Q2686 Wireless CPU®

The rise and fall time of the reception signals (mainly CT103) must be less than 300 ns.

The maximum baud rate of UART1 is 921 kbit/s for the firmware provided in the Open AT

Recommendation: The Q2686 Wireless CPU

Software Suite v2.

is designed to operate using all the serial interface signals. In particular, it is recommended to use RTS and CTS for hardware flow control in order to avoid data loss during transmission.

For use with 5-wire serial interface

• Signal: CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*

• The signal ~CT108-2/DTR1* must be managed by following the V24

protocol signalling, if you want to use the slow idle mode.

• Other signals and their multiplexes are not available.

• Please refer to technical appendixes of AT commands User Guide

[7] for

more information.

For use with 4-wire serial interface

• CT103/TXD1*, CT104/RXD1*, ~CT105/RTS1*, ~CT106/CTS1*

• The signal ~CT108-2/DTR1* must be configured at low level.

• Other signals and their multiplexes are not available.

• Please refer to technical appendixes in the AT commands User Guide

[7]

for more information.

For use with 2-wire serial interface

• This case is possible for connected external chip, but not recommended (and forbidden for AT command or modem use)

• The flow control mechanism has to be managed at the customer side.

• CT103/TXD1*, CT104/RXD1*

• The signal ~CT108-2/DTR1* must be configured at low level.

• The signals ~CT105/RTS1*, ~CT106/CTS1* are not used, please

configure the AT command (AT+IFC=0,0 see AT command User Guide [7]).

• The signal ~CT105/RTS1* must be configured at low level.

• Other signals and their multiplexes are not available.

• Please refer to technical appendixes in the AT commands User Guide

for more information.

[7]

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3.7 Auxiliary Serial Link (UART2)

Q2686 Wireless CPU®

An auxiliary serial interface (UART2) is available on Q2686. This interface may be used to connect a Bluetooth or a GPS chip controlled by an Open AT

Plug-

in.

UART2 interface pin description

Signal Pin

number

CT103 /

31 I 1V8 Z Transmit serial data GPIO14

I/O I/O type Reset

state

Description Multiplexed

with

TXD2*

CT104 /

30 O

1V8

Z Receive serial data GPIO15

RXD2*

~CT106 /

32 O

1V8

Z Clear To Send GPIO16

CTS2*

~CT105 /

33 I

1V8

Z Request To Send GPIO17

RTS2*

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

* According to PC view

The Q2686 is designed to operate using all the serial interface signals. In particular, it is recommended to use RTS and CTS for hardware flow control in order to avoid data corruption during transmission.

The maximum baud rate of UART2 is 921 kbit/s for the firmware provided with Open AT

For use with 4-wire serial interface

Software Suite v2.

• CT103/TXD2*, CT104/RXD2*, ~CT105/RTS2*, ~CT106/CTS2*

• The signal ~CT108-2/DTR2* must be configured at low level.

• Other signals and their multiplexes are not available.

• Please refer to technical appendixes in the AT commands User Guide

[7]

for more information.

For use with 2-wire serial interface

• This case is possible for connected external chip, but not recommended (and forbidden for AT command or modem use)

• The flow control mechanism has to be managed at the customer side.

• CT103/TXD2*, CT104/RXD2*

• The signals ~CT105/RTS2*, ~CT106/CTS2* are not used, you must

configure the AT command (AT+IFC=0,0 see AT commands User Guide [7]).

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• The signal ~CT105/RTS2* must be configured at low level.

• Other signals and their multiplexes are not available.

Q2686 Wireless CPU®

• Please refer to technical appendixes in the AT commands User Guide

[7]

for more information.

3.8 SIM Interface

The Subscriber Identification Module (SIM) may be directly connected to the Q2686 Wireless CPU

3.8.1 General Description

The five signals are:

• SIM-VCC: SIM power supply

• ~SIM-RST: reset

• SIM-CLK: clock

• SIM-IO: I/O port

• SIMPRES: SIM card detect

The SIM interface controls a 3V/1V8 SIM. This interface is fully compliant with the GSM 11.11 recommendations concerning SIM functions.

via this dedicated interface.

SIM interface pin description

Signal Pin

number

I/O I/O type Reset

state

Description Multiplexed

with

SIM-CLK 14 O 2V9 / 1V8 0 SIM Clock Not mux

~SIM-RST 13 O

SIM-IO 11 I/O

SIM-VCC 9 O

2V9 / 1V8

0 SIM Reset

*Pull-up SIM Data

SIM Power

Not mux

Supply

SIMPRES 12 I

1V8

Z SIM Card

GPIO18

Detect

*SIM-IO pull-up is about 10 k Ω.

See Chapter characteristics and Reset state definition.

3.3 “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage

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Q2686 Wireless CPU®

SIM interface electrical characteristics

Parameter Conditions Minim. Typ Maxim. Unit

SIM-IO VIH

SIM-IO VIL I ~SIM-RST, SIM-CLK

SIM-IO VOH

~SIM-RST, SIM-IO, SIMCLK

SIM-VCC current VBATT = 3.6V 10 mA

SIM-CLK Rise/Fall Time Loaded with 30pF 20 ns

~SIM-RST, Rise/Fall Time Loaded with 30pF 20 ns

= ± 20μA

= 1mA 0.4 V

Source current = 20μA 0.9xSIMVCC V

Source current = 20μA 0.8xSIMVCC

Sink current =

-200μA

SIMVCC = 2.9V

IVCC= 1mA

SIMVCC = 1.8V

IVCC= 1mA

0.7xSIMVCC V

0.4 V

2.84 2.9 2.96 V SIM-VCC Output Voltage

1.74 1.8 1.86 V

SIM-IO Rise/Fall Time Loaded with 30pF 0.7 1 μs

SIM-CLK Frequency Loaded with 30pF 3.25 MHz

Note: When SIMPRES is used, a low to high transition means that the SIM card is

inserted and a high to low transition means that the SIM card is removed.

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Q2686 Wireless CPU®

3.9 General Purpose Input/Output

The Q2686 Wireless CPU® provides up to 44 General Purpose I/Os, used to control any external device such as an LCD or a Keyboard backlight.

All I/Os highlighted in grey are 1V8, whereas the others (not highlighted in grey) are 2V8.

GPIO pin description

Signal

number

I/O I/O type*

Reset state

Multiplexed with

Reserved 42 Do not used*

GPIO0 43

GPIO1 51

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

50 I/O 1V8

59 I/O 1V8

60 I/O 1V8

61 I/O 1V8

62 I/O 1V8

63 I/O 1V8

68 I/O 1V8

67 I/O 1V8

66 I/O 1V8

65 I/O 1V8

I/O

2V8 Undefined 32kHz**

1V8 0 Not mux

1V8

Pull-up

Not mux

INT0

COL0

COL1

COL2

COL3

COL4

ROW0

ROW1

ROW2

ROW3

GPIO13

64 I/O 1V8

ROW4

GPIO14 31 I/O 1V8 Z CT103 / TXD2

GPIO15 30 I/O 1V8 Z CT104 / RXD2

GPIO16 32 I/O 1V8 Z ~CT106 / CTS2

GPIO17 33 I/O 1V8 Z ~CT105 / RTS2

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

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12 I/O 1V8

45 I/O 2V8

48 I/O 2V8

47 I/O 2V8

57 I/O 2V8

55 I/O 2V8

Z SIMPRES

Z Not mux

Undefined

Not mux

Not mux*

Z Not mux

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Q2686 Wireless CPU®

Signal

GPIO24

GPIO25

GPIO26

GPIO27

number

I/O I/O type*

58 I/O 2V8

49 I/O 2V8

44 I/O

46 I/O

Open

drain

Open

drain

Reset state

Multiplexed with

Z Not mux

INT1

SCL1

SDA1

GPIO28 23 I/O 2V8 Z SPI1-CLK

GPIO29 25 I/O 2V8 Z SPI1-IO

GPIO30 24 I/O 2V8 Z SP1-I

GPIO31 22 I/O 2V8 Z

GPIO32 26 I/O 2V8 Z SPI2-CLK

GPIO33 27 I/O 2V8 Z SPI2-IO

GPIO34 29 I/O 2V8 Z SP2-I

GPIO35 28 I/O 2V8 Z

GPIO36 71 I/O 2V8 Z CT103 / TXD1

GPIO37 73 I/O 2V8 1 CT104 / RXD1

GPIO38 72 I/O 2V8 Z ~CT105 / RTS1

GPIO39 75 I/O 2V8 Z ~CT106 / CTS1

GPIO40 74 I/O 2V8 Z ~CT107 / DSR1

GPIO41 76 I/O 2V8 Z ~CT108-2 / DTR1

GPIO42 69 I/O 2V8 Undefined ~CT125 / RI1

GPIO43 70 I/O 2V8 Undefined ~CT109 / DCD1

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

* If a Bluetooth module is used with the Q2686 Wireless CPU

** With the Open AT

Software Suite v2: see “AT commands User Guide ” [7].

, these GPIOs must be reserved.

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Q2686 Wireless CPU®

3.10 Analog to Digital Converter

Two Analog to Digital Converter inputs are provided by the Q2686 Wireless

. The converters are more than 10-bit resolution, ranging from 0 to 2V.

CPU ADC1 / BAT-TEMP input can be used, typically, to monitor external

temperature, useful for safety power off in case of application over heating (for Li-Ion battery).

ADC2 input can be used for customer application.

ADC pin description

Signal Pin number I/O I/O type Description

ADC1/BAT-TEMP* 20 I Analog A/D converter

ADC2 21 I Analog A/D converter

* This input can be used for a battery charging temperature sensor, see Chapter

3.13, “Battery Charging interface“.

ADC electrical characteristics

Parameter Min Typ Max Unit

Maximum output code 1635 LSB

Sampling period 0,5 31 s

Input signal range 0 2 V

Input impedance

Sampling rate only for ADC2 and Open AT® application.

ADC1/BAT-

TEMP

ADC2

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Q2686 Wireless CPU®

3.11 Analog Audio Interface

Two different microphone inputs and two different speaker outputs are supported. The Q2686 INSIM Wireless CPU® also includes an echo cancellation feature, which allows hands-free function

In some cases, ESD protection must be added on the audio interface lines.

3.11.1 Microphone Features

The connection can be either differential or single-ended but using a differential connection in order to reject common mode noise and TDMA noise is strongly recommended. When using a single-ended connection, be sure to have a very good ground plane, a very good filtering as well as shielding in order to avoid any disturbance on the audio path.

The gain of MIC inputs is internally adjusted and can be tuned using an AT command.

Both can be configured in differential or single ended. The MIC2 inputs already include the biasing for an electret microphone

allowing an easy connection.

3.11.1.1 MIC1 Microphone Inputs

By default, the MIC1 inputs are single-ended but it can be configured in differential.

The MIC1 inputs do not include an internal bias . The MIC1 input needs to have an external biasing if an electret microphone is used.

AC coupling is already embedded in the Wireless Microprocessor®.

Equivalent circuits of MIC1

DC equivalent circuit AC equivalent circuit

MIC1P

MIC1N

Blocked

MIC1P

MIC1N

GND

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Q2686 Wireless CPU®

Electrical Characteristics of MIC1

Parameters Min Typ Max Unit

DC Characteristics N/A V

AC Characteristics

Z1 70 120 160

kΩ

200 Hz<F<4 kHz

AT+VGT*=3500

Working voltage

AT+VGT*=2000

( MIC1P-MIC1N)

AT+VGT*=700

(4)

13.8 18.6*** mVrms

(4)

77.5 104*** mVrms

(4)

346 465*** mVrms

Positive +7.35 V Maximum rating

voltage

(MIC1P or MIC1N)

• *The input voltage depends of the input micro gain set by AT command. Please refer to the document :AT command User Guide [7]

• **Because MIC2P is internally biased, it is necessary to use a coupling capacitor to connect an audio signal provided by an active generator. Only a passive microphone can be directly connected to the MIC2P and MIC2N inputs.

• *** This value is obtained with digital gain = 0 and for frequency = 1kHz :

(4)

•

This value is given in dB, but it’s possible to toggle to index value. Please refer to the

document :AT command User Guide [7]

Negative

0.9

WARNING:

The voltage input value for MIC1 can’t exceed the maximum working voltage, otherwise clipping will appear.

3.11.1.2 MIC2 Microphone Inputs

By default, the MIC2 inputs are differential ones, but it can be configured in single ended. They already include the convenient biasing for an electret microphone. The electret microphone can be directly connected on those inputs, thus allowing easy connection to a handset.

AC coupling is already embedded in the Wireless CPU

Equivalent circuits of MIC2

DC equivalent circuit AC equivalent circuit

MIC2P

MIC2N

MIC2+

GND

MIC2P

MIC2N

GND

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Q2686 Wireless CPU®

Electrical Characteristics of MIC2

Parameters Min Typ Max Unit

MIC2+ 2 2.1 2.2 V

Internal biasing

DC Characteristics

Output current 0.5 1.5 mA

R2 1650 1900 2150

Z2 MIC2P (MIC2N=Open)

1.1 1.3 1.6

Z2 MIC2N (MIC2P=Open)

AC Characteristics

200 Hz<F<4 kHz

Z2 MIC2P (MIC2N=GND)

Z2 MIC2N

0.9 1.1 1.4

kΩ

(MIC2P=GND)

Impedance between MIC2P

1.3 1.6 2

and MIC2N

AT+VGT*=3500

Working voltage

AT+VGT*=2000

( MIC2P-MIC2N)

AT+VGT*=700

Maximum rating

Positive +7.35**

voltage

(4)

13.8

(4)

77.5 104***

(4)

346 466***

18.6 ***

mVrms

Negative -0.9

(MIC2P or MIC2N)

• *The input voltage depends of the input micro gain set by AT command. Please refer to the document : AT command User Guide[7]

• *** This value is obtained with digital gain = 0 and for frequency = 1kHz ..

• (4) This value is given in dB, but it’s possible to toggle to index value. Please refer to the

document :AT command User Guide [7]

WARNING:

The voltage input value for MIC2 can’t exceed the maximum working voltage, otherwise clipping will appear.

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Q2686 Wireless CPU®

3.11.2 Speaker Features

The connection is single-ended on SPK1 and is differential or single-ended on SPK2. Using a differential connection to reject common mode noise and TDMA noise is strongly recommended. Moreover in single-ended mode, the power is divided by 4. When using a single-ended connection, be sure to have a very good ground plane, a very good filtering as well as shielding in order to avoid any disturbance on the audio path.

Parameter Typ Unit Connection

Z (SPK1P, SPK1N) 16 or 32

Z (SPK2P, SPK2N) 4

Z (SPK2P, SPK2N) 8

single-ended mode

Differential mode

3.11.2.1 Speakers Outputs Power

The both speakers maximum power output are not similar, that is due to the different configuration between the Speaker1 which is only single ended and the speaker2 which can be differential, so speaker2 can provides more power.

The maximal specifications given below are available with the maximum power output configuration values set by an AT command. The typical values are recommended.

3.11.2.1.1 SPK1 Speaker Outputs

With the SPK1 interface, only single ended speaker connection is allowed

Equivalent circuits of SPK1

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Q2686 Wireless CPU®

Electrical Characteristics of SPK1

Parameters Min Typ Max Unit

Biasing

- 1.30 V

voltage

Output swing voltage

RL=16Ω: AT+VGR=-1600**; single-ended

RL=32Ω; AT+VGR=-1600**; single-ended

RL Load resistance 14.5 32 -

IOUT Output current;

single-ended; peak value

POUT

RL=16Ω; AT+VGR*=-1600**

RL=16Ω

RL=32Ω

RL=32Ω; AT+VGR*=-1600**

RPD Output pull-down resistance at

- 1.7 - Vpp

- 1.9 2.75

Vpp

- 40 85 mA

- 22 - mA

- 25 mW

- 16 27 mW

28 40 52

kΩ

power-down

• *The output voltage depends of the output speaker gain set by AT command. Please refer to the document AT command User Guide [7].

• ** This value is given in dB, but it’s possible to toggle to index value. Please refer to the

document :AT command User Guide [7]

3.11.2.1.2 SPK2 Speaker Outputs

The SPK2 interface allows differential and single ended speaker connection

Equivalent circuits of SPK2

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Q2686 Wireless CPU®

Electrical Characteristics of SPK2

Parameters Min Typ Max Unit

Biasing

SPK2P and SPK2N 1.30 V

voltage

Output swing voltage

RL=8Ω: AT+VGR=-1000*; single ended

RL=8Ω: AT+VGR=-1000*;

- - 2 Vpp

- - 4 Vpp

differential

RL=32Ω: AT+VGR=-1000*; single

- - 2.5 Vpp

ended

RL=32Ω: AT+VGR=-1000*;

- - 5 Vpp

differential

RL Load resistance 6 8 -

IOUT

POUT

Output current; peak value; RL=8Ω

RL=8Ω; AT+VGR=-1000*;

RPD Output pull-down resistance at

- - 180 mA

- - 250 mW

28 40 52

kΩ

power-down

VPD Output DC voltage at power-down - - 100 mV

• *The output voltage depends of the output speaker gain set by AT command. Please refer to the document: AT command User Guide [7].This value is given in dB, but it’s possible to toggle to index value.

If a singled ended solution is used with the speaker2 output, only one of the both SPK2 has to be chosen. The result is a maximal output power divided by

3.11.3 Pin description

Signal Pin

I/O I/O type Description

number

MIC1P

MIC1N

MIC2P

MIC2N

SPK1P

SPK1N

SPK2P

SPK2N

I Analog Microphone 1 positive input

I Analog Microphone 1 negative input

I Analog Microphone 2 positive input

I Analog Microphone 2 negative input

O Analog Speaker 1 positive output

O Analog Speaker 1 negative output

O Analog Speaker 2 positive output

O Analog Speaker 2 negative output

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Q2686 Wireless CPU®

3.12 Buzzer Output

This output is controlled by a pulse width modulation controller and may be used only as buzzer.

BUZZER0 is an open drain output. A buzzer can be directly connected between this output and VBATT. The maximum current is 100 mA (PEAK).

Pin description of PWM/Buzzer output

Signal Pin

I/O I/O type Reset state

Description

number

BUZZER0 15 O Open

Z Buzzer output

drain

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

Electrical characteristics

Parameter Condition Minimum Maximum Unit

Iol = 100mA 0.4

OL on

VBATT = VBATTmax

PEAK

100

Frequency 1 50000

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Q2686 Wireless CPU®

3.13 Battery Charging Interface

The Q2686 Wireless CPU® supports one battery charging circuit, two algorithms and one hardware charging mode (pre-charging) for 3 battery technologies:

• Ni-Cd (Nickel-Cadmium) with algorithm 0

• Ni-Mh (Nickel-Métal Hydrure) with algorithm 0

• Li-Ion (Lithium-Ion) with the embedded PCM (Protection Circuit

Module).algorithm 1

The two algorithms control a switch, which connects the CHG-IN signal to the VBATT signal. The algorithm controls the frequency and the connected time of the switching. During the charging procedure, battery charging level is monitored and when Li-Ion algorithm is used, battery temperature is monitored via the ADC1/BAT-TEMP input.

One more charging procedure is provided by the Q2686 Wireless CPU called “Pre-charging” mode, but is a special charging mode because it is activated only when the Wireless CPU

is OFF. Control is in this case only performed by the hardware. The purpose of this charging mode is to avoid battery damage by preventing the battery from being discharged to below the minimum battery level.

. This is

3.13.1 Ni-Cd / Ni-Mh Charging Algorithm

To charge the battery, the algorithm measures battery level when the switch is open (T2) and charges the battery by closing the switch (T3). When the battery is charged (battery voltage has reached BattLevelMax) the switch is open for time T3.

BattLevelMax

Battery Level

T1T2 T3

closed

Switch State

opened

Figure 7: Ni-Cd / Ni-Mh charging waveform

Electrical characteristics of Ni-Cd / Ni-Mh battery timing charge

Parameter Min Typ Max Unit

T1 1 s T2 0.1 s T3 5 s

Note: T1,T2,T3 and BattLevelMax may be configured by AT command.

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Q2686 Wireless CPU®

The battery level is monitored by the software (but not temperature)

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Q2686 Wireless CPU®

3.13.2 Li-Ion Charging Algorithm

The Li-Ion algorithm provides battery temperature monitoring, which is highly recommended to prevent battery damage during the charging phase.

The Li-Ion charger algorithm can be broken down into three phases:

1. Constant charge

2. Beginning of pulse charge

3. End of pulse charge

The three phases can be seen on the following waveform for full charging:

Figure 8: Li-Ion full charging waveform

Electrical characteristics of Li-Ion battery timing charge

Parameter Min Typ Max Unit

Step 1 switching Closed Always s

Open 0.1 s Step 2 switching

Closed 1 s

Open 0.1 3 s Step 3 switching

Closed 1 s

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Q2686 Wireless CPU®

3.13.3 Pre-charging

When a charger DC power supply is connected to the CHG-IN input and if the voltage battery is between 2.8V* and 3.2V, a constant current of 50mA is provided to the battery.

When the battery is able to supply the Q2686 Wireless CPU

, it is automatically

powered on and the software algorithm is activated to finish the charge. * For the Lithium-ion battery, the minimum voltage must be higher than PCM

lock level. Note: When pre-charging is launched, the LED0 output blinks automatically.

WARNING:

The Q2686 Wireless CPU

can not release the PCM protection inside Lithium battery pack. Voltage forbidden on the CHG-IN signal if no battery connected on VBATT signals.

3.13.4 Temperature Monitoring

Temperature monitoring is only available for the Li-Ion battery with algorithm

1. The ADC1/BAT-TEMP (pin 20) input must be used to sample the temperature analog signal provided by an NTC temperature sensor. The minimum and maximum temperature range may be set by AT command.

Pin description of battery charging interface

Signal Pin number I/O I/O type Description

CHG-IN 6,8 I Analog Current source input

ADC1/BAT-

20 I Analog A/D converter

TEMP

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Q2686 Wireless CPU®

Electrical characteristics of battery charging interface

Parameter Minimum Typ Maximum Unit

Charging operating temperature 0 50 °C

ADC1/BAT-TEMP (pin 20 )

CHG-IN (pin 6, 8 )

• * To be configured as specified by the battery manufacturer

• ** : Take care ; this value has to be selected in function of the power consumption mode

used: please refer to the power consumption tables § 3.2.2.

WARNINGS:

o The Charger DC power supply must have an output current limited to

800mA.

o The maximum Charger output current, provided to the battery, must be

accorded to the battery electrical characteristics.

Maximum output

1635

LSB

code

Sampling rate 216 S/s

Input Impedance ( R )

Input signal range 0 2 V

Voltage (for I=Imax) 4.8* V

Voltage (for I=0) 6* V

DC Current

400**

800 mA

o Li-Ion batteries must be used with the embedded PCM (Protection

Circuit Module).

o The maximum charging voltage is up to 4,3V (Software drive) o At the first plug, if the battery Li-ion is locked by its PCM the charger

function doesn't work.

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3.14 ON / ~OFF signal

This input is used to switch the Q2686 Wireless CPU® ON or OFF.

Q2686 Wireless CPU®

A high-level signal must be provided on the ON/~OFF pin to switch ON the Wireless CPU

. The voltage of this signal has to be maintained higher than 0.8 x VBATT during a minimum of 1500ms. This signal can be left at high level until switch-off.

To switch OFF the Wireless CPU Wireless CPU

can be switched off via the Operating System.

, the ON/OFF pin must be released. The

Pin description

Signal Pin number I/O I/O type Description

ON/∼OFF

19 I CMOS Wireless CPU

Power-ON

Electrical characteristics of the signals

Parameter I/O type Minimum Maximum Unit

VIL CMOS VBATT x 0.2 V

VIH CMOS VBATT x 0.8 VBATT V

Warning: All external signals must be inactive when the Wireless CPU® is OFF to avoid

any damage when starting and allow the Wireless CPU® to start and stop correctly.

3.14.1 Operating Sequences

3.14.1.1 Power-ON

Once the Wireless CPU signal to high to start the Wireless CPU signal must be held high during a minimum delay of T delay on the ON/~OFF signal) to power-ON. After this delay, an internal mechanism maintains the Wireless CPU

During the power-ON sequence, an internal reset is automatically performed by the Wireless CPU

for 40ms (typical). Any external reset should be avoided

is supplied, the application must set the ON/OFF

power-ON sequence. The ON/OFF

on/off-hold

in power-ON condition.

(Minimum hold

during this phase. Once initialization is completed (timing is SIM- and network-dependent), the

AT interface answers "OK" to the application. For further details, please check the AT Commands User Guide

[7].

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Q2686 Wireless CPU®

POWER SUPPLY

ON/OFF

INTE RNAL RST

STATE OF THE Wireless CPU

= overall current consumption (Base Band + RF part)

BB+RF

Wireless CPU ®

OFF

< 22μA

(2000ms min)

rst

(40ms typ)

RESET mode

BB+RF

on/off-h old

=20 to 40mA

SIM and Network dependent

Wireless CPU

<120mA

BB+RF

AT answers « OK »

Wireless CPU ®

READY

Figure 9: Power-ON sequence (no PIN code activated)

The duration of the firmware power-up sequence depends on:

• the need to perform a recovery sequence if the power has been lost during a flash memory modification.

Other factors have a minor influence

• the number of parameters stored in EEPROM by the AT commands received so far

• the ageing of the hardware components, especially the flash memory

• the temperature conditions

The

recommended

way to de-assert the ON/~OFF signal is to use either an AT command or WIND indicators: the application must detect the end of the power-up initialization and de-assert ON/~OFF afterwards.

• Send an “AT” command and wait for the “OK” answer: once the

initialization is complete the AT interface answers « OK » to “AT” message

• Wait for the “+WIND: 3” message: after initialization, the Wireless CPU

, if

configured to do so, will return an unsolicited “+WIND: 3” message. The generation of this message is enabled or disabled via an AT command.

Note:

3.14.1.2 Power-OFF

To power-OFF the Wireless CPU ON/OFF signal and then send the AT+CPOF command to deregister from the network and switch off the Wireless CPU

Once the "OK" response is issued by the Wireless CPU

correctly, the application must reset the

, the power supply can

be switched off.

POWER SUPPLY

OFF

AT COMMAND

STATE OF THE

Wireless CPU

= overall curre nt consumption (Base Band + RF part)

BB+RF

Wireless CPU®

READY

T+CPOF

Network dependent

OK response

Wireless CPU

OFF

Figure 10: Power-OFF sequence

Additional notes:

1 If the ON/~OFF pin is maintained to ON (High Level), then the Wireless

CPU® can’t be switched OFF.

2 Connecting a charger on the Wireless CPU

as exactly the same effect than setting the ON/~OFF signal. In particular the Wireless CPU not POWER-OFF after the AT+CPOF command, unless the Charger is disconnected.

will

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Q2686 Wireless CPU®

3.15 BOOT Signal

A specific BOOT control pin is available to download the Q2686 Wireless CPU® (only if the standard XModem download, controlled with AT command, is not possible).

A specific PC software program, provided by Wavecom, is needed to perform this specific download.

The BOOT pin must be connected to VCC_1V8 for this specific download.

Operating mode description

BOOT Operating mode Comment

Leave open Normal use No download

Leave open Download XModem AT command for Download

AT+WDWL

1 Download specific Need Wavecom PC software

For more information, see Q2686 / Open AT® Software Suite v2 AT Command User Guide [7].

This BOOT pin must be left open either for normal use or XModem download. However, in order to render the development and maintenance phases easier,

it is highly recommended to set a test point, either a jumper or a switch on the VCC_1V8 (pin 5) power supply.

Pin description

Signal Pin number I/O I/O type Description

BOOT 16 I 1V8 Download mode selection

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Q2686 Wireless CPU®

3.16 Reset Signal (~RESET)

This signal is used to force a reset procedure by providing low level for at least 200μs. This signal must be considered as an emergency reset only. A reset procedure is already driven by the internal hardware during the power-up sequence.

This signal may also be used to provide a reset to an external device (at powerup only). If no external reset is necessary, this input may be left open. If used (emergency reset), it must be driven by an open collector or an open drain.

The Wireless CPU low.

remains in reset mode as long as the ~RESET signal is held

CAUTION: This signal should only be used for “emergency” resets. An Operating System reset is to be preferred to a hardware reset. Reset sequence: To activate the "emergency" reset sequence, the ~RESET signal must be set to

low for 200μs minimum. As soon as the reset is completed, the AT interface answers "OK" to the application.

~RESET

STATE OF

THE

Wireless CPU

Wireless

CPU

READY

Rt = Min

or Typ

:200μs

= 40ms

RESET mode

=20 to

BB+RF

40mA

Ct = Typ:34ms

Wireless CPU

<120mA

BB+RF

without loc update

SIM and network

dependent

AT answers “OK”

Wireless CPU®

READY

Figure 11: Reset sequence waveform

At power-up, the ~RESET time (Rt) is carried out after switching ON the Wireless CPU

. It is generated by the internal Q2686 Wireless CPU® voltage

supervisor. The ~RESET time is provided by the internal RC component. To keep the same

time, it is not recommended to connect another R or C component on the ~RESET signal. Only a switch or an open drain gate is recommended.

Ct is the cancellation time required for the Wireless CPU Ct is automatically carried out by the Q2686 Wireless CPU

Q2686 initialization.

after a hardware

reset.

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Electrical characteristics of the signals

Q2686 Wireless CPU®

Parameter Minimum

Input Impedance ( R )*

Input Impedance ( C )

~RESET time (Rt) 1

~RESET time (Rt) 2 at power

100

10n

200

20 40 100

Typ Maximum Unit

up only

Cancellation time (Ct)

VIL

VIH

* internal pull-up

* V

Hysterisis Voltage

1 This reset time is the minimum to be carried out on the ~RESET signal when the power supply is already stabilized.

2 This reset time is internally carried out by the Wireless CPU when the Wireless CPU

power supplies are powered ON.

0.57

0 0.57

1.33

power supply supervisor only

Pin description

kΩ

μs

Signal Pin

I/O I/O type Description

number

~RESET 18 I/O Open Drain

1V8 Wireless CPU®

Reset

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Q2686 Wireless CPU®

3.17 External Interrupt

The Q2686 Wireless CPU® provides two external interrupt inputs. These interrupt inputs can be activated on:

• High to low edge

• Low to high edge

• Low to high and high to low edge

When used, the interrupt inputs must not be left open. If not used, they must be configured as GPIOs.

Pin description

Signal Pin

number

I/O I/O type Reset

state

Description Multiplexed

with

INT1 49 I 2V8 Z External Interrupt GPIO25

INT0 50 I 1V8 Z External Interrupt GPIO3

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage characteristics and Reset state definition.

Electrical characteristics of the signals

Parameter Minimum Maximum Unit

INT1

VIL 0.84

1.96

VIL 0.54

INT0

1.33 V

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Q2686 Wireless CPU®

3.18 VCC_2V8 and VCC_1V8 Output

These outputs can only be used to connect pull-up resistor. VCC_2V8 and VCC_1V8 must be used as a reference supply. These voltages supplies are available when the Wireless CPU

Signal Pin number I/O I/O type Description

VCC_2V8 10 O Supply Digital supply

VCC_1V8 5 O Supply Digital supply

Electrical characteristics of the signals

Parameter Minimum Typ Maximum Unit

is ON.

Pin description

Output voltage

2.74 2.8 2.86 V

VCC_2V8

Output Current

Output voltage

15 mA

1.76 1.8 1.94 V

VCC_1V8

Output Current

15 mA

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Q2686 Wireless CPU®

3.19 BAT-RTC (Backup Battery)

The Q2686 Wireless CPU® provides an input/output to connect a Real Time Clock (RTC) power supply.

3.19.1 Interface Description

This pin is used as a back-up power supply for the internal Real Time Clock. The RTC is supported by the Wireless CPU

when VBATT is available, but a back-up power supply is needed to save date and time when VBATT is switched off (VBATT = 0V).

Q2686

from VBATT

to RTC

2.5V

regulator

1.8V

regulator

BAT-RTC (Pin 7)

Figure 12: Real Time Clock power supply

If the RTC is not used, this pin can be left open. If VBATT is available, the back-up battery can be charged by the internal 2.5V

power supply regulator.

Pin description

Signal Pin number I/O I/O type Description

BAT-RTC 7 I/O Supply RTC Back-up supply

Electrical characteristics of the signals

Parameter Minimum Typ Maximum Unit

Input voltage 1.85 3.0 V

Input current

3.3 μA

consumption*

Output voltage 2.45 V

Output current 2 mA

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*Provided by an RTC back-up battery when Wireless CPU® power supply is off (VBATT = 0V).

Page: 67 / 97

Q2686 Wireless CPU®

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Q2686 Wireless CPU®

3.20 LED0 Signal

LED0 is an open drain output. A LED and a resistor can be directly connected between this output and VBATT.

When the Q2686 Wireless CPU is connected on CHG-IN inputs, this output flashes ( 100 ms ON, 900 ms OFF ) to indicate the pre-charging phase of the battery.

When the Q2686 Wireless CPU status.

is OFF, if 2.8V < VBATT < 3.2V and a charger

is ON, this output is used to indicate network

LED0 status

Q2686 state

CPU

OFF

Wireless

CPU

VBATT status LED0 status Q2686 Wireless CPU®

status

VBATT<2.8V or

OFF Wireless CPU® is OFF Wireless

VBATT> 3.2V

2.8V < VBATT <

3.2V

Pre-charge flash LED ON for 100

ms, OFF for 900 ms

Wireless CPU Pre-charging mode (charger must be

connected on CHG-IN to

is OFF,

activate this mode)

VBATT > 3.2V

Permanent Wireless CPU® switched

ON, not registered on the network

Slow flash LED ON for 200

ms, OFF for 2 s

Quick flash LED ON for 200

ms, OFF for 600 ms

Very quick flash LED ON for

100ms, OFF for 200ms

Wireless CPU ON, registered on the network

Wireless CPU ON, registered on the network, communication in progress

Wireless CPU on, software downloaded is either corrupted or noncompatible ("BAD SOFTWARE")

switched

Pin description

Signal Pin

I/O I/O type Reset state Description

number

LED0 17 O Open Drain

Output

See Chapter 3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage

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characteristics and Reset state definition.

1 and

Undefined

LED driving

Page: 69 / 97

Q2686 Wireless CPU®

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Q2686 Wireless CPU®

Figure 13: LED0 state during RESET and Initialization time

LED0 state is high during the RESET time and undefined during the software initialization time. During software initialization time, for 2 seconds max after RESET cancellation, the LED0 signal is toggling and does not provide Wireless

CPU

status. After the 2s period, the LED0 provides the true status of the

Wireless CPU

Electrical characteristics of the signal

Parameter Condition Minimum Typ Maximum Unit

VOL 0.4 V

IOUT 8 mA

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Q2686 Wireless CPU®

3.21 Digital Audio Interface (PCM)

Digital audio interface (PCM) interface mode allows connectivity with audio standard peripherals. It can be used, for example, to connect an external audio codec.

The programmability of this mode allows to address a large range of audio peripherals.

PCM features:

• IOM-2 compatible device on physical level

• Master mode only with 6 slots by frame, user only on slot 0

• Bit rate single clock mode at 768kHz only

• 16 bits data word MSB first only

• Linear Law only (no compression law)

• Long Frame Synchronization only

• Push-pull configuration on PCM-OUT and PCM-IN

The digital audio interface configuration cannot differ from that specified above.

3.21.1 Description

The PCM interface consists of 4 wires:

• PCM-SYNC (output): The frame synchronization signal delivers an 8 kHz

frequency pulse that synchronizes the frame data in and the frame data out.

• PCM-CLK (output): The frame bit clock signal controls data transfer with

the audio peripheral.

• PCM-OUT (output): The frame “data out” relies on the selected

configuration mode.

• PCM-IN (input): The frame “data in” relies on the selected configuration

mode.

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PCM-SYNC

PCM-CLK

PCM-IN

Q2686 Wireless CPU®

Tsync_high Tsync_low

PCM-OUT

PCM-SYNC

PCM-CLK

PCM-IN

SLOT 5

SLOT 0 SLOT 1 SLOT 5 SLOT 0

Figure 14: PCM frame waveform

TSYNC-CLK

TIN-set up

TIN-hold

TCLK-cycle

SLOT 0 bit 15 SLOT 0 bit 14 SLOT 0 bit 13SLOT 5 bit 0

PCM-OUT

TOUTdelay

SLOT 0 bit 15 SLOT 0 bit 14 SLOT 0 bit 13SLOT 5 bit 0

Figure 15: PCM sampling waveform

Page: 73 / 97

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Q2686 Wireless CPU®

AC characteristics

Signal Description Minimum Typ Maximum Unit

Tsync_low +

PCM-SYNC period 125 μs

Tsync_high

Tsync_low PCM-SYNC low time 93 μs

Tsync_high PCM-SYNC high time 32 μs

TSYNC-CLK PCM-SYNC to PCM-CLK time

-154 ns

TCLK-cycle PCM-CLK period 1302 ns

TIN-setup PCM-IN setup time 50 ns

TIN-hold PCM-IN hold time 50 ns

TOUT-delay PCM-OUT delay time 20 ns

Pin description of the PCM interface

Signal Pin

I/O I/O type Reset state Description

number

PCM-SYNC 77 O 1V8 Pull-down Frame synchronization 8

kHz

PCM-CLK 79 O 1V8 Pull-down Data clock

PCM-OUT 80 O 1V8 Pull-up Data output

PCM-IN* 78 I 1V8 Pull-up Data input

*When using analog audio interface, the PCM_IN signal should be in HZ

See Chapter characteristics and Reset state definition.

3.3, “Electrical information for digital I/O” for Open drain, 2V8 and 1V8 voltage

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Q2686 Wireless CPU®

3.22 USB 2.0 Interface

A 4-wire USB slave interface is available which complies with USB 2.0 protocol signaling. But it is not compliant with the electrical interface, due to the 5V of VPAD-USB.

The USB interface signals are VPAD-USB, USB-DP, USB-DM and GND. USB interface features:

• 12Mbit/s full-speed transfer rate

• 3.3V typ compatible

• USB Softconnect feature

• Download feature is not supported by USB

• CDC 1.1 – ACM compliant

NOTE interface power in line (+5V) and the Wireless CPU

: A 5V to 3.3V typ voltage regulator is needed between the external

line (VPAD-USB).

Pin description of the USB interface

Signal Pin

I/O I/O type Description

number

VPAD-USB 52 I VPAD_USB

USB Power Supply

USB-DP 54 I/O VPAD_USB Differential data interface positive

USB-DM 56 I/O VPAD_USB Differential data interface negative

Electrical characteristics of the signals

Parameter

VPAD-USB, USB-DP, USB-DM

VPAD-USB Input current consumption

Min Typ Max Unit

3 3.3 3.6 V

8 mA

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Q2686 Wireless CPU®

3.23 RF Interface

The impedance is 50 Ω nominal and the DC impedance is 0 Ω.

3.23.1 RF Connections

U.FL Connector

A wide variety of cables fitted with U.FL connectors is offered by different suppliers.

Soldered solution

The soldered solution will preferably be based on an RG178 coaxial cable.

IMP connector

This connector is dedicated to board-to-board applications and must be soldered on the customer board. The supplier is Radiall (reference: R107 064 900).

Notes:

• The Q2686 Wireless CPU

does not support an antenna switch for a car kit, but this function can be implemented externally and can be driven using a GPIO.

• The antenna cable and connector should be selected in order to

minimize losses in the frequency bands used for GSM 850/900MHz and 1800/1900MHz.

• 0.5dB may be considered as the maximum value of loss between the

Wireless CPU

and an external connector.

• For mounting, assembly and handling of the IMP connector, please

contact the supplier, Radiall, directly. Wavecom cannot provide customer support for use of this connector.

3.23.2 RF Performance

RF performance is compliant with the ETSI GSM 05.05 recommendation. The main Receiver parameters are:

• GSM850 Reference Sensitivity = -104 dBm Static & TUHigh

• E-GSM900 Reference Sensitivity = -104 dBm Static & TUHigh

• DCS1800 Reference Sensitivity = -102 dBm Static & TUHigh

• PCS1900 Reference Sensitivity = -102 dBm Static & TUHigh

• Selectivity @ 200 kHz: > +9 dBc

• Selectivity @ 400 kHz: > +41 dBc

• Linear dynamic range: 63 dB

• Co-channel rejection: >= 9 dBc

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Q2686 Wireless CPU®

Transmitter parameters:

• Maximum output power (EGSM & GSM850): 33 dBm +/- 2 dB at ambient

temperature

• Maximum output power (GSM1800 & PCS1900): 30 dBm +/- 2 dB at

ambient temperature

• Minimum output power (EGSM & GSM850): 5 dBm +/- 5 dB at ambient

temperature

• Minimum output power (GSM1800 & PCS1900): 0 dBm +/- 5 dB at

ambient temperature

3.23.3 Antenna Specifications

The antenna must meet the following requirements:

• The optimum operating frequency depends on the application. Either a

dual-band or quad-band antenna will operate in these frequency bands and have the following characteristics:

Q2686

Characteristic

E-GSM 900 DCS 1800 GSM 850 PCS 1900

TX Frequency 880 to

915 MHz

RX Frequency 925 to

960 MHz

Impedance

Rx max 1.5:1

VSWR

Tx max 1.5:1

Typical radiated gain

1710 to

1785 MHz

1805

to 1880 MHz

849 MHz

894 MHz

824 to

869 to

0dBi in one direction at least

1850 to

1910 MHz

1930 to

1990 MHz

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Q2686 Wireless CPU®

4 Technical Specifications

4.1 General Purpose Connector Pin-out Description

Description I/O* Voltage

Power

Supply

Power

Supply

1.8V Supply Output

RTC Battery

connection

SIM Power

Supply

SIM Data I/O

SIM reset

Output

Buzzer Output

LED0

Output

ON / ~OFF

Control

Analog to

Digital Input

SPI1 Clock O VCC_2V8 GPIO28 SPI1-CLK

SPI1 Data

Input /

Output

SPI2 Data

Input /

Output

SPI2 Data

Input

Auxiliary

RS232

Transmit

Auxiliary

RS232

Request To

Send

Speaker 1

Output

Positive

I VBATT

O VCC_1V8 VCC_1V8

BAT-

I/O

I/O VCC_2V8 GPIO29 SPI1-IO

I/O VCC_2V8 GPIO33 SPI2-IO

RTC

1V8 or

O Analog SPK1P

1V8 or

Open Drain

I VBATT ON/~OFF

I Analog ADC2

I VCC_2V8 GPIO34 SPI2-I

I VCC_1V8 GPIO14

I VCC_1V8 GPIO17

Signal Name Signal Name

Mux Nominal

ADC0/

VBATT

ADC0/

VBATT

BAT-RTC

SIM-VCC

SIM-IO

~SIM-

LED0

RST

BUZZER

CT103-

TXD2

~CT105-

RTS2

Number

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

Nominal Mux

ADC0/

VBATT

ADC0/

VBATT

CHG-IN CHG-IN I

VCC_2V8 VCC_2V8 O

SIMPRES GPIO18 VCC_1V8 I

SIM-CLK

BOOT VCC_1V8 I Not Used

~RESET VCC_1V8 I/O RESET Input

BAT-

TEMP

GPIO31 VCC_2V8 I/O

SPI1-I GPIO30 VCC_2V8 I

SPI2-CLK GPIO32 VCC_2V8 O SPI2 Clock

GPIO35 VCC_2V8 I/O

CT104-

RXD2

~CT106-

CTS2

MIC2N Analog I

MIC2P Analog I

GPIO15

GPIO16

Voltage I/O* Description

ADC0/

VBATT

ADC0/

VBATT

1V8 or

Analog I

VCC_1V8 O

2.8V Supply

O SIM Clock

temperature

RS232 Clear

Power

Supply

Power

Supply

Charger

input

Charger

input

Output

SIM

Detection

Analog

SPI1 Data

Input

Auxiliary

RS232

Receive

Auxiliary

To Send

Micro 2

Input

Negative

Micro 2

Input

Positive

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Description I/O* Voltage

Speaker 1

Output

Negative

Speaker 2

Output

Positive

Speaker 2

Output

Negative

I/O VCC_2V8 32kHz GPIO0

I/O VCC_2V8 GPIO19

I/O VCC_2V8 GPIO21

Interruption

1 Input

I/O VCC_1V8 ** GPIO1

I/O VCC_1V8 ** GPIO2

I/O VCC_2V8 ** GPIO23

I/O VCC_2V8 ** GPIO22

Keypad column 0

Keypad column 2

Keypad column 4

Keypad Row 3

Keypad Row 1

Main RS232

Ring

Indicator

Main RS232

Transmit

Main RS232

Receive

Main RS232

Clear To

Send

PCM Frame

Synchro

PCM Clock O VCC_1V8

NC-1

O Analog SPK1N

O Analog SPK2P

O Analog SPK2N

I VCC_2V8 GPIO25 INT1

I/O VCC_1V8 GPIO4 COL0

I/O VCC_1V8 GPIO6 COL2

I/O VCC_1V8 GPIO8 COL4

I/O VCC_1V8 GPIO12 ROW3

I/O VCC_1V8 GPIO10 ROW1

O VCC_2V8 GPIO42

I VCC_2V8 GPIO36

O VCC_2V8 GPIO37

O VCC_2V8 GPIO39

O VCC_1V8

Signal Name Signal Name

Mux Nominal

~CT125-

CT103-

TXD1

CT104-

RXD1

~CT106-

CTS1

PCMSYNC

PCM-

CLK

Number

37 38

39 40

41 42

43 44

45 46

47 48

49 50

51 52

53 54

55 56

57 58

59 60

61 62

63 64

65 66

67 68

69 70

71 72

73 74

75 76

77 78

79 80

81 82

Q2686 Wireless CPU®

Nominal Mux

MIC1N Analog I

MIC1P Analog I

Reserved **

SCL1 GPIO26

SDA1 GPIO27

GPIO20 VCC_2V8 I/O

INT0 GPIO3 VCC_1V8 I

VPAD-

USB

USB-DP

USB-DM

GPIO24 VCC_2V8 I/O

COL1 GPIO5 VCC_1V8 I/O

COL3 GPIO7 VCC_1V8 I/O

ROW4 GPIO13 VCC_1V8 I/O

ROW2 GPIO11 VCC_1V8 I/O

ROW0 GPIO9 VCC_1V8 I/O

~CT109-

DCD1

~CT105-

RTS1

~CT107-

DSR1

~CT108-

2-DTR1

PCM-IN VCC_1V8 I

PCM-

OUT

Reserved

GPIO43

GPIO38

GPIO40

GPIO41

Voltage I/O* Description

Open Drain

VPAD-

VCC_1V8 O

USB

VPAD-

USB

VPAD-

USB

VCC_2V8 O

VCC_2V8 I

VCC_2V8 O

VCC_2V8 I

O I²C Clock

I/O I²C Data

Interruption

supply input

I/O USB Data

Keypad Row

Main RS232 Data Carrier

Main RS232

Micro 1

Input

Negative

Micro 1

Input

Positive

0 Input

USB Power

Keypad

column 1

Keypad

column 3

Detect

Request To

Send

Data Set

Ready

Data

Terminal

Ready

PCM Data

Input

PCM Data

Output

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Description I/O* Voltage

Signal Name Signal Name

Mux Nominal

Number

Nominal Mux

Q2686 Wireless CPU®

Voltage I/O* Description

NC-3

NC-5

NC-7

NC-9

NC-11

NC-13

NC-15

NC-17

NC-19

83 84

85 86

87 88

89 90

91 92

93 94

95 96

97 98

99 100

NC-2

NC-4

NC-6

NC-8

NC-10

NC-12

NC-14

NC-16

NC-18

* The I/O direction information is only for the nominal signal. When the signal is configured in

GPIO, it can always be an Input or an Output.

** For more information about the multiplexing of these signals, see “General purpose

input /output”, section

3.9

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Q2686 Wireless CPU®

4.2 Labeling Correspondence between Q2686 and Open AT® Software Suite v2

Each signal has strictly the same characteristics: It is only a new designation in view to conform with the AT Command User Guide [7].

Signal Name

Q2686 with SW

preceding Open AT®

Software Suite v2

Signal Name

Q2686 with SW

from Open AT®

Software Suite v2

+VBATT ADC0 / +VBATT Possibility to read VBATT

Description I/O PIN

number

I 1,2,2,4

value using the ADC0

BAT-TEMP ADC1/BAT-

TEMP

Possibility to read either the Battery’s temperature

I 20

or something else customer specific

AUX-ADC ADC2 Analog to Digital converter I 21

SCL SCL1 O 44

SDA SDA1 I/O 46

FLASHLED LED0 O 17

~SPI1_CS GPIO31 /

O 22

SPI1 Load

~SPI2_CS GPIO35 /

O 28

SPI2-Load

BUZZ-OUT BUZZER0 O 15

GPIO44 GPIO0 I/O 43

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Q2686 Wireless CPU®

4.3 Environmental Specifications

Wavecom specifies the following temperature range for the Q2686 product. The Q2686 Wireless CPU

Conditions Temperature range

Operating / Class A Operating / Class B -30 °C to +85°C

Storage -40 °C to +85°C

Function Status Classification: Class A: The Wireless CPU

remains fully functional, meeting GSM performance criteria

in accordance with ETSI requirements, across the specified temperature range. Class B: The Wireless CPU

remains fully functional, across the specified temperature range. Some GSM parameters may occasionally deviate from the ETSI specified requirements and this deviation does not affect the ability of the Wireless CPU to connect to the cellular network and function fully, as it does within the Class A range.

is compliant with the following operating class.

-20 °C to +55°C

TYPE OF TEST STANDARDS STORAGE TRANSPORTATION OPERATING (PORT USE)

Change of temperature IEC 68-2.14 -40° / +30° C 5 cycles -20° / +30° C (GSM900) 3 cycles

Sinusoidal vibration IEC 68-2.6 5 - 62 Hz : 5 mm / s

Random vibrati on IEC 68-3.36 20 - 500Hz : - 3 dB / oct 12 - 150Hz : - 3 dB / oct

Q2686 ENVIRONNEMENTAL CLASSES

Class 1.2 Class 2.3 Class 7.3

Cold IEC 68-2.1 -25° C 72 h -40° C 72 h -20° C (GSM900) 16 h

Ab test -10° C (GSM1800/1900) 16h

Dry heat IEC 68-2.2 +70° C 72 h +70° C 72 h +55° C 16 h

Bb test

Na/Nb test t1 = 3 h -10° / +30° C (GSM1800/1900):

3 cycles t1 = 3 h

Damp heat IEC 68-2.30 +30° C 2 cycles +40° C 2 cycles +40° C 2 cycles

cyclic Db test 90% - 100% RH 90% - 100% RH 90% - 100% RH

variant 1 variant 1 variant 1

Damp heat IEC 68-2.56 +30° C 4 days +40° C 4 days +40° C 4 days

Cb test

Fc test 62 - 200Hz : 2 m / s2

3 x 5 sweep cycles

5 - 20 Hz : 0.96 m2 / s3 10 -12 Hz : 0.96 m2 / s3

wide band Fdb t est 3 x 10 min 3 x 30 min

Figure 16: Environmental classes

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Q2686 Wireless CPU®

4.4 Conformance with ATEX 94/9/CE directive

To evaluate the conformity of the final product with ATEX 94/9/CE directive the following datas must be taken into account:

• Sum of all capacitors : 84μF

• Sum of all inductances : 12μH

4.5 Mechanical Specifications

4.5.1 Physical Characteristics

The Q2686 Wireless CPU® has a complete self-contained shield.

• Overall dimensions : 32.2x40x4 mm (except shielding pins)

• Weight : <10 g

4.5.2 Mechanical Drawings

The mechanical specifications of the Q2686 Wireless CPU® are shown in the following page.

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Q2686 Wireless CPU®

Figure 17: Mechanical drawing

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Q2686 Wireless CPU®

5 Connector and Peripheral Device References

5.1 General Purpose Connector

The GPC is a 100-pin connector with 0.5mm pitch from the from PANASONIC Group's P5K series, with the following reference:

AXK600347BN1 The matting connector has the following reference: AXK500147BN1J The stacking height is 3.0 mm. Wavecom recommends that you use the AXK500147BN1J connector for your

application to benefit from Wavecom’s prices. For more information, contact Wavecom, specifying the Wavecom connector reference: WM18868.

For further details see the GPC data sheets in the appendix. More information is also available from

http://www.panasonic.com/host/industrl.html

5.2 SIM Card Reader

• ITT CANNON CCM03 series (see http://www.ittcannon.com )

• AMPHENOL C707 series (see http://www.amphenol.com )

• JAE (see http://www.jae.com )

• MOLEX 99228-0002 (connector) / MOLEX 91236-0002 (holder) (see

http://www.molex.com)

5.3 Microphone

Possible suppliers:

• HOSIDEN

• PANASONIC

• PEIKER

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Q2686 Wireless CPU®

5.4 Speaker

Possible suppliers:

• SANYO

• HOSIDEN

• PRIMO

• PHILIPS

5.5 Antenna Cable

A wide variety of cables fitted with UF-L connectors is offered by HIROSE:

 UF-L pigtails, Ex: Ref = U.FL-2LP(V)-04-A-(100)

 UF-L Ref = U.FL-R-SMT  UF-L cable assemblies,  Between series cable assemblies.

More information is also available from A coaxial cable can also be soldered on the RF pad. The following references

have been certified for mounting on the Q2686 Wireless CPU

http://www.hirose-connectors.com/.

• RG178

• RG316

5.6 RF Board-to-board Connector

The supplier for the IMP connector is Radiall (http://www.radiall.com), with the following reference:

• R107 064 900.

5.7 GSM Antenna

GSM antennas and support for antenna adaptation can be obtained from manufacturers such as:

• ALLGON (http://www.allgon.com )

• IRSCHMANN (http://www.hirschmann.com/ )

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Q2686 Wireless CPU®

6 Design Guidelines

The purpose of the following paragraphs is to give design guidelines.

6.1 HARDWARE and RF

6.1.1 EMC Recommendations

The EMC tests must be performed on the application as soon as possible to detect any potential problems.

When designing, special attention should be paid to:

• Possible spurious emission radiated by the application to the RF receiver

in the receiver band

• ESD protection is mandatory on all signals which have external

accessibility (typically human accessibility). See Q2686 Wireless CPU Customer Design Guidelines WM_PRJ_Q2686_PTS_003

[10] for ESD

protection samples.

o Typically, ESD protection is mandatory for the:

 SIM (if accessible from outside)  Serial link

• EMC protection on audio input/output (filters against 900MHz

emissions)

• Biasing of the microphone inputs

• Length of the SIM interface lines (preferably <10cm)

• Ground plane: Wavecom recommends a common ground plane for

analog/digital/RF grounds.

• A metallic case or plastic casing with conductive paint are recommended

Note

The Wireless CPU

does not include any protection against over-voltage.

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Q2686 Wireless CPU®

6.1.2 Power Supply

The power supply is one of the key issues in the design of a GSM terminal. A weak power supply design could, in particular, affect:

• EMC performance

• The emission spectrum

• The phase error and frequency error

WARNING: Careful attention should be paid to:

• The quality of the power supply: low ripple, PFM or PSM systems should

be avoided (PWM converter preferred).

• Capacity to deliver high current peaks in a short time (pulsed radio

emission).

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6.1.3 Layout Requirement

Q2686 Wireless CPU®

Figure 18: Layout requirement

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Q2686 Wireless CPU®

6.1.4 Antenna

WARNING: Wavecom strongly recommends working with an antenna manufacturer either

to develop an antenna adapted to the application or to adapt an existing solution to the application.

Both the mechanical and electrical antenna adaptation is one of the key issues in the design of the GSM terminal.

6.2 Mechanical Integration

Attention should be paid to:

• Antenna cable integration (bending, length, position, etc)

• Leads of the Wireless CPU

to be soldered to the Ground plane

6.3 Operating System Upgrade

The Q2686 Wireless CPU® Operating System is stored in flash memory and can easily be upgraded.

IMPORTANT:

In order to follow regular changes in the GPRS standard and to offer a state-ofthe-art Operating System, Wavecom recommends that the application designed around a Wireless CPU® (or Wireless CPU® based product) allow easy Operating System upgrades on the Wireless CPU® via the standard X-modem protocol. Therefore, the application shall either allow a direct access to the Wireless CPU® serial link through an external connector or implement any mechanism allowing the Wireless CPU® Operating System to be downloaded via X-modem.

The Operating System file can be downloaded to the modem using the Xmodem protocol. The AT+WDWL command allows the download process to be launched (see the description in the AT Command User Guide

[7]). The serial signals required to proceed with X-modem downloading are: Rx, Tx, RTS, CTS and GND. The Operating System file can also be downloaded to the modem using the

DOTA (download over the air) feature. This feature is available with the Open

interface. For more details, please, refer to the Open AT® documentation

listed in section

1.1.1.

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Q2686 Wireless CPU®

7 Appendix

7.1 Standards and Recommendations

GSM ETSI, 3GPP, GCF and NAPRD03 recommendations for Phase II & FCC.

Specification Reference Title

3GPP TS 45.005 v5.5.0 (2002-08) Release 5

GSM 02.07 V8.0.0 (1999-07)

GSM 02.60 V8.1.0 (1999-07)

GSM 03.60 V7.9.0 (2002-09)

3GPP TS 43.064 V5.0.0 (2002-04)

3GPP TS 03.22 V8.7.0 (2002-08)

Technical Specification Group GSM/EDGE. Radio Access Network; Radio transmission and reception

Digital cellular telecommunications system (Phase 2+); Mobile Stations (MS) features (GSM 02.07

version 8.0.0 Release 1999)

Digital cellular telecommunications system (Phase 2+); General Packet Radio Service (GPRS);

Service description, Stage 1 (GSM 02.60 version 8.1.0 Release 1999)

Technical Specification Group Services and System Aspects;

Digital cellular telecommunications system (Phase 2+); General Packet Radio Service (GPRS); Service description; Stage 2 (Release 1998)

Technical Specification Group GERAN; Digital cellular telecommunications system (Phase 2+); General Packet Radio Service (GPRS); Overall description of the GPRS radio interface; Stage 2 (Release 5)

Technical Specification Group GSM/EDGE. Radio Access Network; Functions related to Mobile Station (MS) in idle mode and group receive mode; (Release 1999)

3GPP TS 03.40 V7.5.0 (2001-12)

3GPP TS 03.41 V7.4.0 (2000-09)

Technical Specification Group Terminals; Technical realization of the Short Message Service (SMS) (Release 1998)

Technical Specification Group Terminals; Technical realization of Cell Broadcast Service (CBS) (Release 1998)

ETSI EN 300 903 V8.1.1 (2000-11)

Digital cellular telecommunications system (Phase 2+); Transmission planning aspects of the speech service in the

GSM Public Land Mobile Network (PLMN) system

(GSM 03.50 version 8.1.1 Release 1999)

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Specification Reference Title 3GPP TS 04.06 V8.2.1

(2002-05)

Technical Specification Group GSM/EDGE Radio Access Network; Mobile Station - Base Station System (MS - BSS) interface; Data Link (DL) layer specification (Release 1999)

Q2686 Wireless CPU®

3GPP TS 04.08 V7.18.0 (2002-09)

3GPP TS 04.10 V7.1.0 (2001-12)

3GPP TS 04.11 V7.1.0 (2000-09)

3GPP TS 45.005 v5.5.0 (2002-08)

3GPP TS 45.008 V5.8.0 (2002-08)

3GPP TS 45.010 V5.1.0 (2002-08)

Technical Specification Group Core Network; Digital cellular telecommunications system (Phase 2+); Mobile radio interface layer 3 specification (Release

1998)

Technical Specification Group Core Networks; Mobile radio interface layer 3 Supplementary services

specification; General aspects (Release 1998)

Technical Specification Group Core Network; Digital cellular telecommunications system (Phase 2+); Point-to-Point (PP) Short Message Service (SMS) support on mobile radio interface

(Release 1998)

Technical Specification Group GSM/EDGE. Radio Access Network; Radio transmission and reception (Release 5)

Technical Specification Group GSM/EDGE Radio Access Network; Radio subsystem link control

(Release 5)

Technical Specification Group GSM/EDGE Radio Access Network; Radio subsystem

synchronization (Release 5)

3GPP TS 46.010 V5.0.0 (2002-06)

Technical Specification Group Services and System Aspects;

Full rate speech; Transcoding (Release 5)

3GPP TS 46.011 V5.0.0 (2002-06)

Technical Specification Group Services and System Aspects;

Full rate speech; Substitution and muting of lost frames for

full rate speech channels (Release 5)

3GPP TS 46.012 V5.0.0 (2002-06)

Technical Specification Group Services and System Aspects;

Full rate speech; Comfort noise aspect for full rate speech traffic channels (Release 5)

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Specification Reference Title 3GPP TS 46.031 V5.0.0

(2002-06)

Technical Specification Group Services and System Aspects;

Full rate speech; Discontinuous Transmission (DTX) for full rate speech traffic channels (Release 5)

Q2686 Wireless CPU®

3GPP TS 46.032 V5.0.0 (2002-06)

TS 100 913V8.0.0 (1999-08)

GSM 09.07 V8.0.0 (1999-08)

3GPP TS 51.010-1 v5.0.0 (2002-09)

3GPP TS 51.011 V5.0.0 (2001-12)

Technical Specification Group Services and System Aspects;

Full rate speech; Voice Activity Detector (VAD) for full rate speech traffic channels (Release 5)

Digital cellular telecommunications system (Phase 2+); General on Terminal Adaptation Functions (TAF) for

Mobile Stations (MS) (GSM 07.01 version 8.0.0 Release 1999)

Digital cellular telecommunications system (Phase 2+); General requirements on interworking between the

Public Land Mobile Network (PLMN) and the Integrated Services Digital Network (ISDN) or Public Switched Telephone Network (PSTN) (GSM 09.07 version 8.0.0 Release 1999)

Technical Specification Group GSM/EDGE ; Radio Access Network ;Digital cellular telecommunications system (Phase 2+);Mobile Station (MS) conformance specification; Part 1: Conformance specification (Release 5)

Technical Specification Group Terminals; Specification of the Subscriber Identity Module - Mobile Equipment (SIM - ME) interface (Release 5)

ETS 300 641 (1998-03)

Digital cellular telecommunications system (Phase 2); Specification of the 3 volt Subscriber Identity Module -

Mobile Equipment (SIM-ME) interface (GSM 11.12 version 4.3.1)

GCF-CC V3.7.1 (2002-08) Global Certification Forum – Certification criteria

NAPRD03 V2.6.0 (2002-06) North America Permanent Reference Document for

PTCRB tests

The Q2686 Wireless CPU® connected on a development kit board application is certified to be in accordance with the following Rules and Regulations of the Federal Communications Commission (FCC).

Power listed on the Gant is conducted for Part 22 and conducted for Part 24

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Q2686 Wireless CPU®

This device contains GSM, GPRS Class 10 functions in the 900 and 1800MHz Band, which are not operational in U.S. Territories.

This device is to be used only for mobile and fixed applications. The antenna(s) used for this transmitter must be installed to provide a separation distance of at least 20cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter.

Users and installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF exposure compliance.

Antennas used for this OEM module must not exceed 3.0dBi gain for PCS 1900 MHz and 7.4dBi GSM 850 MHz for mobile and fixed operating configurations. This device is approved as a module to be installed in other devices.

Installed in other portable devices, the exposure conditions require a separate equipment authorization.

The license module had a FCC ID label on the module itself. The FCC ID label must be visible through a window or it must be visible when an access panel, door or cover is easily removed.

If not, a second label must be placed on the outside of the device that contains the following text: Contains FCC ID: O9E-Q2686

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1)

this device may not cause harmful interference,

(2)

this device must accept any interference received, including

interference that may cause undesired operation.

IMPORTANT: Wireless CPU

Manufacturers of mobile or fixed devices incorporating Q2686

are advised to

• clarify any regulatory questions,

• have their completed product tested,

• have product approved for FCC compliance, and

• include instructions according to above mentioned RF exposure

statements in end product user manual.

Please note that changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.

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Q2686 Wireless CPU®

7.2 Safety Recommendations (for information only)

IMPORTANT

FOR THE EFFICIENT AND SAFE OPERATION OF YOUR GSM APPLICATION

BASED ON Q2686

Wireless CPU

PLEASE READ THIS INFORMATION CAREFULLY

7.2.1 RF Safety

7.2.1.1 General

Your GSM terminal is based on the GSM standard for cellular technology. The GSM standard is spread all over the world. It covers Europe, Asia and some parts of America and Africa. This is the most used telecommunication standard.

Your GSM terminal is actually a low power radio transmitter and receiver. It sends out as well as receives radio frequency energy. When you use your GSM application, the cellular system which handles your calls controls both the radio frequency and the power level of your cellular modem.

7.2.1.2 Exposure to RF Energy

There has been some public concern on possible health effects of using GSM terminals. Although research on health effects from RF energy has focused on the current RF technology for many years, scientists have begun research regarding newer radio technologies, such as GSM. After existing research had been reviewed, and after compliance to all applicable safety standards had been tested, it has been concluded that the product was fitted for use.

If you are concerned about exposure to RF energy there are things you can do to minimize exposure. Obviously, limiting the duration of your calls will reduce your exposure to RF energy. In addition, you can reduce RF exposure by operating your cellular terminal efficiently by following the guidelines below.

7.2.1.3 Efficient Terminal Operation

For your GSM terminal to operate at the lowest power level, consistent with satisfactory call quality:

If your terminal has an extendable antenna, extend it fully. Some models allow you to place a call with the antenna retracted. However your GSM terminal operates more efficiently with the antenna when it is fully extended.

Do not hold the antenna when the terminal is "IN USE". Holding the antenna affects call quality and may cause the modem to operate at a higher power level than needed.

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Q2686 Wireless CPU®

7.2.1.4 Antenna Care and Replacement

Do not use the GSM terminal with a damaged antenna. If a damaged antenna comes into contact with the skin, a minor burn may result. Replace a damaged antenna immediately. You may repair antenna to yourself by following the instructions provided to you. If so, use only a manufacturer-approved antenna. Otherwise, have your antenna repaired by a qualified technician.

Buy or replace the antenna only from the approved suppliers list. Using of unauthorized antennas, modifications or attachments could damage the terminal and may violate local RF emission regulations or invalidate type approval.

7.2.2 General Safety

7.2.2.1 Driving

Check the laws and the regulations regarding the use of cellular devices in the area where you have to drive as you always have to comply with them. When using your GSM terminal while driving, please:

• give full attention to driving,

• pull-off from the road and park before making or answering a call if

driving conditions so require.

7.2.2.2 Electronic Devices

Most electronic equipment, for example in hospitals and motor vehicles is shielded from RF energy. However, RF energy may affect some improperly shielded electronic equipment.

7.2.2.3 Vehicle Electronic Equipment

Check your vehicle manufacturer representative to determine if any on-board electronic equipment is adequately shielded from RF energy.

7.2.2.4 Medical Electronic Equipment

Consult the manufacturer of any personal medical devices (such as pacemakers, hearing aids, etc) to determine if they are adequately shielded from external RF energy.

Turn your terminal OFF in health care facilities when any regulations posted in the area instruct you to do so. Hospitals or health care facilities may be using RF monitoring equipment.

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Q2686 Wireless CPU®

7.2.2.5 Aircraft

Turn your terminal OFF before boarding any aircraft.

• Use it on the ground only with crew permission.

• Do not use it in the air.

To prevent possible interference with aircraft systems, Federal Aviation Administration (FAA) regulations require you should have prior permission from a crew member to use your terminal while the aircraft is on the ground. In order to prevent interference with cellular systems, local RF regulations prohibit using your modem while airborne.

7.2.2.6 Children

Do not allow children to play with your GSM terminal. It is not a toy. Children could hurt themselves or others (by poking themselves or others in the eye with the antenna, for example). Children could damage the modem, or make calls that increase your modem bills.

7.2.2.7 Blasting Areas

To avoid interfering with blasting operations, turn your unit OFF when you are in a "blasting area" or in areas posted: "turn off two-way radio". Construction crew often uses remote control RF devices to set off explosives

7.2.2.8 Potentially Explosive Atmospheres

Turn your terminal OFF when in any area with a potentially explosive atmosphere. Though it is rare, but your modem or its accessories could generate sparks. Sparks in such areas could cause an explosion or fire resulting in bodily injuries or even death.

Areas with a potentially explosive atmosphere are often, but not always, clearly marked. They include fuelling areas such as petrol stations; below decks on boats; fuel or chemical transfer or storage facilities; and areas where the air contains chemicals or particles, such as grain, dust, or metal powders.

Do not transport or store flammable gas, liquid, or explosives, in the compartment of your vehicle which contains your terminal or accessories.

Before using your terminal in a vehicle powered by liquefied petroleum gas (such as propane or butane) ensure that the vehicle complies with the relevant fire and safety regulations of the country in which the vehicle is used.

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WAVECOM S.A. : 3 esplanade du Foncet - 92442 Issy-les-Moulineaux - France - Tel: +33 1 46 29 08 00 - Fax: +33 1 46 29 08 08 Wavecom, Inc: 430 Davis Drive, Suite 300 Research Triangle Park, North Carolina, USA - Tel: +1 919 237 4000 - Fax: +1 919 237 4140 WAVECOM Asia-Pacific: Unit 201-207, 2nd Floor, Bio-Informatics Centre No. 2 Science Park West Avenue, Hong Kong Science Park, Shatin, New Territories, Hong Kong (PRC) - Tel: +852-2824 0254 - Fax: +852-2824 0255 [Online contact details, GPS and maps]

Sierra Wireless Q2686 Installation guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1 References

1.1 Reference Documents

1.1.2 AT Software Documentation

1.1.3 Hardware Documents

1.1.4 Other Wavecom Documents

1.1.5 General Reference Documents

1.2 List of Abbreviations

2 General Description

2.1 General Information

2.1.1 Overall Dimensions

2.1.2 Environment and Mechanics

2.1.3 GSM/GPRS Features

2.1.4 Interfaces

2.1.5 Operating System

2.1.6 Connection Interfaces

2.2 Functional Architecture

2.2.1 RF Functionalities

2.2.2 Baseband Functionalities

2.3 Operating System

3 Interfaces

3.1 General Purpose Connector (GPC)

3.2 Power Supply

3.2.1 Power Supply Description

3.2.2 Power Consumption

3.2.2.1 Start-up Current

Power consumption without Open AT® processing

3.2.2.4 Consumption Waveform Samples

3.2.2.5 Power Supply Pin-out

3.3 Electrical Information for Digital I/O

3.4 Serial interface

3.4.1 SPI Bus

3.4.1.1 Characteristics

3.4.1.2 SPI configuration

3.4.1.3 SPI waveforms

3.4.1.4 SPI1 Bus: Pins description

3.4.1.5 SPI2 Bus: Pins description

3.4.2 I2C Bus

3.4.2.1 I²C Waveforms

3.4.2.2 I²C Bus Pin-out

3.5 Keyboard Interface

3.6 Main Serial Link (UART1)

3.7 Auxiliary Serial Link (UART2)

3.8 SIM Interface

3.8.1 General Description

3.9 General Purpose Input/Output

3.10 Analog to Digital Converter

3.11 Analog Audio Interface

3.11.1 Microphone Features

3.11.1.1 MIC1 Microphone Inputs

3.11.1.2 MIC2 Microphone Inputs

3.11.2 Speaker Features

3.11.2.1 Speakers Outputs Power

3.11.3 Pin description

3.12 Buzzer Output

3.13 Battery Charging Interface

3.13.1 Ni-Cd / Ni-Mh Charging Algorithm

3.13.2 Li-Ion Charging Algorithm

3.13.3 Pre-charging

3.13.4 Temperature Monitoring

3.14 ON / ~OFF signal

3.14.1 Operating Sequences

3.14.1.1 Power-ON

3.14.1.2 Power-OFF

3.15 BOOT Signal

3.16 Reset Signal (~RESET)

3.17 External Interrupt

3.18 VCC_2V8 and VCC_1V8 Output

3.19 BAT-RTC (Backup Battery)

3.19.1 Interface Description

3.20 LED0 Signal

3.21 Digital Audio Interface (PCM)

3.21.1 Description

3.22 USB 2.0 Interface

3.23 RF Interface

3.23.1 RF Connections

3.23.2 RF Performance