Siemens PSB4860 Datasheet

ICs for Communications

Digital Answering Machine with Full Duplex Speakerphone
SAM EC

PSB 4860 Version 2.1

Data Sheet 10.97

DS 1

PSB 4860
Revision History: Current Version: 10.97

Previous Version: Preliminary Data Sheet 09.97
Page

(in previous
Version)

Page
(in new
Version)

Subjects (major changes since last revision)

Index added

Edition 10.97



This edition was realized using the software system FrameMaker

Published by Siemens AG,
HL TS

.

© Siemens AG 1997.

All Rights Reserved.
Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and c irc uit s imp lemented within components or as s em blies.

The information describe s the t yp e of co m ponent and shall not be considered as ass ured characteristics.
Terms of delivery and rights to ch ange design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or

the Siemens Companies and R epresentatives worldwide (see address list).
Due to technical requireme nt s com ponents may contain dangerous substances. For informatio n on t he t y pes in

question please contact yo ur nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling ope rat ors k now n t o y ou. W e ca n als o help you – get in touch with your nearest sa les
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
systems

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

2 Life support devices or system s are int ended (a) to be implanted in the human body, or (b) to support and/or

2

with the express written approv al of the Semiconductor Group of Siemens AG.

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.

maintain and sustain human life. If th ey fail, it is rea so nable to assume that the health of the us er m ay be en­dangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-s upport devices or

PSB 4860

Table of Contents Page

1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.4 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.5 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.6 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.6.1 Analog Featurephone with Digital Answering Machine . . . . . . . . . . . . . . .19

1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal . . . . . .21

1.6.3 DECT Basestation with Integrated Digital Answering Machine . . . . . . . . .22

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

2.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.1.1 Full Duplex Speakerphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

2.1.2 Echo Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.1.3 Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.1.4 Line Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

2.1.5 DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

2.1.6 CNG Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

2.1.7 Alert Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

2.1.8 CPT Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

2.1.9 Caller ID Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

2.1.10 DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.1.11 Speech Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

2.1.12 Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.1.13 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

2.1.14 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.1.15 Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.1.16 Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.1.17 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

2.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

2.2.1 File Definition and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

2.2.2 User Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

2.2.3 High Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . .67

2.2.4 Low Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . . .75

2.2.5 Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

2.2.6 Special Notes on File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

2.3 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.3.1 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.3.2 SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.3.3 Reset and Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.3.4 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

2.3.5 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

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Table of Contents Page

2.3.6 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

2.3.7 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

2.3.8 Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

2.3.9 Clock Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

2.3.10 Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

2.4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

®

2.4.1 IOM

2.4.2 SSDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

2.4.3 Analog Front End Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

2.4.4 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

2.4.5 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

2.4.6 Auxiliary Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

3 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

3.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

3.2 Hardware Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

3.3 Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

3.3.1 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

3.3.2 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

4.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

4.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

)

IOM®, IOM®-1, IOM®-2, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC, SLICOFI®, ARCOFI
ARCOFI
SICAT

DigiTape

Semiconductor Group 4 10.97

®

-SP, EPIC®-1, EPIC®-S, ELIC®, IPAT®-2, ITAC®, ISAC®-S, ISAC®-S TE, ISAC®-P, ISAC®-P TE, IDEC®,

®

, OCTAT®-P, QUAT®-S are registered trademarks of S iem ens AG .

™

, MUSAC™-A, FALC™54, IWE™, SARE™, UTPT™, ASM™, ASP™ are trademarks of Siemens AG.

®

, ARCOFI®-BA,

PSB 4860

List of Figures Page
General

Figure 1: Pin Configuration of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2: Logic Symbol of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3: Block Diagram of PSB 4860. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4: Analog Full Duplex Speakerphone with Digital Answering Machine . . . . 20

Figure 5: Featurephone with Answering Machine for ISDN Terminal . . . . . . . . . . . 21

Figure 6: DECT Basestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Functional Units

Figure 7: Functional Units - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 8: Functional Units - Recording a Phone Conversation . . . . . . . . . . . . . . . . 25

Figure 9: Functional Units - Simultaneous Internal and External Call . . . . . . . . . . . 26

Figure 10: Speakerphone - Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11: Speakerphone - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12: Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 13: Echo Cancellation Unit - Typical Room Impulse Response . . . . . . . . . . . 29

Figure 14: Echo Suppression Unit - States of Operation. . . . . . . . . . . . . . . . . . . . . . 30

Figure 15: Echo Suppression Unit - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . 31

Figure 16: Speech Detector - Signal Flow Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 17: Speech Comparator - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18: Speech Comparator - Interdependence of Parameters . . . . . . . . . . . . . . 36

Figure 19: Echo Suppression Unit - Automatic Gain Control. . . . . . . . . . . . . . . . . . . 39

Figure 20: Line Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . 42

Figure 21: DTMF Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22: CNG Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23: Alert Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 24: CPT Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 25: CPT Detector - Cooked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 26: Caller ID Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 27: DTMF Generator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 28: Speech Coder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 29: Speech Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30: Analog Front End Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . 55

Figure 31: Digital Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 32: Universal Attenuator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 33: Automatic Gain Control Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . 59

Figure 34: Equalizer - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Memory Management

Figure 35: Memory Management - Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 36: Memory Management - Directory Structure . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 37: Audio File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 38: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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List of Figures Page

Figure 39: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Miscellaneous

Figure 40: Operation Modes - State Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Interfaces

®-2

Figure 41: IOM
Figure 42: IOM
Figure 43: IOM
Figure 44: IOM

Figure 45: SSDI Interface - Transmitter Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 46: SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47: SSDI Interface - Receiver Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 48: Analog Front End Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . 92

Figure 49: Analog Front End Interface - Frame Start . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 50: Analog Front End Interface - Data Transfer . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 51: Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 52: Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 53: Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 54: Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 55: Configuration Register Write Access or Register Read Command . . . . . 96

Figure 56: ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . 99

Figure 57: ARAM/DRAM Interface - Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . 100

Figure 58: ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . 101

Figure 59: ARAM/DRAM Interface - Refresh Cycle Timing. . . . . . . . . . . . . . . . . . . 101

Figure 60: EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 61: EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 62: Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . 103

Figure 63: Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . 104

Figure 64: Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . 105

Figure 65: Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 66: Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 67: Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 68: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 108

Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

®

-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

®

-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

®

-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Electrical Characteristics

Figure 69: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Timing Diagrams

Figure 70: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

®

Figure 71: SSDI/IOM
Figure 72: SSDI/IOM

-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . 232

®

-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . 232

Figure 73: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

Semiconductor Group 6 10.97

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List of Figures Page

Figure 74: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 75: Analog Front End Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 76: Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 77: Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 78: Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 79: Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 80: Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . 241

Figure 81: Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . 242

Figure 82: Memory Interface - Samsung Data Write . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 83: Memory Interface - Samsung Data Read. . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 84: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 85: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Semiconductor Group 7 10.97

PSB 4860

List of Tables Page
General

Table 1: Pin Definitions and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Functional Units

Table 2: Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 3: Echo Cancellation Unit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 4: Speech Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 5: Speech Comparator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 6: Attenuation Control Unit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 7: SPS Output Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 8: Automatic Gain Control Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 9: Fixed Gain Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 10: Speakerphone Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 11: Line Echo Cancellation Unit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12: DTMF Detector Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 13: DTMF Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 14: DTMF Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 15: CNG Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 16: CNG Detector Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 17: Alert Tone Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 18: Alert Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 19: CPT Detector Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 20: CPT Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 21: Caller ID Decoder Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 22: Caller ID Decoder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 23: Caller ID Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 24: DTMF Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 25: Speech Coder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 26: Speech Coder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 27: Speech Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 28: Analog Front End Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 29: Digital Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 30: Universal Attenuator Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 31: Automatic Gain Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 32: Equalizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Memory Management - General

Table 33: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 34: Memory Management Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 35: Memory Management Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Memory Management - Commands

Table 36: Initialize Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Semiconductor Group 8 10.97

PSB 4860

Table 37: Initialize Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 38: Activate Memory Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 39: Activate Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 40: Activate Memory Result Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 41: Open File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 42: Open Next Free File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 43: Open Next Free File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 44: Seek Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 45: Cut File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 46: Compress File Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 47: Memory Status Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 48: Memory Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 49: Garbage Collection Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 50: Access File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 51: Access File Descriptor Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 52: Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 53: Read Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 54: Write Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 55: Set Address Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 56: DMA Read Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 57: DMA Read Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 58: DMA Write Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 59: Block Erase Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 60: Execution Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Miscellaneous

Table 61: Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 62: SPS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 63: Power Down Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 64: Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 65: Hardware Configuration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 66: Frame Synchronization Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 67: Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 68: File Command Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 69: Module Weights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Interfaces

®

Table 70: SSDI vs. IOM

®

Table 71: IOM

-2 Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 72: SSDI Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 73: Control of ALS Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 74: Analog Front End Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Table 75: Analog Front End Interface Clock Cycles. . . . . . . . . . . . . . . . . . . . . . . . . .93

Semiconductor Group 9 10.97

PSB 4860

Table 76: Command Words for Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Table 77: Address Field W for Configuration Register Write . . . . . . . . . . . . . . . . . . .97

Table 78: Address Field R for Configuration Register Read . . . . . . . . . . . . . . . . . . .97

Table 79: Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Table 80: Address Line Usage (ARAM/DRAM Mode) . . . . . . . . . . . . . . . . . . . . . . .100

Table 81: Refresh Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Table 82: Address Line Usage (Samsung Mode). . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 83: Flash Memory Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 84: Static Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 85: Multiplex Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 86: Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Electrical Characteristics

Table 87: Status Register Update Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

Semiconductor Group 10 10.97

PSB 4860

Overview

1Overview

General
General

Combined with an anal og front end th e PSB 4860 provide s a s olution for embe dde d or
stand alone answering ma chine applica tions. Together wi th a standard microcont roller
for analog telephones these two chi ps form the co re of a featurep hone with fu ll duplex
speakerphone and answering machine capabilities.

™

The chip features recording by DigiTape
Messages recorded with DigiTape

™

can be played back with variable speed without
pitch alteration. Messages recorded with a higher bitrate can be converted into
messages with a lower b itrate arbitrarily. Current m embers of DigiTape (TM) span the
range from 3.3 kbit/s to 10.3 kbit/s.

Furthermore the PSB 4860, V2.1 has a full duplex s peakerphone, a caller ID dec oder,
DTMF recognition and generation and call progress tone detection. The frequency
response of cheap m icro phones or lou dspeak ers can be correct ed by a programma ble
equalizer.

, a family of high performance algorithms.

Messages and user da ta can be stored in ARAM/DRAM or flash mem ory wh ich can be
directly connected to the PSB 4860. The PSB 4860 also supports a voice prompt
EPROM for fixed announcements.

®

The PSB 4860 provides an IOM

-2 compatible inte rface with t wo channels f or speech

data.
Alternatively to the IOM

®

-2 compatible interface the PSB 4 860 su pport s a si mple se rial
data interface (SSDI) with separate strobe sign als for each direction (linear PCM data,
one channel).

A separate interface is used for a glueless connection to the PSB 4851.
The chip is programmed by a simple four wire serial control interface and can inform the

microcontroller of new events by an interrupt sign al. For data retention the PSB 4860
supports a power down mode where only the real time clock and the memory refresh (in
case of ARAM/DRAM) are operational.

The PSB 4860 supports interface pins to +5 V levels.

Semiconductor Group 11 10.97

Digital Answering Machine with Full Duplex

PSB 4860
Speakerphone
SAM EC

Version 2.1 CMOS

1.1 Features

Digital Functions

• High performance recording by DigiTape

• Selectable compression rate (3.3 kbit/s, 10.3 kbit/s)

• Variable playback speed

• Support for ARAM or Flash Memory

• Optional voice prompt EPROM

• Full duplex speakerphone

• DTMF generation and detection

• Call progress tone detection

• Caller ID recognition

• Direct memory access

• Real time clock

• Equalizer

• Automatic gain control

• Automatic timestamp

• Auxiliary parallel port

• Ultra low power refresh mode

™

P-MQFP-80

General Features

®

• SSDI/IOM

-2 compatible interface

• Serial control interface for programming

Type Package

PSB 4860 P-MQFP-80

Semiconductor Group 12 10.97

1.2 Pin Configuration

(top view)

PSB 4860

Overview

V

MA
MA
MA
MA

V

MA

MA
MA
MA

V

MA
MA
MA
MA

RST

V

DD

V

SS

DD

10
11

V

SS

DD

12
13
14
15

V

SS

DDP

1MD2

3

MD

MD0V

DDP

VSSV

SS

VDDV

SS

MA3MA2MA1MA0MD7MD

RO

6

SS

MD5MD4MD

VDDV

4160 50

V

61

4
5
6
7

40

SS

V

DD

SPS

1

SPS

0

CAS1/FCS
CAS0/ALE
RAS

/FOE

/FCLE

8
9

70

SAM EC

PSB 4860

30

VPRD
W

/FWE

FRDY

V

SS

V

DD

DRST
DXST
DD/DR
DU/DX
DCL
FSC

V

SS

V

80

21

DD

110 20

DDA

V

XTAL1XTAL

2

SSA

V

OSC1OSC

2

V

DD

SS

V

INT

CLK

SDR

SDX

SCLK

CS

V

DD

SS

V

AFEFS

AFEDD

AFEDU

AFECLK

Figure 1 Pin Configuration of PSB 4860

Semiconductor Group 13 10.97

1.3 Pin Definitions and Functions

Table 1 Pin Definitions and Functions

PSB 4860

Overview

Pin No.

P-MQFP-80

41, 80

Symbol Dir. Reset Function

V

DDP

-- Power supply (5V %)

10±

Power supply for the interface.

7, 15, 21,
29, 39, 49,

V

DD

-- Power supply (3.0 V - 3.6 V)
Power supply for logic.

58, 61, 67,
73

1

V

DDA

-- Power supply (3.0 V - 3.6 V)
Power supply for clock generator.

4

V

SSA

-- Power supply (0 V)
Ground for clock generator.

9, 16, 22,
30, 40, 48,

V

SS

-- Power supply (0 V)
Ground for logic and interface.

57, 59, 60,
78, 66, 72

17 AFEFS O L Analog Frontend Frame Sync:

8 kHz frame synchronization signal for the
analog front end.

18 AFECLK O L Analog Frontend Clock:

Clock signal for the analog front end.

19 AFEDD O L Analog Frontend Data Downstream:

Data output to the analog frontend.

20 AFEDU I - Analog Frontend Data Upstream:

Data input from the analog frontend.

79 RST I - Reset:

Active high reset signal.

23 FSC I - Data Frame Synchronization:

8 kHz frame synchronization signal (IOM
SSDI mode).

24 DCL I - Data Clock:

Data Clock of the serial data interface.

®

-2 and

Semiconductor Group 14 10.97

Table 1 Pin Definitions and Functions

26 DD/DR I/ODI- IOM®-2 Compatible Mode:

Receive data from IOM

®

-2 controlling device.

SSDI Mode:

Receive data of the strobed serial data interface.

®

25 DU/DX I/OD

O/
OD

- IOM
Transmit data to IOM

SSDI Mode:

Transmit data of the strobed serial data

-2 Compatible Mode:

®

-2 controlling device.

interface.

27 DXST O L DX Strobe:

Strobe for DX in SSDI interface mode.

28 DRST I - DR Strobe:

Strobe for DR in SSDI interface mode.

PSB 4860

Overview

14 CS

I- Chip Select:

Select signal of the serial control interface (SCI).

11 SCLK I - Serial Clock:

Clock signal of the serial control interface (SCI).

13 SDR I - Serial Data Receive:

Data input of the serial control interface (SCI).

12 SDX O/

OD

10 INT

O/

OD

H Serial Data Transmit:

Data Output of the serial control interface (SCI).

H Interrupt

New status available.

Semiconductor Group 15 10.97

Table 1 Pin Definitions and Functions

52
53
54
55
62
63
64
65
68
69
70
71
74
75
76
77

MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

1)

L
L
L
L
L
L
L

Memory Address 0-15:

Multiplexed address outputs for ARAM, DRAM
access.
Non-multiplexed address outputs for voice
prompt EPROM.

Auxiliary Parallel Port:

General purpose I/O.
L
L
L
L
L
L
L
L
L

PSB 4860

Overview

42
43
44
45
46
47
50
51

35

MD
MD
MD
MD
MD
MD
MD
MD

CAS

0
1
2
3
4
5
6
7

0

ALE

36

CAS

1

FCS

34 RAS

/

FOE

33 VPRD

FCLE

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

/

O

/

O

OH

/

OH

-

-

-

-

-

-

-

-

2)

H

2)

2)

Memory Data 0-7:

Memory (ARAM, DRAM, Flash Memory,

EPROM) data bus.

ARAM, DRAM:

Column address strobe for memory bank 0 or 1.

Flash Memory:

Address Latch Enable for address lines A

16-A23

Chip select signal for Flash Memory

ARAM, DRAM:

Row address strobe for both memory banks.

Flash Memory:

Output enable signal for Flash Memory.

ARAM, DRAM:

Read signal for voice prompt EPROM.

Flash Memory:

Command latch enable for Flash Memory.

.

Semiconductor Group 16 10.97

Table 1 Pin Definitions and Functions

32 W/FWE OH

2)

ARAM, DRAM:

Write signal for all memory banks.

Flash Memory:

Write signal for Flash Memory.

31 FRDY I - Flash Memory Ready

Input for Ready/Busy signal of Flash Memory

PSB 4860

Overview

5
6

OSC
OSC

1
2

I
O

­Z

Auxiliary Oscillator:

Oscillator loop for 32.768 kHz crystal.

8CLKI-Alternative AFECLK Source

13,824 MHz

2
3

37
38

XTAL
XTAL

SPS
SPS

I

1

O

2

0
1

O
O

­Z

L
L

Oscillator:

XTAL
XTAL

: External clock or input of oscillator loop.

1

: output of oscillator loop for crystal.

2

Multipurpose Outputs:

General purpose, speakerphone, address lines
or status

56 RO O - Reserved Output

Must be left open.

1)

These lines are driven low with 125 µA until the mode (address lines or auxi liary port ) is def ined.

2)

These lines are driven high with 70 µA during reset.

Semiconductor Group 17 10.97

1.4 Logic Symbol

1

PSB 4860

Overview

PSB

RST

AFECLK
AFEFS
AFEDD
AFEDU

V

DD

V

DDA

V

SS

MA0-MA15MD0-MD

OSC

CLK

PSB 4860

7

CAS0/
ALE

CAS1/
FCS

Memory

1

OSC

XTAL1XTAL

2

RAS/ VPRD/
FOE

W/
FWE

2

FCLE

DU/DX
DD/DR

DCL

FSC
DXST
DRST

SDX

SDR

SCLK

FRDY

IOM®-2
SSDI4851

INT

SCI

CS

Figure 2 Logic Symbol of PSB 4860

Semiconductor Group 18 10.97

1.5 Functional Block Diagram

PSB 4860

Overview

AFECLK

AFEFS
AFEDD
AFEDU

RST

Analog

Front End

Interface

1

OSC

XTAL1XTAL

2

OSC

Reset and Timing Unit

DSP

Memory Interface

2

DRST
DXST

Data

Interface

Control

Interface

DU/DX
DD/DR
DCL
FSC

INT
SDX
SDR
SCLK
CS

FRDY

MA

-MA15MD0-MD7CAS0/

0

ALE

CAS1/
FCS

RAS/VPRD/
FOE

W/
FWE

FCLE

Figure 3 Block Diagram of PSB 4860

1.6 System Integration

The PSB 4860 combined with an analo g fron t end (PSB 4 851 ) can be used in a variety
of applications. This combination offers outstanding features like full duplex
speakerphone and emergenc y operation. Some applicat ions are given in the followin g
sections.

1.6.1 Analog Featurephone with Digital Answering Machine

Figure 4 shows an example of an analog telephone system. The telephone can operate
during power failure by line powering. In this case only the handset and ringer circuit are
active. All other parts of the chipset are shut down leaving enough power for the external
microcontroller to perform basic tasks like keyboard monitoring.

Semiconductor Group 19 10.97

PSB 4860

Overview

For answering machine operation the voice data is stored in ARAM or Flash Memory
devices. In addition, voice pro mpts can be played back from an optional vo ice prompt
EPROM. If flash memory is used the func tionality of the voice prompt EPROM c an be
realized by the flash memory devices. The microcontroller can use the memory attached
to the PSB 4860/PSB 4851 to store and retrieve binary data.

ARAM

Flash Memory

PSB 4860
PSB 4851

Voice Prompt

EPROM

077-3445

tip/

ring

line

Microcontroller

Figure 4 Analog Full Duplex Speakerphone with Digital Answering Machine

Semiconductor Group 20 10.97

PSB 4860

Overview

1.6.2 Featurephone with Digital Answering Machine for ISDN Terminal

Figure 5 shows an ISDN featureph one that takes full advantage of two simu ltaneous
connections. In this a pplication o ne channel o f the PSB 4851 interfa ces to the hands et
and speakerphone while the other provides an interface for an externa l analog device
(e.g. FAX machine).

Flash Memory

PSB 4860
PSB 4851

IOM®-2

Power Controller

PSB 2120/1

SCI

SLIC

POTS

077-3445

Microcontroller

PSB 2186

®

-S TE

ISAC

S

-BUS

0

Figure 5 Featurephone with Answering Machine for ISDN Terminal

In addition, the two chann els of the PSB 485 1 ca n be use d for holdi ng two c on nec tion s
simultaneously. O ne connection can be switch ed to the handset and the other to the
speakerphone box. Local three party conferences are also possible.

Semiconductor Group 21 10.97

PSB 4860

Overview

1.6.3 DECT Basestation with Integrated Digital Answering Machine

Figure 6 shows a DECT basestation based on the PSB 4860/PSB 4851 chi pset. In this
application it is possible to service both an external call and an internal call at the same
time. For programming the serial control interface (SCI) is used while voice data is

®

transferred via the strobed serial data interface (SSDI/IOM

Flash Memory

-2).

PSB 4860
PSB 4851

SSDI/IOM®-2

Antenna

077-3445

tip/

ring

Microcontroller

line

Figure 6 DECT Basestation

SCI

Burstmode

Controller

DECT

HF

Semiconductor Group 22 10.97

PSB 4860

Functional Description

2 Functional Description

Functional Units
Functional Units

The PSB 4860 contains several functional units that can be combined wit h almost no
restrictions to perform a given task. Figure 7 gives an overview of the important
functional units.

®

SSDI/IOM

-2 IOM®-2
Channel 2Channel 1

loud-

speaker

micro­phone

line

out

line

in

S

4

S

2

I

1

I

2

I

3

S

3

S

9

DTMF

Generator

S

10

I

1

I

2

I

3

S

1

S

5

S

14

Universal

Attenuator

I

1

S

6

I1I2I

I1I

I1I

2

Line Echo

Canceller

S

15

3

S

2

acoustic side

Speaker-

phone

line side

S

12

I3I

S

11

4

I1I

AGC

16

S

8

S

I1I2I

7

S

3

13

Speech

Decoder

Memory

Speech

Coder

I1I

2

I

2

1

Equalizer

S

17

S

18

I

1

CNG

Detector

I

1

Alert Tone

Detector

I

1

CPT

Detector

I

1

CID

Decoder

I

1

DTMF

Detector

SCI

signal summation: s igna l sou rc es:

I

1

I

2

I

3

S

,...,S

1

18

Figure 7 Functional Units - Overview

Semiconductor Group 23 10.97

PSB 4860

Functional Description

Each unit has one or more signa l inputs (denoted by I). Most units have at least one
signal output (denoted by S). Any input I can be co nnected to any signal output S. In
addition to the sign als shown in figure 7 there is also the signal S
useful at signal summation points. Table 2 lists the available signals within the PSB 4860
according to their reference points.

Table 2 Signal Summary
Signal Description

(silence), which is

0

S
S
S
S
S
S
S
S
S
S
S
S
S
S
S

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Silence
Analog line input (channel 1 of PSB 4851 interface)
Analog line output (channel 1 of PSB 4851 interface)
Microphone input (channel 2 of PSB 4851 interface)
Loudspeaker/Handset output (channel 2 of PSB 4851 interface)
Serial interface input, channel 1
Serial interface output, channel 1
Serial interface input, channel 2
Serial interface output, channel 2
DTMF generator output
DTMF generator auxiliary output
Speakerphone output (acoustic side)
Speakerphone output (line side)
Speech decoder output
Universal attenuator output

S

15

S

16

S

17

S

18

Semiconductor Group 24 10.97

Line echo canceller output
Automatic gain control output (after gain stage)
Automatic gain control output (before gain stage)
Equalizer output

PSB 4860

Functional Description

The following figures show the connections for two typical states during operation. Units
that are not needed are not shown. Inputs that are not needed are connected to S
provides silence (denoted by 0). In figure 8 a hands-free phone conversation is currently
in progress. The speech coder is used to record the signals of both parties. The alert tone
detector is used to detect an alerting tone o f an of f-hoo k c all er id request while the CID
decoder decodes the actual data transmitted in this case.

which

0

loud-

speaker

micro­phone

line

out

line

in

0
0

0

Speech

coder

acoustic side

Speaker-

phone

line side

AGC

0

0
0

Memory

Line Echo

Canceller

CID

decoder

Alert Tone

Detector

SCI

Figure 8 Functional Units - Recording a Phone Conversation

Semiconductor Group 25 10.97

PSB 4860

Functional Description

In figure 9 a phone conv ersation using the speakerpho ne is in progress. One party is
using the base station of a DECT system while the other party is using a mobile handset.
At the same time an external call is serviced by the answering machine. In the current
state a message (recorded or out going) is being played back. In this case the DTMF
detector is used t o detect sign als for remote a ccess while th e CPT detector is u sed to
determine the end of the external call.

®

SSDI/IOM

Channel 1

-2

loud-

speaker

micro­phone

line

out

line

in

0
0

0
0

00

0

acoustic side

Speaker-

phone

line side

Equalizer

Speech

decoder

0

Memory

Line Echo

Canceller

CPT

decoder

DTMF

Detector

SCI

Figure 9 Functional Units - Simultaneous Internal and External Call

Semiconductor Group 26 10.97

PSB 4860

Functional Description

2.1 Functional Units

In this section the functional units of the PSB 4860 are described in detail. The functional
units can be individually enabled or disabled.

2.1.1 Full Duplex Speakerphone

The speakerphone unit (figure 10) is attached to four signals (microphone, loudspeaker,
line out and line in). The two input signals (microphone, line in) are preceded by a signal
summation point.

I

1

I

2

S

11

microphone

loudspeaker

a
c
o
u
s

t

Speakerphone

i

c
s

i
d
e

line out

l

i
n
e

s

i
d
e

line in

S

12

I

3

I

4

Figure 10 Speakerphone - Signal Connections

Internally, this unit can be divided into an echo cancellation unit and an echo suppression
unit (figure 11). The echo cancell ation unit provides the attenuation G
suppression unit provides the attenuation G
speakerphone is therefore ATT=G

C+Gs

.

. The total attenuation ATT of the

s

while the echo

c

Echo

Cancellation

G

loudspeaker line in

c

Echo

Suppression

G

S

line outmicrophone

Figure 11 Speakerphone - Block Diagram

The echo suppression unit can be enabled without the echo cancellation unit. If the echo
cancellation unit is disabled, the echo suppression unit still provides speakerphone
functionality, albeit onl y half duplex. As the echo cancellation must be dis abled during
recording or playback of speech data, this option allows for speakerphone operation

Semiconductor Group 27 10.97

PSB 4860

Functional Description

even if recording or playback is going on. The echo sup pression unit is also used to
provide additional attenuation if the echo cancellation unit cannot provide all of the
required attenuation itself.

2.1.2 Echo Cancellation A simplified block diagram of the echo cancellation unit is shown in figure 12.

microphone

line out

-

FIR

NLMSControl

loudspeaker

Filter

line in

Figure 12 Echo Cancellation Unit - Block Diagram

The echo cancellation unit consists of an finite impulse response filter (FIR) that models
the expected acoustic echo, an NLMS based adaption unit and a control unit. The
expected echo is subtracted from the actual input signal from the microphone. If the
model is exact and the echo does n ot excee d the len gth of th e filter t hen the e cho can
be completely cancelled. However, even if this ideal state can be achieved for one given
moment the acoustic echo usually changes over time. Therefore the NLMS unit
continuously adapts the coefficients of the FIR filter. This adaption process is steered by
the control unit. As an example, the adaption is inhibited as long as double talk is
detected by the control un it. Fu rthermore t he con trol unit informs the ech o supp ress ion
unit about the achieved echo return loss.

Table 3 shows the registers associated with the echo cancellation unit.

Table 3 Echo Cancellation Unit Registers
Register # of Bits Name Comment

SAELEN 9 LEN Length of FIR filter
SAEATT 15 ATT Attenuation reduction during double-talk
SAEGS 3 GS Global scale (all blocks)

Semiconductor Group 28 10.97

PSB 4860

Functional Description

Table 3 Echo Cancellation Unit Registers

SAEPS1 3 AS Partial scale (for blocks >= SAEPS2:FB)
SAEPS2 3 FB First block affected by partial scale

The length of the FIR filter can be varied from 127 to 511 taps (15.875ms to 63.875ms).
The taps are grouped into blocks. Each block contains 64 taps.

The performance of the FIR filter can be enhanced by p rescaling some or call of the
coefficients of the FIR filter. A coefficient is prescaled by multiplying it by a constant. The
advantage of prescaling is an enhanced precision and consequently an enhanced echo
cancellation. The disadvantage is a reduced echo cancellation performance if the signal
exceeds the maximal coefficient value. More precisely, if a coefficient at tap T
by a factor C
C

(Max: Maximum PCM value). As an example figure shows a typical room impulse

i

then the level of the echo (room impulse response) must not exceed Max/

i

response.

is scaled

i

A

0.5

0.25

t

0.25

t

Figure 13 Echo Cancellation Unit - Typical Room Impulse Response

First of all, the echo never exceeds 0.5 of the maximum value. Furthermore the echo
never exceeds 0.25 of the maximum value after time t
be scaled by a factor of 2 and all co efficients fo r taps correspon ding to times af ter t

. Therefore all coefficients can

0.25

0.25

can be scaled a factor of 4.
The echo cancellati on unit provides thre e parameters for scali ng coefficients. Th e first

parameter (GS) determines a scale for all coefficients. The second parameter (FB)
determines the first block for which an additional scale (PS) takes effect.

This feature can be used for different default settings like large or small rooms.

Semiconductor Group 29 10.97

PSB 4860

Functional Description

2.1.3 Echo Suppression

The echo suppression unit can be in one of three states:

• transmit state

• receive state

• idle state

In transmit state the microphone signal drives the line output while the line input is
attenuated. In receive state the loudspeaker signa l is driven by the line inp ut while the
microphone signal is attenuated. In idle st ate both signal paths are a ctive with evenly
distributed attenuation.

idle state

microphone

loudspeaker

microphone

transmit state

loudspeaker

microphone

receive stat e

loudspeaker

Figure 14 Echo Suppression Unit - States of Operation

line out
line in

line out
line in

line out
line in

Semiconductor Group 30 10.97