Siemens PEB24902, PEF24902 Datasheet
ICs for Communications
Quad ISDN Echocancellation Circuit Analogue Front End
Quad IEC AFE
PEB 24902 Version 1.1
PEF 24902 Version 1.1
Data Sheet 5.96
T2490-211-D2-7600
Edition 5.96
This edition was realized using the software system FrameMaker
.
Published by Siemens AG,
Bereich Halbleiter, Marketi ng-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 1995.
All Rights Re s e rv e d.
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Critical components
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the
express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause
the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to sup port and/or maintain and sustain
human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 24902 Revision History 5.96
Previous Releases: 2.96
p. 21/22
PLL characteristics
p. 24/25
Description of ADC and table 5, ADC
p.26
Fig. 10
p. 28
Description of DAC
PEB 24902
PEF 24902
Table of Contents Page
Semiconductor Group 3 05.96
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2 System Integrat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1 Line Card Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2 NT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.1.1 Specification of the PLL and the 15.36 MHz Master Clock (Pin CL15) . . .19
3.1.2 Specification of the Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2 Analogue Line Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2.1 Analogue-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.2.2 Range Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.2.3 Digital-to-Analogue Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.2.4 External Hybrid and Transformer Parameters . . . . . . . . . . . . . . . . . . . . . .29
3.2.5 Analogue Loop-back Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2.6 Level Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.2.7 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.8 Power-on-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.1 Frame structure on the Digital Interface in the 2B1Q Mode . . . . . . . . . . .35
3.3.2 Frame structure on the Digital Interface in the 4B3T mode . . . . . . . . . . . .36
3.3.3 Propagation Delay in transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.4 NT-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.5 Boundary Scan Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4 Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.1 Static Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.2 Dynamic Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3 Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.1 Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.1 Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
PEB 24902
PEF 24902
Table of Contents Page
Semiconductor Group 4 05.96
7 Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.1 Storage and Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.2 Operating Ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
7.3 Thermal Contact Resitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Semiconductor Group 5 05.96
PEB 24902
PEF 24902
Overview
1Overview
The PEB 24902 Quad IEC AFE (Quadruple ISDN Echocancellat ion Circuit Analogue
Front End) is part of a 2B1Q or 4B3T ISDN U-tra nsceiv er chip set. Up to four lines c an
be accessed simultane ously b y the Quad IEC AFE. The Qu ad IEC AFE is o ptimized to
work in conjunction with the PEB 24901 Quad IEC DFE-T and the PEB 24911 Quad IEC
DFE-Q. An integrated PLL synchro niz es the 1 5.3 6 MH z Master c loc k on to th e 8 kH z o r
2048 kHz PTT Clock. This spec ification desc ribes the fun ctionality f or 2B1Q and 4B3T
interfaces.
P-MQFP-64-1
Semiconductor Group 6 05.96
Quad ISDN Echocancellation Circuit Analogue Front End
Quad IEC AFE
PEB 24902
PEF 24902
Version 1.1 CMOS
1.1 Features
• Digital to Analogue conversion (transmit pulse)
• Output buffering
• Analogue to digital conversion
• Detection of signal on the line
• Master clock generation by PLL
• P-MQFP-64 Package
• Compliant to ANSI T1.601 (1992), ETSI ETR 080
(1995)
• JTAG boundary scan path compliant to IEEE 1149.1
PEB 24902
PEF 24902
Overview
Semiconductor Group 7 05.96
1.2 Logic Symbol
Figure 1
Logic Symbol
ITL07131
SDX
SDR
XDN2
XDN1
XDN3
XDN4
PDM4
PDM3
PDM1
PDM2
Serial Interface
to PEB
PEB
PEB
24911
24901 or
24902
24911from PEB
Transmit Data
in NT Mode
ADC Outputs
BOUT4
AOUT4
AIN4
BIN4
BIN3
AIN3
AOUT3
BOUT3
BOUT2
AOUT2
AIN2
BIN2
BIN1
AIN1
AOUT1
BOUT1
Analog Line Ports
+5 V
V
DD
d1...2, a1...4
V0
GND a1...4d1...2,
CODE
ADDR
PLLF
RES
REF1
V
REF2
V
REF3
V
REF4
V
Mode Settings
Block Capacitors
100 nF to GND
CLOCK
CL15
XIN
XOUT
TMS
TCK
TDI
TDO
TDISS
Boundary Scan Pins
PEB 24902
PEF 24902
Overview
Semiconductor Group 8 05.96
1.3 Functional Block Diagram
Figure 2
Block Diagram of the Quad IEC AFE
ITB07132
Digital
Interface
Interface
DFE
D
Buffer
Level
Hybrid
Trafo
Analogue
IN/OUT
Voltage Reference
Voltage Reference
IN/OUT
Analogue
Trafo
Hybrid
Level
Buffer
PLL
Common
A
D
A
A
D
A
D
PEB 24902
PEF 24902
Overview
Semiconductor Group 9 05.96
1.4 Pin Configuration
Figure 3
Pin Configuration
(top view)
ITP07133
N.C.
12
64
4748
32
345678910111213141516
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
46 45 44 43 42 41 40 39 38 37 36 35 34 33
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PEB 24902
AOUT4
N.C.
BOUT4
CL15
PDM4
N.C.
BOUT2
AOUT2
V
DD
XDN1
BIN2
AIN2
XDN2
SS
V
SDX
CODE
ADDR
CLOCK
BIN1
AIN1
AOUT3
N.C.
BOUT3
N.C.
PDM3
PDM2
BOUT1
N.C.
AOUT1
SS
V
V
DD
XOUT
XIN
N.C.
REF4
V
V
REF3
N.C.
TMS
TCK
V
SS
TDISS
SS
V
XDN4
AIN4
BIN4
TDO
TDI
BIN3
AIN3
XDN3
V
SS
DD
V
N.C.
V
DD
V
SS
REF1
V
RES
PLLF
V
REF2
DD
V
DD
V
PDM1
SDR
PEB 24902
PEF 24902
Overview
Semiconductor Group 10 05.96
1.5 Pin Definitions and Functions
The following tables group the pins according to their functions. They include pin name,
pin number, type, a brief description of the function and cross-references referring to the
sections in which the pin functions are discussed.
Table 1
Pin Definitions and Functions
Pin No. Symbol Input (I)
Output (O)
Description Reference
Power Supply Pins
37 VDD
d1
5V +/-5% digital supply voltage 5.1
11 VDD
d2
34 VDD
a1
5V +/-5% analogue supply voltage 5.1
15 VDD
a2
46 VDD
a3
3VDD
a4
42 GND
d1
0V digital 5.1
6GND
d2
32 GND
a1
0V analogue 5.1
17 GND
a2
49 GND
a3
64 GND
a4
30 VREF
1
I/O VREF pin to Buffer internally
generated voltage with capacitor
100 nF vs. GND
2
19 VREF
2
I/O VREF pin to Buffer internally
generated voltage with capacitor
100 nF vs. GND
2
51 VREF
3
I/O VREF pin to Buffer internally
generated voltage with capacitor
100 nF vs. GND
2
PEB 24902
PEF 24902
Overview
Semiconductor Group 11 05.96
62 VREF
4
I/O VREF pin to Buffer internally
generated voltage with capacitor.
100 nF vs. GND
2
JTAG Boundary Scan
57 TCK I Test Clock. 3.5,4.3
58 TMS I Test Mode Select, internal pullup. 3.5,4.3
55 TDI I Test Data Input, internal pullup. 3.5,4.3
56 TDO O Test Data Output. 3.5,4.3
59 TDISS
I JTAG Boundary Scan Disable, active
low, internal pullup.
3.5
Line Port Pins
29 AIN1 I Differential U interface input.
Line port 1
3.2.1
28 BIN1 I Differential U interface input.
Line port 1
3.2.1
33 AOUT1 O Differential U interface output.
Line port 1
3.2.3
36 BOUT1 O Differential U interface output.
Line port 1
3.2.3
20 AIN2 I Differential U interface input.
Line port 2
3.2.1
21 BIN2 I Differential U interface input.
Line port 2
3.2.1
16 AOUT2 O Differential U interface output.
Line port 2
3.2.3
13 BOUT2 O Differential U interface output.
Line port 2
3.2.3
52 AIN3 I Differential U interface input.
Line port 3
3.2.1
Table 1
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O)
Description Reference
PEB 24902
PEF 24902
Overview
Semiconductor Group 12 05.96
53 BIN3 I Differential U interface input.
Line port 3
3.2.1
47 AOUT3 O Differential U interface output.
Line port 3
3.2.3
44 BOUT3 O Differential U interface output.
Line port 3
3.2.3
61 AIN4 I Differential U interface input.
Line port 4
3.2.1
60 BIN4 I Differential U interface input.
Line port 4
3.2.1
2 AOUT4 O Differential U interface output.
Line port 4
3.2.3
5 BOUT4 O Differential U interface output.
Line port 4
3.2.3
Digital Interface
7 CL15 I/O Master Clock 15.36 MHz. All
operations and the data exchange on
the digital interface are based on this
clock. If a 15.36 MHz clock is
generated by the internal PLL/
oscillator or if an external clock is
provided at XIN then CL15 issues this
clock. If the pin XIN is clamped to low
or high then CL15 is input and an
other device has to provide the 15.36
MHz clock.
3.1.1, 4.2
38 PDM1 O Pulse density modulated output of the
second-order sigma-delta ADC of line
port 1
3.2.1, 4.2
39 PDM2 O Pulse density modulated output of the
second-order sigma-delta ADC of line
port 2
3.2.1, 4.2
Table 1
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O)
Description Reference
PEB 24902
PEF 24902
Overview
Semiconductor Group 13 05.96
40 PDM3 O Pulse density modulated output of the
second-order sigma-delta ADC of line
port 3
3.2.1, 4.2
8 PDM4 O Pulse density modulated output of the
second-order sigma-delta ADC of line
port 4.
3.2.1, 4.2
31 XDN1 I Input for Transmit data in NT mode.
Not used in LT-Mode. Internal
pulldown.
3.4
18 XDN2 I Input for Transmit data in NT mode.
Not used in LT-Mode. Internal
pulldown.
3.4
50 XDN3 I Input for Transmit data in NT mode.
Not used in LT-Mode. Internal
pulldown.
3.4
63 XDN4 I Input for Transmit data in NT mode.
Not used in LT-Mode. Internal
pulldown.
3.4
24 SDX I Interface for the transmit and control
data. Up to eight lines can be
multiplexed on SDX. Transmission
and sampling is based on clock CL15
(15,36 MBit/sec):
For each line port the following bits
are exchanged:
TD0, TD1, TD2: Transmit data
RANGE: Range select
LOOP: Analogue loop back switch
PDOW: Power down/power up
NT: NT-Mode or LT-Mode
Synchronization information
3.3, 4.2
41 SDR O Level information for the detection of
the awake tone. The four lines are
multiplexed on SDR.
3.3, 4.2
Table 1
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O)
Description Reference
PEB 24902
PEF 24902
Overview
Semiconductor Group 14 05.96
27 ADDR I Select the assignment of time slots
and line ports.
3.3
23 CODE I Select 2B1Q or 4B3T code. Code =
low sets 2B1Q Code.
3.3, 3.2.3
25 RES
I Reset and power down of the entire
IEC Quad AFE including PLL and all
four line ports. Asynchronous signal,
active low.
3.2.9
PLL
9 XOUT O Crystal out. 15.36 MHz crystal is
connected. Leave open if not used.
3.1.2
10 XIN I Crystal in. External 15.36 MHz clock
signal or 15.36 MHz cr ystal is
connected. Clamping XIN to either low
or high sets CL15 to Input.
3.1, 3.1.2
26 CLOCK I 8 kHz or 2048 kHz clock as a time
base of the 15.36 MHz clock.Connect
to GND if not used.
3.1
22 PLLF I Select corner frequency of PLL Jitter
Transfer function. Internal pullup
resistor.
3.1
Table 1
Pin Definitions and Functions (cont’d)
Pin No. Symbol Input (I)
Output (O)
Description Reference
PEB 24902
PEF 24902
System Integration
Semiconductor Group 15 05.96
2 System Integration
The Quad IEC AFE is optimized for line modules in the central office or access networks
(LT function) together with the PEB 24 901 Qu ad IEC DFE-T for 4B3T code o r the PEB
24911 Quad IEC DFE-Q for 2B1Q code. Appli cation in the multi channel NT function
together with the PEB 24911 Quad IEC DFE-Q V2.1 is supported. The PEB 24911 Quad
IEC DFE-Q is footprint compatible to t he PEB 24901 Quad IEC DFE-T. This way, one
board layout can be used for both line codes simply by putting the appropriate DFE.
2.1 Line Card Application
The Quad IEC AFE is controlled via the signal at pin SDX. The transmit data is
transferred the same way. Data on SDX is organized such that two Quad IEC AFE
devices can share the same signal.
The Quad IEC AFE can transmit either 2B1Q-data or 4B3T-data. Setting the pin CODE
to low will result in 2B1Q code. For 4B3T code the pin CODE has to be tied to VDD.
Each of the four line ports is biased by a separate voltage reference. This internal
reference voltage has to be decoupled by a capacitor of 100 nF connected to the VREFx
pin and GND.
The 15.36 MHz master clock is generated with a crystal oscillator and synchronized onto
the PTT clock with an integrated PLL. Fig. 4 shows a 4 channel LT application for 2B1Q
line code. Note, that the PEB 24911 Quad IEC DFE-Q is footprint compatible to the PEB
24901 Quad IEC DFE-T. This way, on e board layout can be used for both linecodes
simply by putting the appropriate DFE.
Figure 4
4 channel LT application
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