Siemens BUZ102SL Datasheet
SIPMOS ® Power Transistor
• N channel
• Enhancement mode
• Logic Level
• Avalanche-rated
• dv/dt rated
• 175°C operating temperature
BUZ 102 SL
SPP47N05L
• also in SMD available
Pin 1 Pin 2 Pin 3
G D S
Type
V
DS
I
D
R
DS(on
BUZ 102 SL 55 V 47 A 0.028
)
Ω
Package Ordering Code
TO-220 AB Q67040-S4010-A2
Maximum Ratings
Parameter Symbol Values Unit
Continuous drain current
T
= 25 °C
C
T
= 100 °C
C
Pulsed drain current
T
= 25 °C
C
Avalanche energy, single pulse
I
= 47 A, VDD = 25 V, RGS = 25
D
L = 222 µH, T
= 25 °C
j
Avalanche current,limited by T
Ω
jmax
Avalanche energy,periodic limited by T
Reverse diode dv/dt
jmax
I
D
I
Dpuls
E
AS
I
AR
E
AR
dv/dt
A
47
33
188
mJ
245
47 A
12 mJ
kV/µs
I
= 47 A, VDS = 40 V, diF/dt = 200 A/µs
S
T
= 175 °C
jmax
Gate source voltage V
Power dissipation
T
= 25 °C
C
Semiconductor Group 1 30/Jan/1998
GS
P
tot
6
±
14 V
120
W
BUZ 102 SL
SPP47N05L
Maximum Ratings
Parameter Symbol Values Unit
Operating temperature T
Storage temperature T
Thermal resistance, junction - case R
Thermal resistance, junction - ambient R
j
stg
thJC
thJA
-55 ... + 175 °C
-55 ... + 175
≤
1.25 K/W
≤
62
IEC climatic category, DIN IEC 68-1 55 / 175 / 56
Electrical Characteristics,
Parameter Symbol Values Unit
Static Characteristics
Drain- source breakdown voltage
V
= 0 V, ID = 0.25 mA, Tj = 25 °C
GS
Gate threshold voltage
V
GS=VDS, ID
= 90 µA
Zero gate voltage drain current
V
= 50 V, VGS = 0 V, Tj = -40 °C
DS
V
= 50 V, VGS = 0 V, Tj = 25 °C
DS
V
= 50 V, VGS = 0 V, Tj = 150 °C
DS
Gate-source leakage current
V
= 20 V, VDS = 0 V
GS
Drain-Source on-resistance
V
= 4.5 V, ID = 33 A
GS
V
= 10 V, ID = 33 A
GS
at Tj = 25°C, unless otherwise specified
min. typ. max.
V
(BR)DSS
55 - -
V
GS(th)
1.2 1.6 2
I
DSS
-
-
-
I
GSS
- 10 100
R
DS(on)
-
-
-
0.1
-
0.022
0.014
V
µA
0.1
1
100
nA
Ω
0.028
0.018
Semiconductor Group 2 30/Jan/1998
BUZ 102 SL
SPP47N05L
Electrical Characteristics,
at Tj = 25°C, unless otherwise specified
Parameter Symbol Values Unit
min. typ. max.
Dynamic Characteristics
Transconductance
≥
V
2
DS
* ID * RDS(on)max, ID
= 33 A
Input capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Output capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Reverse transfer capacitance
V
= 0 V, VDS = 25 V, f = 1 MHz
GS
Turn-on delay time
V
= 30 V, VGS = 4.5 V, ID = 47 A
DD
= 3.6
Ω
R
G
Rise time
V
= 30 V, VGS = 4.5 V, ID = 47 A
DD
= 3.6
Ω
R
G
Turn-off delay time
V
= 30 V, VGS = 4.5 V, ID = 47 A
DD
= 3.6
Ω
R
G
Fall time
V
= 30 V, VGS = 4.5 V, ID = 47 A
DD
= 3.6
Ω
R
G
Gate charge at threshold
V
= 40 V, ID = 0.1 A, VGS =0 to 1 V
DD
Gate charge at 5.0 V
V
= 40 V, ID = 47 A, VGS =0 to 5 V
DD
Gate charge total
V
= 40 V, ID = 47 A, VGS =0 to 10 V
DD
Gate plateau voltage
V
= 40 V, ID = 47 A
DD
g
fs
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g(th)
Q
g(5)
Q
g(total)
V
(plateau)
S
10 - -
pF
- 1380 1730
- 410 515
- 230 290
ns
- 15 25
- 30 45
- 30 45
- 20 30
nC
- 2 3
- 35 55
- 60 90
V
- 4.1 -
Semiconductor Group 3 30/Jan/1998
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