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TrilithIC BTS 770 G
Overview
Features
• Quad switch driver
• Free configurable as bridge or quad-switch
• Optimized for DC motor management applications
• Ultra low
R
High-side switch: typ.165 mΩ,
Low-side switch: typ. 55 mΩ
• Very high peak current capability
DS ON
@25°C:
P-DSO-28-9
• Very low quiescent current
• Space- and thermal optimized power P-DSO-Package
• Load and GND-short-circuit-protected
• Operates up to 40 V
• Status flag diagnosis
• Overtemperature shut down with hysteresis
• Short-circuit detection and diagnosis
• Open-load detection and diagnosis
• C-MOS compatible inputs
• Internal clamp diodes
• Isolated sources for external current sensing
• Over- and under-voltage detection with hysteresis
Type Ordering Code Package
BTS 770 G Q67007-A9254 P-DSO-28-9
Description
The BTS 770 G is a TrilithIC contains one double high-side switch and two low-side
switches in one P-DSO-28-9 -Package.
“Silicon instead of heatsink”
becomes true
The ultra low
R
of this device avoids powerdissipation. It saves costs in mechanical
DS ON
construction and mounting and increases the efficiency.
®
The high-side switches are produced in the SIEMENS SMART SIPMOS
technology. It
is fully protected and contains the signal conditioning circuitry for diagnosis. (The
comparable standard high-side product is the BTS 611L1.)
Semiconductor Group 1 1999-01-07
BTS 770 G
For minimized R
the two low-side switches are produced in the SIEMENS Millifet
DS ON
logic level technology (The comparable standard product is the BUZ 101AL).
Each drain of these three chips is mounted on separated leadframes (see P-DSO-28-9
pin configuration). The sources of all four power transistors are connected to separate
pins.
So the BTS 770 G can be used in H-Bridge configuration as well as in any other switch
configuration.
Moreover, it is possible to add current sense resistors.
All these features open a broad range of automotive and industrial applications.
Semiconductor Group 2 1999-01-07
BTS 770 G
DL1
GL1
DL1
N.C.
DHVS
GND
GH1
ST
GH2
DHVS
N.C.
DL2
1
2
3
425
5
6
7
8
9
10
11
12
LS-Lead Frame 1
HS-Lead Frame
LS-Lead Frame 2
28
27
26
24
23
22
21
20
19
18
17
DL1
SL1
SL1
DL1
DHVS
SH1
SH1
SH2
SH2
DHVS
DL2
SL2
GL2
DL2
13
14
AEP02071
16
15
SL2
DL2
Figure 1 Pin Configuration (top view)
Semiconductor Group 3 1999-01-07
BTS 770 G
Pin Definitions and Functions
Pin No. Symbol Function
1, 3, 25, 28 DL1 Drain of low-side switch1
Leadframe 1
2 GL1 Gate of low-side switch1
4 N.C. not connected
5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage
Leadframe 2
6 GND Ground
7 GH1 Gate of high-side switch1
8 ST Status of high-side switches; open Drain output
9 GH2 Gate of high-side switch2
1)
1)
11 N.C. not connected
12, 14, 15, 18 DL2 Drain of low-side switch2
Leadframe 3
1)
13 GL2 Gate of low-side switch2
16, 17 SL2 Source of low-side switch2
20, 21 SH2 Source of high-side switch2
22, 23 SH1 Source of high-side switch1
26, 27 SL1 Source of low-side switch1
1)
To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
Bold type: Pin needs power wiring
Semiconductor Group 4 1999-01-07
ST
BTS 770 G
DHVS
2419,10,5,
8
GH1
GH2
GND
GL1
GL2
7
9
6
2
13
DST
C6V1
R
I1
3.5 kΩ
R
I2
Diagnosis
Biasing and Protection
Driver
IN OUT
1212
DI1
00
C6V1
0
1
Ωk3.5
LL
1
HL
0
LH
11
HH
DI2
C6V1
R
O1
10 kΩ Ωk10
R
O2
2120,
1815,14,12,
22, 23
25, 283,1,
SH2
DL2
SH1
DL1
26, 16,27 17
SL1 SL2
AEB02072
Figure 2 Block Diagram
Semiconductor Group 5 1999-01-07
BTS 770 G
Circuit Description
Input Circuit
The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with
hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into
the necessary form for driving the power output stages.
The inputs GH1 and GH2 are connected to a standard N-channel logic level power-MOS
gate.
Output Stages
The output stages consist of an ultra low
R
Power-MOS H-Bridge. Protective circuits
DS ON
make the outputs short circuit proof to ground and load short circuit proof. Positive and
negative voltage spikes, which occur when driving inductive loads, are limited by
integrated power clamp diodes.
Short Circuit Protection (valid only for the high-side switches)
The outputs are protected against
– output short circuit to ground, and
– overload (load short circuit).
An internal OP-Amp controls the Drain-Source-Voltage of the HS-Switches by
comparing the DS-Voltage-Drop with an internal reference voltage. Above this trippoint
the OP-Amp reduces the output current depending on the junction temperature and the
drop voltage.
In the case of overloaded high-side switches the status output is set to low.
R
If the HS-Switches are in OFF-state-Condition internal resistors
from SH1,2 to GND
O1,2
pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output
examiner circuit compares the output voltages with the internal reference voltage VEO.
This results in switching the status output to low. In H-Bridge condition this feature can
be used to protect the low-side switches against short circuit during the OFF-period.
Overtemperature Protection (valid only for the high-side-switches)
The chip also incorporates an overtemperature protection circuit with hysteresis which
switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
V
When
reaches the switch-on voltage V
S
The High-Side output transistors are switched off if the supply voltage
the switch off value
Semiconductor Group 6 1999-01-07
V
UVOFF
.
the IC becomes active with a hysteresis.
UVON
V
drops below
S
BTS 770 G
Overvoltage-Lockout (OVLO)
V
When
reaches the switch-off voltage V
S
switched off with a hysteresis. The IC becomes active if the supply voltage
below the switch-on value
V
OVON
.
Open Load Detection
Open load is detected by current measurement. If the output current drops below an
internal fixed level the error flag is set with a delay.
Status Flag
Various errors as listed in the table “Diagnosis” are detected by switching the open drain
output ST to low.
the High-Side output transistors are
OVOFF
V
drops
S
Semiconductor Group 7 1999-01-07
BTS 770 G
Truthtable and Diagnosis (valid only for the High-Side-Switches)
Flag GH1 GH2 SH1 SH2 ST Remarks
Inputs Outputs
Normal operation;
identical with functional truth table
Open load at high-side switch1
Open load at high-side switch2
Short circuit to DHVS at high-side switch1
Short circuit to DHVS at high-side switch2
Overtemperature high-side switch1 0
Overtemperature high-side switch2 X
0
0
1
1
0
0
1
0
1
X
0
0
1
0
1
X
1
X
0
1
0
1
0
1
X
0
0
1
0
1
X
0
0
1
X
X
0
1
L
L
H
H
Z
Z
H
L
H
X
H
H
H
L
H
X
L
L
X
X
L
H
L
H
L
H
X
Z
Z
H
L
H
X
H
H
H
X
X
L
L
1
stand-by mode
1
switch2 active
1
switch1 active
1
both switches
active
1
1
0
detected
1
1
0
detected
0
detected
1
1
0
detected
1
1
1
0 detected
1
0 detected
Overtemperature both high-side switch 0
X
1
Over- and Under-Voltage X X L L 1 not detected
Inputs: Outputs: Status:
0 = Logic LOW Z = Output in tristate condition 1 = No error
1 = Logic HIGH L = Output in sink condition 0 = Error
X = don’t care H = Output in source condition
X = Voltage level undefined
0
1
X
L
L
L
L
L
L
1
0
0
detected
detected
Semiconductor Group 8 1999-01-07
Electrical Characteristics
Absolute Maximum Ratings
– 40 °C <
T
< 150 °C
j
Parameter Symbol Limit Values Unit Remarks
min. max.
High-Side-Switches (Pins DHVS, GH1,2 and SH1,2)
BTS 770 G
Supply voltage
HS-drain current
HS-input current
HS-input voltage
V
I
I
V
S
DHS
GH
GH
– 0.3 43 V –
– 8 * A * internally limited
– 2 2 mA Pin GH1 and GH2
– 10 16 V Pin GH1 and GH2
Status Output ST
Status Output current
I
ST
– 5 5 mA Pin ST
Low-Side-Switches (Pins DL1,2, GL1,2 and SL1,2)
Break-down voltage
LS-drain current
LS-drain current
LS-drain current
lS-input voltage
V
(BR)DSS
I
DLS
I
DLS
I
DLS
V
GL
50 – V VGS = 0 V; ID<= 1 mA
–10A–
–20At < 1 ms; ν<0.1
–30At < 0.1 ms; ν<0.1
– 10 14 V Pin GL1 and GL2
Temperatures
Junction temperature
Storage temperature
T
j
T
stg
– 40 150 °C–
– 50 150 °C–
Thermal Resistances (one HS-LS-Path active)
LS-junction case
HS-junction case
Junction ambient
R
R
R
thjCLS
thjCHS
thja
– 20 K/W measured to pin3 or 12
– 20 K/W measured to pin19
– 60 K/W –
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Semiconductor Group 9 1999-01-07
BTS 770 G
Operating Range
Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage
Input voltages V
Input voltages
Output current
HS-junction temperature
LS-junction temperature
V
V
I
T
T
S
GH
GL
ST
jHS
jLS
V
UVOFF
34 V After VS rising
above
– 0.3 15 V –
– 9 13 V –
0 2 mA –
– 40 150 °C–
– 40 150 °C–
V
UVON
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group 10 1999-01-07
BTS 770 G
Electrical Characteristics
I
= I
SH1
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
Current Consumption
SH2
= I
SL1
= I
= 0 A; – 40 °C < Tj < 150 °C; 8 V > VS> 18 V
SL2
min. typ. max.
Quiescent current I
Quiescent current
Supply current
Supply current
S
I
S
I
S
I
S
Under Voltage Lockout (UVLO)
Switch-ON voltage V
Switch-OFF voltage
Switch ON/OFF hysteresis
UVON
V
UVOFF
V
UVHY
Over Voltage Lockout (OVLO)
Switch-OFF voltage
V
OVOFF
–1630µA GH1 = GH2 = L
V
= 13.2 V
S
T
= 25 °C
j
––35µA GH1 = GH2 = L
V
= 13.2 V
S
– 2 3.5 mA GH1 or GH2 = H
– 4 7 mA GH1 and GH2 = H
– 5.4 7 V VS increasing
3.5 4.3 – V VSdecreasing
– 1.1 – V V
UVON
– V
UVOFF
36 38 43 V VSincreasing
Switch-ON voltage
Switch OFF/ON hysteresis
V
V
OVON
OVHY
35 37.3 – V VS decreasing
– 0.7 – V V
OVOFF
– V
OVON
Short Circuit of Highside Switch to GND
Initial peak SC current
Initial peak SC current
Initial peak SC current
Semiconductor Group 11 1999-01-07
I
I
I
SCP
SCP
SCP
81013ATj = – 40 °C
6.5 8.5 11 A Tj = 25 °C
3.9 5 7 A Tj = 150 °C
BTS 770 G
Electrical Characteristics (cont’d)
I
= I
SH1
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
SH2
= I
SL1
= I
= 0 A; – 40 °C < Tj < 150 °C; 8 V > VS> 18 V
SL2
min. typ. max.
Short Circuit of Highside Switch to V
OFF-state
V
EO
S
234VVGH = 0 V
examiner-voltage
Output pull-down-resistor
R
O
4 1130kΩ –
Open Circuit Detection of Highside Switch
Detection current I
OCD
10 90 200 mA –
Switching Times of Highside Switch
Switch-ON-time;
to 90%
V
SH
Switch-OFF-time;
to 10%
V
SH
t
ON_H
t
OFF_H
– 0.2 0.4 ms resistive load
– 0.15 0.4 ms resistive load
Control Inputs of Highside Switches GH 1, 2
I
= 1 A; VS = 12 V
SH
I
= 1 A; VS = 12 V
SH
H-input voltage V
L-input voltage
Input voltage hysterese
H-input current
L-input current
Input series resistance
Zener limit voltage
V
V
I
I
R
V
GHH
GHL
GHHY
GHH
GHL
I
GHZ
– 2.8 3.5 V –
1.5 2.3 – V –
– 0.5 – V –
20 60 90 µA VGH = 5 V
12550µA VGH = 0.4 V
2.5 3.5 6 kΩ –
5.4 – – V IGH = 1.6 mA
Status Flag Output ST of Highside Switch
Low output voltage V
Leakage current
Zener-limit-voltage
Semiconductor Group 12 1999-01-07
I
STLK
V
STL
STZ
– 0.25 0.6 V IST = 1.6 mA
– 0.5 10 µA VST = 5 V
5.4 – – V IST = 1.6 mA
BTS 770 G
Electrical Characteristics (cont’d)
I
= I
SH1
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
Control Inputs of Lowside Switches GL1, 2
SH2
= I
SL1
= I
= 0 A; – 40 °C < Tj < 150 °C; 8 V > VS> 18 V
SL2
min. typ. max.
Gate-threshold-voltage
Transconductance
V
g
GL(th)
fs
Switching Times of Lowside Switch
Switch-ON delay time;
V
= 5 V; RGS= 50Ω
GS
Switch-ON time;
V
= 5 V; RGS= 50Ω
GS
Switch-OFF delay time;
V
= 5 V; RGS= 50Ω
GS
Switch-OFF time;
V
= 5 V; RGS= 50Ω
GS
t
d_ON_L
t
ON_L
t
d_OFF_L
t
OFF_L
Thermal Shutdown
0.8 1.6 2.5 V VGL = V
I
= 1 mA
DL
–5–SV
DSL
I
= 20 A
DL
= 20 V;
DSL
;
– 25 40 ns resistive load
I
= 1 A; VS = 12 V
SL
– 95 140 ns resistive load
I
= 1 A; VS = 12 V
SL
– 140 190 ns resistive load
I
= 1 A; VS = 12 V
SL
– 85 115 ns resistive load
I
= 1 A; VS = 12 V
SL
Thermal shutdown junction
T
jSD
155 – 190 °C–
temperature
Thermal switch-on junction
T
jSO
150 – 180 °C–
temperature
Temperature hysteresis ∆
Semiconductor Group 13 1999-01-07
T –10–°C ∆T = T
jSD
–T
jSO
BTS 770 G
Electrical Characteristics (cont’d)
I
= I
SH1
unless otherwise specified
Parameter Symbol Limit Values Unit Test Condition
Output Stages
SH2
= I
SL1
= I
= 0 A; – 40 °C < Tj < 150 °C; 8 V > VS> 18 V
SL2
min. typ. max.
Leakage current
of highside switch
Leakage current
of lowside switch
Clamp-diode
of highside switch;
Forward-Voltage
Clamp-diode leakage-
I
current (
+ ISH)
FH
of highside switch
Clamp-diode
of lowside switch;
forward-voltage
Static drain-source
on-resistance
of highside switch
Static drain-source
on-resistance
of lowside switch
I
HSLK
I
LSLK
V
FH
I
LKCL
V
FL
R
DS ON H
R
DS ON L
–512µA VGH = VSH = 0 V
– 20 100 µA VGL = 0 V
V
= 18 V
DS
– 0.8 1.5 V IFH = 3 A
– 2 10 mA IFH = 3 A
– 0.8 1.5 V IFL = 3 A
– 165 220 mΩ ISH =1A
T
= 25 °C
j
– 4565mΩ ISL = 1 A;
V
= 5 V
GL
T
= 25 °C
j
Static path on-resistance
R
DS ON
– – 500 mΩ
R
DS ON H
I
=1A
SH
+ R
DS ON L
;
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at
T
= 25°C and
A
the given supply voltage.
Semiconductor Group 14 1999-01-07
BTS 770 G
Ι
S
Ι
FH1,2
C
S
470nF
C
L
F100
µ
DHVS
Ι
Ι
,
STLK
ST
ST
8
5, 10, 19, 24
V
+
S
DST
C6V1
Ι
GH1
V
ST
V
STL
V
STZ
V
GH1
V
GH2
Ι
GH2
Ι
Ι
GH2 9
GND 6
GND
LKCL1,
R
I1
7GH1
3.5 kΩ
DI1
C6V1
R
I2
Ωk3.5
DI2
C6V1
2
Diagnosis
Driver
IN OUT
1212
00
LL
0
1
HL
0
1
LH
11
HH
Biasing and Protection
R
O1
R
O2
10 kΩ Ω10 k
12, 14, 15, 18
22, 23
1, 3,
25, 28
20
21
SH2
DL2
SH1
DL1
Ι
Ι
Ι
Ι
Ι
Ι
SH2
DL2
LKL
SH1
DL1
LKL
V
V
DSH2
FH2
--
V
DSH1
V
FH1
V
UVON
V
UVOFF
V
OVON
V
OVOFF
GL1 2
V
GL1
V
GL(th)1
V
GL2
V
GL(th)2
GL2 13
26, 27 16, 17
SL1 SL2
Ι
Ι
SL2SL1
V
V
V
--
EO1
DSL1
FL1
V
V
V
EO2
DSL2
FL2
R
V
= =
DSONH
DSH
Ι
R
SH
DSONL
V
Ι
DSL
SL
AES02079
Figure 3 Test Circuit
HS-Source-Current Named during
Short Circuit
I
SH1,2
Semiconductor Group 15 1999-01-07
I
SCP
Named during
Open Circuit
I
OCD
Named during
Leakage-Cond.
I
HSLK
Watchdog
Reset
Q
TLE 4268G
BTS 770 G
I
DO1
V
=12V
S
WD R
P
µ
R
Q
100 kΩ
V
CC
R
S
ST
8
Ωk10
C
22 F
DST
Q
C6V1
R
I1
7GH1
3.5 kΩ
R
GH2 9
I2
Ω3.5 k
GND 6
D GND
Diagnosis
Driver
IN OUT
1212
DI1
C6V1
00
0
1
0
1
11
DI2
C6V1
C
D
100nF
DHVS
Biasing and Protection
R
LL
HL
LH
O1
10 kΩ Ωk10
HH
5, 10, 19, 24
R
O2
12, 14, 15, 18
22, 23
C
S
22 F
µ
20
21
1, 3,
SH2
DL2
SH1
DL1
M1
25, 28
GL1 2
GL2 13
26, 27 16, 17
SL1 SL2
AES02074
Figure 4 Application Circuit
Semiconductor Group 16 1999-01-07
Package Outlines
P-DSO-28-9
(Plastic Dual Small Outline Package)
1.27
+0.15
0.35
2)
0.2 28x
BTS 770 G
0.35 x 45˚
-0.2
-0.1
0.2
2.45
2.65 max
0.1
1528
7.6
0.4
10.3
-0.2
1)
+0.8
±0.3
+0.09
0.23
8˚ max
114
18.1
-0.4
1)
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max rer side
2) Does not include dambar protrusion of 0.05 max per side
GPS05123
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group 17 1999-01-07
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